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Float arithmetic needs i64 lowering as register pairs #127

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@Zaneham

runtime/soft_fp.c is built on uint64_t mantissa arithmetic throughout and RV32 has no 64-bit registers. The isel now refuses i64 rather than silently truncating it, so the soft-float runtime cannot compile for the baby cores at all.

The right fix is type legalization, splitting i64 into register pairs the way LLVM's SelectionDAG legalizer and GCC's lower-subreg do. RV32 has no carry flag, so add becomes add lo, sltu carry, add hi, add carry. Multiply is three mul/mulhu pairs and compares test high then low. Variable shifts are the fiddly part.

Worth doing properly rather than rewriting the runtime to dodge it, since it also unblocks any user code using long long, and f64 later.

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    backend: TensixTenstorrent Tensix / Metalium backendenhancementNew feature or request

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