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xusheng6xusheng6
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Add armv8 to the free version. Fix Vector35/binaryninja#1153 
1 parent e3abb2e commit 032b5d6

8 files changed

Lines changed: 62 additions & 62 deletions

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‎arch/arm64/arch_arm64.cpp‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,7 @@ class Arm64Architecture : public Architecture
420420
{
421421
if (operand->shiftType != ShiftType_NONE)
422422
{
423-
const char* shiftStr = get_shift(operand->shiftType);
423+
const char* shiftStr = aarch64_get_shift(operand->shiftType);
424424
if (shiftStr == NULL)
425425
return FAILED_TO_DISASSEMBLE_OPERAND;
426426

@@ -494,7 +494,7 @@ class Arm64Architecture : public Architecture
494494
uint32_t tokenize_shifted_register(const InstructionOperand* restrict operand,
495495
uint32_t registerNumber, vector<InstructionTextToken>& result)
496496
{
497-
const char* reg = get_register_name(operand->reg[registerNumber]);
497+
const char* reg = aarch64_get_register_name(operand->reg[registerNumber]);
498498
if (EMPTY(reg))
499499
return FAILED_TO_DISASSEMBLE_REGISTER;
500500

@@ -533,7 +533,7 @@ class Arm64Architecture : public Architecture
533533
return tokenize_shifted_register(operand, registerNumber, result);
534534
}
535535

536-
const char* reg = get_register_name(operand->reg[registerNumber]);
536+
const char* reg = aarch64_get_register_name(operand->reg[registerNumber]);
537537
if (EMPTY(reg))
538538
return FAILED_TO_DISASSEMBLE_REGISTER;
539539

@@ -573,7 +573,7 @@ class Arm64Architecture : public Architecture
573573
char paramBuff[32] = {0};
574574
const char *reg0, *reg1;
575575

576-
reg0 = get_register_name(operand->reg[0]);
576+
reg0 = aarch64_get_register_name(operand->reg[0]);
577577
if (EMPTY(reg0))
578578
return FAILED_TO_DISASSEMBLE_REGISTER;
579579

@@ -615,7 +615,7 @@ class Arm64Architecture : public Architecture
615615
}
616616
else
617617
{
618-
reg1 = get_register_name(operand->reg[1]);
618+
reg1 = aarch64_get_register_name(operand->reg[1]);
619619
if (EMPTY(reg1))
620620
return FAILED_TO_DISASSEMBLE_REGISTER;
621621
result.emplace_back(EndMemoryOperandToken, "");
@@ -639,7 +639,7 @@ class Arm64Architecture : public Architecture
639639
break;
640640
case MEM_EXTENDED: // [<reg>, <reg> optional(shift optional(imm))]
641641
result.emplace_back(TextToken, ", ");
642-
reg1 = get_register_name(operand->reg[1]);
642+
reg1 = aarch64_get_register_name(operand->reg[1]);
643643
if (EMPTY(reg1))
644644
return FAILED_TO_DISASSEMBLE_REGISTER;
645645
result.emplace_back(RegisterToken, reg1);
@@ -690,7 +690,7 @@ class Arm64Architecture : public Architecture
690690
uint32_t tokenize_condition(
691691
const InstructionOperand* restrict operand, vector<InstructionTextToken>& result)
692692
{
693-
const char* condStr = get_condition((Condition)operand->cond);
693+
const char* condStr = aarch64_get_condition((Condition)operand->cond);
694694
if (condStr == NULL)
695695
return FAILED_TO_DISASSEMBLE_OPERAND;
696696

@@ -802,7 +802,7 @@ class Arm64Architecture : public Architecture
802802
return false;
803803

804804
memset(buf, 0x20, sizeof(buf));
805-
const char* operation = get_operation(&instr);
805+
const char* operation = aarch64_get_operation(&instr);
806806
if (operation == nullptr)
807807
return false;
808808

@@ -868,7 +868,7 @@ class Arm64Architecture : public Architecture
868868
case ACCUM_ARRAY: /* eg: "za[w12, #0x6]" */
869869
result.emplace_back(TextToken, "ZA");
870870
result.emplace_back(BraceToken, "[");
871-
snprintf(buf, sizeof(buf), "%s", get_register_name(operand->reg[0]));
871+
snprintf(buf, sizeof(buf), "%s", aarch64_get_register_name(operand->reg[0]));
872872
result.emplace_back(RegisterToken, buf);
873873
result.emplace_back(OperandSeparatorToken, ", ");
874874
result.emplace_back(OperationToken, " #");
@@ -888,7 +888,7 @@ class Arm64Architecture : public Architecture
888888
if (operand->reg[0] != REG_NONE)
889889
{
890890
result.emplace_back(BraceToken, "[");
891-
snprintf(buf, sizeof(buf), "%s", get_register_name(operand->reg[0]));
891+
snprintf(buf, sizeof(buf), "%s", aarch64_get_register_name(operand->reg[0]));
892892
result.emplace_back(RegisterToken, buf);
893893
if (operand->arrSpec != ARRSPEC_FULL)
894894
{
@@ -902,10 +902,10 @@ class Arm64Architecture : public Architecture
902902
tokenizeSuccess = true;
903903
break;
904904
case INDEXED_ELEMENT: /* eg: "p12.d[w15, #0xf]" */
905-
result.emplace_back(RegisterToken, get_register_name(operand->reg[0]));
905+
result.emplace_back(RegisterToken, aarch64_get_register_name(operand->reg[0]));
906906
result.emplace_back(TextToken, get_arrspec_str_truncated(operand->arrSpec));
907907
result.emplace_back(BraceToken, "[");
908-
result.emplace_back(RegisterToken, get_register_name(operand->reg[1]));
908+
result.emplace_back(RegisterToken, aarch64_get_register_name(operand->reg[1]));
909909
if (operand->immediate)
910910
{
911911
result.emplace_back(OperandSeparatorToken, ", ");
@@ -1673,7 +1673,7 @@ class Arm64Architecture : public Architecture
16731673
virtual string GetRegisterName(uint32_t reg_) override
16741674
{
16751675
if (reg_ > REG_NONE && reg_ < REG_END)
1676-
return get_register_name((enum Register)reg_);
1676+
return aarch64_get_register_name((enum Register)reg_);
16771677

16781678
if (reg_ > SYSREG_NONE && reg_ < SYSREG_END)
16791679
return get_system_register_name((enum SystemReg)reg_);

‎arch/arm64/disassembler/decode.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -903,7 +903,7 @@ extern "C"
903903
#endif
904904

905905
int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t address);
906-
size_t get_register_size(enum Register);
906+
size_t aarch64_get_register_size(enum Register);
907907

908908
#ifdef __cplusplus
909909
}

‎arch/arm64/disassembler/format.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ const char *get_register_arrspec(Register reg, const InstructionOperand *operand
7070

7171
int get_register_full(Register reg, const InstructionOperand *operand, char *result)
7272
{
73-
strcpy(result, get_register_name(reg));
73+
strcpy(result, aarch64_get_register_name(reg));
7474
if(result[0] == '\0')
7575
return -1;
7676

@@ -95,7 +95,7 @@ uint32_t get_implementation_specific(const InstructionOperand *operand, char *ou
9595
operand->implspec[4]) >= outBufferSize;
9696
}
9797

98-
const char *get_operation(const Instruction *inst)
98+
const char *aarch64_get_operation(const Instruction *inst)
9999
{
100100
return operation_to_str(inst->operation);
101101
}
@@ -107,7 +107,7 @@ static const char *const ConditionString[] = {
107107
"gt", "le", "al", "nv"
108108
};
109109

110-
const char *get_condition(Condition cond)
110+
const char *aarch64_get_condition(Condition cond)
111111
{
112112
if (cond < 0 || cond >= END_CONDITION)
113113
return NULL;
@@ -122,7 +122,7 @@ static const char *const ShiftString[] = {
122122
"uxtb", "msl"
123123
};
124124

125-
const char *get_shift(ShiftType shift)
125+
const char *aarch64_get_shift(ShiftType shift)
126126
{
127127
if (shift <= ShiftType_NONE || shift >= ShiftType_END)
128128
return NULL;
@@ -156,7 +156,7 @@ static inline uint32_t get_shifted_register(
156156
return FAILED_TO_DISASSEMBLE_REGISTER;
157157
}
158158
}
159-
const char *shiftStr = get_shift(operand->shiftType);
159+
const char *shiftStr = aarch64_get_shift(operand->shiftType);
160160
if (shiftStr == NULL)
161161
return FAILED_TO_DISASSEMBLE_OPERAND;
162162
snprintf(
@@ -248,7 +248,7 @@ uint32_t get_memory_operand(
248248
if (operand->shiftType != ShiftType_NONE)
249249
{
250250
if (snprintf(extendBuff, sizeof(extendBuff), ", %s%s",
251-
get_shift(operand->shiftType), immBuff) >= sizeof(extendBuff))
251+
aarch64_get_shift(operand->shiftType), immBuff) >= sizeof(extendBuff))
252252
{
253253
return FAILED_TO_DISASSEMBLE_OPERAND;
254254
}
@@ -371,7 +371,7 @@ uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, cha
371371
return FAILED_TO_DISASSEMBLE_REGISTER;
372372
}
373373
}
374-
const char *shiftStr = get_shift(instructionOperand->shiftType);
374+
const char *shiftStr = aarch64_get_shift(instructionOperand->shiftType);
375375
if (shiftStr == NULL)
376376
return FAILED_TO_DISASSEMBLE_OPERAND;
377377
snprintf(
@@ -419,9 +419,9 @@ uint32_t get_sme_tile(const InstructionOperand *operand, char *outBuffer, uint32
419419
char base_offset[32] = {'\0'};
420420
if(operand->reg[0] != REG_NONE) {
421421
if(operand->arrSpec == ARRSPEC_FULL)
422-
snprintf(base_offset, sizeof(base_offset), "[%s]", get_register_name(operand->reg[0]));
422+
snprintf(base_offset, sizeof(base_offset), "[%s]", aarch64_get_register_name(operand->reg[0]));
423423
else
424-
snprintf(base_offset, sizeof(base_offset), "[%s, #%" PRIu64 "]", get_register_name(operand->reg[0]), operand->immediate);
424+
snprintf(base_offset, sizeof(base_offset), "[%s, #%" PRIu64 "]", aarch64_get_register_name(operand->reg[0]), operand->immediate);
425425
}
426426

427427
char *slice = "";
@@ -451,9 +451,9 @@ uint32_t get_indexed_element(const InstructionOperand *operand, char *outBuffer,
451451

452452
// <Pn>.<T>[<Wm>{, #<imm>}]
453453
if(snprintf(outBuffer, outBufferSize, "%s%s[%s%s]",
454-
get_register_name(operand->reg[0]),
454+
aarch64_get_register_name(operand->reg[0]),
455455
get_arrspec_str_truncated(operand->arrSpec),
456-
get_register_name(operand->reg[1]),
456+
aarch64_get_register_name(operand->reg[1]),
457457
optional_comma_and
458458
) >= outBufferSize)
459459
return FAILED_TO_DISASSEMBLE_OPERAND;
@@ -464,7 +464,7 @@ uint32_t get_indexed_element(const InstructionOperand *operand, char *outBuffer,
464464
uint32_t get_accum_array(const InstructionOperand *operand, char *outBuffer, uint32_t outBufferSize)
465465
{
466466
if(snprintf(outBuffer, outBufferSize, "ZA[%s, #%" PRIu64 "]",
467-
get_register_name(operand->reg[0]), operand->immediate
467+
aarch64_get_register_name(operand->reg[0]), operand->immediate
468468
) >= outBufferSize)
469469
return FAILED_TO_DISASSEMBLE_OPERAND;
470470

@@ -484,7 +484,7 @@ int aarch64_disassemble(Instruction *instruction, char *buf, size_t buf_sz)
484484
return INVALID_ARGUMENTS;
485485

486486
memset(operandStrings, 0, sizeof(operandStrings));
487-
const char *operation = get_operation(instruction);
487+
const char *operation = aarch64_get_operation(instruction);
488488
if (operation == NULL)
489489
return FAILED_TO_DISASSEMBLE_OPERATION;
490490

@@ -497,7 +497,7 @@ int aarch64_disassemble(Instruction *instruction, char *buf, size_t buf_sz)
497497
{
498498
case CONDITION:
499499
if (snprintf(tmpOperandString, sizeof(tmpOperandString), "%s",
500-
get_condition((Condition)instruction->operands[i].cond)) >= sizeof(tmpOperandString))
500+
aarch64_get_condition((Condition)instruction->operands[i].cond)) >= sizeof(tmpOperandString))
501501
return FAILED_TO_DISASSEMBLE_OPERAND;
502502
operand = tmpOperandString;
503503
break;
@@ -592,7 +592,7 @@ int aarch64_disassemble(Instruction *instruction, char *buf, size_t buf_sz)
592592
}
593593
memset(buf, 0, buf_sz);
594594
if (snprintf(buf, buf_sz, "%s%s%s%s%s%s",
595-
get_operation(instruction),
595+
aarch64_get_operation(instruction),
596596
operandStrings[0],
597597
operandStrings[1],
598598
operandStrings[2],

‎arch/arm64/disassembler/format.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@ int get_register_full(enum Register, const InstructionOperand *, char *result);
4040
const char *get_register_arrspec(enum Register, const InstructionOperand *);
4141

4242
// miscellany to string
43-
const char *get_operation(const Instruction *instruction);
44-
const char *get_shift(ShiftType shift);
45-
const char *get_condition(Condition cond);
43+
const char *aarch64_get_operation(const Instruction *instruction);
44+
const char *aarch64_get_shift(ShiftType shift);
45+
const char *aarch64_get_condition(Condition cond);
4646
uint32_t get_implementation_specific(
4747
const InstructionOperand *operand,
4848
char *outBuffer,

‎arch/arm64/disassembler/regs.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,15 +166,15 @@ static const char* const RegisterString[] = {"NONE", "w0", "w1", "w2", "w3", "w4
166166
"pstl1keep", "pstl1strm", "pstl2keep", "pstl2strm", "pstl3keep", "pstl3strm", "#0x16", "#0x17",
167167
"#0x18", "#0x19", "#0x1a", "#0x1b", "#0x1c", "#0x1d", "#0x1e", "#0x1f", "zt0", "END"};
168168

169-
const char* get_register_name(enum Register r)
169+
const char* aarch64_get_register_name(enum Register r)
170170
{
171171
if (r > REG_NONE && r < REG_END)
172172
return RegisterString[r];
173173

174174
return "";
175175
}
176176

177-
size_t get_register_size(enum Register r)
177+
size_t aarch64_get_register_size(enum Register r)
178178
{
179179
// Comparison done in order of likelyhood to occur
180180
if ((r >= REG_X0 && r <= REG_SP) || (r >= REG_D0 && r <= REG_D31))

‎arch/arm64/disassembler/regs.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1341,8 +1341,8 @@ enum Register
13411341
extern "C"
13421342
{
13431343
#endif
1344-
const char* get_register_name(enum Register);
1345-
size_t get_register_size(enum Register);
1344+
const char* aarch64_get_register_name(enum Register);
1345+
size_t aarch64_get_register_size(enum Register);
13461346
#ifdef __cplusplus
13471347
}
13481348
#endif

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