Design: OpenOFDM
Repository: https://github.com/jhshi/openofdm (active fork: https://github.com/open-sdr/openofdm)
License: Apache-2.0
Language: Verilog
Stars: 465
Description
A synthesizable, modular Verilog implementation of an 802.11 OFDM PHY decoder. Supports 802.11a/g (all bit rates) and 802.11n (20MHz BW, MCS 0-7). Takes 32-bit I/Q samples as input and outputs decoded packet bytes.
Why it's a good benchmark candidate
- New architecture: First wireless PHY / signal processing pipeline in the suite. A completely new design category — no overlap with existing processors, accelerators, or network MACs.
- Large design: Full receive chain with deep pipeline: synchronization → FFT → channel estimation → equalization → deinterleaving → Viterbi decoding → descrambling. Bundles multiple DSP blocks into a realistic system-level design.
- Industry-relevant: 802.11 WiFi is ubiquitous. OFDM decoders are a staple of wireless ASIC/FPGA design and representative of real signal processing workloads.
- Active development: The open-sdr fork was updated Feb 2026 and is used in the openwifi project (open-source WiFi chip).
Estimated complexity
- Gate count: Large (FFT engine, Viterbi decoder, channel estimator, equalizer, control logic)
- Memories: Yes — FFT buffers, interleaver/deinterleaver storage, Viterbi traceback memory will need FakeRAM
- IO count: Medium (32-bit I/Q input, decoded byte output, control signals)
Verification
Verified on Ettus Research USRP N210 hardware. Includes simulation test inputs (both simulated and captured over-the-air). Documentation at openofdm.readthedocs.io.
Conversion notes
Pure Verilog — no conversion needed. May need to stub out or exclude any USRP-specific I/O wrappers; the core dot11 module is self-contained.
Target platforms
Design: OpenOFDM
Repository: https://github.com/jhshi/openofdm (active fork: https://github.com/open-sdr/openofdm)
License: Apache-2.0
Language: Verilog
Stars: 465
Description
A synthesizable, modular Verilog implementation of an 802.11 OFDM PHY decoder. Supports 802.11a/g (all bit rates) and 802.11n (20MHz BW, MCS 0-7). Takes 32-bit I/Q samples as input and outputs decoded packet bytes.
Why it's a good benchmark candidate
Estimated complexity
Verification
Verified on Ettus Research USRP N210 hardware. Includes simulation test inputs (both simulated and captured over-the-air). Documentation at openofdm.readthedocs.io.
Conversion notes
Pure Verilog — no conversion needed. May need to stub out or exclude any USRP-specific I/O wrappers; the core
dot11module is self-contained.Target platforms