diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 161e77d5a2..0abd1aa460 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -311,6 +311,7 @@ configuration file. | SYNTH_RETIME_MODULES| *This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion # 8080.| | | SYNTH_SKIP_KEEP| Only meaningful together with SYNTH_CHECKPOINT. When set, signals that the supplied checkpoint is still canonical RTLIL (coarse synth and `keep_hierarchy` have not been run yet), so synth.tcl runs the full coarse+fine synthesis flattened. When unset and SYNTH_CHECKPOINT is used, synth.tcl assumes the checkpoint already has coarse synth + `keep_hierarchy` done and resumes from `coarse:fine`.| 0| | SYNTH_SLANG_ARGS| Additional arguments passed to the slang frontend during synthesis.| | +| SYNTH_USE_SYN| If set to 1, run synthesis using the "syn" tool built into OpenROAD (the synth_syn.tcl flow) instead of the default Yosys-based flow. Defaults to 0 (Yosys flow).| 0| | SYNTH_WRAPPED_ADDERS| Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.| | | SYNTH_WRAPPED_MULTIPLIERS| Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.| | | SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | @@ -349,6 +350,7 @@ configuration file. - [PRE_SYNTH_TCL](#PRE_SYNTH_TCL) - [SDC_FILE](#SDC_FILE) - [SDC_GUT](#SDC_GUT) +- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [SLANG_PLUGIN_PATH](#SLANG_PLUGIN_PATH) - [SYNTH_ARGS](#SYNTH_ARGS) - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES) @@ -371,6 +373,7 @@ configuration file. - [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES) - [SYNTH_SKIP_KEEP](#SYNTH_SKIP_KEEP) - [SYNTH_SLANG_ARGS](#SYNTH_SLANG_ARGS) +- [SYNTH_USE_SYN](#SYNTH_USE_SYN) - [SYNTH_WRAPPED_ADDERS](#SYNTH_WRAPPED_ADDERS) - [SYNTH_WRAPPED_MULTIPLIERS](#SYNTH_WRAPPED_MULTIPLIERS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) diff --git a/flow/Makefile b/flow/Makefile index 1bb45047a4..a6759a87f9 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -404,7 +404,11 @@ floorplan_to_place: $(RESULTS_DIR)/1_synth.odb $(RESULTS_DIR)/1_synth.sdc # ============================================================================== +ifeq ($(SYNTH_USE_SYN),1) +$(eval $(call do-step,1_synth,$(VERILOG_FILES) $(SDC_FILE) $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_syn)) +else $(eval $(call do-step,1_synth,$(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_2_yosys.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_odb)) +endif $(RESULTS_DIR)/1_synth.sdc: $(RESULTS_DIR)/1_synth.odb diff --git a/flow/designs/asap7/aes/config.mk b/flow/designs/asap7/aes/config.mk index 8eb7038a73..c254c713c5 100644 --- a/flow/designs/asap7/aes/config.mk +++ b/flow/designs/asap7/aes/config.mk @@ -6,8 +6,6 @@ export DESIGN_NICKNAME = aes export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export ABC_AREA = 1 - export CORE_UTILIZATION = 70 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 @@ -27,3 +25,4 @@ else ifeq ($(FLOW_VARIANT),combine) $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v endif +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/asap7/aes/rules-base.json b/flow/designs/asap7/aes/rules-base.json index 5d36509e04..87ff6f59df 100644 --- a/flow/designs/asap7/aes/rules-base.json +++ b/flow/designs/asap7/aes/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "3882365f5e814a21a600274234b3a087270968d4", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "a04d44da52dba7d4a701d80927ba32d1d89ef9a1", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/asap7/aes_lvt/config.mk b/flow/designs/asap7/aes_lvt/config.mk index 3f210c389b..aa5a147286 100644 --- a/flow/designs/asap7/aes_lvt/config.mk +++ b/flow/designs/asap7/aes_lvt/config.mk @@ -18,4 +18,4 @@ export ASAP7_USE_VT = LVT export RECOVER_POWER = 100 - +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json index 57d3b5a17a..946c1a9d6b 100644 --- a/flow/designs/asap7/aes_lvt/rules-base.json +++ b/flow/designs/asap7/aes_lvt/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "7cb97d6d20f0fb4831af6dc20aea1d411aecc09a", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "d84684a5256bf993bde8bccdff31af8237663019", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json index 519f25d02c..a9d7e0917a 100644 --- a/flow/designs/asap7/gcd-ccs/rules-base.json +++ b/flow/designs/asap7/gcd-ccs/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "7250dc152c2381ac020b86c78a5191b1c336244b", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "a954b979a1a0eff89ed870fa50d202847b6807bf", + "value": "N/A", "compare": "==", "level": "warning" }, @@ -38,7 +38,7 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -79.2, + "value": -90.0, "compare": ">=" }, "cts__timing__setup__tns": { diff --git a/flow/designs/asap7/gcd/config.mk b/flow/designs/asap7/gcd/config.mk index c98498e7a8..0f8de35b61 100644 --- a/flow/designs/asap7/gcd/config.mk +++ b/flow/designs/asap7/gcd/config.mk @@ -16,3 +16,4 @@ export PLACE_DENSITY = 0.35 # few last gasp iterations export SKIP_LAST_GASP ?= 1 +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json index 58770d2029..0bbfbf8dc7 100644 --- a/flow/designs/asap7/gcd/rules-base.json +++ b/flow/designs/asap7/gcd/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "9b1daddbf16520e983085be7f06a02bc2fc2e27a", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "2d3fbf9f1b7357c0cadb1e193d984ae458d68fa8", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/asap7/jpeg/config.mk b/flow/designs/asap7/jpeg/config.mk index 04e7fb1ca9..831e1d4150 100644 --- a/flow/designs/asap7/jpeg/config.mk +++ b/flow/designs/asap7/jpeg/config.mk @@ -15,3 +15,4 @@ export PLACE_DENSITY = 0.75 export TNS_END_PERCENT = 100 +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json index ca27aae59b..44bfc463fb 100644 --- a/flow/designs/asap7/jpeg/rules-base.json +++ b/flow/designs/asap7/jpeg/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "b67ad398424800920e8203a11987e51a89b89070", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "d045877b85c5a9e18d5284e8ad3a41dcbc5f3f11", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk index f09ae0d4bb..da51b9caaf 100644 --- a/flow/designs/asap7/jpeg_lvt/config.mk +++ b/flow/designs/asap7/jpeg_lvt/config.mk @@ -18,3 +18,4 @@ export RECOVER_POWER = 100 export ASAP7_USE_VT = LVT +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json index e7d684b889..1828e18feb 100644 --- a/flow/designs/asap7/jpeg_lvt/rules-base.json +++ b/flow/designs/asap7/jpeg_lvt/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "c46712834957de101139bda123c9da786f05b392", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "8c44353e931d56077e9f64190819c1fe10a05909", + "value": "N/A", "compare": "==", "level": "warning" }, @@ -90,11 +90,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -30.0, + "value": -63.9, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -303.0, + "value": -514.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json index 66e03a5a6e..0886b8fe76 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json +++ b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json @@ -1,6 +1,6 @@ { "synth__canonical_netlist__hash": { - "value": "855cc88198fc9faaf17317eaea4a3a07a4340d1d", + "value": "58bf274dad2592154068ebaf8f3893ccf8b388fa", "compare": "==", "level": "warning" }, @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -230.0, + "value": -2770.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index d340068a4a..85f2a39643 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -1,6 +1,6 @@ { "synth__canonical_netlist__hash": { - "value": "48ea06f839af2a2b1eaada6c74e256cfe1064972", + "value": "6539c6f38d2e14aa6b73a233552bb9e77150c29e", "compare": "==", "level": "warning" }, diff --git a/flow/designs/ihp-sg13g2/aes/config.mk b/flow/designs/ihp-sg13g2/aes/config.mk index 5acb53d84d..269fa64602 100644 --- a/flow/designs/ihp-sg13g2/aes/config.mk +++ b/flow/designs/ihp-sg13g2/aes/config.mk @@ -14,3 +14,5 @@ export TNS_END_PERCENT = 100 export USE_FILL = 1 export REMOVE_ABC_BUFFERS = 1 + +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index 1ee4ac2f8b..8f40b47a23 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "03f345300073bffe008c28ae418579c55a61a047", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "9ed4fbb1904f7531317bb9162ca084ebe650f588", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/ihp-sg13g2/gcd/config.mk b/flow/designs/ihp-sg13g2/gcd/config.mk index fc554fb8f8..a3d8798bbc 100644 --- a/flow/designs/ihp-sg13g2/gcd/config.mk +++ b/flow/designs/ihp-sg13g2/gcd/config.mk @@ -12,3 +12,4 @@ export TNS_END_PERCENT = 100 export SWAP_ARITH_OPERATORS = 1 export OPENROAD_HIERARCHICAL = 1 +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/ihp-sg13g2/gcd/rules-base.json b/flow/designs/ihp-sg13g2/gcd/rules-base.json index cb9c2aa47d..67d871075a 100644 --- a/flow/designs/ihp-sg13g2/gcd/rules-base.json +++ b/flow/designs/ihp-sg13g2/gcd/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "5a518ec61d78294e2e31f7564caba70a2e603a8b", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "3fd7066325a56dedbd71ff32ffc04a42a6888885", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index aadab0de16..40d1f0c119 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -1,6 +1,6 @@ { "synth__canonical_netlist__hash": { - "value": "6a79c1ff7404b566e96c52493d7eec2316d12f6a", + "value": "343adb65c551c257442500e3d05ced3bcc4adf88", "compare": "==", "level": "warning" }, diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json index 3eb023fcba..b40601e98c 100644 --- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json +++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json @@ -86,7 +86,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 109, + "value": 121, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/nangate45/aes/rules-base.json b/flow/designs/nangate45/aes/rules-base.json index d0029ea200..49b50f11d4 100644 --- a/flow/designs/nangate45/aes/rules-base.json +++ b/flow/designs/nangate45/aes/rules-base.json @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -0.167, + "value": -0.362, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json index 80a9eb92cd..079e71af6a 100644 --- a/flow/designs/nangate45/ariane133/rules-base.json +++ b/flow/designs/nangate45/ariane133/rules-base.json @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -576.0, + "value": -585.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 9d2fa02777..397e977054 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -19.1, + "value": -20.2, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index 6397935139..5ce196d6d5 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -1.23, + "value": -1.75, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/dynamic_node/config.mk b/flow/designs/nangate45/dynamic_node/config.mk index 3e514eccf8..42a289122e 100644 --- a/flow/designs/nangate45/dynamic_node/config.mk +++ b/flow/designs/nangate45/dynamic_node/config.mk @@ -15,3 +15,4 @@ export TNS_END_PERCENT = 100 export SWAP_ARITH_OPERATORS = 1 export OPENROAD_HIERARCHICAL = 1 +export SYNTH_USE_SYN = 1 diff --git a/flow/designs/nangate45/dynamic_node/rules-base.json b/flow/designs/nangate45/dynamic_node/rules-base.json index 6fee368470..7bfbb31540 100644 --- a/flow/designs/nangate45/dynamic_node/rules-base.json +++ b/flow/designs/nangate45/dynamic_node/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "2427a81238731cb7068ba9ca3da18ec2837ebf31", + "value": "N/A", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "4617e66bebd8728c158a91b4760b8d4ca0bb2114", + "value": "N/A", "compare": "==", "level": "warning" }, diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index 5e95636eb2..b16069bdef 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -485.0, + "value": -502.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -479.0, + "value": -507.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 044be6a8aa..91eb064a45 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -146.0, + "value": -157.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -126.0, + "value": -143.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json index 134736e0e2..5b67339d09 100644 --- a/flow/designs/sky130hd/chameleon/rules-base.json +++ b/flow/designs/sky130hd/chameleon/rules-base.json @@ -54,7 +54,7 @@ "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 196, + "value": 200, "compare": "<=" }, "globalroute__timing__setup__ws": { diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index c8f2846085..16ab2423db 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -88.8, + "value": -89.0, "compare": ">=" }, "globalroute__timing__hold__ws": { diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json index bbf97b08b7..93e736fb2a 100644 --- a/flow/designs/sky130hd/jpeg/rules-base.json +++ b/flow/designs/sky130hd/jpeg/rules-base.json @@ -54,7 +54,7 @@ "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 100, + "value": 102, "compare": "<=" }, "globalroute__timing__setup__ws": { @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -111.0, + "value": -113.0, "compare": ">=" }, "globalroute__timing__hold__ws": { diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index 051d2b461c..c24967d4f6 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -54,7 +54,7 @@ "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 1333, + "value": 1364, "compare": "<=" }, "globalroute__timing__setup__ws": { @@ -82,7 +82,7 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna_diodes_count": { diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index ec2ef0be19..437daa32fe 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -300.0, + "value": -304.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -167.0, + "value": -169.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index 0f8405e64e..3e6641d4f8 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -23.4, + "value": -43.4, "compare": ">=" }, "globalroute__timing__hold__ws": { diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index 73af5f9450..73a8cd29f9 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -62,7 +62,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -134.0, + "value": -142.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -94,7 +94,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -20.9, + "value": -26.5, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/scripts/synth_odb.tcl b/flow/scripts/synth_odb.tcl index d6f53cda3e..63bdc98cda 100644 --- a/flow/scripts/synth_odb.tcl +++ b/flow/scripts/synth_odb.tcl @@ -1,4 +1,4 @@ -utl::set_metrics_stage "floorplan__{}" +utl::set_metrics_stage "synth__{}" source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables synth load_design 1_2_yosys.v 1_2_yosys.sdc @@ -24,6 +24,9 @@ source_step_tcl PRE SYNTH # asap7/jpeg_lvt, asap7/swerv_wrapper, nangate45/ariane133). log_cmd eliminate_dead_logic +report_design_area +report_design_area_metrics + source_step_tcl POST SYNTH orfs_write_db $::env(RESULTS_DIR)/1_synth.odb # Canonicalize 1_synth.sdc. The original SDC_FILE provided by diff --git a/flow/scripts/synth_syn.tcl b/flow/scripts/synth_syn.tcl new file mode 100644 index 0000000000..e5706d3faf --- /dev/null +++ b/flow/scripts/synth_syn.tcl @@ -0,0 +1,76 @@ +utl::set_metrics_stage "synth__{}" +source $::env(SCRIPTS_DIR)/load.tcl +erase_non_stage_variables synth + +source_env_var_if_exists PLATFORM_TCL +source $::env(SCRIPTS_DIR)/read_liberty.tcl + +read_lef $::env(TECH_LEF) +read_lef $::env(SC_LEF) +if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { + foreach lef $::env(ADDITIONAL_LEFS) { + read_lef $lef + } +} +if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { + set_dont_use $::env(DONT_USE_CELLS) +} + +# Setup verilog include directories +set vIdirsArgs "" +if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { + foreach dir $::env(VERILOG_INCLUDE_DIRS) { + lappend vIdirsArgs "-I$dir" + } + set vIdirsArgs [join $vIdirsArgs] +} + +set elaborate_args [list \ + -D SYNTHESIS --compat=vcs --ignore-assertions --no-implicit-memories --top $::env(DESIGN_NAME) \ + {*}$vIdirsArgs {*}[env_var_or_empty VERILOG_DEFINES]] + +lappend elaborate_args {*}$::env(VERILOG_FILES) + +# Apply top-level parameters +dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] { + lappend elaborate_args -G "$key=$value" +} + +# Apply module blackboxing based on module names as they appear +# in the input, that is before any module name mangling done +# by elaboration and synthesis +if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { + foreach m $::env(SYNTH_BLACKBOXES) { + lappend elaborate_args --blackboxed-module "$m" + } +} + +lappend elaborate_args {*}$::env(SYNTH_SLANG_ARGS) + +# If the sources are solely .v files, enable Verilog compatibility +set has_non_v_files false +foreach fn $::env(VERILOG_FILES) { + if { [file extension [string trim $fn]] != ".v" } { + set has_non_v_files true + } +} +if { !$has_non_v_files } { + lappend elaborate_args --std=1364-2005 +} + +sv_elaborate {*}$elaborate_args +syn::stats + +synthesize + +read_sdc $::env(SDC_FILE) +repair_design -pre_placement + +report_metrics 1 "synth" false false + +orfs_write_db $::env(RESULTS_DIR)/1_synth.odb +# Canonicalize 1_synth.sdc. The original SDC_FILE provided by +# the user could have dependencies, such as sourcing util.tcl, +# which are read in here and a canonicalized version is written +# out by OpenSTA that has no dependencies. +orfs_write_sdc $::env(RESULTS_DIR)/1_synth.sdc diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 369ed53179..bd34b1bcaf 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -1196,6 +1196,7 @@ "default": 0, "description": "If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.\n", "stages": [ + "synth", "floorplan", "place", "cts", @@ -1366,6 +1367,13 @@ "synth" ] }, + "SYNTH_USE_SYN": { + "default": 0, + "description": "If set to 1, run synthesis using the \"syn\" tool built into OpenROAD (the synth_syn.tcl flow) instead of the default Yosys-based flow. Defaults to 0 (Yosys flow).\n", + "stages": [ + "synth" + ] + }, "SYNTH_WRAPPED_ADDERS": { "description": "Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.\n", "stages": [ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 6eee57b4c2..bbf1398f4d 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -115,6 +115,7 @@ SKIP_REPORT_METRICS: If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds. stages: + - synth - floorplan - place - cts @@ -180,6 +181,14 @@ SYNTH_HIERARCHICAL: stages: - synth default: 0 +SYNTH_USE_SYN: + description: > + If set to 1, run synthesis using the "syn" tool built into OpenROAD + (the synth_syn.tcl flow) instead of the default Yosys-based flow. + Defaults to 0 (Yosys flow). + stages: + - synth + default: 0 SYNTH_MEMORY_MAX_BITS: description: > Maximum number of bits for memory synthesis. diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index 6424712e27..fa54254809 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -245,22 +245,7 @@ def extract_metrics( # Synthesis # ========================================================================= - - # The new format (>= 0.57) with -hierarchy is: - # cells - extractTagFromFile( - "synth__design__instance__count__stdcell", - metrics_dict, - "^\\s+(\\d+)\\s+[-0-9.]+\\s+\\S+\\s+\\S+\\s+cells$", - rptPath + "/synth_stat.txt", - ) - - extractTagFromFile( - "synth__design__instance__area__stdcell", - metrics_dict, - "Chip area for (?:top )?module.*: +(\\S+)", - rptPath + "/synth_stat.txt", - ) + merge_jsons(logPath, metrics_dict, "1_*.json") # Netlist hashes: fingerprints of the canonical RTLIL (pre-ABC) and # the final post-synthesis Verilog so the rules-base.json check