diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
index af50c62b1e4..9a55fe3218b 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config
@@ -248,7 +248,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_PHY_V2 is not set
-# CONFIG_RT_USING_ADC is not set
+CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
@@ -269,8 +269,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_RPMSG is not set
# CONFIG_RT_USING_BLK is not set
-# CONFIG_RT_USING_VIRTIO is not set
+# CONFIG_RT_USING_REGULATOR is not set
+# CONFIG_RT_USING_POWER_SUPPLY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_CHERRYUSB is not set
# end of Device Drivers
@@ -584,6 +586,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# tools packages
#
# CONFIG_PKG_USING_VECTOR is not set
+# CONFIG_PKG_USING_SORCH is not set
+# CONFIG_PKG_USING_DICT is not set
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_MCOREDUMP is not set
# CONFIG_PKG_USING_EASYFLASH is not set
@@ -730,6 +734,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# CONFIG_PKG_USING_CHERRYECAT is not set
+# CONFIG_PKG_USING_EVENT_LOOP is not set
+# CONFIG_PKG_USING_THREAD_MANAGER is not set
# end of system packages
#
@@ -813,7 +819,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-# CONFIG_PKG_USING_MM32 is not set
+
+#
+# MM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set
+# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set
+# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set
+# end of MM32 HAL & SDK Drivers
#
# WCH HAL & SDK Drivers
@@ -878,9 +898,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
#
# NUVOTON Drivers
#
-# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
-# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
# end of NUVOTON Drivers
#
@@ -906,6 +924,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set
# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set
# end of FT32 HAL & SDK Drivers
+
+#
+# NOVOSNS Drivers
+#
+# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set
+# end of NOVOSNS Drivers
# end of HAL & SDK Drivers
#
@@ -1086,6 +1110,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
# CONFIG_PKG_USING_ISOTP_C is not set
# CONFIG_PKG_USING_IKUNLED is not set
# CONFIG_PKG_USING_INS5T8025 is not set
+# CONFIG_PKG_USING_IRUART is not set
# CONFIG_PKG_USING_ST7305 is not set
# CONFIG_PKG_USING_TM1668 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
@@ -1441,6 +1466,9 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_DMA=y
+CONFIG_BSP_USING_LPADC=y
+CONFIG_BSP_USING_LPADC1=y
+CONFIG_BSP_LPADC1_USING_DMA=y
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_USB is not set
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig
index 699499cf041..7f351c3580e 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig
@@ -26,6 +26,24 @@ menu "On-chip Peripheral Drivers"
bool "Enable DMA"
default n
+ menuconfig BSP_USING_LPADC
+ bool "Enable ADC"
+ default n
+
+ if BSP_USING_LPADC
+
+ config BSP_USING_LPADC1
+ bool "Enable LPADC1"
+ default n
+
+ config BSP_LPADC1_USING_DMA
+ bool "Enable LPADC1 DMA"
+ depends on BSP_USING_LPADC1
+ depends on BSP_USING_DMA
+ default n
+
+ endif
+
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/MCUX_Config.mex b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/MCUX_Config.mex
new file mode 100644
index 00000000000..fee765231f9
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/MCUX_Config.mex
@@ -0,0 +1,9092 @@
+
+
+
+ MIMXRT1189xxxxx
+ MIMXRT1189CVM8C
+ MIMXRT1180-EVK
+ ksdk2_0
+
+
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+
+
+ true
+ false
+
+ /*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ true
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\ No newline at end of file
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.c
new file mode 100644
index 00000000000..edd739e5077
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.c
@@ -0,0 +1,836 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v20.0
+processor: MIMXRT1189xxxxx
+package_id: MIMXRT1189CVM8C
+mcu_data: ksdk2_0
+processor_version: 26.03.10
+board: MIMXRT1180-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_misc.h"
+#include "fsl_dcdc.h"
+#include "fsl_pmu.h"
+#include "fsl_clock.h"
+#include "fsl_ele_base_api.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_FlexspiClockSafeConfig
+ * Description : FLEXSPI clock source safe configuration weak function.
+ * Called before clock source configuration.
+ * Note : Users need override this function to change FLEXSPI clock source to stable source when executing
+ * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source
+ * to a stable clock to avoid instruction/data fetch issue during clock updating.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_SetFlexspiClock
+ * Description : This function should be overridden if executing code on FLEXSPI memory(XIP).
+ * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
+ * After the clock is changed and stable, move back to run on FLEXSPI.
+ * Param base : FLEXSPI peripheral base address.
+ * Param src : FLEXSPI clock source.
+ * Param divider : FLEXSPI clock divider.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EdgeLock_SetClock
+ * Description : Set EdgeLock clock via safe method
+ * Note : It requires specific sequence to change edgelock clock source,
+ * otherwise the soc behavior is unpredictable.
+ *END**************************************************************************/
+__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DCDC_SetVoltage
+ * Description : Set DCDC voltage via safe method
+ * Note : It requires specific sequence to change DCDC voltage when GDET
+ * is enabled, otherwise the soc behavior is unpredictable.
+ *END**************************************************************************/
+__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage)
+{
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ACMP_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: ADC1_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: ADC2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: ARM_PLL_CLK.outFreq, value: 792 MHz}
+- {id: ASRC_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: ECAT_CLK_ROOT.outFreq, value: 100 MHz}
+- {id: ECAT_PORT0_REF_CLK.outFreq, value: 50 MHz}
+- {id: ECAT_PORT1_REF_CLK.outFreq, value: 50 MHz}
+- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz}
+- {id: ENET_REFCLK_ROOT.outFreq, value: 125 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz}
+- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2160/11 MHz}
+- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPSPI0102_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: LPSPI0304_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: LPSPI0506_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: M33_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
+- {id: M7_CLK_ROOT.outFreq, value: 792 MHz}
+- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
+- {id: MAC0_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: MAC1_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: MAC2_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: MAC3_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: MAC4_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: MIC_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: NETC_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: NETC_PORT0_REF_CLK.outFreq, value: 50 MHz}
+- {id: NETC_PORT1_REF_CLK.outFreq, value: 50 MHz}
+- {id: NETC_PORT2_REF_CLK.outFreq, value: 50 MHz}
+- {id: NETC_PORT3_REF_CLK.outFreq, value: 50 MHz}
+- {id: NETC_PORT4_REF_CLK.outFreq, value: 50 MHz}
+- {id: OSC_24M.outFreq, value: 24 MHz}
+- {id: OSC_32K.outFreq, value: 32.768 kHz}
+- {id: OSC_RC_24M.outFreq, value: 24 MHz}
+- {id: OSC_RC_400M.outFreq, value: 400 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 200 MHz}
+- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz}
+- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz}
+- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz}
+- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
+- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
+- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
+- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
+- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
+- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
+- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
+- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz}
+- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 2880/11 MHz}
+- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 4320/11 MHz}
+- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 480 MHz}
+- {id: TMR_1588_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: TMR_1588_REF_CLK.outFreq, value: 240 MHz}
+- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 396 MHz}
+- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz}
+settings:
+- {id: AONDomainVoltage, value: OD}
+- {id: CoreClockRootsInitializationConfig, value: selectedCore}
+- {id: SOCDomainVoltage, value: OD}
+- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
+- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
+- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '2', locked: true}
+- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true}
+- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true}
+- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
+- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455', locked: true}
+- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
+- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
+- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'}
+- {id: ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale, value: '33', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale, value: '18', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale, value: '22', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale, value: '18', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '18'}
+- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
+- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true}
+- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
+- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true}
+- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M}
+- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK}
+- {id: CCM.CLOCK_ROOT22.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK}
+- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true}
+- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true}
+- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true}
+- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT27.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT28.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT29.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT30.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT31.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT32.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT36.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK}
+- {id: CCM.CLOCK_ROOT37.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK}
+- {id: CCM.CLOCK_ROOT38.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK}
+- {id: CCM.CLOCK_ROOT39.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT40.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT41.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK}
+- {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK}
+- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '5', locked: true}
+- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_CLK}
+- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '5', locked: true}
+- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT49.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT50.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
+- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT53.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT55.DIV.scale, value: '10', locked: true}
+- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT65.DIV.scale, value: '12', locked: true}
+- {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK}
+- {id: CCM.CLOCK_ROOT66.DIV.scale, value: '12', locked: true}
+- {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK}
+- {id: CCM.CLOCK_ROOT67.DIV.scale, value: '12', locked: true}
+- {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK}
+- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '12', locked: true}
+- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK}
+- {id: CCM.CLOCK_ROOT69.DIV.scale, value: '12', locked: true}
+- {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK}
+- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true}
+- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M}
+- {id: CCM.CLOCK_ROOT70.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT71.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT72.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT73.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240', locked: true}
+- {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_24M}
+- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+sources:
+- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq, value: 100 kHz}
+- {id: BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq, value: 200 kHz}
+- {id: BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq, value: 300 kHz}
+- {id: BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq, value: 400 kHz}
+- {id: BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq, value: 2 MHz}
+- {id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
+ .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+ .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+ };
+
+const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = {
+ .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */
+ .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */
+ .ss = NULL, /* Spread spectrum parameter */
+ .ssEnable = false, /* Enable spread spectrum or not */
+ };
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = {
+ .mfd = 268435455, /* Denominator of spread spectrum */
+ .ss = NULL, /* Spread spectrum parameter */
+ .ssEnable = false, /* Enable spread spectrum or not */
+ };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ clock_root_config_t rootCfg = {0};
+
+ /* Init OSC RC 400M */
+ CLOCK_OSC_EnableOscRc400M();
+
+ /* Switch both core to OscRC400M first */
+#if (__CORTEX_M == 7)
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+#if (__CORTEX_M == 33)
+ /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4
+ of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M)
+ firstly as common setting */
+ rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+#if (__CORTEX_M == 7)
+ DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V);
+ DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V);
+ /* FBB need to be enabled in OverDrive(OD) mode */
+ PMU_EnableFBB(ANADIG_PMU, true);
+#endif
+
+ /* Config CLK_1M */
+ CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+ /* Init OSC RC 24M */
+ CLOCK_OSC_EnableOscRc24M(true);
+
+ /* Config OSC 24M */
+ ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+ /* Wait for 24M OSC to be stable. */
+ while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+ (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
+ {
+ }
+
+ /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid
+ instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */
+ BOARD_FlexspiClockSafeConfig();
+
+ /* Init Arm Pll. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+
+ /* Init Sys Pll1. */
+ CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
+
+#ifndef USE_SDRAM
+ /* Init Sys Pll2. */
+ CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+ /* Init System Pll2 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+#endif
+ /* Init System Pll2 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+ /* Init System Pll2 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+ /* Init System Pll2 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+#ifndef USE_HYPERRAM
+ /* Init Sys Pll3. */
+ CLOCK_InitSysPll3();
+#endif
+ /* Init System Pll3 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22);
+ /* Init System Pll3 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33);
+#ifndef USE_HYPERRAM
+ /* Init System Pll3 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22);
+#endif
+ /* Init System Pll3 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18);
+
+ /* Bypass Audio Pll. */
+ CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+ /* DeInit Audio Pll. */
+ CLOCK_DeinitAudioPll();
+
+ /* Module clock root configurations. */
+ /* Configure M7 using ARM_PLL_CLK */
+#if (__CORTEX_M == 7)
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+ /* Configure M33 using SYS_PLL3_CLK */
+#if (__CORTEX_M == 33)
+ rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+ /* Configure EDGELOCK using OSC_RC_400M */
+ EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2);
+
+ /* Configure BUS_AON using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg);
+
+ /* Configure BUS_WAKEUP using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg);
+
+ /* Configure WAKEUP_AXI using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg);
+
+ /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg);
+
+ /* Configure M33_SYSTICK using OSC_24M */
+#if (__CORTEX_M == 33)
+ rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut;
+ rootCfg.div = 240;
+ CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg);
+#endif
+
+ /* Configure M7_SYSTICK using OSC_24M */
+#if (__CORTEX_M == 7)
+ rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut;
+ rootCfg.div = 240;
+ CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+ /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
+
+ /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 5;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
+
+ /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg);
+
+ /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg);
+
+ /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg);
+
+ /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg);
+
+ /* Configure TPM2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg);
+
+ /* Configure TPM4 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg);
+
+ /* Configure TPM5 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg);
+
+ /* Configure TPM6 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg);
+
+ /* Configure GPT1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
+
+ /* Configure GPT2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
+
+ /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */
+ BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0, 3U);
+
+ /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */
+#ifndef USE_HYPERRAM
+ BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 2U);
+#endif
+
+ /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg);
+
+ /* Configure CAN1 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 6;
+ CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
+
+ /* Configure CAN2 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 6;
+ CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
+
+ /* Configure CAN3 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 6;
+ CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
+
+ /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg);
+
+ /* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg);
+
+ /* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg);
+
+ /* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg);
+
+ /* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg);
+
+ /* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg);
+
+ /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg);
+
+ /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg);
+
+ /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg);
+
+ /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
+ rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
+
+ /* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */
+ rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg);
+
+ /* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */
+ rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg);
+
+ /* Configure I3C1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg);
+
+ /* Configure I3C2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg);
+
+ /* Configure USDHC1 using SYS_PLL2_PFD2_CLK */
+ rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
+
+ /* Configure USDHC2 using SYS_PLL2_PFD2_CLK */
+ rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
+
+ /* Configure SEMC using SYS_PLL1_CLK */
+#ifndef USE_SDRAM
+ rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll1Out;
+ rootCfg.div = 5;
+ CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
+#endif
+
+ /* Configure ADC1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
+
+ /* Configure ADC2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
+
+ /* Configure ACMP using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
+
+ /* Configure ECAT using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 5;
+ CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg);
+
+ /* Configure ENET using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg);
+
+ /* Configure TMR_1588 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg);
+
+ /* Configure NETC using SYS_PLL3_PFD3_CLK */
+ rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg);
+
+ /* Configure MAC0 using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg);
+
+ /* Configure MAC1 using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg);
+
+ /* Configure MAC2 using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg);
+
+ /* Configure MAC3 using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg);
+
+ /* Configure MAC4 using SYS_PLL1_DIV2_CLK */
+ rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2;
+ rootCfg.div = 10;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg);
+
+ /* Configure SAI1 using PLL_AUDIO_CLK */
+ rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxAudioPllOut;
+ rootCfg.div = 12;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
+
+ /* Configure SAI2 using PLL_AUDIO_CLK */
+ rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxAudioPllOut;
+ rootCfg.div = 12;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
+
+ /* Configure SAI3 using PLL_AUDIO_CLK */
+ rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxAudioPllOut;
+ rootCfg.div = 12;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
+
+ /* Configure SAI4 using PLL_AUDIO_CLK */
+ rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut;
+ rootCfg.div = 12;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
+
+ /* Configure SPDIF using PLL_AUDIO_CLK */
+ rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut;
+ rootCfg.div = 12;
+ CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
+
+ /* Configure ASRC using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
+
+ /* Configure MIC using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
+
+ /* Configure CKO1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
+
+ /* Configure CKO2 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
+
+ /* Set SAI MCLK clock source. */
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0);
+
+ /* Set ECAT PORT Ref clock source. */
+ BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK;
+ BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK;
+
+ /* Set NETC PORT Ref clock source. */
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK;
+
+ /* Set TMR 1588 Ref clock source. */
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK;
+
+#if (__CORTEX_M == 7)
+ SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
+#else
+ SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33);
+#endif
+}
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.h
new file mode 100644
index 00000000000..c93b94e2bf7
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/clock_config.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if __CORTEX_M == 7
+ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */
+#else
+ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */
+#endif
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
+#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */
+#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */
+#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
+#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */
+#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */
+#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */
+#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */
+#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
+#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
+#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */
+#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */
+#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */
+#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */
+#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */
+#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */
+#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */
+#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */
+#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */
+#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */
+#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */
+#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */
+#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */
+#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */
+#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */
+#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */
+#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */
+#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */
+#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */
+#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */
+#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */
+#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */
+#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
+#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */
+#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */
+#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */
+#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
+#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.c
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index 00000000000..e15d4f9f149
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.c
@@ -0,0 +1,533 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: MIMXRT1189xxxxx
+package_id: MIMXRT1189CVM8C
+mcu_data: ksdk2_0
+processor_version: 26.03.10
+board: MIMXRT1180-EVK
+functionalGroups:
+- name: BOARD_InitPeripherals
+ UUID: e05a8704-a0aa-436e-89f3-59a6570dd2ff
+ called_from_default_init: true
+ selectedCore: cm33
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system'
+- global_system_definitions:
+ - user_definitions: ''
+ - user_includes: ''
+ - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common'
+- global_USART_CMSIS_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common'
+- global_gpio_adapter_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+#ifdef BSP_LPADC1_USING_DMA
+/***********************************************************************************************************************
+ * DMA4 initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'DMA4'
+- type: 'edma4'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'edma4_2.9.0'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'DMA4'
+- config_sets:
+ - fsl_edma:
+ - dmamux_devices: []
+ - common_settings:
+ - vars: []
+ - enableHaltOnError: 'true'
+ - enableDebugMode: 'false'
+ - enableRoundRobinArbitration: 'fixedPriority'
+ - enableGlobalChannelLink: 'true'
+ - enableMasterIdReplication: 'false'
+ - dma_table:
+ - 0: []
+ - edma_channels:
+ - 0:
+ - apiMode: 'trans'
+ - edma_channel:
+ - channel_prefix_id: 'CH0'
+ - uid: '1780195171347'
+ - eDMAn: '0'
+ - eDMA_source: 'kDma4RequestMuxADC1Request0'
+ - init_channel_priority: 'false'
+ - edma_channel_Preemption:
+ - enableChannelPreemption: 'false'
+ - enablePreemptAbility: 'false'
+ - channelPriority: '0'
+ - initMemoryAttributes: 'false'
+ - memAttributes:
+ - writeCache: 'buffer'
+ - readCache: 'buffer'
+ - setChannelSwapSize: 'noInit'
+ - signExtension: 'noInit'
+ - setChannelAccessType: 'noInit'
+ - masterIdReplicationEnable: 'noInit'
+ - securityLevel: 'noInit'
+ - protectionLevel: 'noInit'
+ - enable_custom_name: 'false'
+ - resetChannel: 'false'
+ - enableChannelRequest: 'true'
+ - enableAsyncRequest: 'false'
+ - enableAutoStop: 'false'
+ - tcd_pool_enable: 'false'
+ - tcd_settings:
+ - tcd_size: '1'
+ - tcd_memory_ptr_id: 'default'
+ - transfer_config:
+ - 0:
+ - uid: '1780716022754'
+ - tcdID: 'CH0_TRANSFER0'
+ - ssize: 'kEDMA_TransferSize4Bytes'
+ - saddr_expr: '&ADC1->RESFIFO[0]'
+ - saddr_def: ''
+ - soff: '0'
+ - soff_def: ''
+ - smod: 'kEDMA_ModuloDisable'
+ - dsize: 'kEDMA_TransferSize4Bytes'
+ - daddr_expr: '&adc_result[0]'
+ - daddr_def: 'AT_NONCACHEABLE_SECTION_ALIGN_INIT(extern uint32_t adc_result[], sizeof(uint32_t));'
+ - doff: 'sizeof(uint32_t)'
+ - doff_def: ''
+ - dmod: 'kEDMA_ModuloDisable'
+ - nbytes: '4'
+ - MLconfig:
+ - offsetType: 'disabled'
+ - mloff: '0'
+ - enableChannelLinkMinor: 'false'
+ - linkedChannelMinor: '1780195171347'
+ - citer: '7'
+ - slast: '0'
+ - dlast: '-28'
+ - enableChannelLinkMajor: 'false'
+ - linkedChannelMajor: '1780195171347'
+ - submitTransfer: 'true'
+ - loopTransfer: 'false'
+ - no_init_uid: '1780195171376'
+ - init_callback: 'true'
+ - callback_function: 'DMA_Callback'
+ - callback_user_data: ''
+ - channel_enabled_interrupts: ''
+ - interrupt_channel:
+ - IRQn: 'DMA4_CH0_CH1_CH32_CH33_IRQn'
+ - enable_priority: 'false'
+ - priority: '0'
+ - errInterruptConfig:
+ - enableErrInterrupt: 'false'
+ - errorInterrupt:
+ - IRQn: 'DMA4_ERROR_IRQn'
+ - enable_interrrupt: 'enabled'
+ - enable_priority: 'false'
+ - priority: '0'
+ - enable_custom_name: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+edma_config_t DMA4_config = {
+ .enableMasterIdReplication = false,
+ .enableGlobalChannelLink = true,
+ .enableHaltOnError = true,
+ .enableDebugMode = false,
+ .enableRoundRobinArbitration = false
+};
+/* Tansactional transfer configurations */
+edma_transfer_config_t DMA4_CH0_Transfers_config[1];
+edma_handle_t DMA4_CH0_Handle;
+
+static void DMA4_init(void)
+{
+ status_t status;
+ (void)status;
+
+ /* Channel CH0 initialization */
+ /* Set the kDma4RequestMuxADC1Request0 request */
+ EDMA_SetChannelMux(DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL, DMA4_CH0_DMA_REQUEST);
+ /* Create the eDMA DMA4_CH0_Handle handle */
+ EDMA_CreateHandle(&DMA4_CH0_Handle, DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL);
+ /* DMA callback initialization */
+ EDMA_SetCallback(&DMA4_CH0_Handle, DMA_Callback, NULL);
+ /* DMA4 transfer CH0_TRANSFER0 configuration */
+ EDMA_PrepareTransferConfig(&DMA4_CH0_TRANSFER0_CONFIG, (void *) &ADC1->RESFIFO[0], 1 << kEDMA_TransferSize4Bytes, 0, (void *) &adc_result[0], 1 << kEDMA_TransferSize4Bytes, sizeof(uint32_t), 4U, 28U);
+ DMA4_CH0_TRANSFER0_CONFIG.dstMajorLoopOffset = -28;
+ /* DMA4 transfer CH0_TRANSFER0 submit */
+ status = EDMA_SubmitTransfer(&DMA4_CH0_Handle, &DMA4_CH0_TRANSFER0_CONFIG);
+ assert(status == kStatus_Success);
+ /* DMA4 hardware channel 0 request auto stop */
+ EDMA_EnableAutoStopRequest(DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL, false);
+ /* DMA4 channel 0 peripheral request */
+ EDMA_EnableChannelRequest(DMA4_DMA_BASEADDR, DMA4_CH0_DMA_CHANNEL);
+}
+#endif
+/***********************************************************************************************************************
+ * CM33_NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'CM33_NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'CM33_NVIC'
+- config_sets:
+ - nvic:
+ - interrupt_table:
+ - 0: []
+ - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void CM33_NVIC_init(void)
+{
+} */
+
+/***********************************************************************************************************************
+ * LPUART1 initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'LPUART1'
+- type: 'lpuart'
+- mode: 'polling'
+- custom_name_enabled: 'false'
+- type_id: 'lpuart_2.11.0'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'LPUART1'
+- config_sets:
+ - lpuartConfig_t:
+ - lpuartConfig:
+ - clockSource: 'LpuartClock'
+ - lpuartSrcClkFreq: 'ClocksTool_DefaultInit'
+ - baudRate_Bps: '115200'
+ - parityMode: 'kLPUART_ParityDisabled'
+ - dataBitsCount: 'kLPUART_EightDataBits'
+ - isMsb: 'false'
+ - stopBitCount: 'kLPUART_OneStopBit'
+ - enableMatchAddress1: 'false'
+ - matchAddress1: '0'
+ - enableMatchAddress2: 'false'
+ - matchAddress2: '0'
+ - txFifoWatermark: '0'
+ - rxFifoWatermark: '1'
+ - enableRxRTS: 'false'
+ - enableTxRTS: 'false'
+ - enableTxCTS: 'false'
+ - txCtsSource: 'kLPUART_CtsSourcePin'
+ - txCtsConfig: 'kLPUART_CtsSampleAtStart'
+ - txRtsPolarity: 'kLPUART_RtsPolarityLow'
+ - rtsWatermark: '0'
+ - rxIdleType: 'kLPUART_IdleTypeStartBit'
+ - rxIdleConfig: 'kLPUART_IdleCharacter1'
+ - enableTx: 'true'
+ - enableRx: 'true'
+ - inverseTxd: 'false'
+ - quick_selection: 'QuickSelection1'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const lpuart_config_t LPUART1_config = {
+ .baudRate_Bps = 115200UL,
+ .parityMode = kLPUART_ParityDisabled,
+ .dataBitsCount = kLPUART_EightDataBits,
+ .isMsb = false,
+ .stopBitCount = kLPUART_OneStopBit,
+ .txFifoWatermark = 0U,
+ .rxFifoWatermark = 1U,
+ .enableRxRTS = false,
+ .enableTxRTS = false,
+ .enableTxCTS = false,
+ .txCtsSource = kLPUART_CtsSourcePin,
+ .txCtsConfig = kLPUART_CtsSampleAtStart,
+ .txRtsPolarity = kLPUART_RtsPolarityLow,
+ .rtsWatermark = 0U,
+ .rxIdleType = kLPUART_IdleTypeStartBit,
+ .rxIdleConfig = kLPUART_IdleCharacter1,
+ .enableTx = true,
+ .enableRx = true,
+ .inverseTxd = false
+};
+
+static void LPUART1_init(void)
+{
+ LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
+}
+
+/***********************************************************************************************************************
+ * RGPIO4 initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'RGPIO4'
+- type: 'rgpio'
+- mode: 'GPIO'
+- custom_name_enabled: 'false'
+- type_id: 'rgpio_2.1.0'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'RGPIO4'
+- config_sets:
+ - fsl_gpio:
+ - interrupts:
+ - 0:
+ - enable_irq: 'false'
+ - gpio_interrupt:
+ - IRQn: 'GPIO4_IRQn'
+ - enable_interrrupt: 'enabled'
+ - enable_priority: 'false'
+ - priority: '0'
+ - enable_custom_name: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void RGPIO4_init(void)
+{
+} */
+
+#ifdef BSP_USING_LPADC
+/***********************************************************************************************************************
+ * ADC1 initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'ADC1'
+- type: 'lpadc'
+- mode: 'LPADC'
+- custom_name_enabled: 'false'
+- type_id: 'lpadc_2.8.1'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'ADC1'
+- config_sets:
+ - fsl_lpadc:
+ - lpadcConfig:
+ - clockSource: 'AsynchronousFunctionClock'
+ - clockSourceFreq: 'ClocksTool_DefaultInit'
+ - enableJustifiedLeft: 'false'
+ - enableInDozeMode: 'true'
+ - conversionAverageMode: 'kLPADC_ConversionAverage2'
+ - offsetCalibration: 'yes'
+ - autoCalibrate: 'true'
+ - enableAnalogPreliminary: 'false'
+ - powerUpDelay: '0x80'
+ - referenceVoltageSource: 'kLPADC_ReferenceVoltageAlt2'
+ - triggerPriorityPolicy: 'kLPADC_ConvPreemptImmediatelyNotAutoResumed'
+ - enableConvPause: 'false'
+ - convPauseDelay: '0'
+ - FIFO0Watermark: '0'
+ - FIFO1Watermark: '0'
+ - FIFO0WatermarkDMA: 'true'
+ - FIFO1WatermarkDMA: 'false'
+ - lpadcConvCommandConfig:
+ - 0:
+ - user_commandId: 'GRPA'
+ - commandId: '1'
+ - chainedNextCommandNumber: '2'
+ - sampleChannelMode: 'kLPADC_SampleChannelSingleEndSideA'
+ - sampleScaleMode: 'kLPADC_SampleFullScale'
+ - channelNumber: 'A.1_4'
+ - enableChannelB_b: 'false'
+ - channelBScaleMode_e: 'kLPADC_SampleFullScale'
+ - channelBNumber: 'B.1_0'
+ - enableAutoChannelIncrement: 'true'
+ - loopCount: '3'
+ - hardwareAverageMode: 'kLPADC_HardwareAverageCount1'
+ - sampleTimeMode: 'kLPADC_SampleTimeADCK3'
+ - hardwareCompareMode: 'kLPADC_HardwareCompareDisabled'
+ - hardwareCompareValueHigh: '0'
+ - hardwareCompareValueLow: '0'
+ - conversionResoultuionMode: 'kLPADC_ConversionResolutionHigh'
+ - enableWaitTrigger: 'true'
+ - 1:
+ - user_commandId: 'GRPB'
+ - commandId: '2'
+ - chainedNextCommandNumber: '0'
+ - sampleChannelMode: 'kLPADC_SampleChannelSingleEndSideB'
+ - sampleScaleMode: 'kLPADC_SampleFullScale'
+ - channelNumber: 'B.1_5'
+ - enableChannelB_b: 'false'
+ - channelBScaleMode_e: 'kLPADC_SampleFullScale'
+ - channelBNumber: 'B.1_0'
+ - enableAutoChannelIncrement: 'true'
+ - loopCount: '2'
+ - hardwareAverageMode: 'kLPADC_HardwareAverageCount1'
+ - sampleTimeMode: 'kLPADC_SampleTimeADCK3'
+ - hardwareCompareMode: 'kLPADC_HardwareCompareDisabled'
+ - hardwareCompareValueHigh: '0'
+ - hardwareCompareValueLow: '0'
+ - conversionResoultuionMode: 'kLPADC_ConversionResolutionHigh'
+ - enableWaitTrigger: 'false'
+ - lpadcConvTriggerConfig:
+ - 0:
+ - user_triggerId: 'TRIG'
+ - triggerId: '0'
+ - targetCommandId: '1'
+ - delayPower: '0'
+ - priority: 'false'
+ - channelAFIFOSelect: '0'
+ - channelBFIFOSelect: '0'
+ - enableHardwareTrigger: 'false'
+ - IRQ_cfg:
+ - interrupt_type: ''
+ - enable_irq: 'false'
+ - adc_interrupt:
+ - IRQn: 'ADC1_IRQn'
+ - enable_interrrupt: 'enabled'
+ - enable_priority: 'false'
+ - priority: '0'
+ - enable_custom_name: 'true'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const lpadc_config_t ADC1_config = {
+ .enableInDozeMode = true,
+ .conversionAverageMode = kLPADC_ConversionAverage2,
+ .enableAnalogPreliminary = false,
+ .powerUpDelay = 0x80UL,
+ .referenceVoltageSource = kLPADC_ReferenceVoltageAlt2,
+ .triggerPriorityPolicy = kLPADC_ConvPreemptImmediatelyNotAutoResumed,
+ .enableConvPause = false,
+ .convPauseDelay = 0UL,
+ .FIFO0Watermark = 0UL,
+ .FIFO1Watermark = 0UL
+};
+lpadc_conv_command_config_t ADC1_commandsConfig[2] = {
+ {
+ .sampleScaleMode = kLPADC_SampleFullScale,
+ .channelBScaleMode = kLPADC_SampleFullScale,
+ .sampleChannelMode = kLPADC_SampleChannelSingleEndSideA,
+ .channelNumber = 4U,
+ .channelBNumber = 0U,
+ .chainedNextCommandNumber = 2,
+ .enableChannelB = false,
+ .enableAutoChannelIncrement = true,
+ .loopCount = 3UL,
+ .hardwareAverageMode = kLPADC_HardwareAverageCount1,
+ .sampleTimeMode = kLPADC_SampleTimeADCK3,
+ .hardwareCompareMode = kLPADC_HardwareCompareDisabled,
+ .hardwareCompareValueHigh = 0UL,
+ .hardwareCompareValueLow = 0UL,
+ .conversionResolutionMode = kLPADC_ConversionResolutionHigh,
+ .enableWaitTrigger = true
+ },
+ {
+ .sampleScaleMode = kLPADC_SampleFullScale,
+ .channelBScaleMode = kLPADC_SampleFullScale,
+ .sampleChannelMode = kLPADC_SampleChannelSingleEndSideB,
+ .channelNumber = 5U,
+ .channelBNumber = 0U,
+ .chainedNextCommandNumber = 0,
+ .enableChannelB = false,
+ .enableAutoChannelIncrement = true,
+ .loopCount = 2UL,
+ .hardwareAverageMode = kLPADC_HardwareAverageCount1,
+ .sampleTimeMode = kLPADC_SampleTimeADCK3,
+ .hardwareCompareMode = kLPADC_HardwareCompareDisabled,
+ .hardwareCompareValueHigh = 0UL,
+ .hardwareCompareValueLow = 0UL,
+ .conversionResolutionMode = kLPADC_ConversionResolutionHigh,
+ .enableWaitTrigger = false
+ }
+};
+lpadc_conv_trigger_config_t ADC1_triggersConfig[1] = {
+ {
+ .targetCommandId = 1,
+ .delayPower = 0UL,
+ .channelAFIFOSelect = 0,
+ .channelBFIFOSelect = 0,
+ .priority = 1,
+ .enableHardwareTrigger = false
+ }
+};
+
+static void ADC1_init(void)
+{
+ /* Initialize LPADC converter */
+ LPADC_Init(ADC1_PERIPHERAL, &ADC1_config);
+ /* Perform offset calibration */
+ LPADC_DoOffsetCalibration(ADC1_PERIPHERAL);
+ /* Perform auto calibration */
+ LPADC_DoAutoCalibration(ADC1_PERIPHERAL);
+ /* Enable DMA request on FIFO 0 watermark event */
+ LPADC_EnableFIFO0WatermarkDMA(ADC1_PERIPHERAL, true);
+ /* Configure conversion command 1. */
+ LPADC_SetConvCommandConfig(ADC1_PERIPHERAL, ADC1_GRPA, &ADC1_commandsConfig[0]);
+ /* Configure conversion command 2. */
+ LPADC_SetConvCommandConfig(ADC1_PERIPHERAL, ADC1_GRPB, &ADC1_commandsConfig[1]);
+ /* Configure trigger 0. */
+ LPADC_SetConvTriggerConfig(ADC1_PERIPHERAL, ADC1_TRIG, &ADC1_triggersConfig[0]);
+}
+#endif
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+#ifdef BSP_USING_LPADC
+ ADC1_init();
+#ifdef BSP_LPADC1_USING_DMA
+ /* Global initialization */
+ (void)memset(DMA4_config.channelConfig, 0, FSL_FEATURE_EDMA_INSTANCE_CHANNELn(DMA4_DMA_BASEADDR) * sizeof(edma_channel_config_t *));
+ EDMA_Init(DMA4_DMA_BASEADDR, &DMA4_config);
+ /* Initialize components */
+ DMA4_init();
+#endif
+#endif
+ LPUART1_init();
+
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+ BOARD_InitPeripherals();
+}
+
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.h
new file mode 100644
index 00000000000..7bdb3c317ff
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/peripherals.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_edma.h"
+#include
+#include "fsl_memory.h"
+#include "fsl_common.h"
+#include "fsl_lpuart.h"
+#include "fsl_clock.h"
+#include "fsl_rgpio.h"
+#include "fsl_lpadc.h"
+#include "rtconfig.h"
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals functional group */
+/* Used DMA device. */
+#define DMA4_DMA_BASEADDR (EDMA_Type *)DMA4
+
+ /* Channel CH0 definitions */
+/* DMA4 eDMA source request. */
+#define DMA4_CH0_DMA_REQUEST kDma4RequestMuxADC1Request0
+/* Selected eDMA channel number. */
+#define DMA4_CH0_DMA_CHANNEL 0
+/* TCD pool size */
+#define DMA4_CH0_TCD_SIZE 1
+/* DMA4 interrupt vector ID (number). */
+#define DMA4_DMA_CH_INT_DONE_0_IRQN DMA4_CH0_CH1_CH32_CH33_IRQn
+/* Transfer structure index 0 definition */
+#define DMA4_CH0_TRANSFER0_CONFIG DMA4_CH0_Transfers_config[0]
+/* Definition of peripheral ID */
+#define LPUART1_PERIPHERAL LPUART1
+/* Definition of the clock source frequency */
+#define LPUART1_CLOCK_SOURCE 24000000UL
+/* Alias for ADC1 peripheral */
+#define ADC1_PERIPHERAL ADC1
+/* Command 1 - GRPA */
+#define ADC1_GRPA 1U
+/* Command 2 - GRPB */
+#define ADC1_GRPB 2U
+/* Trigger 0 - TRIG */
+#define ADC1_TRIG 0U
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+#ifdef BSP_LPADC1_USING_DMA
+extern edma_config_t DMA4_config;
+/* Destination address extern definition */
+extern AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[], sizeof(uint32_t));
+extern edma_handle_t DMA4_CH0_Handle;
+/* Transactional transfer configurations */
+extern edma_transfer_config_t DMA4_CH0_Transfers_config[1];
+#endif
+extern const lpuart_config_t LPUART1_config;
+extern const lpadc_config_t ADC1_config;
+extern lpadc_conv_command_config_t ADC1_commandsConfig[2];
+extern lpadc_conv_trigger_config_t ADC1_triggersConfig[1];
+#ifdef BSP_LPADC1_USING_DMA
+/***********************************************************************************************************************
+ * Callback functions
+ **********************************************************************************************************************/
+/* eDMA callback function for the 0 channel.*/
+extern void DMA_Callback(edma_handle_t*, void*, bool, uint32_t);
+#endif
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.c
new file mode 100644
index 00000000000..40511d92e06
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v17.0
+processor: MIMXRT1189xxxxx
+package_id: MIMXRT1189CVM8C
+mcu_data: ksdk2_0
+processor_version: 26.03.10
+board: MIMXRT1180-EVK
+external_user_signals: {}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_rgpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
+- pin_list:
+ - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08}
+ - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09}
+ - {pin_num: M16, peripheral: RGPIO4, signal: 'gpio_io, 27', pin_signal: GPIO_AD_27, direction: OUTPUT, drive_strength: Normal}
+ - {pin_num: R13, peripheral: ADC1, signal: 'A, 1_7', pin_signal: GPIO_AD_02}
+ - {pin_num: T17, peripheral: ADC1, signal: 'B, 1_5', pin_signal: GPIO_AD_07}
+ - {pin_num: T14, peripheral: ADC1, signal: 'A, 1_4', pin_signal: GPIO_AD_08}
+ - {pin_num: R15, peripheral: ADC1, signal: 'B, 1_7', pin_signal: GPIO_AD_03}
+ - {pin_num: P15, peripheral: ADC1, signal: 'A, 1_6', pin_signal: GPIO_AD_04}
+ - {pin_num: P13, peripheral: ADC1, signal: 'B, 1_6', pin_signal: GPIO_AD_05}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core.
+ * Description :
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
+ CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
+
+ /* GPIO configuration of USER_LED_CTL1 on GPIO_AD_27 (pin M16) */
+ rgpio_pin_config_t USER_LED_CTL1_config = {
+ .pinDirection = kRGPIO_DigitalOutput,
+ .outputLogic = 0U,
+ };
+ /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */
+ RGPIO_PinInit(RGPIO4, 27U, &USER_LED_CTL1_config);
+
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_02_GPIO4_IO02, /* GPIO_AD_02 is configured as GPIO4_IO02 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_03_GPIO4_IO03, /* GPIO_AD_03 is configured as GPIO4_IO03 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_04_GPIO4_IO04, /* GPIO_AD_04 is configured as GPIO4_IO04 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_05_GPIO4_IO05, /* GPIO_AD_05 is configured as GPIO4_IO05 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_07_GPIO4_IO07, /* GPIO_AD_07 is configured as GPIO4_IO07 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_08_GPIO4_IO08, /* GPIO_AD_08 is configured as GPIO4_IO08 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinConfig(
+ IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 PAD functional properties : */
+ 0x04U); /* Slew Rate Field: Fast Slew Rate
+ Drive Strength Field: normal driver
+ Pull / Keep Select Field: Pull Enable
+ Pull Up / Down Config. Field: Weak pull down
+ Open Drain Field: Disabled
+ Force ibe off Field: Disabled */
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.h
new file mode 100644
index 00000000000..b718ad80b42
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/pin_mux.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AON_08 (coord B1), LPUART1_TXD/U61[4]/J39[4]/J70[4] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */
+
+/* GPIO_AON_09 (coord A5), LPUART1_RXD/U61[3]/J39[2]/J70[3] */
+/* Routed pin properties */
+#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
+#define BOARD_INITPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */
+
+/* GPIO_AD_27 (coord M16), USER_LED_CTL1/Q7[1] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_CTL1_PERIPHERAL RGPIO4 /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_CTL1_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CTL1_CHANNEL 27U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_CTL1_GPIO RGPIO4 /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_CTL1_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
+#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN 27U /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */
+
+/* GPIO_AD_02 (coord R13), DMIC_DATA1/U118[1]/J45[11]/J69[5]/J41[2]/J67[6] */
+/* Routed pin properties */
+#define BOARD_INITPINS_DMIC_DATA1_PERIPHERAL ADC1 /*!< Peripheral name */
+#define BOARD_INITPINS_DMIC_DATA1_SIGNAL A /*!< Signal name */
+#define BOARD_INITPINS_DMIC_DATA1_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_AD_07 (coord T17), USB_OTG2_PWR/WIFI_RST_B/J39[14]/J44[3]/J69[10]/U43[3] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USB_OTG2_PWR_PERIPHERAL ADC1 /*!< Peripheral name */
+#define BOARD_INITPINS_USB_OTG2_PWR_SIGNAL B /*!< Signal name */
+#define BOARD_INITPINS_USB_OTG2_PWR_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_AD_08 (coord T14), USB_OTG2_ID/J39[16]/J69[11]/J62[1]/J68[4]/U40[3]/U39[A1] */
+/* Routed pin properties */
+#define BOARD_INITPINS_USB_OTG2_ID_PERIPHERAL ADC1 /*!< Peripheral name */
+#define BOARD_INITPINS_USB_OTG2_ID_SIGNAL A /*!< Signal name */
+#define BOARD_INITPINS_USB_OTG2_ID_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_AD_03 (coord R15), DMIC_DATA2/U117[1]/J45[9]/J69[6]/J41[4]/J67[8] */
+/* Routed pin properties */
+#define BOARD_INITPINS_DMIC_DATA2_PERIPHERAL ADC1 /*!< Peripheral name */
+#define BOARD_INITPINS_DMIC_DATA2_SIGNAL B /*!< Signal name */
+#define BOARD_INITPINS_DMIC_DATA2_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_AD_04 (coord P15), DMIC_DATA3/U119[1]/J45[5]/J69[7]/J41[6]/J67[10] */
+/* Routed pin properties */
+#define BOARD_INITPINS_DMIC_DATA3_PERIPHERAL ADC1 /*!< Peripheral name */
+#define BOARD_INITPINS_DMIC_DATA3_SIGNAL A /*!< Signal name */
+#define BOARD_INITPINS_DMIC_DATA3_CHANNEL 1U /*!< Signal channel */
+
+/* GPIO_AD_05 (coord P13), WL_DEV_WAKE/J45[7]/J69[8]/J41[8]/U43[10] */
+/* Routed pin properties */
+#define BOARD_INITPINS_WL_DEV_WAKE_PERIPHERAL ADC1 /*!< Peripheral name */
+#define BOARD_INITPINS_WL_DEV_WAKE_SIGNAL B /*!< Signal name */
+#define BOARD_INITPINS_WL_DEV_WAKE_CHANNEL 1U /*!< Signal channel */
+
+/*!
+ * @brief
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/readme.txt b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/readme.txt
new file mode 100644
index 00000000000..2efc2b7e661
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config_LPADC1/readme.txt
@@ -0,0 +1,113 @@
+## On-chip peripheral configuration of imxrt1180-nxp-evk --LPADC1
+
+### 1. Demo feature list
+
+- [x] use MCUX_Config software to set pin_mux, clock and LPADC1 peripheral.
+- [x] board boots up from XIP (FlexSPI1_A- QSPI Flash W25Q128)
+- [x] multichannel ADC enables to sample voltage from arduino connector.
+- [x] only LPADC1 enabled, eDMA4 CH0 is optional to use for CPU offload.
+- [x] channel A1_4, A1_5, A1_7; B1_5, B1_6, B1_7 of LPADC1 are verified.
+
+### 1. Hardware configuration
+
+### 1.1 pin configuration in MCUX_Config software
+
+
+
+### 1.2 channel allocation in hardware
+
+
+
+### 2. LPADC1 configurations
+
+### 2.1 General configuration
+
+
+
+- LPADC1 Clock: 80Mhz
+- enable doze mode to reduce current leakage
+- enable auto calibration, offset calibration
+- VREFH select VDDA_ADC_1P8, selecting from power pin directly
+- enable FIFO 0 watermark event for DMA trigger
+
+### 2.2 Command configuration
+
+Command settings are consisted of group A and group B (GRPA, GRPB). GRPA is used for channel A1_4, A1_5, A1_7, while GRPB is used for channelB1_5, B1_6, B1_7.
+
+
+
+- next command: 2
+- sample mode: single
+- channel starts from A1_4
+- auto channel increment enabled, conversion continues to the end.
+- full scale, which means max input of analog pin is 1.8V
+- conversion resolution: 16-bit
+- wait for software trigger
+
+
+
+- next command: none
+
+- sample mode: single
+
+- channel starts from B1_5
+
+- auto channel increment enabled, conversion continues to the end.
+
+- full scale, which means max input of analog pin is 1.8V
+
+- conversion resolution: 16-bit
+
+- loop count: 2
+
+
+
+### 2.3 trigger configuration
+
+
+
+software trigger TRIG is used to trigger command group A.
+
+### 2.4 EDMA configuration
+
+
+
+- Channel ID: CH0
+- request source: #57: ADC1 Request 0
+- enable peripheral request to trigger DMA
+
+
+
+- source address: ADC1 result register
+- destination address: NONCACHEABLE memory
+- minor loop transfer: 4
+- major loop count: 7
+- adjust address after each transfer: -28
+
+## 3. RTT &chip sdk configuration
+
+type "menuconfig.exe" in env tool, go to "Hardware Drivers Config" --> "On-chip Peripheral Drivers":
+
+
+
+
+
+
+
+The codes below shall be added to sdk module to enable codes chip-specific adding to the project.
+
+
+
+
+
+## 4. LPADC1 test
+
+in MSH console, the command below can be entered to start LPDAC1 driver test.
+
+
+
+## 5. limitation for this demo
+
+- Strongly relying on MCUX_Config for LPADC1 peripheral initialization, lack flexible for drv_lpadc
+- Only demonstrate how to implement multichannel ADC sampling
+- Max supported number of single end channel is eight, limited from RTT device driver level. verified channel in this demo is channel 4-7 representing A1_4, B1_5, A1_6, A1_7 separately.
\ No newline at end of file
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c
index 2557a72bc40..627f6a47c44 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c
@@ -436,7 +436,7 @@ void BOARD_ConfigMPU(void)
// Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K]
// non-shareable, read/write in privilege and non-privilege, executable. Attr 3
- ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U));
+// ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U));
// Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K]
// non-shareable, read/write in privilege and non-privilege, executable. Attr 3
@@ -1250,13 +1250,15 @@ void imxrt_uart_pins_init(void)
void rt_hw_board_init()
{
-// BOARD_CommonSetting();
+ BOARD_CommonSetting();
BOARD_ConfigMPU();
+
+ /* MCU_Config start */
BOARD_InitPins();
-
- BOARD_InitLeds();
- BOARD_BootClockRUN();
-
+ BOARD_BootClockRUN();
+ BOARD_InitPeripherals();
+ /* MCU_Config end */
+
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h
index 46f34985b9e..8429f2d2672 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h
@@ -10,6 +10,7 @@
#include "clock_config.h"
#include "pin_mux.h"
+#include "peripherals.h"
#include "fsl_common.h"
#include "fsl_rgpio.h"
#include "fsl_clock.h"
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
index c0b50be6fce..4c728b11f47 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h
@@ -149,6 +149,7 @@
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_ADC
#define RT_USING_PIN
/* end of Device Drivers */
@@ -296,6 +297,10 @@
/* end of Kendryte SDK */
+/* MM32 HAL & SDK Drivers */
+
+/* end of MM32 HAL & SDK Drivers */
+
/* WCH HAL & SDK Drivers */
/* end of WCH HAL & SDK Drivers */
@@ -329,6 +334,10 @@
/* FT32 HAL & SDK Drivers */
/* end of FT32 HAL & SDK Drivers */
+
+/* NOVOSNS Drivers */
+
+/* end of NOVOSNS Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */
@@ -419,6 +428,9 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_DMA
+#define BSP_USING_LPADC
+#define BSP_USING_LPADC1
+#define BSP_LPADC1_USING_DMA
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
/* end of On-chip Peripheral Drivers */
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c
index 519f21bfa1f..5a03139a77b 100644
--- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_adc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2023, RT-Thread Development Team
+ * Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c
index 8f4f9b10be5..09aa93618b9 100644
--- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.c
@@ -36,71 +36,119 @@ static struct rt_adc_device lpadc1_device;
static struct rt_adc_device lpadc2_device;
#endif
-#if (defined(DEMO_LPADC_USE_HIGH_RESOLUTION) && DEMO_LPADC_USE_HIGH_RESOLUTION)
-uint32_t g_LpadcResultShift = 0U;
-#else
-uint32_t g_LpadcResultShift = 3U;
-#endif /* DEMO_LPADC_USE_HIGH_RESOLUTION */
+#if defined(BSP_LPADC1_USING_DMA)
+#include "fsl_edma.h"
+#include "peripherals.h"
+
+volatile bool g_Transfer_Done = false;
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t adc_result[7], sizeof(uint32_t)) = {0x0,0x0,0x0,0x0,0x0,0x0,0x0};
-static rt_err_t imxrt_hp_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+/* User callback function for EDMA transfer. */
+void DMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
{
+ if (transferDone)
+ {
+ g_Transfer_Done = true;
+ }
+}
+#endif
+
+static rt_err_t imxrt_lp_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
+{
+ ADC_Type *base;
+ /* channel check*/
+
+ if(channel < 4) return -RT_EINVAL;
+
+ base = (ADC_Type *)(device->parent.user_data);
+ if( RT_TRUE == enabled )
+ {
+ LPADC_Enable(base, true);
+ } else
+ {
+ LPADC_Enable(base, false);
+ }
+
return RT_EOK;
}
-static rt_err_t imxrt_hp_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+static rt_err_t imxrt_lp_adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
{
- LPADC1_BASE *base;
- lpadc_conv_command_config_t mLpadcCommandConfigStruct;
- lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct;
- lpadc_conv_result_t mLpadcResultConfigStruct;
- base = (LPADC1_BASE *)(device->parent.user_data);
-
- //ADC_SetChannelConfig(base, 0, &adc_channel);
- LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct);
- mLpadcCommandConfigStruct.channelNumber = channel;
-#if defined(DEMO_LPADC_USE_HIGH_RESOLUTION) && DEMO_LPADC_USE_HIGH_RESOLUTION
- mLpadcCommandConfigStruct.conversionResolutionMode = kLPADC_ConversionResolutionHigh;
-#endif /* DEMO_LPADC_USE_HIGH_RESOLUTION */
- LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct);
-
- /* Set trigger configuration. */
- LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct);
- mLpadcTriggerConfigStruct.targetCommandId = 1U;
- mLpadcTriggerConfigStruct.enableHardwareTrigger = false;
- LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */
+ ADC_Type *base;
+ uint32_t data_mask=0xffffffff;
+#if defined(BSP_LPADC1_USING_DMA)
+
+#else
+ uint8_t i=0;
+ uint32_t adc_result[7] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0}; /* conv sequence: A1_4, A1_5(INVALID), A1_6, A1_7, B1_5, B1_6, B1_7 */
+ lpadc_conv_result_t mLpadcResultConfigStruct;
+#endif
+
+ base = (ADC_Type *)(device->parent.user_data);
LPADC_DoSoftwareTrigger(base, 1U);
-
+#if defined(BSP_LPADC1_USING_DMA)
+ data_mask = 0xffff;
+ g_Transfer_Done = false;
+ EDMA_StartTransfer(&DMA4_CH0_Handle);
+ /* Wait for EDMA transfer finish */
+ while (g_Transfer_Done != true)
+ {
+ }
+#else
+ for(i=0;i<7;i++) {
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
- while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U))
+ while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U))
#else
- while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct))
+ while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct))
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
- {
- }
- *value = (mLpadcResultConfigStruct.convValue) >> g_LpadcResultShift;
+ {
+ }
+ adc_result[i] = (mLpadcResultConfigStruct.convValue);
+ }
+#endif
+ switch(channel)
+ {
+ case 4: *value = adc_result[0] & data_mask;
+ break;
+ case 5: *value = adc_result[4] & data_mask;
+ break;
+ case 6: *value = adc_result[2] & data_mask;
+ break;
+ case 7: *value = adc_result[3] & data_mask;
+ break;
+ default: *value = 0; return -RT_EINVAL;
+ }
return RT_EOK;
}
+static rt_uint8_t imxrt_lp_adc_get_resolution(struct rt_adc_device *device)
+{
+ return 16;
+}
+
+static rt_int16_t imxrt_lp_adc_get_vref(struct rt_adc_device *device)
+{
+ return 1800;
+}
+
+
static struct rt_adc_ops imxrt_lpadc_ops =
{
- .enabled = imxrt_hp_adc_enabled,
- .convert = imxrt_hp_adc_convert,
+ .enabled = imxrt_lp_adc_enabled,
+ .convert = imxrt_lp_adc_convert,
+ .get_resolution = imxrt_lp_adc_get_resolution,
+ .get_vref = imxrt_lp_adc_get_vref,
};
int rt_hw_adc_init(void)
{
int result = RT_EOK;
- LPADC_GetDefaultConfig(&mLpadcConfigStruct);
- mLpadcConfigStruct.enableAnalogPreliminary = true;
-#if defined(kLPADC_ReferenceVoltageAlt1)
- mLpadcConfigStruct.referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
-#endif /* DEMO_LPADC_VREF_SOURCE */
#if defined(BSP_USING_LPADC1)
- LPADC_Init(LPADC1, &mLpadcConfigStruct);
- result = rt_hw_adc_register(&lpadc1_device, "lpadc1", &imxrt_lpadc_ops, LPADC1);
+/* on-chip peripherals are initialized in BOARD_InitPeripherals function of board.c */
+ result = rt_hw_adc_register(&lpadc1_device, "lpadc1", &imxrt_lpadc_ops, ADC1);
if (result != RT_EOK)
{
LOG_E("register lpadc1 device failed error code = %d\n", result);
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h
index 2aca3ca8d8a..d10a7e6e7e2 100644
--- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_lpadc.h
@@ -12,6 +12,42 @@
#define DRV_ADC_H__
#include
+
+/* drv adc channel definition */
+/*
+#define RT_DRV_ADC_CH_A_0 0x01
+#define RT_DRV_ADC_CH_A_1 0x02
+#define RT_DRV_ADC_CH_A_2 0x04
+#define RT_DRV_ADC_CH_A_3 0x08
+#define RT_DRV_ADC_CH_A_4 0x10
+#define RT_DRV_ADC_CH_A_5 0x20
+#define RT_DRV_ADC_CH_A_6 0x40
+#define RT_DRV_ADC_CH_A_7 0x80
+
+#define RT_DRV_ADC_CH_B_0 0x01
+#define RT_DRV_ADC_CH_B_1 0x02
+#define RT_DRV_ADC_CH_B_2 0x04
+#define RT_DRV_ADC_CH_B_3 0x08
+#define RT_DRV_ADC_CH_B_4 0x10
+#define RT_DRV_ADC_CH_B_5 0x20
+#define RT_DRV_ADC_CH_B_6 0x40
+#define RT_DRV_ADC_CH_B_7 0x80
+*/
+
+/*
+imxrt1180-nxp-evk arduino interface ADC channel configuration:
+ADC1:
+RT_DRV_ADC1_CH_A_4, RT_DRV_ADC1_CH_A_6, RT_DRV_ADC1_CH_A_7
+RT_DRV_ADC1_CH_B_5, RT_DRV_ADC1_CH_B_6, RT_DRV_ADC1_CH_B_7
+
+ADC2:
+RT_DRV_ADC1_CH_A_0, RT_DRV_ADC1_CH_B_0
+
+IMPORTANT!!
+Propose to change rt_adc_ops structure from rt_int8_t to rt_int16_t to enable side A and side B simultineously in same ADC !!!
+*/
+
+
int rt_hw_adc_init(void);
#endif /* DRV_ADC_H__ */