From fa9f129cf2c969f47053dfc94e5eb8ddb9fc7571 Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin <6576495+widgetii@users.noreply.github.com> Date: Fri, 2 Oct 2026 11:03:34 +0300 Subject: [PATCH 1/2] agent: add gk7605v100 gk7605v100 shares the gk7205v200 memory map: the kernel device trees for the two differ only by two extra GPIO banks, with UART0 at 0x12040000, FMC at 0x10000000 (window 0x14000000), CRG 0x12010000, sysctrl 0x12020000 and the watchdog at 0x12030000 on both. It gets its own Makefile stanza, like gk7205v300, so `make SOC=gk7605v100` works, and it maps to the gk7205v200 build in _CHIP_TO_AGENT. The board has 256M of DDR, but the agent only maps the first 128 MiB from RAM_BASE. That is enough for every staging buffer it uses. Verified on a gk7605v100 board (sc2239, 256M, 8MB FM25Q64 NOR): make -C agent SOC=gk7605v100 # 18008 bytes defib agent upload -c gk7605v100 -p /dev/ttyUSB0 defib agent info -p /dev/ttyUSB0 defib agent read -p /dev/ttyUSB0 -o dump.bin Upload went through the boot ROM with the full U-Boot as SPL (boundary auto-detected) and reached READY. info reported JEDEC a14017, 8192 KB, 64 KB sectors, agent v4 with flash_stream/set_baud/scan/membw capabilities. The full 8 MiB read took 94 s at 89 KB/s, CRC32 OK. The dump is byte-identical to an independent U-Boot `sf read` + tftpput backup over boot+env, and to the OpenIPC lite release uImage and rootfs.squashfs over the kernel and rootfs partitions. Write paths were not exercised on this board. --- CLAUDE.md | 6 +++--- agent/Makefile | 12 +++++++++++- agent/README.md | 1 + src/defib/agent/client.py | 1 + 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/CLAUDE.md b/CLAUDE.md index 3c6ebf9..1b33c15 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -57,7 +57,7 @@ node --test web/protocol.test.js web/profile-parity.test.js # Cross-compile flash agent (ARM32; needs arm-none-eabi-gcc + newlib) make -C agent # default: SOC=hi3516ev300 make -C agent SOC=hi3516cv300 # specific SoC -make -C agent all-socs # only 4 representative SoCs, not all 10 +make -C agent all-socs # only 4 representative SoCs, not all 11 ``` Apart from the single-test and cross-compile lines, those are exactly what the @@ -126,13 +126,13 @@ the handshake, reverting to 115200 after ~30 s idle. 13 commands: `INFO 0x01`, optional features through a capability bitmask (`client.py`). Backends: `spi_flash.c` (fmc100), `spi_flash_hisfc350.c` (V1-era parts), -`emmc_himci.c`. Ten SoCs are supported; each has its own `ifeq` stanza in +`emmc_himci.c`. Eleven SoCs are supported; each has its own `ifeq` stanza in `agent/Makefile` carrying `LOAD_ADDR` (and `SPI_DRIVER` where it differs). `link.ld` itself is generic — it just places `. = LOAD_ADDR`. ### Other key modules -- **Profiles** (`src/defib/profiles/`) — 112 JSON SoC definitions in `data/`, +- **Profiles** (`src/defib/profiles/`) — 113 JSON SoC definitions in `data/`, validated with Pydantic (`schema.py`). `defib list-chips` combines those profiles with hardcoded V500/CV6xx chips and exact registered vendor-U-Boot migration selectors. diff --git a/agent/Makefile b/agent/Makefile index d31fb9b..0575507 100644 --- a/agent/Makefile +++ b/agent/Makefile @@ -59,6 +59,16 @@ else ifeq ($(SOC),gk7205v300) WDT_BASE = 0x12030000 CRG_BASE = 0x12010000 SYSCTRL_REBOOT = 0x12020004 +else ifeq ($(SOC),gk7605v100) + UART_BASE = 0x12040000 + UART_CLOCK = 24000000 + LOAD_ADDR = 0x41000000 + FLASH_MEM = 0x14000000 + FMC_BASE = 0x10000000 + RAM_BASE = 0x40000000 + WDT_BASE = 0x12030000 + CRG_BASE = 0x12010000 + SYSCTRL_REBOOT = 0x12020004 else ifeq ($(SOC),hi3516cv300) # V3 generation: ARM926EJ-S (ARMv5TEJ), not Cortex-A7. # UART is PL011 (same as ev300 family) at a different base. @@ -178,7 +188,7 @@ else ifeq ($(SOC),hi3520dv200) SYSCTRL_REBOOT = 0x20050004 SPI_DRIVER = hisfc350 else - $(error Unknown SOC: $(SOC). Supported: hi3516ev300 hi3516ev200 gk7205v200 gk7205v300 hi3516cv300 hi3516cv500 hi3518ev200 hi3516cv610 hi3519v101 hi3520dv200) + $(error Unknown SOC: $(SOC). Supported: hi3516ev300 hi3516ev200 gk7205v200 gk7205v300 gk7605v100 hi3516cv300 hi3516cv500 hi3518ev200 hi3516cv610 hi3519v101 hi3520dv200) endif # Per-SoC CPU. V3 chips (cv300) are ARM926EJ-S (ARMv5TEJ); diff --git a/agent/README.md b/agent/README.md index 0f2846e..bd4ad70 100644 --- a/agent/README.md +++ b/agent/README.md @@ -74,6 +74,7 @@ Requires `arm-none-eabi-gcc` (Arch: `pacman -S arm-none-eabi-gcc arm-none-eabi-n | hi3516ev200 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 | | gk7205v200 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 | | gk7205v300 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 | +| gk7605v100 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 | | hi3516cv300 | 0x12100000 | 0x14000000 | 0x80000000 | 0x81000000 | | hi3516cv500 | 0x12100000 | 0x14000000 | 0x80000000 | 0x81000000 | | hi3518ev200 | 0x12100000 | 0x14000000 | 0x80000000 | 0x81000000 | diff --git a/src/defib/agent/client.py b/src/defib/agent/client.py index 8d1b92d..4c25242 100644 --- a/src/defib/agent/client.py +++ b/src/defib/agent/client.py @@ -152,6 +152,7 @@ def bad_block(self) -> list[SectorResult]: "gk7205v200": "gk7205v200", "gk7205v300": "gk7205v200", "gk7202v300": "gk7205v200", + "gk7605v100": "gk7205v200", "hi3516cv300": "hi3516cv300", "hi3516cv500": "hi3516cv500", "hi3516av300": "hi3516cv500", # cv500-family, same memory map From cde8d03dc5082bebf92fab14e9903063d1ac2495 Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin <6576495+widgetii@users.noreply.github.com> Date: Fri, 2 Oct 2026 11:16:30 +0300 Subject: [PATCH 2/2] CLAUDE.md: keep the HiSiliconStandard profile count in step The Profiles section now says 113 after the gk7605v100 profile; the protocol section still said 112. --- CLAUDE.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CLAUDE.md b/CLAUDE.md index 1b33c15..fd816f1 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -82,7 +82,7 @@ five CI jobs in `.github/workflows/ci.yml` run (`test`, `fuzz`, `lint`, `BootProtocol`, registered via the `@register` decorator and exposed as entry points in pyproject.toml: - `HiSiliconStandard` — matches **any chip that has a profile JSON**, i.e. all - 112; classic init_bootmode handshake + 113; classic init_bootmode handshake - `HiSiliconV500` — `gk7205v500/510/530`, `xm7205v500/510/530`; different handshake - `HiSiliconCV6xx` — `hi3516cv608/610/613`, `hi3516dv500`, `hi3519dv500`; multi-stage