如果採用，此提交將完成第六章第二節工作項目四，目前電路結果仍有錯誤

修改項目:

模組:

議題38

Author: timmy61109

Digital_Logic_Practice/CH6/CH6-2/BCD_seven_seg_seven_four_two_four_eight.vwf

@@ -50,4 +50,9 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
 set_global_assignment -name BDF_FILE BCD_seven_seg_seven_four_two_four_eight_error.bdf
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE BCD_seven_seg_seven_four_two_four_eight_error.vwf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top