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修改項目: 模組: 議題38
1 parent 9fa8c40 commit d9f2a76

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Lines changed: 782 additions & 71 deletions

‎CH6/CH6-2/BCD_seven_seg_seven_four_two_four_eight_error.qsf‎

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@@ -42,11 +42,12 @@ set_global_assignment -name DEVICE 5CGXFC7C7F23C8
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set_global_assignment -name TOP_LEVEL_ENTITY BCD_seven_seg_seven_four_two_four_eight_error
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:20:51 MARCH 23, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
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set_global_assignment -name LAST_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name BDF_FILE BCD_seven_seg_seven_four_two_four_eight_error.bdf
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set_global_assignment -name BDF_FILE BCD_seven_seg_seven_four_two_four_eight_error.bdf
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"

‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight.cmp.hdb‎

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‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight.cmp.rdb‎

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‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight.eda.qmsg‎

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600616713200 ""}
2-
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition " "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600616713202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 20 23:45:12 2020 " "Processing started: Sun Sep 20 23:45:12 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600616713202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600616713202 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off BCD_seven_seg_seven_four_two_four_eight -c BCD_seven_seg_seven_four_two_four_eight " "Command: quartus_eda --read_settings_files=off --write_settings_files=off BCD_seven_seg_seven_four_two_four_eight -c BCD_seven_seg_seven_four_two_four_eight" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600616713202 ""}
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{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation files although EDA timing simulation option is chosen." { } { } 0 10905 "Generated the EDA functional simulation files although EDA timing simulation option is chosen." 0 0 "Quartus II" 0 -1 1600616714767 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_seven_seg_seven_four_two_four_eight.vho /home/timmy/Git/Learn-VHDL/CH6/CH6-2/simulation/modelsim/ simulation " "Generated file BCD_seven_seg_seven_four_two_four_eight.vho in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-2/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1600616715008 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1163 " "Peak virtual memory: 1163 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600616715140 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 20 23:45:15 2020 " "Processing ended: Sun Sep 20 23:45:15 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600616715140 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600616715140 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600616715140 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600616715140 ""}
1+
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600658718527 ""}
2+
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition " "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2015 Altera Corporation. All rights reserved. " "Copyright (C) 1991-2015 Altera Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions " "Your use of Altera Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License " "to the terms and conditions of the Altera Program License " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Altera Quartus II License Agreement, " "Subscription Agreement, the Altera Quartus II License Agreement," { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Altera MegaCore Function License Agreement, or other " "the Altera MegaCore Function License Agreement, or other " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable license agreement, including, without limitation, " "applicable license agreement, including, without limitation, " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "that your use is for the sole purpose of programming logic " "that your use is for the sole purpose of programming logic " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "devices manufactured by Altera and sold by Altera or its " "devices manufactured by Altera and sold by Altera or its " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "authorized distributors. Please refer to the applicable " "authorized distributors. Please refer to the applicable " { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement for further details. " "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 21 11:25:18 2020 " "Processing started: Mon Sep 21 11:25:18 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600658718529 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-2/simulation/qsim/ BCD_seven_seg_seven_four_two_four_eight -c BCD_seven_seg_seven_four_two_four_eight " "Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/home/timmy/Git/Learn-VHDL/CH6/CH6-2/simulation/qsim/ BCD_seven_seg_seven_four_two_four_eight -c BCD_seven_seg_seven_four_two_four_eight" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600658718530 ""}
4+
{ "Info" "IWSC_DONE_HDL_GENERATION" "BCD_seven_seg_seven_four_two_four_eight.vo /home/timmy/Git/Learn-VHDL/CH6/CH6-2/simulation/qsim// simulation " "Generated file BCD_seven_seg_seven_four_two_four_eight.vo in folder \"/home/timmy/Git/Learn-VHDL/CH6/CH6-2/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1600658720255 ""}
5+
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1155 " "Peak virtual memory: 1155 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600658720316 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 21 11:25:20 2020 " "Processing ended: Mon Sep 21 11:25:20 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600658720316 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600658720316 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600658720316 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600658720316 ""}

‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight.smart_action.txt‎

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1-
DONE
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SOURCE

‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight.tmw_info‎

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start_full_compilation:s:00:03:02
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start_analysis_synthesis:s:00:00:38-start_full_compilation
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start_full_compilation:s
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start_analysis_synthesis:s-start_full_compilation
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start_analysis_elaboration:s-start_full_compilation
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start_fitter:s:00:01:39-start_full_compilation
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start_assembler:s:00:00:26-start_full_compilation
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start_timing_analyzer:s:00:00:13-start_full_compilation
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start_eda_netlist_writer:s:00:00:06-start_full_compilation
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start_fitter:s-start_full_compilation
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start_assembler:s-start_full_compilation
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start_timing_analyzer:s-start_full_compilation
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start_eda_netlist_writer:s-start_full_compilation

‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight_error.pplq.rdb‎

299 Bytes
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‎CH6/CH6-2/db/BCD_seven_seg_seven_four_two_four_eight_error.sld_design_entry.sci‎

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