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Author: timmy61109

VHDL Digital Logic Design Practice/CH2/NAND_2.sym

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+-- MAX+plus II Compiler Fit File      
+-- Version 10.2 07/10/2002            
+-- Compiled: 05/07/2004 08:28:05      
+
+-- Copyright (C) 1988-2002 Altera Corporation
+-- Any megafunction design, and related net list (encrypted or decrypted),
+-- support information, device programming or simulation file, and any other
+-- associated documentation or information provided by Altera or a partner
+-- under Altera's Megafunction Partnership Program may be used only to
+-- program PLD devices (but not masked PLD devices) from Altera.  Any other
+-- use of such megafunction design, net list, support information, device
+-- programming or simulation file, or any other related documentation or
+-- information is prohibited for any other purpose, including, but not
+-- limited to modification, reverse engineering, de-compiling, or use with
+-- any other silicon devices, unless such use is explicitly licensed under
+-- a separate agreement with Altera or a megafunction partner.  Title to
+-- the intellectual property, including patents, copyrights, trademarks,
+-- trade secrets, or maskworks, embodied in any such megafunction design,
+-- net list, support information, device programming or simulation file, or
+-- any other related documentation or information provided by Altera or a
+-- megafunction partner, remains with Altera, the megafunction partner, or
+-- their respective licensors.  No other licenses, including any licenses
+-- needed under any third party's intellectual property, are provided herein.
+
+CHIP "nand_2"
+BEGIN
+
+    DEVICE = "EPM3064ALC44-4";
+
+    "A"                            : INPUT_PIN  = 4      ; -- LC16
+    "B"                            : INPUT_PIN  = 5      ; -- LC14
+    "F"                            : OUTPUT_PIN = 41     ; -- LC64
+
+END;
+
+INTERNAL_INFO "nand_2"
+BEGIN
+	DEVICE = EPM3064ALC44-4;
+	LC64    : LORAX = "G114R0";
+	OH13R0P5 : LORAX = "G34R0,PA13R0C3";
+	OH15R0P4 : LORAX = "G36R0,PA14R0C3";
+END;

VHDL Digital Logic Design Practice/CH2/nand_2.acf

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+HIF003
+--
+-- Copyright (C) 1988-2002 Altera Corporation
+-- Any megafunction design, and related net list (encrypted or decrypted),
+-- support information, device programming or simulation file, and any other
+-- associated documentation or information provided by Altera or a partner
+-- under Altera's Megafunction Partnership Program may be used only to
+-- program PLD devices (but not masked PLD devices) from Altera.  Any other
+-- use of such megafunction design, net list, support information, device
+-- programming or simulation file, or any other related documentation or
+-- information is prohibited for any other purpose, including, but not
+-- limited to modification, reverse engineering, de-compiling, or use with
+-- any other silicon devices, unless such use is explicitly licensed under
+-- a separate agreement with Altera or a megafunction partner.  Title to
+-- the intellectual property, including patents, copyrights, trademarks,
+-- trade secrets, or maskworks, embodied in any such megafunction design,
+-- net list, support information, device programming or simulation file, or
+-- any other related documentation or information provided by Altera or a
+-- megafunction partner, remains with Altera, the megafunction partner, or
+-- their respective licensors.  No other licenses, including any licenses
+-- needed under any third party's intellectual property, are provided herein.
+--
+-- Warning: do not edit this file!
+--
+FILES
+{
+	nand_2.gdf
+	{
+		nand_2 [] []
+		{
+			0 [] [];
+		}
+	}
+}
+TREE
+{
+	nand_2::(0,0):(0): nand_2.gdf;
+}