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如果採用，此提交將新增T型正反器
修改項目: 模組: 議題57
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‎Digital_Logic_Practice/CH7/CH7-2/T_FF.bdf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
10+
functions, and any output files from any of the foregoing
11+
(including device programming or simulation files), and any
12+
associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
15+
the Altera MegaCore Function License Agreement, or other
16+
applicable license agreement, including, without limitation,
17+
that your use is for the sole purpose of programming logic
18+
devices manufactured by Altera and sold by Altera or its
19+
authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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(header "graphic" (version "1.4"))
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(pin
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(input)
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(rect 224 176 392 192)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "T" (rect 5 0 13 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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)
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(pin
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(input)
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(rect 224 192 392 208)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "CK" (rect 5 0 22 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 4)(pt 109 4))
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(line (pt 113 8)(pt 168 8))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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)
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(pin
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(input)
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(rect 224 144 392 160)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "PR" (rect 5 0 22 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 109 12)(pt 113 8))
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)
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)
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(pin
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(rect 224 240 392 256)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "CLR" (rect 5 0 29 11)(font "Arial" ))
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(pt 168 8)
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)
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(text "T" (rect 16 20 24 31)(font "Courier New" (bold)))
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(line (pt 0 24)(pt 12 24))
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)
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(port
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(pt 0 40)
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(input)
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(text "CLK" (rect 2 28 23 39)(font "Courier New" (bold))(invisible))
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(text "CLK" (rect 2 28 23 39)(font "Courier New" (bold))(invisible))
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(line (pt 0 40)(pt 12 40))
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)
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(port
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(pt 64 24)
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(text "Q" (rect 45 20 53 31)(font "Courier New" (bold)))
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(line (pt 52 24)(pt 64 24))
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(drawing
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(line (pt 12 12)(pt 52 12))
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(circle (rect 28 4 36 12))
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(circle (rect 28 68 36 76))
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)

‎Digital_Logic_Practice/CH7/CH7-2/T_FF.vwf‎

Lines changed: 196 additions & 0 deletions
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1+
/*
2+
WARNING: Do NOT edit the input and output ports in this file in a text
3+
editor if you plan to continue editing the block that represents it in
4+
the Block Editor! File corruption is VERY likely to occur.
5+
*/
6+
7+
/*
8+
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
9+
Your use of Altera Corporation's design tools, logic functions
10+
and other software and tools, and its AMPP partner logic
11+
functions, and any output files from any of the foregoing
12+
(including device programming or simulation files), and any
13+
associated documentation or information are expressly subject
14+
to the terms and conditions of the Altera Program License
15+
Subscription Agreement, the Altera Quartus II License Agreement,
16+
the Altera MegaCore Function License Agreement, or other
17+
applicable license agreement, including, without limitation,
18+
that your use is for the sole purpose of programming logic
19+
devices manufactured by Altera and sold by Altera or its
20+
authorized distributors. Please refer to the applicable
21+
agreement for further details.
22+
*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("CK")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("CLR")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("PR")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("Q")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("T")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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TRANSITION_LIST("CK")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 50;
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LEVEL 0 FOR 10.0;
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LEVEL 1 FOR 10.0;
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}
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}
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}
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TRANSITION_LIST("CLR")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 10.0;
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LEVEL 1 FOR 970.0;
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}
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}
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TRANSITION_LIST("PR")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 10.0;
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LEVEL 1 FOR 990.0;
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}
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}
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TRANSITION_LIST("Q")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("T")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 100.0;
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NODE
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{
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REPEAT = 4;
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LEVEL 0 FOR 100.0;
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LEVEL 1 FOR 100.0;
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}
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LEVEL 0 FOR 100.0;
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "PR";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "CLR";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "CK";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "T";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 3;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "Q";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 4;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;

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