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18 files changed

Lines changed: 60 additions & 57 deletions

‎CH3-2/Work1/Learn_VHDL.qws‎

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‎CH3-2/Work1/db/Learn_VHDL.cmp.rdb‎

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‎CH3-2/Work1/db/Learn_VHDL.db_info‎

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Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Version_Index = 318808576
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Creation_Time = Tue Jul 30 13:52:41 2019
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Creation_Time = Tue Jul 30 21:37:34 2019

‎CH3-2/Work1/db/Learn_VHDL.eda.qmsg‎

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1561203007126 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1561203007128 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 22 19:30:06 2019 " "Processing started: Sat Jun 22 19:30:06 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1561203007128 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1561203007128 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Learn_VHDL -c Learn_VHDL " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Learn_VHDL -c Learn_VHDL" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1561203007130 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_85c_slow.vho /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203007854 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_0c_slow.vho /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203007884 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_min_1200mv_0c_fast.vho /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203007914 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL.vho /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL.vho in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203007955 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203007990 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203008023 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203008060 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_vhd.sdo /home/timmy/Git/Learn_VHDL/simulation/modelsim/ simulation " "Generated file Learn_VHDL_vhd.sdo in folder \"/home/timmy/Git/Learn_VHDL/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1561203008093 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1561203008186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 22 19:30:08 2019 " "Processing ended: Sat Jun 22 19:30:08 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1561203008186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1561203008186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1561203008186 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1561203008186 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1564493910287 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1564493910289 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 30 21:38:29 2019 " "Processing started: Tue Jul 30 21:38:29 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1564493910289 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1564493910289 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off Learn_VHDL -c Learn_VHDL " "Command: quartus_eda --read_settings_files=on --write_settings_files=off Learn_VHDL -c Learn_VHDL" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1564493910290 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_85c_slow.vho /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_85c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911166 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_0c_slow.vho /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_0c_slow.vho in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911195 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_min_1200mv_0c_fast.vho /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_min_1200mv_0c_fast.vho in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911224 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL.vho /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL.vho in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911256 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_85c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_85c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911293 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_6_1200mv_0c_vhd_slow.sdo /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_6_1200mv_0c_vhd_slow.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911329 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_min_1200mv_0c_vhd_fast.sdo /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_min_1200mv_0c_vhd_fast.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911366 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "Learn_VHDL_vhd.sdo /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/ simulation " "Generated file Learn_VHDL_vhd.sdo in folder \"/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1564493911396 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "348 " "Peak virtual memory: 348 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1564493911444 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 30 21:38:31 2019 " "Processing ended: Tue Jul 30 21:38:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1564493911444 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1564493911444 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1564493911444 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1564493911444 ""}

‎CH3-2/Work1/db/Learn_VHDL.smart_action.txt‎

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DONE
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SOURCE

‎CH3-2/Work1/db/Learn_VHDL.tmw_info‎

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start_analysis_elaboration:s
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start_fitter:s
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start_timing_analyzer:s
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start_eda_netlist_writer:s
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start_eda_netlist_writer:s:00:00:06

‎CH3-2/Work1/output_files/Learn_VHDL.done‎

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Sat Jun 22 19:30:08 2019
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Tue Jul 30 21:38:31 2019

‎CH3-2/Work1/output_files/Learn_VHDL.eda.rpt‎

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EDA Netlist Writer report for Learn_VHDL
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Sat Jun 22 19:30:08 2019
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Tue Jul 30 21:38:31 2019
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Sat Jun 22 19:30:08 2019 ;
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; EDA Netlist Writer Status ; Successful - Tue Jul 30 21:38:31 2019 ;
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; Revision Name ; Learn_VHDL ;
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; Top-level Entity Name ; Learn_VHDL ;
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; Family ; Cyclone III ;
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+---------------------------------------------------------------------------------------------------+------------------------+
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+--------------------------------------------------------------------------------------+
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; Simulation Generated Files ;
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+--------------------------------------------------------------------------------------+
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; Generated Files ;
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+--------------------------------------------------------------------------------------+
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_6_1200mv_85c_slow.vho ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_6_1200mv_0c_slow.vho ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_min_1200mv_0c_fast.vho ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL.vho ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_6_1200mv_85c_vhd_slow.sdo ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_6_1200mv_0c_vhd_slow.sdo ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_min_1200mv_0c_vhd_fast.sdo ;
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; /home/timmy/Git/Learn_VHDL/simulation/modelsim/Learn_VHDL_vhd.sdo ;
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+--------------------------------------------------------------------------------------+
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+--------------------------------------------------------------------------------------------------+
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; Simulation Generated Files ;
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+--------------------------------------------------------------------------------------------------+
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; Generated Files ;
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+--------------------------------------------------------------------------------------------------+
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_6_1200mv_85c_slow.vho ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_6_1200mv_0c_slow.vho ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_min_1200mv_0c_fast.vho ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL.vho ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_6_1200mv_85c_vhd_slow.sdo ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_6_1200mv_0c_vhd_slow.sdo ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_min_1200mv_0c_vhd_fast.sdo ;
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; /home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/Learn_VHDL_vhd.sdo ;
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+--------------------------------------------------------------------------------------------------+
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus II 32-bit EDA Netlist Writer
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Info: Processing started: Sat Jun 22 19:30:06 2019
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Learn_VHDL -c Learn_VHDL
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Info (204019): Generated file Learn_VHDL_6_1200mv_85c_slow.vho in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_6_1200mv_0c_slow.vho in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_min_1200mv_0c_fast.vho in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL.vho in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_6_1200mv_85c_vhd_slow.sdo in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_6_1200mv_0c_vhd_slow.sdo in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_min_1200mv_0c_vhd_fast.sdo in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_vhd.sdo in folder "/home/timmy/Git/Learn_VHDL/simulation/modelsim/" for EDA simulation tool
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Info: Processing started: Tue Jul 30 21:38:29 2019
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Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off Learn_VHDL -c Learn_VHDL
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Info (204019): Generated file Learn_VHDL_6_1200mv_85c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_6_1200mv_0c_slow.vho in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_min_1200mv_0c_fast.vho in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL.vho in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_6_1200mv_85c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_6_1200mv_0c_vhd_slow.sdo in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_min_1200mv_0c_vhd_fast.sdo in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info (204019): Generated file Learn_VHDL_vhd.sdo in folder "/home/timmy/Git/Learn-VHDL/CH3-2/Work1/simulation/modelsim/" for EDA simulation tool
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Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 344 megabytes
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Info: Processing ended: Sat Jun 22 19:30:08 2019
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Info: Peak virtual memory: 348 megabytes
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Info: Processing ended: Tue Jul 30 21:38:31 2019
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Info: Elapsed time: 00:00:02
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Info: Total CPU time (on all processors): 00:00:01
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