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Merge pull request #28 from timmy61109/release/v5.3.4-beta
Release/v5.3.4-beta
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‎CH5/CH5-2/Full_subtractor_S.bdf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
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the Altera MegaCore Function License Agreement, or other
16+
applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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‎CH5/CH5-2/Full_subtractor_S.qpf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
4+
# Your use of Altera Corporation's design tools, logic functions
5+
# and other software and tools, and its AMPP partner logic
6+
# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
8+
# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
10+
# Subscription Agreement, the Altera Quartus II License Agreement,
11+
# the Altera MegaCore Function License Agreement, or other
12+
# applicable license agreement, including, without limitation,
13+
# that your use is for the sole purpose of programming logic
14+
# devices manufactured by Altera and sold by Altera or its
15+
# authorized distributors. Please refer to the applicable
16+
# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
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# Date created = 17:08:29 August 26, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "15.0"
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DATE = "17:08:29 August 26, 2019"
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# Revisions
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PROJECT_REVISION = "Full_subtractor_S"

‎CH5/CH5-2/Full_subtractor_S.qsf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
4+
# Your use of Altera Corporation's design tools, logic functions
5+
# and other software and tools, and its AMPP partner logic
6+
# functions, and any output files from any of the foregoing
7+
# (including device programming or simulation files), and any
8+
# associated documentation or information are expressly subject
9+
# to the terms and conditions of the Altera Program License
10+
# Subscription Agreement, the Altera Quartus II License Agreement,
11+
# the Altera MegaCore Function License Agreement, or other
12+
# applicable license agreement, including, without limitation,
13+
# that your use is for the sole purpose of programming logic
14+
# devices manufactured by Altera and sold by Altera or its
15+
# authorized distributors. Please refer to the applicable
16+
# agreement for further details.
17+
#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
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# Date created = 17:08:29 August 26, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# Full_subtractor_S_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSXFC6D6F31C8
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set_global_assignment -name TOP_LEVEL_ENTITY Full_subtractor_S
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:08:29 AUGUST 26, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name BDF_FILE Full_subtractor_S.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE Full_subtractor_S.vwf
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set_global_assignment -name CDF_FILE output_files/Full_subtractor_S.cdf
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_location_assignment PIN_W25 -to A
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set_location_assignment PIN_V25 -to B
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set_location_assignment PIN_AC28 -to Bi
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set_location_assignment PIN_AF10 -to Bo
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set_location_assignment PIN_AD10 -to Do
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎CH5/CH5-2/Full_subtractor_S.qws‎

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