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如果採用，此提交將新增《數位邏輯實習 FPGA篇》所有實習項目
修改項目: 模組: 議題
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‎Digital_Logic_Practice/CH3/CH3-2/NAND_2.bdf‎

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‎Digital_Logic_Practice/CH3/NAND_2.bdf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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//#pragma file_not_in_maxplusii_format
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(header "graphic" (version "1.3"))
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(pin
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(input)
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(rect -8 8 160 24)
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(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
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(text "A" (rect 5 0 13 15)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 92 12)(pt 117 12)(line_width 1))
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(line (pt 121 8)(pt 168 8)(line_width 1))
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(line (pt 92 12)(pt 92 4)(line_width 1))
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(line (pt 117 4)(pt 121 8)(line_width 1))
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(line (pt 117 12)(pt 121 8)(line_width 1))
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)
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(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
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)
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(pin
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(input)
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(rect -8 24 160 40)
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(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
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(text "B" (rect 5 0 14 15)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 92 12)(pt 117 12)(line_width 1))
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(line (pt 92 4)(pt 117 4)(line_width 1))
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(line (pt 121 8)(pt 168 8)(line_width 1))
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(line (pt 92 12)(pt 92 4)(line_width 1))
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(line (pt 117 4)(pt 121 8)(line_width 1))
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(line (pt 117 12)(pt 121 8)(line_width 1))
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)
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(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
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)
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(pin
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(output)
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(rect 272 16 448 32)
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(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
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(text "F" (rect 90 0 98 15)(font "Arial" ))
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(pt 0 8)
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(drawing
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(line (pt 0 8)(pt 52 8)(line_width 1))
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(line (pt 82 8)(pt 78 12)(line_width 1))
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(line (pt 78 12)(pt 82 8)(line_width 1))
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)
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)
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(symbol
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(rect 184 0 248 48)
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(text "NAND2" (rect 1 0 41 13)(font "Arial" (font_size 6)))
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(text "inst" (rect 3 37 26 52)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
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(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
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(line (pt 0 32)(pt 15 32)(line_width 1))
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)
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(port
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(pt 0 16)
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(input)
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(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
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(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
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(line (pt 0 16)(pt 15 16)(line_width 1))
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)
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(port
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(pt 64 24)
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(output)
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(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
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(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
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(line (pt 52 24)(pt 64 24)(line_width 1))
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)
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(line (pt 15 37)(pt 32 37)(line_width 1))
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(arc (pt 32 36)(pt 32 12)(rect 20 12 45 37)(line_width 1))
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(circle (rect 44 20 52 28)(line_width 1))
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(connector
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(pt 160 16)
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(pt 184 16)
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)
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(connector
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(pt 160 32)
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(pt 184 32)
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)
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(connector
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(pt 248 24)
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(pt 272 24)
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)

‎Digital_Logic_Practice/CH3/NAND_2.cdf‎

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/* Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition */
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JedecChain;
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FileRevision(JESD32A);
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DefaultMfr(6E);
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P ActionCode(Cfg)
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Device PartName(EPM570T144) Path("E:/CH3/") File("NAND_2.pof") MfrSpec(OpMask(1) SEC_Device(EPM570T144) Child_OpMask(2 0 0));
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ChainEnd;
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AlteraBegin;
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ChainType(JTAG);
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AlteraEnd;

‎Digital_Logic_Practice/CH3/NAND_2.dpf‎

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<?xml version="1.0" encoding="UTF-8"?>
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<pin_planner>
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<pin_info>
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</pin_info>
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<buses>
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</buses>
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<group_file_association>
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</group_file_association>
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<pin_planner_file_specifies>
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</pin_planner_file_specifies>
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</pin_planner>

Digital_Logic_Practice/CH3/CH3-2/NAND_2.qpf renamed to Digital_Logic_Practice/CH3/NAND_2.qpf

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
5-
# and other software and tools, and its AMPP partner logic
6-
# functions, and any output files from any of the foregoing
7-
# (including device programming or simulation files), and any
8-
# associated documentation or information are expressly subject
9-
# to the terms and conditions of the Altera Program License
10-
# Subscription Agreement, Altera MegaCore Function License
11-
# Agreement, or other applicable license agreement, including,
12-
# without limitation, that your use is for the sole purpose of
13-
# programming logic devices manufactured by Altera and sold by
14-
# Altera or its authorized distributors. Please refer to the
15-
# applicable agreement for further details.
16-
#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 21:46:28 July 30, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "13.1"
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DATE = "21:46:28 July 30, 2019"
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# Revisions
29-
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PROJECT_REVISION = "NAND_2"
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2010 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
5+
# and other software and tools, and its AMPP partner logic
6+
# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
8+
# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
10+
# Subscription Agreement, Altera MegaCore Function License
11+
# Agreement, or other applicable license agreement, including,
12+
# without limitation, that your use is for the sole purpose of
13+
# programming logic devices manufactured by Altera and sold by
14+
# Altera or its authorized distributors. Please refer to the
15+
# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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# Date created = 20:53:05 July 16, 2014
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "9.1"
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DATE = "20:53:05 July 16, 2014"
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# Revisions
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30+
PROJECT_REVISION = "NAND_2"

Digital_Logic_Practice/CH3/CH3-2/NAND_2.qsf renamed to Digital_Logic_Practice/CH3/NAND_2.qsf

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@@ -1,75 +1,58 @@
1-
# -------------------------------------------------------------------------- #
2-
#
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# Copyright (C) 1991-2013 Altera Corporation
4-
# Your use of Altera Corporation's design tools, logic functions
5-
# and other software and tools, and its AMPP partner logic
6-
# functions, and any output files from any of the foregoing
7-
# (including device programming or simulation files), and any
8-
# associated documentation or information are expressly subject
9-
# to the terms and conditions of the Altera Program License
10-
# Subscription Agreement, Altera MegaCore Function License
11-
# Agreement, or other applicable license agreement, including,
12-
# without limitation, that your use is for the sole purpose of
13-
# programming logic devices manufactured by Altera and sold by
14-
# Altera or its authorized distributors. Please refer to the
15-
# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 21:46:28 July 30, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# NAND_2_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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38-
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE EP3C16F484C6
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set_global_assignment -name TOP_LEVEL_ENTITY NAND_2
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:46:28 JULY 30, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_location_assignment PIN_D2 -to A
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set_location_assignment PIN_E4 -to B
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set_location_assignment PIN_B1 -to F
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set_global_assignment -name BDF_FILE Work1.bdf
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set_global_assignment -name BDF_FILE NAND_2.bdf
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set_location_assignment PIN_E3 -to A1
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set_location_assignment PIN_H7 -to B1
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set_location_assignment PIN_J7 -to A2
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set_location_assignment PIN_G5 -to B2
63-
set_location_assignment PIN_G4 -to A3
64-
set_location_assignment PIN_H6 -to B3
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set_location_assignment PIN_B2 -to F1
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set_location_assignment PIN_C2 -to F2
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set_location_assignment PIN_E1 -to F4
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set_location_assignment PIN_F2 -to F5
69-
set_location_assignment PIN_H5 -to A4
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set_location_assignment PIN_F1 -to A5
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set_location_assignment PIN_J6 -to B4
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set_location_assignment PIN_G3 -to B5
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set_location_assignment PIN_C1 -to F3
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set_location_assignment PIN_H1 -to F6
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2010 Altera Corporation
4+
# Your use of Altera Corporation's design tools, logic functions
5+
# and other software and tools, and its AMPP partner logic
6+
# functions, and any output files from any of the foregoing
7+
# (including device programming or simulation files), and any
8+
# associated documentation or information are expressly subject
9+
# to the terms and conditions of the Altera Program License
10+
# Subscription Agreement, Altera MegaCore Function License
11+
# Agreement, or other applicable license agreement, including,
12+
# without limitation, that your use is for the sole purpose of
13+
# programming logic devices manufactured by Altera and sold by
14+
# Altera or its authorized distributors. Please refer to the
15+
# applicable agreement for further details.
16+
#
17+
# -------------------------------------------------------------------------- #
18+
#
19+
# Quartus II
20+
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
21+
# Date created = 20:53:05 July 16, 2014
22+
#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
27+
# 1) The default values for assignments are stored in the file:
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# NAND_2_assignment_defaults.qdf
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# If this file doesn't exist, see file:
30+
# assignment_defaults.qdf
31+
#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
34+
# and any changes you make may be lost or overwritten.
35+
#
36+
# -------------------------------------------------------------------------- #
37+
38+
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C5T144C8
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set_global_assignment -name TOP_LEVEL_ENTITY NAND_2
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:53:05 JULY 16, 2014"
44+
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
45+
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
46+
set_global_assignment -name BDF_FILE NAND_2.bdf
47+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
48+
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
49+
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
50+
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name MISC_FILE "E:/CH3/NAND_2.dpf"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
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set_global_assignment -name INCREMENTAL_COMPILATION OFF
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
58+
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

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