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如果採用，此提交將完成6-2範例與練習
修改項目: 模組: 議題
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‎VerilogHDL_Practice/CH6/CH6-2/block.v‎

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module block (D, Clk, X, Y);
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input D, Clk;
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output [3:0] X, Y;
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reg [3:0] X, Y;
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always @ (posedge Clk) begin
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X[0] = D;
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X[1] = X[0];
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X[2] = X[1];
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X[3] = X[2];
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Y[0] <= D;
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Y[1] <= Y[0];
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Y[2] <= Y[1];
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Y[3] <= Y[2];
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end
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endmodule // block

‎VerilogHDL_Practice/CH6/CH6-2/block/block.xpr‎

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="49" Path="/home/timmy/Git/Digital-Logic-Design/VerilogHDL_Practice/CH6/block/block.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="f4825676cef44aaa9af6c6646667ceb6"/>
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<Option Name="Part" Val="xc7a35tcsg324-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirIES" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="WTXSimLaunchSim" Val="7"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../block.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="block"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../block_test.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="block_test"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="PamDesignTestbench" Val=""/>
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<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
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<Simulator Name="IES">
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<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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</Simulator>
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<Simulator Name="Xcelium">
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<Option Name="Description" Val="Xcelium Parallel Simulator"/>
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</Simulator>
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="11">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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</Runs>
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<Board/>
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<DashboardSummary Version="1" Minor="0">
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<Dashboards>
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<Dashboard Name="default_dashboard">
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<Gadgets>
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<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
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</Gadget>
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<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
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</Gadget>
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<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
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</Gadget>
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<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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</Gadget>
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<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
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<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
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<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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</Gadget>
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<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
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</Gadget>
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</Gadgets>
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</Dashboard>
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<CurrentDashboard>default_dashboard</CurrentDashboard>
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</Dashboards>
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</DashboardSummary>
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</Project>

‎VerilogHDL_Practice/CH6/CH6-2/block_test.v‎

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`timescale 1ns / 1ps
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module block_test ();
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reg D, Clk = 0;
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wire [3:0] X, Y;
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block UUT (.D(D), .Clk(Clk), .X(X), .Y(Y));
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initial begin
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#80 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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#270 D = 1; #150 D = 0;
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end
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initial begin
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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#100 Clk = 1; #100 Clk = 0;
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end
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initial begin
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#6400;
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$finish;
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end
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endmodule // block_test

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