Skip to content

Commit 2537764

Browse files
committed
如果採用,此提交將修改說明文件
修改項目:
1 parent a2563fd commit 2537764

1 file changed

Lines changed: 3 additions & 2 deletions

File tree

README.md

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,3 @@
1-
# Learn VHDL
2-
學習VHDL的過程檔案。
1+
Learn VHDL
2+
===
3+
使用Altera DE0與Altera Cyclone V SoC Kit學習使用FPGA與VHDL的過程檔案。

0 commit comments

Comments
 (0)