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如果採用，此提交將新增Verilog硬體描述語言實務第二單元完成
修改項目: 模組: 議題
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‎Verilog/CH2/and_gate.qpf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
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# Date created = 16:33:18 十月 15, 2020
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "15.0"
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DATE = "16:33:18 十月 15, 2020"
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# Revisions
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PROJECT_REVISION = "and_gate"

‎Verilog/CH2/and_gate.qsf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition
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# Date created = 16:33:18 十月 15, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# and_gate_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSXFC6D6F31C8
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set_global_assignment -name TOP_LEVEL_ENTITY and_gate
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:33:18 十月 15, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION 15.0.2
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name VERILOG_FILE and_gate/and_gate.srcs/sources_1/new/and_gate.v
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set_global_assignment -name VERILOG_FILE and_gate/and_gate.srcs/sim_1/new/and_gate_test.v
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎Verilog/CH2/and_gate/and_gate.cache/wt/gui_handlers.wdf‎

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eof:779821452

‎Verilog/CH2/and_gate/and_gate.cache/wt/java_command_handlers.wdf‎

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‎Verilog/CH2/and_gate/and_gate.cache/wt/project.wpc‎

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eof:

‎Verilog/CH2/and_gate/and_gate.cache/wt/synthesis.wdf‎

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‎Verilog/CH2/and_gate/and_gate.cache/wt/synthesis_details.wdf‎

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eof:2511430288

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