Commit 71fdc54
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Add predefined project 1.0.2 (ECC hang bug fixed)
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- project/Predefined/2Ch8Way-1.0.2
- IPRepo-1.0.2
- Interface
- NVMeHostController4L
- src
- pcie_7x_0_core_top
- xgui
- NVMeHostController
- src
- pcie_7x_0_core_top
- xgui
- Tiger4NSC
- src
- DCDPRAM16x1280WC
- DPBDCFIFO16x128W_32x64R
- DPBDCFIFO16x128W_32x64R
- blk_mem_gen_v8_2/hdl
- doc
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO18x64W_9x128R
- DPBDCFIFO18x64W_9x128R
- blk_mem_gen_v8_2/hdl
- doc
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO32x64W_16x128R
- DPBDCFIFO32x64W_16x128R
- blk_mem_gen_v8_2/hdl
- doc
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO36x16DR
- DPBDCFIFO64x16DR
- DPBDCFIFO9x128W_18x64R
- DPBDCFIFO9x128W_18x64R
- blk_mem_gen_v8_2/hdl
- doc
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO128x64WC
- DPBSCFIFO40x64WC
- DPBSCFIFO64x64WC
- DPBSCFIFO80x64WC
- DRSCFIFO288x16WC
- sim
- tiger4nsc_v1_2_3-1_project
- Tiger4NSC_v1_2_3-1_project.cache/wt
- xgui
- V2NFC100DDR
- src
- SDPRAM_16A9024X32B4512
- SDPRAM_9A16x9B16
- c_sub
- xgui
- OpenSSD2_2Ch8Way-1.0.2
- OpenSSD2.srcs
- constrs_1/implementation
- sources_1
- bd/OpenSSD2
- hdl
- hw_handoff
- ip
- OpenSSD2_Dispatcher_uCode_0_0
- doc
- sim
- synth
- OpenSSD2_NVMeHostController_0_0
- sim
- src/pcie_7x_0_core_top
- sim
- source
- synth
- synth
- OpenSSD2_Tiger4NSC_0_0
- sim
- src
- DCDPRAM16x1280WC
- blk_mem_gen_v8_2
- hdl
- simulation
- sim
- synth
- DPBDCFIFO16x128W_32x64R
- DPBDCFIFO16x128W_32x64R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO18x64W_9x128R
- DPBDCFIFO18x64W_9x128R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO32x64W_16x128R
- DPBDCFIFO32x64W_16x128R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO36x16DR
- DPBDCFIFO36x16DR
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO64x16DR
- DPBDCFIFO64x16DR
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO9x128W_18x64R
- DPBDCFIFO9x128W_18x64R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO128x64WC
- DPBSCFIFO128x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO40x64WC
- DPBSCFIFO40x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO64x64WC
- DPBSCFIFO64x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO80x64WC
- DPBSCFIFO80x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DRSCFIFO288x16WC
- DRSCFIFO288x16WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- synth
- OpenSSD2_Tiger4NSC_1_0
- sim
- src
- DCDPRAM16x1280WC
- blk_mem_gen_v8_2
- hdl
- simulation
- sim
- synth
- DPBDCFIFO16x128W_32x64R
- DPBDCFIFO16x128W_32x64R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO18x64W_9x128R
- DPBDCFIFO18x64W_9x128R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO32x64W_16x128R
- DPBDCFIFO32x64W_16x128R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO36x16DR
- DPBDCFIFO36x16DR
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO64x16DR
- DPBDCFIFO64x16DR
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBDCFIFO9x128W_18x64R
- DPBDCFIFO9x128W_18x64R
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO128x64WC
- DPBSCFIFO128x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO40x64WC
- DPBSCFIFO40x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO64x64WC
- DPBSCFIFO64x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DPBSCFIFO80x64WC
- DPBSCFIFO80x64WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- DRSCFIFO288x16WC
- DRSCFIFO288x16WC
- blk_mem_gen_v8_2/hdl
- fifo_generator_v12_0/hdl
- sim
- synth
- synth
- OpenSSD2_V2NFC100DDR_0_0
- sim
- src
- SDPRAM_16A9024X32B4512
- blk_mem_gen_v8_2
- hdl
- simulation
- sim
- synth
- SDPRAM_9A16x9B16
- blk_mem_gen_v8_2
- hdl
- simulation
- sim
- synth
- c_sub
- c_addsub_v12_0/hdl
- c_reg_fd_v12_0/hdl
- sim
- synth
- xbip_addsub_v3_0/hdl
- xbip_dsp48_addsub_v3_0/hdl
- xbip_dsp48_wrapper_v3_0/hdl
- xbip_pipe_v3_0/hdl
- xbip_utils_v3_0/hdl
- synth
- OpenSSD2_V2NFC100DDR_1_0
- sim
- src
- SDPRAM_16A9024X32B4512
- blk_mem_gen_v8_2
- hdl
- simulation
- sim
- synth
- SDPRAM_9A16x9B16
- blk_mem_gen_v8_2
- hdl
- simulation
- sim
- synth
- c_sub
- c_addsub_v12_0/hdl
- c_reg_fd_v12_0/hdl
- sim
- synth
- xbip_addsub_v3_0/hdl
- xbip_dsp48_addsub_v3_0/hdl
- xbip_dsp48_wrapper_v3_0/hdl
- xbip_pipe_v3_0/hdl
- xbip_utils_v3_0/hdl
- synth
- OpenSSD2_auto_pc_0
- axi_protocol_converter_v2_1/doc
- sim
- synth
- OpenSSD2_auto_pc_1
- axi_protocol_converter_v2_1/doc
- sim
- synth
- OpenSSD2_auto_pc_2
- axi_protocol_converter_v2_1/doc
- sim
- synth
- OpenSSD2_auto_pc_3
- axi_protocol_converter_v2_1/doc
- sim
- synth
- OpenSSD2_auto_us_cc_df_0
- axi_dwidth_converter_v2_1/doc
- sim
- synth
- OpenSSD2_auto_us_cc_df_1
- axi_dwidth_converter_v2_1/doc
- sim
- synth
- OpenSSD2_axi_interconnect_0_0
- OpenSSD2_axi_interconnect_0_1
- OpenSSD2_axi_interconnect_0_2
- OpenSSD2_axi_interconnect_0_3
- OpenSSD2_blk_mem_gen_0_0
- doc
- sim
- synth
- OpenSSD2_clk_wiz_0_0
- doc
- OpenSSD2_m00_data_fifo_0
- axi_data_fifo_v2_1/doc
- sim
- synth
- OpenSSD2_m00_regslice_0
- axi_register_slice_v2_1/doc
- sim
- synth
- OpenSSD2_proc_sys_reset_0_0
- doc
- sim
- synth
- OpenSSD2_proc_sys_reset_2_0
- doc
- sim
- synth
- OpenSSD2_proc_sys_reset_3_0
- doc
- sim
- synth
- OpenSSD2_processing_system7_0_0
- doc
- hdl/verilog
- sim
- synth
- OpenSSD2_s00_regslice_0
- axi_register_slice_v2_1/doc
- sim
- synth
- OpenSSD2_s01_regslice_0
- axi_register_slice_v2_1/doc
- sim
- synth
- OpenSSD2_xbar_0
- axi_crossbar_v2_1/doc
- sim
- synth
- OpenSSD2_xbar_1
- axi_crossbar_v2_1/doc
- sim
- synth
- ui
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