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    <h1 id="logo"><a href="#">CUDA<span class="light">Tutorial</span></a></h1>
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          <h2>Tutorial Outline</h2>
		  To provide a profound understanding of how CUDA applications can achieve peak performance, the first two parts of this tutorial outline the modern CUDA architecture. Following a basic introduction, we expose how language features are linked to---and constrained by---the underlying physical hardware components. Furthermore, we describe common applications for massively parallel programming, offer a detailed breakdown of potential issues, and list ways to mitigate performance impacts. An exemplary analysis of PTX and SASS snippets illustrates how code patterns in CUDA are mapped to actual hardware instructions.
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In parts 3 and 4, we focus on novel features that were enabled by the arrival of CUDA 10+ toolkits and the Volta+ architectures, such as ITS, tensor cores, and the graph API. In addition to basic use case demonstrations, we outline our own experiences with these capabilities and their potential performance benefits. We also discuss how long-standing best practices are affected by these changes and describe common caveats for dealing with legacy code on recent GPU models. We show how these considerations can be implemented in practice by presenting state-of-the-art research into task-based GPU scheduling, and how the dynamic adjustment of thread roles and group configurations can significantly increase performance.
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    <div id="footer"> <span class="f-left">&copy; 2021 <a href="mailto:kerbl@cg.tuwien.ac.at">Michael Kenzel, Bernhard Kerbl, Martin Winter and Markus Steinberger</a></span> <span class="f-right">Design: <a href="http://www.davidkohout.cz">David Kohout</a></span> </div>
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