diff --git a/docs/developer-guide.md b/docs/developer-guide.md
index 0e49790..640804d 100644
--- a/docs/developer-guide.md
+++ b/docs/developer-guide.md
@@ -117,7 +117,7 @@ both banks is the cheapest proof that the board holds what you built.
 
 **Wiring a J-Link to the board.** The debug header is a row of pads labelled on the silkscreen,
 and five wires connect it to the J-Link's 20-pin header. Pin 1 is at the bottom-right corner of
-both connectors. The mapping is from the Spark Board SWD Connection Guide v1.1:
+both connectors. The mapping is:
 
 | J-Link pin       | Signal                 | Board pad      |
 | ---------------- | ---------------------- | -------------- |
diff --git a/docs/hardware/datasheet.md b/docs/hardware/datasheet.md
index bba4a12..797dec8 100644
--- a/docs/hardware/datasheet.md
+++ b/docs/hardware/datasheet.md
@@ -571,9 +571,8 @@ first board shipped. Source: the revision summary on the Rev2 schematic cover sh
   charging thresholds and timers.
 - Texas Instruments INA190 datasheet, SBOS863D: gain options, gain error, zero-current
   output offset and output swing.
-- BrainChip board test records: post-fabrication PCB test report (version 1.0, 2026-03-13),
-  PCB testing checklist and procedures (version 1.0, 2026-02-18) and Spark board SWD
-  connection guide (version 1.1, 2026-04-10).
+- BrainChip board test records: post-fabrication PCB test report (version 1.0, 2026-03-13)
+  and PCB testing checklist and procedures (version 1.0, 2026-02-18).
 - BrainChip AKD1500 documentation for the strap meanings and the Safe Mode clock behaviour.
 - Texas Instruments BQ27427 datasheet, SLUSEB5B: pin functions.
 - BrainChip product decisions of September 2026: the enclosure ships with the board, the box