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+# AkidaTag block diagram
+
+This page shows how the parts on the AkidaTag board connect to each other: the system
+block diagram, the power tree, every bus between the host and its peripherals, and the
+configuration the AKD1500 is strapped into. The engineering detail behind each block is in
+the [datasheet](datasheet.md); the buyer-facing summary is the
+[technical specifications](technical-specifications.md).
+
+| Document status | |
+|---|---|
+| Hardware described | AkidaTag hardware revision 2 |
+
+---
+
+## 1. System block diagram
+
+
+
+The board has seven functional groups. **Compute and memory** is the Nordic nRF5340
+host and the BrainChip AKD1500 AI co-processor, each with its own 16 MB SPI NOR flash.
+**Power system** takes 5 V from USB-C or a single-cell Li-ion battery through the BQ25185
+charger and power path, the BQ27427 fuel gauge and the on/off switch, and makes the 1.8 V,
+0.8 V and 3.3 V rails. **USB and debug** is the CP2105 USB-to-UART bridge on the USB-C
+data lines and the 10-pin SWD header. **RF front-end** is the antenna matching network and
+the 2.4 GHz chip antenna. **Sensors** are the ISM330DHCX six-axis IMU on I2C and two PDM
+MEMS microphones. **Expansion** is the camera header with a level-shifted SPI bus and a
+switched 3.3 V supply. **Indicators and controls** are the RGB LED, the white LED and the
+user button.
+
+| Block | Part |
+|---|---|
+| nRF5340 | Nordic nRF5340-QKAA (U3); 32 MHz and 32.768 kHz crystals |
+| AKD1500 | BrainChip AKD1500 (U7); 25 MHz crystal |
+| Flash (MCU), Flash (AI) | Winbond W25Q128JWPIQ, 128 Mbit (IC1, IC2) |
+| RF matching, chip antenna | Abracon AMCA31-2R450G-S1F-T3 (AE1); U.FL footprint J3 not fitted |
+| 6-axis IMU | STMicroelectronics ISM330DHCX (U5) |
+| PDM mic 1, PDM mic 2 | Infineon IM73D122V01XTMA1 (U19, U20) |
+| SPI camera header | 10-pin 1.27 mm header J1 behind two SN74AXC2T245 level shifters (U14, U15) |
+| Charger + fuel gauge | Texas Instruments BQ25185 (U13) and BQ27427 (U12) |
+| On/off switch | Slide switch SW2 |
+| Power rails | TPS631000 1.8 V buck-boost (U1), TLV62585 0.8 V buck (U11), TPS7A2033 3.3 V LDO (U16), five TPS22991 load switches, two INA190A3 current-sense amplifiers |
+| USB-C | Würth 632722200211 receptacle J5 |
+| USB-UART bridge | Silicon Labs CP2105 (U6) |
+| SWD header | 10-pin 1.27 mm header J2 |
+| RGB LED + white LED | Würth 150505M173300 (D1), Inolux IN-S42ATUW (LED1) |
+| User button | Tactile switch SW1 |
+
+The buses in the figure are detailed in section 3; the power rails and enables in
+section 2.
+
+### Changes from the earlier diagram
+
+Revision 2 is the first board shipped, but an earlier system block diagram of the
+first revision has circulated, so the differences are worth stating. That board had a
+20-pin expansion connector carrying GPIO, I2S, I2C, SPI, USB and UART, three buttons, 4-pin
+SWD debug pads, two status LEDs, a fitted U.FL connector and a 42 mm x 30 mm outline.
+Revision 2 replaces the expansion connector with the 10-pin camera header, has one button
+and an on/off switch, a 10-pin SWD header, an RGB LED and a white LED, an unfitted U.FL
+footprint, two current-sense amplifiers, and a 27.7 mm x 39.5 mm outline. The processors,
+flashes, radio, IMU, microphones, charger and fuel gauge are the same. Sources: the
+revision 2 netlist, bill of materials and board outline; the earlier system block diagram
+and labelled layout drawing.
+
+---
+
+## 2. Power tree
+
+
+
+Power enters from the USB-C receptacle J5 (VBUS, 5 V) or from the battery on J4. The
+BQ25185 charger's power path produces the SYS node, which reaches the rest of the board
+only through the on/off slide switch SW2 as VCC_SYS (3.0 to 4.2 V). VCC_SYS feeds four
+things directly: the TPS631000 buck-boost that makes the 1.8 V system rail, the TLV62585
+buck that makes the 0.8 V AKD1500 core rail, the TPS7A2033 LDO that makes the 3.3 V
+camera rail, and the anodes of the RGB and white LEDs.
+
+The 1.8 V rail passes through a 0.1 ohm shunt watched by INA190 U18, then powers the
+nRF5340, the CP2105 bridge, flash IC1 and the pull-up resistors, and feeds three TPS22991
+load switches: U10 for the AKD1500 I/O and its flash IC2, U4 for the IMU, and U8 for the
+microphones. The 0.8 V buck is enabled through a fourth load switch, U9, and its output
+passes through a 0.02 ohm shunt watched by INA190 U17. The 3.3 V rail powers the B side
+of the camera level shifters and, through the fifth load switch U2, the camera header.
+Each switch has a pull-down on its enable, so every switched rail is off until the
+firmware drives the enable high.
+
+| Enable | nRF5340 pin | Switch | Rail |
+|---|---|---|---|
+| VDD_1V8_AKD_EN | P0.19 | U10 | VDD_1V8_AKD |
+| VDD_1V8_ACC_EN | P0.20 | U4 | VDD_1V8_ACC |
+| VDD_1V8_PDM_EN | P0.21 | U8 | VDD_1V8_PDM |
+| VDD_0V8_AKD_EN | P0.22 | U9, then TLV62585 EN | VDD_0V8_AKD |
+| CAM_PWR_EN | P1.06 | U2 | VDD_3V3_1V8_CAM |
+
+The battery sits behind the BQ27427 fuel gauge: the charger's BAT pin reaches the gauge's
+SRX sense input, and the gauge's BAT pin reaches the connector, which is the orientation the
+BQ27427 datasheet specifies. The gauge is on I2C1 at
+address 0x55 and raises its GPOUT interrupt line to P0.30 when the state of charge
+changes. The charger's STAT1 and STAT2 outputs go to P0.23 and P0.24 with pull-ups; a
+10 kilohm NTC thermistor is on the charger's TS pin and a second on the gauge's BIN pin.
+
+---
+
+## 3. Buses and signals
+
+### 3.1 Host to AKD1500: SPIM4
+
+| Signal | nRF5340 | AKD1500 | Notes |
+|---|---|---|---|
+| SCK | P0.08 | SPI_S_SCK | Test point TP5; high-drive pin mode in firmware |
+| MOSI | P0.09 | SPI_S_IO0 | |
+| MISO | P0.10 | SPI_S_IO1 | |
+| CS0 | P0.11 | SPI_S_CS_N | 10 kilohm pull-up to VDD_1V8_AKD |
+| CS1 | P0.12 | SPI_S_2MCS0_N | 10 kilohm pull-up; selects the AKD1500's flash through its slave-to-master feed-through |
+| SLEEP | P1.07 | SLEEP | Through 0 ohm R48; firmware `akd_lp`, asserted between inferences |
+| PWR_GOOD | P1.05 | PWR_GOOD | Through 0 ohm R47; 10 kilohm pull-up to VDD_1V8_AKD; not driven by the firmware |
+| GPIO0 | P1.11 | GPIO_00 | Not used by the firmware |
+| GPIO1 | P1.12 | GPIO_01 | Not used by the firmware |
+| GPIO2 | P0.02 | GPIO_02 | Not used by the firmware; test point TP16 |
+| GPIO3 | P0.03 | GPIO_03 | Firmware `akd_async`, inference-complete interrupt |
+
+The firmware runs this bus at 8 MHz by default and supports up to 32 MHz; the AKD1500's
+second chip-select line (SPI_S_2MCS1_N) is pulled up and unused.
+
+### 3.2 AKD1500 to its flash: SPI master
+
+| AKD1500 | Flash IC2 | Notes |
+|---|---|---|
+| SPI_M_CS0_N | S# | 10 kilohm pull-up |
+| SPI_M_SCK | C | Test point TP10 |
+| SPI_M_IO0..IO3 | DQ0..DQ3 | Quad wiring with 4.7 kilohm pull-ups on the data lines |
+| SPI_M_CS1_N | test point TP14 only | Second flash position not fitted |
+| SPI_M_SCKX | test point TP15 only | |
+
+IC2 is powered from VDD_1V8_AKD, so it is off whenever the AKD1500 I/O rail is off.
+
+### 3.3 Host to flash IC1: SPIM3
+
+| Signal | nRF5340 | Flash IC1 | Notes |
+|---|---|---|---|
+| SCK | P0.17 | C | Test point TP4 |
+| MOSI | P0.13 | DQ0 | |
+| MISO | P0.14 | DQ1 | |
+| CS | P0.18 | S# | 10 kilohm pull-up |
+| W#/DQ2 | P0.15 | DQ2 | Pulled up; single-lane operation in firmware |
+| HOLD#/DQ3 | P0.16 | DQ3 | Pulled up; single-lane operation in firmware |
+
+IC1 is on the always-on 1.8 V rail, which is what lets MCUboot read the update slot before
+the application has enabled anything.
+
+### 3.4 I2C1: IMU and fuel gauge
+
+| Signal | nRF5340 | Devices | Notes |
+|---|---|---|---|
+| SCL | P1.03 | ISM330DHCX SCL, BQ27427 SCL | 2.2 kilohm pull-up to VDD_1V8_ACC |
+| SDA | P1.02 | ISM330DHCX SDA, BQ27427 SDA | 2.2 kilohm pull-up to VDD_1V8_ACC |
+| IMU INT1 | P0.31 | ISM330DHCX INT1 | |
+| IMU INT2 | P1.00 | ISM330DHCX INT2 | Not used by the firmware |
+| Gauge interrupt | P0.30 | BQ27427 GPOUT | 10 kilohm pull-up |
+
+The IMU's SA0 pin is grounded, giving address 0x6A; the gauge answers at 0x55. The bus
+pull-ups hang off the switched IMU rail, so the bus is only pulled up while VDD_1V8_ACC is
+enabled.
+
+### 3.5 PDM: microphones
+
+| Signal | nRF5340 | Microphones | Notes |
+|---|---|---|---|
+| CLOCK | P1.09 | U19 CLOCK, U20 CLOCK | |
+| DATA | P1.10 | U19 DATA, U20 DATA | 100 ohm series resistor on each microphone |
+
+U19's SELECT pin is tied to its supply and U20's to ground, so the two microphones occupy
+opposite channels of the PDM frame. Both are powered from VDD_1V8_PDM through a ferrite
+bead each.
+
+### 3.6 Camera header J1
+
+| Signal | nRF5340 | Level shifter | J1 pin |
+|---|---|---|---|
+| CLK | P0.06 | U15 A1 to B1 | 3 |
+| MOSI | P0.07 | U15 A2 to B2 | 5 |
+| MISO | P0.26 | U14 A1 from B1 | 4 |
+| CS | P0.25 | U14 A2 to B2 | 6 |
+| Output enable | P1.15 | U14 and U15 OE (active low), 100 kilohm pull-downs | |
+| Supply enable | P1.06 | Load switch U2 | 1, 2 |
+
+The shifters' A side is VDD_1V8 and their B side is the 3.3 V rail; a 1.8 V option for
+the B side and for the header supply exists through resistors that are not fitted.
+
+### 3.7 USB-C and console UART
+
+| Signal | Path |
+|---|---|
+| VBUS | J5 VBUS pins, TVS, ferrite bead L11, then the charger input and the CP2105 REGIN |
+| D+, D- | J5, TVS array D2, CP2105 D+ and D- |
+| CC1, CC2 | 5.1 kilohm pull-downs (sink) |
+| Console TX | nRF5340 P0.29 to CP2105 RXD_SCI, test point TP11 |
+| Console RX | nRF5340 P1.04 from CP2105 TXD_SCI, test point TP13 |
+| CP2105 ECI port | Not connected |
+| Shell | Chassis net through a ferrite bead |
+
+### 3.8 SWD header J2
+
+| J2 pin | Signal |
+|---|---|
+| 1 | VDD_1V8 |
+| 2 | SWDIO (nRF5340 SWDIO, ESD diode D5, 10 kilohm pull-up) |
+| 3, 5, 9 | GND |
+| 4 | SWDCLK (nRF5340 SWDCLK, ESD diode D4, 10 kilohm pull-up) |
+| 6 | nRESET (nRF5340 RESET, ESD diode D3) |
+| 7, 8, 10 | Not connected |
+
+### 3.9 Radio
+
+The nRF5340 ANT pin passes through a 2.2 nH series inductor with a 0.1 uF shunt to a
+fitted 0 ohm link (R8) into the chip antenna AE1. A second link (R9, not fitted) leads to
+the U.FL footprint J3.
+
+### 3.10 LEDs and controls
+
+| Signal | nRF5340 | Circuit |
+|---|---|---|
+| LED_R | P1.14 | Q2 base; D1 red cathode through 500 ohm |
+| LED_G | P0.27 | Q3 base; D1 green cathode through 249 ohm |
+| LED_B | P1.13 | Q1 base; D1 blue cathode through 249 ohm |
+| LED_W_1 | P0.28 | Q4 base; LED1 cathode through 270 ohm |
+| USER_IO | P1.01 | SW1 to ground, 10 kilohm pull-up to VDD_1V8 |
+
+D1's common anode and LED1's anode are on VCC_SYS. Q1 to Q4 are pre-biased NPN
+transistors (DTC043ZUB), so each LED is on when its host pin is high.
+
+### 3.11 Current sense
+
+| Rail | Shunt | Amplifier | nRF5340 |
+|---|---|---|---|
+| VDD_1V8 | R55, 0.1 ohm | INA190A3 U18, gain 100 V/V | P0.04 (AIN0), test point TP7 |
+| VDD_0V8_AKD | R28, 0.02 ohm | INA190A3 U17, gain 100 V/V | P0.05 (AIN1), test point TP6 |
+
+Both amplifiers run from VDD_1V8 with their enable pins tied high. The A3 gain option is
+100 V/V per the Texas Instruments INA190 datasheet (SBOS863D).
+
+---
+
+## 4. AKD1500 configuration
+
+| Pin | Board setting | Meaning on this board |
+|---|---|---|
+| PCIE_HOST_SEL | Low (0 ohm to ground; pull-up not fitted) | SPI host interface selected |
+| SEL_CLK | Low (0 ohm to ground; pull-up not fitted) | Crystal reference on OSC_XI and OSC_XO |
+| SPI_S_MODE0, SPI_S_MODE1 | Low, low (0 ohm to ground; pull-ups not fitted) | Single-lane SPI slave |
+| OP_MODE0 | Low (0 ohm to ground; pull-up not fitted) | Crystal oscillator is the internal clock source |
+| OP_MODE1 | High (10 kilohm to VDD_1V8_AKD; pull-down not fitted) | Safe Mode: the chip stays on the 25 MHz reference after reset and the host switches it onto the PLL once the PLL locks; the firmware does this before raising the host SPI clock, since the host clock must stay at or below a quarter of the AKD1500's SPI slave core clock |
+| TAP_SEL, TESTMODE | Low (0 ohm to ground) | Test access off |
+| PCIE_PERST_N | Not connected (resistor not fitted) | PCIe unused |
+| PCIe receive lanes and reference clock inputs | Tied to ground | PCIe unused |
+| PCIe transmit lanes | Not connected | PCIe unused |
+| PCIe PHY supplies (VP, VPH, VPTX0, VPTX1) | 0 ohm to ground | PCIe unused |
+| RESREF | 200 ohm to ground | Reference resistor |
+| Crystal | 25 MHz (ABM10W-25.0000MHZ-7-B1U-T3), 7 pF load capacitors, 1 megohm feedback resistor, 0 ohm series link on OSC_XI | |
+| PLL supplies | VDDAPLL18 from VDD_1V8_AKD through ferrite bead L8; VDDPLL08 from VDD_0V8_AKD through ferrite bead L9; AVS_PLL to ground | |
+| eFuse supplies (VDDIO_EFUSE, VQPS_EFUSE, VPD) | Not connected | Fuse programming unused |
+
+---
+
+## Sources
+
+The revision 2 schematic (SI-NRF-AKD_BRD-002 V11, 2026-08-25), netlist report, bill of
+materials and board outline; the earlier system block diagram and labelled layout
+drawing (January 2026); the Texas Instruments INA190 datasheet (SBOS863D) and BQ27427
+datasheet (SLUSEB5B); BrainChip AKD1500 documentation for the strap meanings; and the
+firmware board overlay `src/boards/nrf5340_cpuapp_akidatag.overlay`,
+`src/core/interface/gpio/gpio.c`, `src/core/interface/akd_spi_flash/akd_spi_flash_handler.cpp`
+and `src/README.md` on `main`.
+
+---
+
+© 2026 BrainChip Holdings Ltd. All rights reserved.
diff --git a/docs/hardware/datasheet.md b/docs/hardware/datasheet.md
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+# AkidaTag datasheet
+
+AkidaTag is a battery-powered, Bluetooth Low Energy edge-AI development device that pairs a
+Nordic nRF5340 wireless system-on-chip with the BrainChip AKD1500 Akida neuromorphic
+co-processor. It carries two MEMS microphones, a six-axis inertial sensor, a camera
+expansion header, on-board model storage, a single-cell Li-ion charger and fuel gauge, and
+a USB-C port for charging and firmware update. The companion BrainChip Connect mobile
+application connects to it over Bluetooth to load models and run the demonstrations.
+
+This page is the engineering reference for the board. The buyer-facing summary is the
+[technical specifications](technical-specifications.md) page, and the circuit-level view
+is the [block diagram](block-diagram.md) page.
+
+| Document status | |
+|---|---|
+| Hardware described | AkidaTag hardware revision 2, design NRF-AKD1500-002 |
+| Firmware referenced | The AkidaTag firmware in this repository; the current build is the [latest release](https://github.com/Brainchip-Inc/AkidaTag/releases/latest) |
+
+---
+
+## 1. Features
+
+- **Host processor:** Nordic nRF5340, dual Arm Cortex-M33; 128 MHz application core with
+ 1 MB flash and 512 KB RAM, 64 MHz network core running the Bluetooth Low Energy
+ controller.
+- **AI co-processor:** BrainChip AKD1500 Akida neuromorphic processor, 22 nm FD-SOI,
+ 7 mm x 7 mm BGA, driven over a dedicated high-speed SPI host interface at up to 32 MHz,
+ with a 25 MHz crystal and an internal PLL for a core clock of up to 400 MHz.
+- **On-device learning:** the AKD1500 learns new classes on the device itself; the
+ firmware exposes this over Bluetooth for keyword spotting.
+- **Model storage:** 16 MB SPI NOR flash attached to the AKD1500's own SPI master port,
+ written by the host through the AKD1500's slave-to-master feed-through.
+- **Firmware storage:** 16 MB SPI NOR flash on the nRF5340 holding the firmware update
+ slot and a LittleFS file system.
+- **Audio:** two digital PDM MEMS microphones on a shared PDM bus, powered through a
+ switched rail.
+- **Motion:** STMicroelectronics ISM330DHCX six-axis accelerometer and gyroscope on I2C,
+ with its INT1 line to the host.
+- **Camera expansion:** 10-pin 1.27 mm header with a level-shifted SPI bus and a switched
+ 3.3 V supply, used by the firmware with an ArduCam Mega SPI camera.
+- **Wireless:** Bluetooth Low Energy through an on-board 2.4 GHz chip antenna, with an
+ unpopulated U.FL footprint for a test connector.
+- **Power:** single-cell Li-ion battery (not supplied) with a BQ25185 linear charger and power path, a
+ BQ27427 fuel gauge, a 1.8 V buck-boost converter, a 0.8 V buck converter for the
+ AKD1500 core, a 3.3 V LDO for the camera header, five load switches under firmware
+ control, and two INA190 current-sense amplifiers feeding the nRF5340 ADC so the
+ firmware can measure the 1.8 V and 0.8 V rails.
+- **USB-C:** 5 V input for charging and a CP2105 USB-to-UART bridge for the console and
+ for MCUboot serial recovery. The nRF5340's own USB pins are not connected.
+- **Indicators and controls:** one RGB LED, one white LED, one push button and an on/off
+ slide switch.
+- **Debug:** 10-pin 1.27 mm SWD header.
+- **Board:** 27.7 mm x 39.5 mm, six-layer PCB.
+
+---
+
+## 2. Block diagram
+
+
+
+The figure names blocks only; the part in each block is in section 3, and the
+[block diagram page](block-diagram.md) lists them in one table.
+
+The nRF5340 owns every peripheral. The AKD1500 is a slave on the nRF5340's SPIM4 bus and
+in turn masters its own NOR flash; the nRF5340 reaches that flash through the AKD1500's
+feed-through on the second chip select. Power enters from USB-C or the battery, passes
+through the charger's power path and the slide switch, and is split into the 1.8 V system
+rail, the 0.8 V AKD1500 core rail and the 3.3 V camera rail, with the AKD1500, IMU,
+microphone and camera supplies each behind a load switch that the firmware turns on.
+
+---
+
+## 3. Functional description
+
+### 3.1 Host processor: nRF5340
+
+The host is a Nordic nRF5340 system-on-chip (NRF5340-QKAA-R7, aQFN94 package). Its
+application core runs the AkidaTag firmware, a Zephyr RTOS application built with the
+nRF Connect SDK; its network core runs the Bluetooth Low Energy controller. The firmware
+raises the application core to 128 MHz, which SPIM4 needs to reach 32 MHz.
+
+| Item | Value | Source |
+|---|---|---|
+| Cores | Two Arm Cortex-M33: application core up to 128 MHz, network core 64 MHz | Nordic nRF5340 product page |
+| Application core memory | 1 MB flash, 512 KB RAM | Nordic nRF5340 product page; firmware partition map |
+| Network core memory | 256 KB flash, 64 KB RAM | Nordic nRF5340 product page |
+| Radio | Bluetooth Low Energy (Bluetooth 5.4 qualified silicon) | Nordic nRF5340 product page |
+| High-frequency crystal | 32 MHz (X1) | Rev2 bill of materials |
+| Low-frequency crystal | 32.768 kHz (Y1) | Rev2 bill of materials |
+| Supply | VDD_1V8 on all VDD pins and VDDH, that is normal-voltage mode at 1.8 V | Rev2 netlist |
+| NFC pins | Re-purposed as GPIO for AKD1500 GPIO2 and GPIO3; the firmware programs `nfct-pins-as-gpios` into UICR, a one-time setting | Board overlay, `src/README.md` |
+| Application core clock in firmware | 128 MHz (`CONFIG_SYS_CPU_128MHZ`) | `src/Kconfig` |
+
+The nRF5340's USB interface, VBUS pin and NFC antenna interface are not used on this board.
+
+### 3.2 AI co-processor: AKD1500
+
+The BrainChip AKD1500 is an event-based neuromorphic AI accelerator built on the Akida
+neuron fabric. On AkidaTag it is used as an SPI-attached co-processor: the host loads a
+compiled model into it, streams pre-processed sensor data in, and reads inference results
+back. The chip can learn new classes on the device.
+
+| Item | Value | Source |
+|---|---|---|
+| Part | BrainChip AKD-1500, MFCTFBGA169, 7 mm x 7 mm, 0.5 mm ball pitch | AKD1500 product brief V2.4 |
+| Process | 22 nm FD-SOI | AKD1500 product brief V2.4 |
+| On-chip memory | 1 MB | AKD1500 product brief V2.4 |
+| Host interface used | SPI slave, single lane, from nRF5340 SPIM4 | Rev2 netlist; board overlay |
+| Memory expansion | SPI master port to NOR flash IC2, quad data lines wired | Rev2 netlist |
+| Clock reference | 25 MHz crystal (XTAL1, ABM10W-25.0000MHZ-7-B1U-T3) | Rev2 bill of materials |
+| Core clock in firmware | 400 MHz default from the internal 800 MHz PLL; 5 to 400 MHz selectable | `src/Kconfig`, `src/README.md`; product brief gives the 5 to 400 MHz range |
+| Host SPI clock in firmware | 8 MHz default, runtime selectable 1 to 32 MHz | `src/Kconfig`, `src/README.md` |
+| Supplies | 0.8 V core (VDD_0V8_AKD), 1.8 V I/O (VDD_1V8_AKD); PLL supplies through ferrite beads from the same rails; PCIe PHY supplies tied to ground | Rev2 netlist |
+| Strapping | PCIe host select low (SPI host); SEL_CLK low (crystal oscillator); SPI slave mode pins low; OP_MODE0 low (crystal as the clock source); OP_MODE1 high (Safe Mode, see below); TAP_SEL and TESTMODE low | Rev2 netlist; BrainChip AKD1500 documentation for the strap meanings |
+| Host control lines | SLEEP from P1.07; PWR_GOOD from P1.05 (pulled up on the board); GPIO0..GPIO3 to P1.11, P1.12, P0.02, P0.03 | Rev2 netlist |
+| Reset | No host-driven reset line is wired; PCIE_PERST_N is left unconnected | Rev2 netlist |
+
+Between inferences the firmware asserts SLEEP, which gates the AKD1500 clocks while the
+loaded model is retained, and releases it on demand with a reference count. The
+`app stop` command additionally turns the AKD1500 PLL off for the lowest idle power.
+GPIO3 (P0.03) is the completion interrupt the firmware waits on after each inference.
+
+OP_MODE1 is strapped high, which puts the AKD1500 in Safe Mode: after reset it stays on the
+25 MHz reference clock instead of switching itself onto its PLL, and the host has to make
+that switch once the PLL reports lock. The firmware does this at a low host SPI clock and
+only then raises the clock, because the AKD1500 requires the host clock to stay at or below
+a quarter of its SPI slave core clock, which caps the host at a few megahertz while the
+reference clock is in use. Source: `src/core/interface/akd_spi_flash/akd_spi_flash_handler.cpp`,
+which documents the mode and performs the switch.
+
+### 3.3 Memory
+
+Two 128 Mbit (16 MB) SPI NOR flash devices are fitted.
+
+| Device | Bus | Contents |
+|---|---|---|
+| IC1, on nRF5340 SPIM3 (chip select P0.18) | Single-lane SPI at 8 MHz; the DQ2 and DQ3 lines are pulled up and unused | MCUboot secondary (update) slot, 960 KB, then a LittleFS volume from 0xF0000 to 0x800000 |
+| IC2, on the AKD1500 SPI master port | Quad SPI wired from the AKD1500; reached from the nRF5340 through the AKD1500 feed-through on SPIM4 chip select P0.12 | AKD1500 model program and the model metadata records |
+
+The nRF5340 internal flash holds MCUboot (48 KB at 0x0), the primary application slot
+(960 KB from 0xC000, including the 512-byte image header) and 8 KB of settings storage at
+0xFC000. Application RAM is 448 KB, with the top 64 KB reserved for the inter-core
+channel. Source: `src/pm_static.yml`.
+
+The firmware's partition map uses the first 8 MB of IC1. Source: `src/pm_static.yml`.
+
+Both positions are fitted with the Winbond W25Q128JWPIQ (1.8 V, 128 Mbit) listed in the
+Rev2 bill of materials. The firmware on `main` still identifies the devices by the JEDEC ID
+of the Micron part named in the schematic symbols, so it does not match the fitted part.
+
+### 3.4 Audio: microphones
+
+Two Infineon IM73D122V01XTMA1 digital PDM MEMS microphones (U19, U20) share one PDM clock
+(P1.09) and one data line (P1.10), each through a 100 ohm series resistor. Their SELECT pins are tied
+opposite ways, so each occupies one channel of the stereo PDM frame. They are powered from
+the switched VDD_1V8_PDM rail (load switch U8, enable P0.21) through ferrite beads.
+
+The firmware captures one channel, the left slot of the PDM frame, at 16 kHz, 16-bit, with
+a PDM clock between 1.0 and 1.2 MHz, and sets the PDM gain register directly because the
+Zephyr DMIC API has no gain field. The keyword spotting demonstration runs on that single
+channel; the second microphone is available to firmware that requests both. Source:
+`src/core/interface/audio/pdm_mic.c`, `src/include/audio/pdm_mic.h`.
+
+The part number is from the Rev2 bill of materials. The footprint name in the design files
+and the notes in this repository still carry the name of a different Infineon part, the
+IM69D130.
+
+### 3.5 Motion: inertial measurement unit
+
+An STMicroelectronics ISM330DHCX six-axis accelerometer and gyroscope (U5) sits on I2C1
+(SCL P1.03, SDA P1.02, 400 kHz) at address 0x6A, with INT1 to P0.31 and INT2 to P1.00. It
+is powered from the switched VDD_1V8_ACC rail (load switch U4, enable P0.20).
+
+The firmware defaults are 208 Hz output data rate for both sensors, plus or minus 8 g
+accelerometer full scale and plus or minus 500 degrees per second gyroscope full scale, in
+polling mode with FIFO batching. Source: `src/imu_app.conf`, `src/Kconfig`.
+
+### 3.6 Camera and expansion header
+
+J1 is a 10-pin, 1.27 mm pitch header intended for an SPI camera. Its four SPI signals
+pass through two SN74AXC2T245 bidirectional level shifters (U14, U15) whose A side is
+VDD_1V8 and whose B side is the 3.3 V rail, and whose output enable is driven by P1.15.
+The header's supply pins are fed by load switch U2 (enable P1.06) from the 3.3 V LDO
+output; a 1.8 V option exists through unpopulated resistors.
+
+The firmware drives an ArduCam Mega camera and supports 96 x 96 and 128 x 128 RGB
+frames. Source: `src/README.md`, `src/include/camera/spi_camera.h`.
+
+See section 5.3 for the pinout and section 4 for a difference between the header's wiring
+and the pins the current firmware uses.
+
+### 3.7 Wireless
+
+The nRF5340 ANT pin is matched with a 2.2 nH inductor and shunt capacitor to an Abracon
+AMCA31-2R450G-S1F-T3 2.4 GHz chip antenna (AE1) through a fitted 0 ohm link (R8). A
+U.FL receptacle footprint (J3) is on the board, connected through R9, which is not fitted.
+Source: Rev2 netlist and bill of materials.
+
+Bluetooth Low Energy behaviour is set by the firmware; see section 8.
+
+Nordic specifies the nRF5340 radio for a configurable transmit power of -40 to +3 dBm and
+a receiver sensitivity of -98 dBm at 1 Mbps. The firmware does not set a transmit power, so
+the Bluetooth controller's default applies. Source: nRF5340 product specification, key
+features; `src/prj.conf`.
+
+### 3.8 USB-C and console
+
+J5 is a USB Type-C receptacle. Both CC pins carry 5.1 kilohm pull-downs, so the port
+presents as a sink, and VBUS feeds the charger input and the CP2105 through a ferrite bead
+(L11). D+ and D- go to a Silicon Labs CP2105 dual USB-to-UART bridge (U6) behind an
+SP0503 TVS array. Only the CP2105's standard port (SCI) is wired: its RXD receives the
+nRF5340 console transmit (P0.29) and its TXD drives the nRF5340 receive (P1.04). The
+enhanced port (ECI) is unconnected, which is why the board presents two serial ports of
+which only one carries data.
+
+The console runs at 115200 baud, 8N1, and is the Zephyr shell of the application. The
+same UART is the MCUboot serial recovery channel: at every boot MCUboot listens for about
+one second for an mcumgr command, so firmware can be updated over the cable with no button
+and no probe. Source: `src/sysbuild/mcuboot.conf`,
+[firmware update over USB](../firmware-update-over-usb.md).
+
+### 3.9 Debug: SWD
+
+J2 is a 10-pin, 1.27 mm pitch header carrying SWDIO, SWDCLK and reset, with ESD diodes
+on all three lines. Its pinout is in section 5.4. The board's reference voltage on this
+header is VDD_1V8.
+
+Pin 6 carries nRESET and pin 10 is not connected, as the revision 2 schematic wires it. That
+differs from the Arm 10-pin Cortex Debug layout, which puts SWO on pin 6 and nRESET on
+pin 10, so a probe's reset line does not reach the board through a pin-to-pin cable.
+
+### 3.10 Indicators and controls
+
+| Item | Part | Drive | Host pin |
+|---|---|---|---|
+| RGB LED red | D1 (Würth 150505M173300, common anode to VCC_SYS) | NPN transistor Q2, active high | P1.14 |
+| RGB LED green | D1 | Q3, active high | P0.27 |
+| RGB LED blue | D1 | Q1, active high | P1.13 |
+| White LED | LED1 (Inolux IN-S42ATUW, anode to VCC_SYS) | Q4, active high | P0.28 |
+| Push button | SW1, tactile, to ground with a 10 kilohm pull-up to VDD_1V8 | Input, active low | P1.01 |
+| On/off switch | SW2, slide, in series between the charger SYS output and VCC_SYS | Not readable by the host | none |
+
+Source: Rev2 netlist and bill of materials. See section 4 for how the current firmware maps
+its LED states onto these pins.
+
+### 3.11 Power subsystem
+
+
+
+| Stage | Part | Input | Output | Notes |
+|---|---|---|---|---|
+| Charger and power path | Texas Instruments BQ25185 (U13) | VBUS 5 V | SYS to the board, BAT to the battery | STAT1 and STAT2 to P0.23 and P0.24; R85 (560 ohm) on ISET sets a nominal 536 mA fast-charge current; R84 (13 kilohm) on ILIM/VSET selects 4.2 V battery regulation and a 1100 mA input current limit; a 10 kilohm NTC on the TS pin |
+| Fuel gauge | Texas Instruments BQ27427 (U12) | In the battery path | I2C1 address 0x55, SOC interrupt (GPOUT) to P0.30 | Impedance Track gauge; the firmware writes design capacity and taper parameters at start-up |
+| On/off | SW2 slide switch | SYS | VCC_SYS | Disconnects the whole board except the charger |
+| 1.8 V rail | Texas Instruments TPS631000 buck-boost (U1) | VCC_SYS | VDD_1V8 | Feeds the nRF5340, the CP2105 I/O, flash IC1, the pull-ups and the four 1.8 V load switches; passes through the 0.1 ohm shunt R55 read by INA190 U18 |
+| 0.8 V rail | Texas Instruments TLV62585 buck (U11) | VCC_SYS | VDD_0V8_AKD | AKD1500 core; enabled by P0.22 through load switch U9; passes through the 0.02 ohm shunt R28 read by INA190 U17 |
+| 3.3 V rail | Texas Instruments TPS7A2033 LDO (U16) | VCC_SYS | EXT_VDD_3V3 | Camera level shifter B side and, through load switch U2, the camera header |
+| Switched 1.8 V rails | Texas Instruments TPS22991 load switches U10, U4, U8 | VDD_1V8 | VDD_1V8_AKD, VDD_1V8_ACC, VDD_1V8_PDM | Enables P0.19, P0.20, P0.21, each with a 100 kilohm pull-down so a rail is off until the firmware turns it on |
+| Current sense | Texas Instruments INA190A3 (U18, U17), gain 100 V/V | Shunts R55, R28 | P0.04 (AIN0), P0.05 (AIN1) | Read by the nRF5340 SAADC at 12 bits, gain 1/3, internal reference |
+
+Source: Rev2 schematic, netlist and bill of materials; firmware `src/README.md` and
+`src/core/interface/current_ic/current_ic.c`.
+
+The charge current follows from the charger's formula (300 A·ohm divided by the ISET
+resistor) with a stated accuracy of plus or minus 10 %. The charger precharges at 20 % of
+that current while the battery is below 3.0 V, terminates at 10 % of it, and has a 6 hour
+safety timer. Source: BQ25185 datasheet SLUSF65B, electrical characteristics and Table 6-1;
+Rev2 bill of materials for R84 and R85.
+
+The firmware's power-up order is: 0.8 V AKD1500 core, then the AKD1500 1.8 V rail, then
+the IMU, then the microphones, then the camera enable. Source:
+`akidatag_peripherals_power_enable()` in `src/core/interface/gpio/gpio.c`.
+
+No battery is supplied with the board. The firmware programs the fuel gauge for an
+1100 mAh, 4.2 V cell with a 3000 mV terminate voltage and a 4150 mV taper voltage, and the
+source notes that these values are for a test battery, so the state of charge it reports is
+only as good as the match between those parameters and the cell fitted. Revision 2
+connects the battery to the gauge's BAT pin and the charger to its SRX pin, which is the
+orientation the BQ27427 datasheet specifies for its integrated sense resistor. The firmware
+on `main` still inverts the sign of the gauge's current reading to correct for a sense
+resistor that its code describes as physically reversed, a correction that inverts the sign
+on this orientation. Source: Rev2 netlist; BQ27427 datasheet SLUSEB5B, pin functions;
+`src/include/fuel_gauge/fuel_gauge.h`, `src/core/interface/fuel_gauge/fuel_gauge.c`.
+
+---
+
+## 4. Pin assignment
+
+The table lists every nRF5340 GPIO as wired on hardware revision 2, and how the firmware on
+`main` uses it. Rows marked **differs** are places where the firmware's board definition
+still describes the previous board revision; they are listed together after the table.
+
+| nRF5340 pin | Rev2 signal | Connected to | Firmware use on `main` |
+|---|---|---|---|
+| P0.00 / XL1 | XL1 | 32.768 kHz crystal Y1 | Low-frequency crystal |
+| P0.01 / XL2 | XL2 | 32.768 kHz crystal Y1 | Low-frequency crystal |
+| P0.02 / NFC1 | AKD_GPIO2 | AKD1500 GPIO_02, test point TP16 | Not used |
+| P0.03 / NFC2 | AKD_GPIO3 | AKD1500 GPIO_03 | `akd_async` input, inference-complete interrupt |
+| P0.04 / AIN0 | I1V8_AIN0 | INA190 U18 output (1.8 V rail current), TP7 | SAADC channel 0 |
+| P0.05 / AIN1 | I0V8_AIN1 | INA190 U17 output (0.8 V rail current), TP6 | SAADC channel 1 |
+| P0.06 / AIN2 | CAM_SPI_CLK | Level shifter U15 to J1 pin 3 | Not used, **differs** (camera SCK expected on P0.17) |
+| P0.07 / AIN3 | CAM_SPI_MOSI | Level shifter U15 to J1 pin 5 | Not used, **differs** (camera MOSI expected on P0.13) |
+| P0.08 | HSPI_SCK | AKD1500 SPI_S_SCK, TP5 | SPIM4 SCK, high drive |
+| P0.09 | HSPI_MOSI | AKD1500 SPI_S_IO0 | SPIM4 MOSI |
+| P0.10 | HSPI_MISO | AKD1500 SPI_S_IO1 | SPIM4 MISO |
+| P0.11 | HSPI_CS0 | AKD1500 SPI_S_CS_N, 10 kilohm pull-up | SPIM4 chip select 0, AKD1500 |
+| P0.12 | HSPI_CS1 | AKD1500 SPI_S_2MCS0_N, 10 kilohm pull-up | SPIM4 chip select 1, flash IC2 through the feed-through |
+| P0.13 | QSPI_IO0_MOSI | Flash IC1 DQ0 | SPIM3 MOSI |
+| P0.14 | QSPI_IO1_MISO | Flash IC1 DQ1 | SPIM3 MISO |
+| P0.15 | QSPI_IO2 | Flash IC1 W#/DQ2, pull-up | Not used |
+| P0.16 | QSPI_IO3 | Flash IC1 HOLD#/DQ3, pull-up | Not used |
+| P0.17 | QSPI_CLK | Flash IC1 C, TP4 | SPIM3 SCK |
+| P0.18 | QSPI_CS_0 | Flash IC1 S#, pull-up | SPIM3 chip select 1 (application), chip select 0 (MCUboot) |
+| P0.19 | VDD_1V8_AKD_EN | Load switch U10 ON, 100 kilohm pull-down | `akd_enb` output |
+| P0.20 | VDD_1V8_ACC_EN | Load switch U4 ON, pull-down | `acc_enb` output |
+| P0.21 | VDD_1V8_PDM_EN | Load switch U8 ON, pull-down | `pdm_enb` output |
+| P0.22 | VDD_0V8_AKD_EN | Load switch U9 ON, then TLV62585 EN | `akd_0v_enb` output |
+| P0.23 | CHGR_STS1 | BQ25185 STAT1, 10 kilohm pull-up | `chgr_sts1` input |
+| P0.24 | CHGR_STS2 | BQ25185 STAT2, pull-up | `chgr_sts2` input |
+| P0.25 / AIN4 | CAM_SPI_CS | Level shifter U14 to J1 pin 6, 10 kilohm pull-up | SPIM3 chip select 0, camera |
+| P0.26 / AIN5 | CAM_SPI_MISO | Level shifter U14 from J1 pin 4 | `user_btn` input, **differs** (no button on this pin) |
+| P0.27 / AIN6 | LED_G | Q3, RGB LED green | `led_green` output |
+| P0.28 / AIN7 | LED_W_1 | Q4, white LED | `led_red` output, **differs** (drives the white LED); MCUboot DFU LED |
+| P0.29 | DBG_TXD | CP2105 RXD_SCI, TP11 | UART0 TX |
+| P0.30 | INT_FL_GAUG | BQ27427 GPOUT, pull-up | `fg_int` input |
+| P0.31 | ACC_INT1 | ISM330DHCX INT1 | `imui` input |
+| P1.00 | ACC_INT2 | ISM330DHCX INT2 | Not used |
+| P1.01 | USER_IO | Push button SW1, 10 kilohm pull-up | MCUboot DFU button only, **differs** (the application's button is defined on P0.26) |
+| P1.02 | ACC_FG_SDA | ISM330DHCX SDA, BQ27427 SDA, 2.2 kilohm pull-up | I2C1 SDA |
+| P1.03 | ACC_FG_SCL | ISM330DHCX SCL, BQ27427 SCL, 2.2 kilohm pull-up | I2C1 SCL |
+| P1.04 | DBG_RXD | CP2105 TXD_SCI, TP13 | UART0 RX |
+| P1.05 | AKD_PGOOD | AKD1500 PWR_GOOD through R47, 10 kilohm pull-up to VDD_1V8_AKD, TP1 | Not used |
+| P1.06 | CAM_PWR_EN | Load switch U2 ON (camera 3.3 V), 100 kilohm pull-down | Not used, **differs** (camera header power is never enabled) |
+| P1.07 | AKD_LP | AKD1500 SLEEP through R48 | `akd_lp` output, sleep control |
+| P1.08 | not connected | | Not used on this board |
+| P1.09 | PDM_PCLK | Microphones U19 and U20 CLOCK | PDM clock |
+| P1.10 | PDM_PDAT | Microphones U19 and U20 DATA, 100 ohm each | PDM data |
+| P1.11 | AKD_GPIO0 | AKD1500 GPIO_00 | Not used |
+| P1.12 | AKD_GPIO1 | AKD1500 GPIO_01 | Not used |
+| P1.13 | LED_B | Q1, RGB LED blue | `akdreset` node, unused by code, **differs** |
+| P1.14 | LED_R | Q2, RGB LED red | Not used, **differs** (the firmware's red indication is on P0.28) |
+| P1.15 | CAM_SPI_EN | Level shifters U14 and U15 output enable, pull-down | `cam_enb` output |
+
+Dedicated pins: SWDIO and SWDCLK to J2; RESET to J2 pin 6; ANT to the antenna matching
+network; D+, D- and VBUS not connected. Source: Rev2 netlist joined with the nRF5340 ball
+map; firmware `src/boards/nrf5340_cpuapp_akidatag.overlay` and
+`src/sysbuild/mcuboot_akidatag.overlay`.
+
+**Differences between the revision 2 wiring and the firmware on `main`.** The firmware's
+board definition predates this revision in five places: the camera SPI lines (it shares the
+flash bus on P0.17, P0.13 and P0.14, where revision 2 wires the camera to P0.06, P0.07 and
+P0.26), the camera supply enable on P1.06 (never driven), the push button (defined on
+P0.26, wired on P1.01), the LEDs (the firmware's red LED is the white LED on P0.28; the RGB
+red and blue on P1.14 and P1.13 are not driven), and the `akdreset` node on P1.13, which is
+the blue LED. The pin table is the hardware; the firmware column describes `main` as it is
+today.
+
+---
+
+## 5. Connectors
+
+### 5.1 J5, USB Type-C receptacle
+
+Würth Elektronik 632722200211, 24-pin. VBUS, D+, D-, CC1, CC2, GND and the shell are used.
+The two CC pins have 5.1 kilohm pull-downs (sink). The shell is tied to a separate chassis
+net through a ferrite bead. Source: Rev2 netlist and bill of materials.
+
+### 5.2 J4, battery connector
+
+JST XH series, 2-pin, 2.5 mm pitch (B2B-XH-A). Pin 1 is VCC_BAT (battery positive, through
+the BQ27427 sense path to the charger), pin 2 is GND. Source: Rev2 netlist and bill of
+materials.
+
+No battery is supplied with the board. Fit a single-cell rechargeable Li-ion or Li-Po cell
+with a JST XH 2-pin plug, positive on pin 1. The charger regulates the cell to 4.2 V and the
+board is designed for 3.0 to 4.2 V on VCC_SYS (section 6.1).
+
+### 5.3 J1, camera header
+
+10-pin, 2 x 5, 1.27 mm pitch (CNC Tech 3221-10-0100-00). Signals are on the 3.3 V side of
+the level shifters. Source: Rev2 netlist.
+
+| Pin | Signal | Pin | Signal |
+|---|---|---|---|
+| 1 | VDD_3V3_1V8_CAM (switched supply) | 2 | VDD_3V3_1V8_CAM |
+| 3 | SPI CLK | 4 | SPI MISO |
+| 5 | SPI MOSI | 6 | SPI CS |
+| 7 | not connected | 8 | not connected |
+| 9 | GND | 10 | GND |
+
+### 5.4 J2, SWD header
+
+10-pin, 2 x 5, 1.27 mm pitch. Source: Rev2 netlist.
+
+| Pin | Signal | Pin | Signal |
+|---|---|---|---|
+| 1 | VDD_1V8 (target reference) | 2 | SWDIO |
+| 3 | GND | 4 | SWDCLK |
+| 5 | GND | 6 | nRESET |
+| 7 | not connected | 8 | not connected |
+| 9 | GND | 10 | not connected |
+
+### 5.5 J3, U.FL
+
+Hirose U.FL-R-SMT-1(80) footprint on the antenna feed, connected through R9. R9 is not
+fitted, so the connector is not part of the default build. Source: Rev2 netlist and bill
+of materials.
+
+### 5.6 Test points
+
+TP1 through TP20 are 1 mm surface-mount test points. Those on host signals: TP1 AKD1500
+PWR_GOOD, TP4 flash IC1 clock, TP5 AKD1500 host SPI clock, TP6 and TP7 the two INA190
+outputs, TP11 and TP13 the console TX and RX, TP16 AKD1500 GPIO2. Rail test points: TP3
+VDD_1V8, TP8 VDD_1V8_AKD, TP9 VDD_1V8_ACC, TP12 VDD_1V8_PDM, TP17 VDD_0V8_AKD, TP2
+camera supply, TP18 VCC_BAT. TP10, TP14 and TP15 are on the AKD1500 SPI master port.
+Source: Rev2 netlist.
+
+---
+
+## 6. Electrical characteristics
+
+The values below are the settings the revision 2 design makes. Measured characteristics
+will be added in a later revision of this document.
+
+### 6.1 Recommended operating conditions
+
+| Parameter | Min | Typ | Max | Unit | Source |
+|---|---|---|---|---|---|
+| USB input voltage | | 5 | | V | Rev2 schematic (VBUS 5 V) |
+| Battery voltage (VCC_SYS) | 3.0 | | 4.2 | V | Rev2 schematic power block diagram |
+| VDD_1V8 system rail | | 1.8 | | V | Rev2 schematic |
+| VDD_0V8_AKD core rail | | 0.8 | | V | Rev2 schematic |
+| EXT_VDD_3V3 camera rail | | 3.3 | | V | Rev2 schematic |
+| Camera header supply | | 3.3 (1.8 option not fitted) | | V | Rev2 netlist |
+
+### 6.2 Current consumption
+
+Power consumption figures, per operating state and for the charge current drawn from USB,
+will be added in a later revision of this document. The charger's 536 mA nominal
+fast-charge setting is in section 3.11.
+
+The firmware measures the 1.8 V and 0.8 V rails itself through the INA190 amplifiers
+(`power read`, `power measure`): the shunts are 0.1 ohm on the 1.8 V rail and 0.02 ohm on
+the 0.8 V rail, and revision 2 fits the 100 V/V amplifier, so run `power variant a3` first
+because the firmware's build-time default is the 25 V/V A1 part. The total draw, which
+also covers the charger, the LEDs and the 3.3 V rail, needs a meter in series with the
+battery or the USB input. Source: Rev2 bill of materials, `src/README.md`.
+
+What the on-board measurement can resolve follows from the INA190 datasheet. The A3 device
+has a gain error of plus or minus 0.3 % and a zero-current output offset of up to 3 mV at a
+1.8 V supply, which corresponds to 0.3 mA on the 1.8 V rail and 1.5 mA on the 0.8 V rail.
+With the firmware's ADC setting of gain 1/3 against the internal 0.6 V reference, full scale
+is 1.8 V at the amplifier output, or 180 mA on the 1.8 V rail and 900 mA on the 0.8 V rail,
+less the amplifier's 20 mV swing limit below its supply. Source: INA190 datasheet SBOS863D;
+`src/core/interface/current_ic/current_ic.c`.
+
+---
+
+## 7. Power modes
+
+The firmware has no single "power mode" register; the states below are what the sources
+describe.
+
+| State | What is on | Source |
+|---|---|---|
+| Off | SW2 open: nothing after the charger is powered. The charger still charges the battery from USB. | Rev2 schematic |
+| Idle, advertising | nRF5340 running the application with Zephyr device power management; AKD1500 in SLEEP (clocks gated, model retained); microphone, IMU and camera rails as left by the application | `src/prj.conf`, `gpio.c` |
+| Application stopped (`app stop`) | As idle, and the AKD1500 PLL turned off | `src/README.md` |
+| Inference | AKD1500 woken through SLEEP for each inference, host SPI at the configured clock, microphone capture running | `src/README.md`, `gpio.c` |
+| Serial recovery | MCUboot only, listening on the console UART | `src/sysbuild/mcuboot.conf` |
+
+Battery life in each state depends on the cell fitted; no battery is supplied with the
+board.
+
+---
+
+## 8. Firmware interfaces
+
+| Interface | Detail | Source |
+|---|---|---|
+| Bluetooth device name | `AkidaTag` (`AkidaTag-DK` on the development-kit build) | `src/prj.conf`, `src/boards/dk.conf` |
+| Bluetooth role and security | Peripheral; LE Secure Connections only, MITM protection required, bonding with up to 3 bonds, 128-bit keys, resolvable private address rotated every 900 s | `src/prj.conf` |
+| Advertising | Flags, complete device name, manufacturer-specific data; the device serial is never advertised | `ble_initialization.c` |
+| Model transfer service | `f000aa00-0451-4000-b000-000000000000`, one flash sector per stage with an absolute offset in every write | [BLE model transfer](../ble-model-transfer.md) |
+| Edge learning service | `f000bb11-0111-9000-c000-000000000000` (command `f000bb10`, acknowledgement `f000bb12`) | `edge_learning.c` |
+| Command and streaming channel | Nordic UART Service frames, including battery state of charge and charger status | `src/README.md`, `battery_service.c` |
+| Firmware update over Bluetooth | MCUmgr SMP over Bluetooth with the image, OS and statistics groups; MCUboot with RSA-3072 signatures, two updateable images (application and network core) | `src/prj.conf`, `src/sysbuild/mcuboot.conf` |
+| Firmware update over USB-C | MCUboot serial recovery on the CP2105 UART, entered without a button | [firmware update over USB](../firmware-update-over-usb.md) |
+| Console | Zephyr shell on UART0 at 115200 8N1 | `src/prj.conf`, board overlay |
+| Watchdog | 8 s application watchdog | `src/prj.conf` |
+| Firmware version | Readable over Bluetooth with `smpmgr image state-read`; the current build is the [latest release](https://github.com/Brainchip-Inc/AkidaTag/releases/latest) | `VERSION`, `AGENTS.md` |
+
+---
+
+## 9. Mechanical
+
+
+
+In the drawing: the camera header is J1, the SWD header J2, the U.FL footprint J3, the
+battery connector J4, the USB-C receptacle J5, the button SW1, the on/off switch SW2, the
+two flashes IC1 (top right) and IC2 (right), and the microphones U19 and U20.
+
+| Item | Value | Source |
+|---|---|---|
+| Board size | 27.7 mm x 39.5 mm | Rev2 board outline (DXF) |
+| Corners | 0.889 mm chamfer on all four corners | Rev2 board outline (DXF) |
+| Layer count | 6 | Rev2 fabrication artwork layer set |
+| Mounting holes | None | Rev2 board outline (DXF) |
+| USB-C position | Bottom side, centred near one short edge, receptacle projecting beyond the edge | Rev2 placement data |
+| Microphones | Bottom side, one in each corner beside the USB-C edge | Rev2 placement data |
+| Board thickness | 1.00 mm, plus or minus 10 % | Rev2 fabrication notes |
+| Enclosure | The board ships in its enclosure | BrainChip product decision |
+
+---
+
+## 10. Product information
+
+| Item | Value |
+|---|---|
+| Product name | AkidaTag |
+| What is in the box | The AkidaTag board in its enclosure. No battery, USB-C cable or camera is included |
+| Companion app | BrainChip Connect for Android 13 or later, in [pre-registration on Google Play](https://play.google.com/store/apps/details?id=com.brainchip.connect), and coming soon to the iOS App Store |
+| Firmware and models | The [latest firmware release](https://github.com/Brainchip-Inc/AkidaTag/releases/latest) of this repository; every release attaches the model packages `akidatag-kws-model.zip` and `akidatag-kws-edge-learning-model.zip` |
+| Licence | Apache License 2.0, in `LICENSE` at the root of this repository |
+| Documentation | [AkidaTag documentation](https://brainchip-inc.github.io/AkidaTag/), [BrainChip Connect documentation](https://brainchip-inc.github.io/BrainChip-Connect/), [AkidaTag on the BrainChip Developer Hub](https://developer.brainchip.com/akida-tag/) and [Developer Hub sign-up](https://developer.brainchip.com/signup/) |
+| Support | Help on the [BrainChip Discord](https://discord.com/invite/9bmd9g52vn); bugs as [GitHub issues](https://github.com/Brainchip-Inc/AkidaTag/issues); security problems reported privately through the repository's Security tab ("Report a vulnerability") |
+
+---
+
+## 11. Revision history
+
+### Hardware
+
+| Revision | Design | Changes |
+|---|---|---|
+| 2 | NRF-AKD1500-002 (V-002), schematic V11, changes dated 2026-07-07, released 2026-08-25 | Test pads added on the ADC inputs; INA190 changed to the gain-100 variant with matching shunts; camera signals brought to a header; LDO added for the camera supply; new level-shifter part for the camera signals; SWD connector added; one RGB LED added; on/off switch added; one user button added |
+
+Revision 1 (V-001, dated 2025-12-24) was not released outside BrainChip; revision 2 is the
+first board shipped. Source: the revision summary on the Rev2 schematic cover sheet.
+
+### Document
+
+| Date | Change |
+|---|---|
+| 2026-09-25 | First edition, from the revision 2 design files and the firmware on `main` |
+
+---
+
+## 12. Sources
+
+- Revision 2 design files: schematic SI-NRF-AKD_BRD-002 V11 (2026-08-25), bill of
+ materials NRF-AKD1500-002 V11, netlist report (2026-08-24), placement file, board
+ outline DXF and fabrication artwork set.
+- Firmware on `main` of this repository: `src/boards/nrf5340_cpuapp_akidatag.overlay`,
+ `src/sysbuild/mcuboot_akidatag.overlay`, `src/sysbuild/mcuboot.conf`, `src/prj.conf`,
+ `src/Kconfig`, `src/pm_static.yml`, `src/apps/demo_apps/custom_app.conf`,
+ `src/imu_app.conf`, `src/README.md`, `src/core/interface/gpio/gpio.c`,
+ `src/core/interface/audio/pdm_mic.c`, `src/core/interface/ble_services/`,
+ `src/include/fuel_gauge/fuel_gauge.h`, `docs/ble-model-transfer.md`,
+ `docs/firmware-update-over-usb.md`, `AGENTS.md`.
+- [AKD1500 Product Brief V2.4](https://brainchip.com/wp-content/uploads/2025/10/AKD1500-Product-Brief-V2.4-Oct.25.pdf).
+- [Nordic Semiconductor nRF5340 product page](https://www.nordicsemi.com/Products/nRF5340)
+ and [product specification key features](https://docs.nordicsemi.com/bundle/ps_nrf5340/page/keyfeatures_html5.html).
+- Texas Instruments BQ25185 datasheet, SLUSF65B: charge-current formula, ILIM/VSET table,
+ charging thresholds and timers.
+- Texas Instruments INA190 datasheet, SBOS863D: gain options, gain error, zero-current
+ output offset and output swing.
+- BrainChip board test records: post-fabrication PCB test report (version 1.0, 2026-03-13),
+ PCB testing checklist and procedures (version 1.0, 2026-02-18) and Spark board SWD
+ connection guide (version 1.1, 2026-04-10).
+- BrainChip AKD1500 documentation for the strap meanings and the Safe Mode clock behaviour.
+- Texas Instruments BQ27427 datasheet, SLUSEB5B: pin functions.
+- BrainChip product decisions of September 2026: the enclosure ships with the board, the box
+ contents, and the companion app platforms.
+- [BrainChip Connect on Google Play](https://play.google.com/store/apps/details?id=com.brainchip.connect)
+ for the Android version.
+
+---
+
+© 2026 BrainChip Holdings Ltd. All rights reserved.
diff --git a/docs/hardware/images/akidatag-block-diagram.svg b/docs/hardware/images/akidatag-block-diagram.svg
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+
diff --git a/docs/hardware/images/akidatag-board-outline.svg b/docs/hardware/images/akidatag-board-outline.svg
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+
diff --git a/docs/hardware/images/akidatag-power-tree.svg b/docs/hardware/images/akidatag-power-tree.svg
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+
diff --git a/docs/hardware/technical-specifications.md b/docs/hardware/technical-specifications.md
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@@ -0,0 +1,126 @@
+# AkidaTag technical specifications
+
+AkidaTag is a compact, battery-powered edge-AI device built on BrainChip's Akida™
+neuromorphic processing engine. It runs neural networks on the AKD1500 AI co-processor,
+listens through two on-board microphones, senses motion, and talks to the BrainChip
+Connect app over Bluetooth Low Energy. Models are built with BrainChip's MetaTF™ flow and
+loaded from the app, and the device learns new keywords on-device, with no cloud
+connection. AkidaTag is made for developers who want to evaluate event-based AI on a
+wearable-sized, always-on device.
+
+This page is the buyer-facing summary. The engineering reference, with pinouts, the power
+tree and the full connector detail, is the [datasheet](datasheet.md); the system view is
+the [block diagram](block-diagram.md).
+
+| Document status | |
+|---|---|
+| Hardware described | AkidaTag hardware revision 2 |
+| Firmware referenced | The AkidaTag firmware in this repository; the current build is the [latest release](https://github.com/Brainchip-Inc/AkidaTag/releases/latest) |
+
+---
+
+## Key features
+
+- BrainChip AKD1500 Akida neuromorphic AI co-processor with on-device learning
+- Nordic nRF5340 dual-core Arm Cortex-M33 host with Bluetooth Low Energy
+- 16 MB of model storage for the AI processor and 16 MB of firmware and file storage
+ for the host
+- Two digital MEMS microphones for always-on audio
+- Six-axis accelerometer and gyroscope
+- SPI camera header for vision experiments
+- Single-cell Li-ion battery support with USB-C charging, fuel gauge and on/off switch
+- On-board current sensing of the AI and system rails for power measurements
+- Firmware update over Bluetooth or over the USB-C cable
+- Companion BrainChip Connect app to load models, run the demonstrations and start
+ on-device learning
+
+## Applications
+
+- Keyword spotting and voice control with on-device personalisation
+- Vibration and motion classification, anomaly detection
+- Low-power vision with an attached SPI camera
+- Evaluation of Akida event-based inference on a battery-powered device
+
+---
+
+## Specifications
+
+| | |
+|---|---|
+| **AI co-processor** | BrainChip AKD1500: Akida neuron fabric, event-based neuromorphic architecture, 22 nm FD-SOI, 7 mm x 7 mm package |
+| **AI on-chip memory** | 1 MB |
+| **AI clock** | Up to 400 MHz core clock from an on-board 25 MHz crystal; 400 MHz default in firmware |
+| **On-device learning** | Yes; keyword learning exposed over Bluetooth |
+| **Host to AI interface** | SPI, 8 MHz by default, up to 32 MHz |
+| **Host processor** | Nordic nRF5340: 128 MHz Arm Cortex-M33 application core with 1 MB flash and 512 KB RAM, plus a 64 MHz Arm Cortex-M33 network core for Bluetooth |
+| **Operating system** | Zephyr RTOS on the nRF Connect SDK, MCUboot bootloader |
+| **Model storage** | 16 MB SPI NOR flash dedicated to the AI processor |
+| **Firmware storage** | 16 MB SPI NOR flash for firmware updates and a LittleFS file system, in addition to the host's 1 MB internal flash |
+| **Microphones** | Two digital PDM MEMS microphones; the firmware captures audio at 16 kHz, 16-bit, and the keyword spotting demonstration uses one of the two |
+| **Motion sensor** | STMicroelectronics ISM330DHCX six-axis accelerometer and gyroscope; firmware defaults 208 Hz, plus or minus 8 g and plus or minus 500 degrees per second |
+| **Camera** | SPI camera header (10-pin, 1.27 mm pitch) with switched 3.3 V supply; the firmware supports an ArduCam Mega camera at 96 x 96 and 128 x 128 pixels |
+| **Battery monitoring** | Fuel gauge reporting state of charge to the app; charger status reporting |
+| **Power monitoring** | On-board current sensing of the 1.8 V system rail and the 0.8 V AI core rail, readable from the firmware console |
+| **Bluetooth** | Bluetooth Low Energy peripheral, device name `AkidaTag`; LE Secure Connections only with bonding; firmware update over Bluetooth |
+| **Radio** | nRF5340 radio, specified by Nordic for -40 to +3 dBm configurable transmit power and -98 dBm sensitivity at 1 Mbps; on-board 2.4 GHz chip antenna |
+| **USB** | USB-C: 5 V charging input and a USB-to-serial console at 115200 baud; firmware update over the cable with nothing but a computer |
+| **Debug** | 10-pin 1.27 mm SWD header |
+| **Battery** | Not included. Fits a single-cell rechargeable Li-ion or Li-Po cell, 3.0 to 4.2 V, on a JST XH 2-pin connector |
+| **Battery life** | Depends on the cell fitted |
+| **Charging** | On-board linear charger with power path, 536 mA nominal fast charge from USB-C 5 V; the device runs while charging; charge time depends on the cell fitted |
+| **Power switch** | On/off slide switch |
+| **Power consumption** | Power consumption figures will be added in a later revision of this document |
+| **Indicators** | One RGB LED and one white LED under firmware control |
+| **Controls** | One user button; the on/off slide switch |
+| **Board dimensions** | 27.7 mm x 39.5 mm, 1.0 mm thick, six-layer PCB, chamfered corners |
+| **Enclosure** | Ships in its enclosure |
+| **What is in the box** | The AkidaTag board in its enclosure. No battery, USB-C cable or camera is included |
+
+---
+
+## Software
+
+Models for AkidaTag are built with BrainChip's MetaTF flow from TensorFlow/Keras or
+PyTorch, packaged with the model workflow in this repository, and sent to the device by
+the BrainChip Connect app over Bluetooth. The firmware in this repository runs the
+demonstrations: keyword spotting with on-device edge learning, motion sensing, and camera
+capture from the console. Firmware updates arrive over Bluetooth (MCUmgr) or over the
+USB-C cable from a computer.
+
+| | |
+|---|---|
+| **Companion app** | BrainChip Connect for Android 13 or later, in pre-registration on Google Play, and coming soon to the iOS App Store |
+| **Firmware** | This repository, under the Apache License 2.0; the current build is the [latest release](https://github.com/Brainchip-Inc/AkidaTag/releases/latest) |
+| **Models** | Every firmware release attaches the keyword spotting model packages `akidatag-kws-model.zip` and `akidatag-kws-edge-learning-model.zip` |
+| **Demonstrations** | Keyword spotting with on-device edge learning; motion sensing; camera capture |
+
+## Resources
+
+- [AkidaTag documentation](https://brainchip-inc.github.io/AkidaTag/)
+- [BrainChip Connect documentation](https://brainchip-inc.github.io/BrainChip-Connect/)
+- [AkidaTag firmware releases](https://github.com/Brainchip-Inc/AkidaTag/releases/latest)
+- [AkidaTag on the BrainChip Developer Hub](https://developer.brainchip.com/akida-tag/)
+- [Developer Hub sign-up](https://developer.brainchip.com/signup/)
+- [BrainChip Connect on Google Play (pre-registration)](https://play.google.com/store/apps/details?id=com.brainchip.connect)
+- [AKD1500 product brief](https://brainchip.com/wp-content/uploads/2025/10/AKD1500-Product-Brief-V2.4-Oct.25.pdf)
+- Help: the [BrainChip Discord](https://discord.com/invite/9bmd9g52vn) for questions and
+ [GitHub issues](https://github.com/Brainchip-Inc/AkidaTag/issues) for bugs. Security
+ problems are reported privately through the repository's Security tab
+ ("Report a vulnerability")
+
+---
+
+## Sources
+
+Every value on this page is taken from the AkidaTag revision 2 design files, the AkidaTag
+firmware in this repository, the
+[AKD1500 Product Brief V2.4](https://brainchip.com/wp-content/uploads/2025/10/AKD1500-Product-Brief-V2.4-Oct.25.pdf),
+the [Nordic nRF5340 product specification](https://docs.nordicsemi.com/bundle/ps_nrf5340/page/keyfeatures_html5.html),
+the Texas Instruments BQ25185 datasheet, the
+[Google Play listing](https://play.google.com/store/apps/details?id=com.brainchip.connect)
+or BrainChip's product decisions of September 2026 on the enclosure, the box contents and
+the app platforms. The [datasheet](datasheet.md) lists the source next to each value.
+
+---
+
+© 2026 BrainChip Holdings Ltd. All rights reserved.