diff --git a/.gitmodules b/.gitmodules index f4f7c4ff270..78e2c880f6b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,3 +26,6 @@ url = ../fsp.git update = none ignore = dirty +[submodule "opensbi"] + path = 3rdparty/opensbi + url = ../opensbi.git diff --git a/3rdparty/fsp b/3rdparty/fsp index 162719b6cb5..1d2b7e1a94c 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6 +Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index f70eddafbc2..b3b9fa34bb9 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit f70eddafbc2c6045a14e2f8bbb3273ee738fbaf7 +Subproject commit b3b9fa34bb99d33d0fc6a69c64966a71cebd5bd6 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index 637f2a4f21e..bd0ed91cb98 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit 637f2a4f21ead8ccc45d5256834eb27ce72088db +Subproject commit bd0ed91cb985a697033edd9fd62d322aa017e791 diff --git a/3rdparty/opensbi b/3rdparty/opensbi new file mode 160000 index 00000000000..804b997ed41 --- /dev/null +++ b/3rdparty/opensbi @@ -0,0 +1 @@ +Subproject commit 804b997ed415001097803e4b537fd63d043874b9 diff --git a/3rdparty/vboot b/3rdparty/vboot index 304aa429c1a..dac763c782c 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca +Subproject commit dac763c782ce05476dec02e855f349d2b6f3a910 diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index b4daa960a9d..9d8aad05e9d 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -29,7 +29,6 @@

x86 coreboot Development

  • SoC support
  • Board support
  • -
  • Verified Boot (vboot) support
  • diff --git a/Documentation/Intel/vboot.html b/Documentation/Intel/vboot.html deleted file mode 100644 index ca49ac2e2d8..00000000000 --- a/Documentation/Intel/vboot.html +++ /dev/null @@ -1,402 +0,0 @@ - - - - vboot - Verified Boot Support - - - -

    vboot - Verified Boot Support

    - -

    -Google's verified boot support consists of: -

    - - -Google's vboot verifies the firmware and places measurements -within the TPM. - -
    -

    Root of Trust

    -

    -When using vboot, the root-of-trust is basically the read-only portion of the -SPI flash. The following items factor into the trust equation: -

    - - -

    -The firmware is typically protected using the write-protect pin on the SPI -flash part and setting some of the write-protect bits in the status register -during manufacturing. The protected area is platform specific and for x86 -platforms is typically 1/4th of the SPI flash -part size. Because this portion of the SPI flash is hardware write protected, -it is not possible to update this portion of the SPI flash in the field, -without altering the system to eliminate the ground connection to the SPI flash -write-protect pin. Without hardware modifications, this portion of the SPI -flash maintains the manufactured state during the system's lifetime. -

    - -
    -

    Firmware Layout

    -

    -Several sections are added to the firmware layout to support vboot: -

    - -

    -The following sections describe the various portions of the flash layout. -

    - -

    Read-Only Section

    -

    -The read-only section contains a coreboot file system (CBFS) that contains all -of the boot firmware necessary to perform recovery for the system. This -firmware is typically protected using the write-protect pin on the SPI flash -part and setting some of the write-protect bits in the status register during -manufacturing. The protected area is typically 1/4th of the SPI flash part -size and must cover the entire read-only section which consists of: -

    - - -

    Google Binary Blob (GBB) Area

    -

    -The GBB area is part of the read-only section. This area contains a 4096 or -8192 bit public root RSA key that is used to verify the VBLOCK area to obtain -the firmware signing key. -

    - -

    Recovery Firmware

    -

    -The recovery firmware is contained within a coreboot file system and consists -of: -

    - - -

    -The recovery firmware is written during manufacturing and typically contains -code to write the storage device (eMMC device or hard disk). The recovery -image is usually contained on a socketed device such as a USB flash drive or -an SD card. Depending upon the payload firmware doing the recovery, it may -be possible for the user to interact with the system to specify the recovery -image path. Part of the recovery is also to write the A and B areas of the -SPI flash device to boot the system. -

    - - -

    Read/Write Section

    - -

    -The read/write sections contain an area which contains the firmware signing -key and signature and an area containing a coreboot file system with a subset -of the firmware. The firmware files in FW_MAIN_A and FW_MAIN_B are: -

    - - -

    -The firmware subset enables most issues to be fixed in the field with firmware -updates. The firmware files handle memory and most of silicon initialization. -These files also produce the tables which get passed to the operating system. -

    - -
    -

    Firmware Updates

    -

    -The read/write sections exist in one of three states: -

    - - - - - - -
    -Where is this state information written? -
    CMOS? -
    RW_NVRAM? -
    RW_FWID_* -
    - -

    -Firmware updates are handled by the operating system by writing any read/write -section that is not in the "successfully booted" state. Upon the next reboot, -vboot determines the section to boot. If it finds one in the "ready to boot" -state then it attempts to boot using that section. If the boot fails then -vboot marks the section as invalid and attempts to fall back to a read/write -section in the "successfully booted" state. If vboot is not able to find a -section in the "successfully booted" state then vboot enters recovery mode. -

    - -

    -Only the operating system is able to transition a section from the "ready to -boot" state to the "successfully booted" state. The transition is typically -done after the operating system has been running for a while indicating -that successful boot was possible and the operating system is stable. -

    - -

    -Note that as long as the SPI write protection is in place then the system is -always recoverable. If the flash update fails then the system will continue -to boot using the previous read/write area. The same is true if coreboot -passes control to the payload or the operating system and then the boot fails. -In the worst case, the SPI flash gets totally corrupted in which case vboot -fails the signature checks and enters recovery mode. There are no times where -the SPI flash is exposed and the reset vector or part of the recovery firmware -gets corrupted. -

    - -
    -

    Build Flags

    -

    -The following Kconfig values need to be selected to enable vboot: -

    - - -

    -The starting stage needs to be specified by selecting either -VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE. -

    - -

    -If vboot starts in bootblock then vboot may be built as a separate stage by -selecting VBOOT_SEPARATE_VERSTAGE. Additionally, if static RAM is too small -to fit both verstage and romstage then selecting VBOOT_RETURN_FROM_VERSTAGE -enables bootblock to reuse the RAM occupied by verstage for romstage. -

    - -

    -Non-volatile flash is needed for vboot operation. This flash area may be in -CMOS, the EC, or in a read/write area of the SPI flash device. Select one of -the following: -

    - -

    -More non-volatile storage features may be found in src/vboot/Kconfig. -

    - -

    -A TPM is also required for vboot operation. TPMs are available in -drivers/i2c/tpm and drivers/pc80/tpm. -

    - -

    -In addition to adding the coreboot files into the read-only region, enabling -vboot causes the build script to add the read/write files into coreboot file -systems in FW_MAIN_A and FW_MAIN_B. -

    - -
    -

    Signing the coreboot Image

    -

    -The following command script is an example of how to sign the coreboot image file. -This script is used on the Intel Galileo board and creates the GBB area and -inserts it into the coreboot image. It also updates the VBLOCK areas with the -firmware signing key and the signature for the FW_MAIN firmware. More details -are available in 3rdparty/vboot/README. -

    - -
    #!/bin/sh
    -#
    -#  The necessary tools were built and installed using the following commands:
    -#
    -#        pushd 3rdparty/vboot
    -#        make
    -#        sudo make install
    -#        popd
    -#
    -#  The keys were made using the following command
    -#
    -#        3rdparty/vboot/scripts/keygeneration/create_new_keys.sh  \
    -#                --4k --4k-root --output $PWD/keys
    -#
    -#
    -#  The "magic" numbers below are derived from the GBB section in
    -#  src/mainboard/intel/galileo/vboot.fmd.
    -#
    -#  GBB Header Size:     0x80
    -#  GBB Offset:      0x611000, 4KiB block number: 1553 (0x611)
    -#  GBB Length:       0x7f000, 4KiB blocks:        127  (0x7f)
    -#  COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690)
    -#  COREBOOT Length: 0x170000, 4KiB blocks:        368 (0x170)
    -#
    -#  0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000
    -#
    -#  Create the GBB area blob
    -#  Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size
    -#
    -gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
    -
    -#
    -#  Copy from the start of the flash to the GBB region into the signed flash
    -#  image.
    -#
    -#  1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB
    -#
    -dd  conv=fdatasync  ibs=4096  obs=4096  count=1553  \
    -    if=build/coreboot.rom  of=build/coreboot.signed.rom
    -
    -#
    -#  Append the empty GBB area to the coreboot.rom image.
    -#
    -#  1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB
    -#
    -dd  conv=fdatasync  obs=4096  obs=4096  seek=1553  if=gbb.blob  \
    -    of=build/coreboot.signed.rom
    -
    -#
    -#  Append the rest of the read-only region into the signed flash image.
    -#
    -#  1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area
    -#   368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area
    -#
    -dd  conv=fdatasync  ibs=4096  obs=4096  skip=1680  seek=1680  count=368  \
    -    if=build/coreboot.rom  of=build/coreboot.signed.rom
    -
    -#
    -#  Insert the HWID and public root and recovery RSA keys into the GBB area.
    -#
    -gbb_utility                          \
    -   --set --hwid='Galileo'            \
    -   -r $PWD/keys/recovery_key.vbpubk  \
    -   -k $PWD/keys/root_key.vbpubk      \
    -   build/coreboot.signed.rom
    -
    -#
    -#  Sign the read/write firmware areas with the private signing key and update
    -#  the VBLOCK_A and VBLOCK_B regions.
    -#
    -3rdparty/vboot/scripts/image_signing/sign_firmware.sh  \
    -   build/coreboot.signed.rom                           \
    -   $PWD/keys                                           \
    -   build/coreboot.signed.rom
    -
    - -
    -

    Boot Flow

    -

    -The reset vector exist in the read-only area and points to the bootblock entry -point. The only copy of the bootblock exists in the read-only area of the SPI -flash. Verstage may be part of the bootblock or a separate stage. If separate -then the bootblock loads verstage from the read-only area and transfers control -to it. -

    - -

    -Upon first boot, verstage attempts to verify the read/write section A. It gets -the public root key from the GBB area and uses that to verify the VBLOCK area -in read-write section A. If the VBLOCK area is valid then it extracts the -firmware signing key (1024-8192 bits) and uses that to verify the FW_MAIN_A -area of read/write section A. If the verification is successful then verstage -instructs coreboot to use the coreboot file system in read/write section A for -the contents of the remaining boot firmware (romstage, postcar, ramstage and -the payload). -

    - -

    -If verification fails for the read/write area and the other read/write area is -not valid vboot falls back to the read-only area to boot into system recovery. -

    - -
    -

    Chromebook Special Features

    -

    -Google's Chromebooks have some special features: -

    - - -

    Developer Mode

    -

    -Developer mode allows the user to use coreboot to boot another operating system. -This may be a another (beta) version of Chrome OS, or another flavor of -GNU/Linux. Use of developer mode does not void the system warranty. Upon -entry into developer mode, all locally saved data on the system is lost. -This prevents someone from entering developer mode to subvert the system -security to access files on the local system or cloud. -

    - -

    Write Protect Screw

    -

    -Chromebooks have a write-protect screw which provides the ground to the -write-protect pin of the SPI flash. Google specifically did this to allow -the manufacturing line and advanced developers to re-write the entire SPI flash -part. Once the screw is removed, any firmware may be placed on the device. -However, accessing this screw requires opening the case and voids the system -warranty! -

    - -
    -

    Modified: 2 May 2017

    - - diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 5d337b629dd..0e67dd173cc 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -16,6 +16,12 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0x66 Devices have been enumerated 0x88 Devices have been configured 0x89 Devices have been enabled +0xe0 Boot media (e.g. SPI ROM) is corrupt +0xe1 Resource stored within CBFS is corrupt +0xe2 Vendor binary (e.g. FSP) generated a fatal error +0xe3 RAM could not be initialized +0xe4 Critical hardware component could not initialize +0xe5 Video subsystem failed to initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 249fd4600e9..852ca08bf94 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -1165,8 +1165,6 @@ saved .config file. As always, a 'select' statement overrides any specified - coreboot has added the glob operator '*' for the 'source' keyword. - coreboot’s Kconfig always defines variables except for strings. In other Kconfig implementations, bools set to false/0/no are not defined. -- IS_ENABLED() is ‘false’ for undefined variables and ‘0’ variables. In Linux - (where the macro comes from) it’s ‘true’ as soon as the variable is defined. - coreboot’s version of Kconfig adds the KCONFIG_STRICT environment variable to error out if there are any issues in the Kconfig files. In the Linux kernel, Kconfig will generate a warning, but will still output an updated .config or diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index d6f800c2901..ae70c70cbc2 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -5,10 +5,10 @@ If you already have an account, skip to Part 2. Otherwise, go to in your preferred web browser. -Select **Register** in the upper right corner. +Select **Sign in** in the upper right corner. Select the appropriate sign-in. For example, if you have a Google account, -select **Google OAuth2** (gerrit-oauth-provider plugin)".**Note:** Your +select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your username for the account will be the username of the account you used to sign-in with. (ex. your Google username). @@ -17,7 +17,7 @@ sign-in with. (ex. your Google username). If you prefer to use an HTTP password instead, skip to Part 2b. For the most up-to-date instructions on how to set up SSH keys with Gerrit go to - + and follow the instructions there. Then, skip to Part 3. Additionally, that section of the Web site provides explanation on starting @@ -35,13 +35,13 @@ doing so could overwrite an existing key. In the upper right corner, select your name and click on **Settings**. Select **SSH Public Keys** on the left-hand side. -In a terminal, run "ssh-keygen" and confirm the default path ".ssh/id_rsa". +In a terminal, run `ssh-keygen` and confirm the default path `.ssh/id_rsa`. Make a passphrase -- remember this phrase. It will be needed whenever you use this RSA Public Key. **Note:** You might want to use a short password, or forego the password altogether as you will be using it very often. -Open "id_rsa.pub", copy all contents and paste into the textbox under +Open `id_rsa.pub`, copy all contents and paste into the textbox under "Add SSH Public Key" in the https://review.coreboot.org webpage. ## Part 2b: Setting up an HTTP Password @@ -51,7 +51,7 @@ after you select your name and click on **Settings** on the left-hand side, rath than selecting **SSH Public Keys**, select **HTTP Password**. Click **Generate Password**. This should fill the "Password" box with a password. Copy -the password, and add the following to your $HOME/.netrc file: +the password, and add the following to your `$HOME/.netrc` file: machine review.coreboot.org login YourUserNameHere password YourPasswordHere @@ -61,15 +61,19 @@ just generated. ## Part 3: Clone coreboot and configure it for submitting patches On Gerrit, click on the **Browse** tab in the upper left corner and select -**Repositories**. From the listing, select the "coreboot" repo. You may have +**Repositories**. From the listing, select the "coreboot" repo. You may have to click the next page arrow at the bottom a few times to find it. If you are using SSH keys, select **ssh** from the tabs under "Project coreboot" and run the "clone with commit-msg hook" command that's provided. This should prompt you for your id_rsa passphrase, if you previously set one. +**Note:** if the **ssh** option is not showing, check that you have a username +set. Click the profile picture at the top right and select **User Settings**, +then set your username in the **Profile** section. + If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" -and run the command that appears +and run the command that appears. Now is a good time to configure your global git identity, if you haven't already. @@ -87,13 +91,13 @@ and other configurations. An easy first commit to make is fixing existing checkpatch errors and warnings in the source files. To see errors that are already present, build the files in -the repository by running 'make lint' in the coreboot directory. Alternatively, -if you want to run 'make lint' on a specific directory, run: +the repository by running `make lint` in the coreboot directory. Alternatively, +if you want to run `make lint` on a specific directory, run: - for file in $(git ls-files | grep src/amd/quadcore); do \ + for file in $(git ls-files | grep ); do \ util/lint/checkpatch.pl --file $file --terse; done -where is the filepath of the directory (ex. src/cpu/amd/car). +where `filepath` is the filepath of the directory (ex. `src/cpu/amd/car`). Any changes made to files under the src directory are made locally, and can be submitted for review. @@ -116,7 +120,7 @@ To commit the change, run git commit -s **Note:** The -s adds a signed-off-by line by the committer. Your commit should be -signed off with your name and email (i.e. **Your Name** ****, based on +signed off with your name and email (i.e. **Your Name** **\**, based on what you set with git config earlier). Running git commit first checks for any errors and warnings using lint. If @@ -130,65 +134,73 @@ The first line of your commit message is your commit summary. This is a brief one-line description of what you changed in the files using the template below: -`: Short description` -*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors* + : Short description + +For example, + + cpu/amd/pi/00630F01: Fix checkpatch warnings and errors **Note:** It is good practice to use present tense in your descriptions and do not punctuate your summary. Then hit Enter. The next paragraph should be a more in-depth explanation of the changes you've made to the files. Again, it is good practice to use present -tense. -*ex. Fix space prohibited between function name and open parenthesis, -line over 80 characters, unnecessary braces for single statement blocks, -space required before open brace errors and warnings.* +tense. Ex. + + Fix space prohibited between function name and open parenthesis, + line over 80 characters, unnecessary braces for single statement blocks, + space required before open brace errors and warnings. When you have finished writing your commit message, save and exit the text editor. You have finished committing your change. If, after submitting your -commit, you wish to make changes to it, running "git commit --amend" allows +commit, you wish to make changes to it, running `git commit --amend` allows you to take back your commit and amend it. -When you are done with your commit, run 'git push' to push your commit to +When you are done with your commit, run `git push` to push your commit to coreboot.org. **Note:** To submit as a draft, use -'git push origin HEAD:refs/drafts/master' Submitting as a draft means that +`git push origin HEAD:refs/drafts/master`. Submitting as a draft means that your commit will be on coreboot.org, but is only visible to those you add as reviewers. This has been a quick primer on how to submit a change to Gerrit for review -using git. You may wish to review the [Gerrit code review workflow +using git. You may wish to review the [Gerrit code review workflow documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review), especially if you plan to work on multiple changes at the same time. ## Part 4b: Using git cola to stage and submit a commit If git cola is not installed on your machine, see -https://git-cola.github.io/downloads.html for download instructions. + for download instructions. -After making some edits to src files, rather than run "git add," run -'git cola' from the command line. You should see all of the files +After making some edits to src files, rather than run `git add`, run +`git cola` from the command line. You should see all of the files edited under "Modified". In the textbox labeled "Commit summary" provide a brief one-line description of what you changed in the files according to the template below: -`: Short description` -*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors* + : Short description + +For example, + + cpu/amd/pi/00630F01: Fix checkpatch warnings and errors **Note:** It is good practice to use present tense in your descriptions and do not punctuate your short description. In the larger text box labeled 'Extended description...' provide a more in-depth explanation of the changes you've made to the files. Again, it -is good practice to use present tense. -*ex. Fix space prohibited between function name and open parenthesis, -line over 80 characters, unnecessary braces for single statement blocks, -space required before open brace errors and warnings.* +is good practice to use present tense. Ex. + + Fix space prohibited between function name and open parenthesis, + line over 80 characters, unnecessary braces for single statement blocks, + space required before open brace errors and warnings. Then press Enter two times to move the cursor to below your description. To the left of the text boxes, there is an icon with an downward arrow. Press the arrow and select "Sign Off." Make sure that you are signing off -with your name and email (i.e. **Your Name** ****, based on what +with your name and email (i.e. **Your Name** **\**, based on what you set with git config earlier). Now, review each of your changes and mark either individual changes or @@ -214,30 +226,30 @@ Note: Be sure to add any other changes that haven't already been explained in the extended description. When ready, select 'Commit' again. Once all errors have been satisfied -and the commit succeeds, move to the command line and run 'git push'. -**Note:** To submit as a draft, use 'git push origin HEAD:refs/drafts/master' +and the commit succeeds, move to the command line and run `git push`. +**Note:** To submit as a draft, use `git push origin HEAD:refs/drafts/master`. Submitting as a draft means that your commit will be on coreboot.org, but is only visible to those you add as reviewers. ## Part 5: Getting your commit reviewed -Your commits can now be seen on review.coreboot.org if you select “Your” -and click on “Changes” and can be reviewed by others. Your code will +Your commits can now be seen on review.coreboot.org if you select "Your" +and click on "Changes" and can be reviewed by others. Your code will first be reviewed by build bot (Jenkins), which will either give you a warning or verify a successful build; if so, your commit will receive a +1. Other -users may also give your commit +1. For a commit to be merged, it needs -to receive a +2.**Note:** A +1 and a +1 does not make a +2. Only certain users +users may also give your commit +1. For a commit to be merged, it needs +to receive a +2. **Note:** A +1 and a +1 does not make a +2. Only certain users can give a +2. ## Part 6 (optional): bash-git-prompt To help make it easier to understand the state of the git repository -without running 'git status' or 'git log', there is a way to make the +without running `git status` or `git log`, there is a way to make the command line show the status of the repository at every point. This is through bash-git-prompt. Instructions for installing this are found at: -https://github.com/magicmonty/bash-git-prompt +. **Note:** Feel free to search for different versions of git prompt, as this one is specific to bash. @@ -250,7 +262,7 @@ Run the following two commands in the command line: **Note:** cd will change your directory to your home directory, so the git clone command will be run there. -Finally, open the ~/.bashrc file and append the following two lines: +Finally, open the `~/.bashrc` file and append the following two lines: GIT_PROMPT_ONLY_IN_REPO=1 source ~/.bash-git-prompt/gitprompt.sh @@ -260,7 +272,7 @@ its state. There also are additional configurations that you can change depending on your preferences. If you wish to do so, look at the "All configs for .bashrc" section -on https://github.com/magicmonty/bash-git-prompt. Listed in that section are +on . Listed in that section are various lines that you can copy, uncomment and add to your .bashrc file to change the configurations. Example configurations include avoid fetching remote status, and supporting versions of Git older than 1.7.10. @@ -273,7 +285,7 @@ Suppose you would like to update a commit that has already been pushed to the remote repository. If the commit you wish to update is the most recent commit you have made, after making your desired changes, stage the files (either using git add or in git cola), and amend the commit. To do so, -if you are using the command line, run "git commit --amend." If you are +if you are using the command line, run `git commit --amend`. If you are using git cola, click on the gear icon located on the upper left side under **Commit** and select **Amend Last Commit** in the drop down menu. Then, stage the files you have changed, commit the changes, and run git push to push the diff --git a/Documentation/mainboard/asus/p8h61-m_pro.jpg b/Documentation/mainboard/asus/p8h61-m_pro.jpg new file mode 100644 index 00000000000..f3d60071b55 Binary files /dev/null and b/Documentation/mainboard/asus/p8h61-m_pro.jpg differ diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md new file mode 100644 index 00000000000..169678efcd5 --- /dev/null +++ b/Documentation/mainboard/asus/p8h61-m_pro.md @@ -0,0 +1,103 @@ +# ASUS P8H61-M Pro + +This page describes how to run coreboot on the [ASUS P8H61-M Pro]. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | W25Q32BV | ++---------------------+------------+ +| Size | 4 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +The flash IC is located right next to one of the SATA ports: +![](p8h61-m_pro.jpg) + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region (Management Engine or flash descriptor), then an external +programmer is required. + +The following command may be used to flash coreboot: + +``` +$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +## Known issues + +- There is no automatic, OS-independent fan control. This is because + the super I/O hardware monitor can only obtain valid CPU temperature + readings from the PECI agent, whose complete initialisation is not + publicly documented. The `coretemp` driver can still be used for + accurate CPU temperature readings. + +- me_cleaner breaks LPC bus and attached components! +- PS/2 mouse doesn't work + +## Untested + +- parallel port +- EHCI debug +- S/PDIF audio + +## Working + +- PS/2 keyboard +- PCIe graphics +- USB +- Gigabit Ethernet +- Integrated graphics +- SATA +- Serial port +- hardware monitor (see [Known issues](#known-issues) for caveats) +- front panel audio +- Native raminit (2 x 2GB, DDR3-1333) +- Native graphics init (libgfxinit) +- Wake-on-LAN +- TPM on TPM-header + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q32BV] + +[ASUS P8H61-M Pro]: https://www.asus.com/Motherboards/P8H61M_Pro/ +[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md new file mode 100644 index 00000000000..89e8a6abbca --- /dev/null +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -0,0 +1,83 @@ +# Facebook FBG-1701 + +This page describes how to run coreboot on the Facebook FBG1701. + +FBG1701 are assembled with different onboard memory modules: + Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + +Use make menuconfig to configure `onboard memory manufacturer` in Mainboard +menu. + +## Required blobs + +This board currently requires: +fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd +Microcode Intel Braswell cpuid 1046C4 version 410 + (Used pre-build binary retrieved from Intel site) + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located to the top middle side of the board. It's located +between SoC and Q7 connector. Use clip (or solder wires) to program +the chip. +Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found +[here][W25Q64FW]. + +The system has an external flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located in the middle of carrier board close to the flex cable +connection. +Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found +[here][W25Q64FV]. + +## Known issues + +- None + +## Untested + +- hardware monitor +- SDIO +- Full Embedded Controller support + +## Working + +- USB +- Gigabit Ethernet +- integrated graphics +- flashrom +- external graphics +- PCIe +- eMMC +- SATA +- serial port +- SMBus +- HDA +- initialization with FSP MR2 +- SeaBIOS payload +- Embedded Linux (Ubuntu 4.15+) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Atom Processor N3710 | ++------------------+--------------------------------------------------+ +| CPU | Intel Braswell (N3710) | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE8256 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf +[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md new file mode 100644 index 00000000000..714745aa043 --- /dev/null +++ b/Documentation/mainboard/hp/8760w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8760w + +This page describes how to run coreboot on the [HP EliteBook 8760w]. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q64.V | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +![8760w_chip_location](8760w_flash.jpg) + +## Untested + +- dock: serial port, parallel port, ... +- TPM +- S3 suspend/resume +- Gigabit Ethernet + +## Working + +- i7-2630QM, 0+4G+8G+0 +- i7-3720QM, 8G+8G+8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is at the right side, next to the charging port +- SATA +- eSATA +- USB2 and USB3 +- keyboard, touchpad, trackpad +- WLAN +- WWAN +- EC ACPI +- Using `me_cleaner` + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8760w]: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/5071180 diff --git a/Documentation/mainboard/hp/8760w_flash.jpg b/Documentation/mainboard/hp/8760w_flash.jpg new file mode 100644 index 00000000000..d9bbac6788a Binary files /dev/null and b/Documentation/mainboard/hp/8760w_flash.jpg differ diff --git a/Documentation/mainboard/hp/elitebook_series.md b/Documentation/mainboard/hp/elitebook_series.md new file mode 100644 index 00000000000..6668928008f --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_series.md @@ -0,0 +1,111 @@ +# HP EliteBook series + +This document is about HP EliteBook series laptops up to Ivy Bridge era +which use SMSC KBC1126 as embedded controller. + +## EC + +SMSC KBC1098/KBC1126 has been used in HP EliteBooks for many generations. +They use similar EC firmware that will load other code and data from the +SPI flash chip, so we need to put some firmware blobs to the coreboot image. + +The following document takes EliteBook 2760p as an example. + +First, you need to extract the blobs needed by EC firmware using util/kbc1126. +You can extract them from your backup firmware image, or firmware update +provided by HP with [unar] as follows: + +```bash +wget https://ftp.hp.com/pub/softpaq/sp79501-80000/sp79710.exe +unar sp79710.exe +${COREBOOT_DIR}/util/kbc1126/kbc1126_ec_dump sp79710/Rompaq/68SOU.BIN +mv 68SOU.BIN.fw1 ${COREBOOT_DIR}/2760p-fw1.bin +mv 68SOU.BIN.fw2 ${COREBOOT_DIR}/2760p-fw2.bin +``` + +When you config coreboot, select: + +```text +Chipset ---> + [*] Add firmware images for KBC1126 EC + (2760p-fw1.bin) KBC1126 firmware #1 path and filename + (2760p-fw2.bin) KBC1126 filename #2 path and filename +``` + +## Super I/O + +EliteBook 8000 series laptops have SMSC LPC47n217 Super I/O to provide +a serial port and a parallel port, you can debug the laptop via this +serial port. + +## porting + +To port coreboot to an HP EliteBook laptop, you need to do the following: + +- select Kconfig option `EC_HP_KBC1126` +- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 Super I/O +- initialize EC and Super I/O in romstage +- add EC and Super I/O support to devicetree.cb + +To get the related values for EC in devicetree.cb, you need to extract the EFI +module EcThermalInit from the vendor UEFI firmware with [UEFITool]. Usually, +`ec_data_port`, `ec_cmd_port` and `ec_ctrl_reg` has the following values: + +- For xx60 series: 0x60, 0x64, 0xca +- For xx70 series: 0x62, 0x66, 0x81 + +You can use [radare2] and the following [r2pipe] Python script to find +these values from the EcThermalInit EFI module: + +```python +#!/usr/bin/env python + +# install radare2 and use `pip3 install --user r2pipe` to install r2pipe + +import r2pipe +import sys + +if len(sys.argv) < 2: + fn = "ecthermalinit.efi" +else: + fn = sys.argv[1] + +r2 = r2pipe.open(fn) +r2.cmd("aa") +entryf = r2.cmdj("pdfj") + +for insn in entryf["ops"]: + if "lea r8" in insn["opcode"]: + _callback = insn["ptr"] + break + +r2.cmd("af @ {}".format(_callback)) +callbackf_insns = r2.cmdj("pdfj @ {}".format(_callback))["ops"] + +def find_port(addr): + ops = r2.cmdj("pdfj @ {}".format(addr))["ops"] + for insn in ops: + if "lea r8d" in insn["opcode"]: + return insn["ptr"] + +ctrl_reg_found = False + +for i in range(0, len(callbackf_insns)): + if not ctrl_reg_found and "mov cl" in callbackf_insns[i]["opcode"]: + ctrl_reg_found = True + ctrl_reg = callbackf_insns[i]["ptr"] + print("ec_ctrl_reg = 0x%02x" % ctrl_reg) + cmd_port = find_port(callbackf_insns[i+1]["jump"]) + data_port = find_port(callbackf_insns[i+3]["jump"]) + print("ec_cmd_port = 0x%02x\nec_data_port = 0x%02x" % (cmd_port, data_port)) + + if "mov bl" in callbackf_insns[i]["opcode"]: + ctrl_value = callbackf_insns[i]["ptr"] + print("ec_fan_ctrl_value = 0x%02x" % ctrl_value) +``` + + +[unar]: https://theunarchiver.com/command-line +[UEFITool]: https://github.com/LongSoft/UEFITool +[radare2]: https://radare.org/ +[r2pipe]: https://github.com/radare/radare2-r2pipe diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 7eaf425e209..f63ef763fb0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -6,6 +6,7 @@ This section contains documentation about coreboot on specific mainboards. - [F2A85-M](asus/f2a85-m.md) - [P8H61-M LX](asus/p8h61-m_lx.md) +- [P8H61-M Pro](asus/p8h61-m_pro.md) ## ASRock @@ -29,6 +30,10 @@ The boards in this section are not real mainboards, but emulators. - [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) +## Facebook + +- [FBG-1701](facebook/fbg1701.md) + ## Foxconn - [D41S](foxconn/d41s.md) @@ -44,11 +49,17 @@ The boards in this section are not real mainboards, but emulators. ## Open Cellular - [Elgon](opencellular/elgon.md) +- [Rotundu](opencellular/rotundu.md) ## HP - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +### EliteBook series + +- [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8760w](hp/8760w.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) @@ -70,6 +81,14 @@ The boards in this section are not real mainboards, but emulators. - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md) +## MSI + +- [MS-7707](msi/ms7707/ms7707.md) + +## Roda + +- [RK9 Flash Header](roda/rk9/flash_header.md) + ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) @@ -77,3 +96,7 @@ The boards in this section are not real mainboards, but emulators. ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) + +## UP + +- [Squared](up/squared/index.md) diff --git a/Documentation/mainboard/msi/ms7707/J1-flash-protect.jpg b/Documentation/mainboard/msi/ms7707/J1-flash-protect.jpg new file mode 100644 index 00000000000..b649d059a81 Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/J1-flash-protect.jpg differ diff --git a/Documentation/mainboard/msi/ms7707/JSPI1-Winbond-W25Q32BVSIG.jpg b/Documentation/mainboard/msi/ms7707/JSPI1-Winbond-W25Q32BVSIG.jpg new file mode 100644 index 00000000000..7a0df71dd77 Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/JSPI1-Winbond-W25Q32BVSIG.jpg differ diff --git a/Documentation/mainboard/msi/ms7707/JSPI1-connected.jpg b/Documentation/mainboard/msi/ms7707/JSPI1-connected.jpg new file mode 100644 index 00000000000..d1eed2760ed Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/JSPI1-connected.jpg differ diff --git a/Documentation/mainboard/msi/ms7707/JSPI1.png b/Documentation/mainboard/msi/ms7707/JSPI1.png new file mode 100644 index 00000000000..b1eadc28e68 Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/JSPI1.png differ diff --git a/Documentation/mainboard/msi/ms7707/flashlayout.svg b/Documentation/mainboard/msi/ms7707/flashlayout.svg new file mode 100644 index 00000000000..2bd826b10ca --- /dev/null +++ b/Documentation/mainboard/msi/ms7707/flashlayout.svg @@ -0,0 +1,34 @@ + + + + + + image/svg+xml + + + + + + + + IFD + + BIOS + + + + ME + + + GBE + + 0x000000 + 0x001000 + 0x003000 + 0x200000 + 0x400000 + + + + Flash + diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md new file mode 100644 index 00000000000..789431872cc --- /dev/null +++ b/Documentation/mainboard/msi/ms7707/ms7707.md @@ -0,0 +1,112 @@ +# MSI MS-7707 V1.1 + +* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) +* SandyBridge Intel P67 (BD82x6x) +* Winbond 25Q32BV (4MB) +* Fintek F71808A SuperIO +* Intel 82579V Gigabit +* NEC uPD720200 USB 3.0 Host Controller +* IME 7.0.4.1197 + +## Flash chip (Winbond 25Q32BV) +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Size | 4 MiB | ++---------------------+--------------------+ +| BIOS range | 2 MiB | ++---------------------+--------------------+ +| Write protection | Yes (via jumper) | ++---------------------+--------------------+ +| Header | Yes (JSPI1) | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +| Socketed flash | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| ME removable | Yes | ++---------------------+--------------------+ +``` + +## Installation instructions +* The standard method is to only flash the 2MiB BIOS region. In that case it's +not needed to extract blobs from vendor firmware and internal flashing is +sufficient. +* To flash the whole chip (e.g. to disable ME) blobs are needed to build +coreboot. Blobs can be extracted with util/ifdtool from 4MiB full dump image +(see below). Its recommended to include the VGA BIOS as well (4MiB write only). +Kconfig is prepared already if it gets enabled (path and 8086,0102). +``` +coreboot/3rdparty/blobs/mainboard/msi/ms7707 +├── descriptor.bin +├── gbe.bin +├── me.bin +└── vgabios.bin +``` +* Never write a full 4MiB image if blobs are not included. The generated +coreboot.rom file is always 4MiB but the 2MiB flash command below will only +flash the last 2MiB (BIOS) block. +* The J1-Jumper sets the 'Flash Descriptor Override Strap-Pin' and enables +full 4MiB access for internal flasher (read and write). +* **Write BIOS-range** (2MiB) with J1-Jumper=off (as on picture/default + position): +``` +flashrom -p internal:ich_spi_force=yes --noverify-all --ifd -i bios -w coreboot.rom +``` +* **Read full dump** (4MiB) with J1-jumper=on: +``` +flashrom -p internal -r original.rom +``` +* **Write full dump** (4MiB) with J1-Jumper=on: +``` +flashrom -p internal -w coreboot.rom +``` +* After successful flashing turn main power off, wait some seconds to drain +the capacitors, pull the battery and set the JBAT (clrcmos) jumper for some +seconds. Setting the jumper alone is not enough (the Fintek is VBAT backed). +Put all back in place and restart the board. It might need 1-2 AC power cycles +to reinitialize (running at full fan speed - don't panic). +* External flashing has been tested with RPi2 without main power connected. +3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html). +* In case of going back to proprietary BIOS create/save cmos settings as early +as possible (do not leave BIOS on first start without saving settings). +The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state +that needs an external flasher to revive. If stuck, reset the Fintek (see +above) and restart the system several times and/or try setting J1 to +temporarily disable ME. + +![](J1-flash-protect.jpg) + +* The JSPI1 header (5×2 2.0mm pitch pin header) for external flashing is +directly connected to the flash chip. Additional 3.3V to /HOLD and /WP is not +needed (internally re-routed already). + +![](JSPI1-Winbond-W25Q32BVSIG.jpg) + +![](JSPI1-connected.jpg) + +![](JSPI1.png) + +## Flash layout + +* The 4MiB flashrom is divided into 4 sections: + +![][flashlayout] + +## Links + +- [BIOS ROM] +- [Fintek F71808A datasheet] +- [Winbond 25Q32BV datasheet] + +[BIOS ROM]: https://www.medion.com/de/servicebackend/_lightbox/treiber_details.php?did=9744 +[Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf +[Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html +[flashlayout]: flashlayout.svg diff --git a/Documentation/mainboard/opencellular/rotundu.md b/Documentation/mainboard/opencellular/rotundu.md new file mode 100644 index 00000000000..8773e960a3b --- /dev/null +++ b/Documentation/mainboard/opencellular/rotundu.md @@ -0,0 +1,76 @@ +# Rutundu + +This page describes how to run coreboot on the [Rotundu] compute board +from [OpenCellular]. + +## TODO + +* Configure UART +* EC interface + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q128 | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit. +Directly connecting a Pomona test-clip on the flash is also possible. + +**Closeup view of SOIC-8 flash IC** + +![][rotundu_flash] + +[rotundu_flash]: rotundu_flash.jpg + +**SPI header** + +![][rotundu_header2] + +[rotundu_header2]: rotundu_header2.jpg + +**SPI header pinout** + +Dediprog compatible pinout. + +![][rotundu_j16] + +[rotundu_j16]: rotundu_j16.png + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Baytrail | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[Rotundu]: https://github.com/Telecominfraproject/OpenCellular +[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/ +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/opencellular/rotundu_flash.jpg b/Documentation/mainboard/opencellular/rotundu_flash.jpg new file mode 100644 index 00000000000..f14617c17aa Binary files /dev/null and b/Documentation/mainboard/opencellular/rotundu_flash.jpg differ diff --git a/Documentation/mainboard/opencellular/rotundu_header2.jpg b/Documentation/mainboard/opencellular/rotundu_header2.jpg new file mode 100644 index 00000000000..f6923068423 Binary files /dev/null and b/Documentation/mainboard/opencellular/rotundu_header2.jpg differ diff --git a/Documentation/mainboard/opencellular/rotundu_j16.png b/Documentation/mainboard/opencellular/rotundu_j16.png new file mode 100644 index 00000000000..1936365d801 Binary files /dev/null and b/Documentation/mainboard/opencellular/rotundu_j16.png differ diff --git a/Documentation/mainboard/roda/rk9/flash_header.md b/Documentation/mainboard/roda/rk9/flash_header.md new file mode 100644 index 00000000000..c2978cbe682 --- /dev/null +++ b/Documentation/mainboard/roda/rk9/flash_header.md @@ -0,0 +1,23 @@ +Roda RK9 Flash Header +===================== + +There is a 5x2 pin, 1.27mm pitch header *J1* south of the BIOS flash. It +follows the pinout of the Dediprog adaptor board: + + +------+ + | 1 2 | 1: HOLD 2 2: CS 2 + | 3 4 | 3: CS 1 4: VCC + | 5 6 | 5: MISO 6: HOLD 1 + | 7 8 | 7: 8: CLK + | 9 10 | 9: GND 10: MOSI + +------+ + +Pins 3 to 10 directly map to the regular SPI flash pinout. + +There is also a *JP17* around. Ideally, it should be closed during +programming (isolates the SPI bus from the southbridge): + + +---+ + | 1 | 1: SF100-I/O3 + | 2 | 2: GND + +---+ diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index cd7c93ca0b9..495dade2122 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -12,15 +12,13 @@ For general setup instructions, please refer to the [Getting Started Guide]. The following things are still missing from this coreboot port: - Support running romstage from flash (fix stack) to support boot mode 1 -- CBMEM support -- FU540 clock configuration -- FU540 RAM init -- Placing the ramstage in DRAM - Starting the U54 cores - FU540 PIN configuration and GPIO access macros - Provide serial number to payload (e.g. in device tree) +- Implement instruction emulation - Support for booting Linux on RISC-V - +- Add support to run OpenSBI payload in m-mode +- SMP support in trap handler ## Configuration diff --git a/Documentation/mainboard/up/squared/bottom.jpg b/Documentation/mainboard/up/squared/bottom.jpg new file mode 100644 index 00000000000..f9aa85db50a Binary files /dev/null and b/Documentation/mainboard/up/squared/bottom.jpg differ diff --git a/Documentation/mainboard/up/squared/index.md b/Documentation/mainboard/up/squared/index.md new file mode 100644 index 00000000000..dcf3ed192de --- /dev/null +++ b/Documentation/mainboard/up/squared/index.md @@ -0,0 +1,99 @@ +# Squared + +## Overview +### Top +![][overview_top] + +### Bottom +![][overview_bottom] + +## Mainboard components +### Platform +```eval_rst ++------------------+----------------------------------+ +| CPU | Intel Atom, Celeron, Pentium | ++------------------+----------------------------------+ +| PCH | Intel Apollo Lake | ++------------------+----------------------------------+ +| EC / Super IO | N/A | ++------------------+----------------------------------+ +| Coprocessor | Intel TXE 3.0 | ++------------------+----------------------------------+ +``` + +### Flash chip +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q128FW | ++---------------------+------------+ +| Voltage | 1.8V | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Internal flashing | No | ++---------------------+------------+ +| In curcuit flashing | Yes | ++---------------------+------------+ +``` + +## Board status +### Working +- bootblock, romstage, ramstage +- Serial console UART0, UART1 +- SPI flash console +- iGPU init with libgfxinit +- LAN1, LAN2 +- USB2, USB3 +- HDMI, DisplayPort +- eMMC +- flashing with flashrom externally + +### Work in progress +- Documentation +- ACPI + +### Not working / Known issues +- Generally SeaBIOS works, but it can't find the CBFS region and therefore it can't load seavgabios. This is because of changes at the Apollolake platform. + +### Untested +- GPIO pin header +- 60 pin EXHAT +- Camera interface + - MIPI-CSI2 2-lane (2MP) + - MIPI-CSI2 4-lane (8MP) +- SATA3 +- USB3 OTG +- embedded DisplayPort +- M.2 slot +- mini PCIe +- flashing with flashrom internally using Linux + +## Building and flashing coreboot +### Building + +```bash +make distclean +touch .config +./util/scripts/config --enable VENDOR_UP +./util/scripts/config --enable BOARD_UP_SQUARED +./util/scripts/config --enable NEED_IFWI +./util/scripts/config --enable HAVE_IFD_BIN +./util/scripts/config --set-str IFWI_FILE_NAME "" +./util/scripts/config --set-str IFD_BIN_PATH "" +make olddefconfig +``` + +### Flashing + +[overview_top]: top.jpg +[overview_bottom]: bottom.jpg diff --git a/Documentation/mainboard/up/squared/top.jpg b/Documentation/mainboard/up/squared/top.jpg new file mode 100644 index 00000000000..71adf459b73 Binary files /dev/null and b/Documentation/mainboard/up/squared/top.jpg differ diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index 36ab4c4385d..edfe4b8b84a 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -27,6 +27,83 @@ Now, place `mrc.bin` in the root of the coreboot directory. Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to its location when building coreboot. +## SPD Addresses + +When porting a board from vendor firmware, the SPD addresses can be obtained +through `i2c-tools`, which can be found in many GNU/Linux distributions. A more +[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of +the procedure and beyond can be found in +[Hannu Hartikainen's blog](https://hannuhartikainen.fi). + +First load the kernel modules: + +```bash +modprobe i2c-dev +modprobe eeprom +``` + +Find the SMBus and the addresses of the DIMM's EEPROMs (example output): +```bash +$ decode-dimms | grep Decoding +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050 +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052 +``` + +Alternatively, look at the sys filesystem: +```bash +$ ls -l /sys/bus/i2c/drivers/eeprom/ +total 0 +lrwxrwxrwx 1 root root 0 Apr 4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/ +--w------- 1 root root 4096 Apr 4 01:47 bind +lrwxrwxrwx 1 root root 0 Apr 4 01:47 module -> ../../../../module/eeprom/ +--w------- 1 root root 4096 Apr 4 01:46 uevent +--w------- 1 root root 4096 Apr 4 01:47 unbind +``` + +The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`. +Note that the above values are actually hex values. + +You can check the correctness of the SMBus and the addresses of the EEPROMs via +`i2cdetect`: + +```bash +$ i2cdetect -l +i2c-3 unknown i915 gmbus dpc N/A +i2c-1 unknown i915 gmbus vga N/A +i2c-6 unknown DPDDC-A N/A +i2c-4 unknown i915 gmbus dpb N/A +i2c-2 unknown i915 gmbus panel N/A +i2c-0 unknown i915 gmbus ssc N/A +i2c-7 unknown SMBus I801 adapter at f040 N/A +i2c-5 unknown i915 gmbus dpd N/A +``` + +Probing the SMBus: + +```bash +$ i2cdetect -r 7 +WARNING! This program can confuse your I2C bus, cause data loss and worse! +I will probe file /dev/i2c-7 using receive byte commands. +I will probe address range 0x03-0x77. +Continue? [Y/n] + 0 1 2 3 4 5 6 7 8 9 a b c d e f +00: -- -- -- -- -- -- -- -- -- -- -- -- -- +10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- +50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- +60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +70: -- -- -- -- -- -- -- -- +``` + +The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied +by 2. For example, if the addresses read through `i2c-tools` when booted from +vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and +`0xa4`. This is because the I2C addresses are 7 bits long. + ## ECC DRAM When `mrc.bin` has finished executing, ECC is active on the channels diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index dcb090aad69..c1d4b9948d2 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -6,3 +6,4 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid - [Native Ram Initialization](nri.md) - [RAM initialization feature matrix](nri_features.md) +- [ME Cleaner](me_cleaner.md) diff --git a/Documentation/northbridge/intel/sandybridge/me_cleaner.md b/Documentation/northbridge/intel/sandybridge/me_cleaner.md new file mode 100644 index 00000000000..1086e7e0919 --- /dev/null +++ b/Documentation/northbridge/intel/sandybridge/me_cleaner.md @@ -0,0 +1,20 @@ +# ME Cleaner +It's possible to 'clean' the ME partition within the flash medium as part +of the build process. While cleaning as much code as possible is removed +from the ME firmware partition. In this state the ME errors out and doesn't +operate any more. + +**Using a 'cleaned' ME partition may lead to issues and its use should be +carefully evaulated.** + +## Observations with 'cleaned' ME + +* Instable LPC bus + * SuperIO is malfunctioning + * TPM is malfunctioning + * Random system shutdowns on high bus activity + +## Filing bug reports + +Always test with unmodified IFD and ME section before reporting bugs to the +coreboot project. diff --git a/Documentation/security/index.md b/Documentation/security/index.md index 89db42eceec..9ad54866c2a 100644 --- a/Documentation/security/index.md +++ b/Documentation/security/index.md @@ -4,4 +4,5 @@ This section describes documentation about the security architecture of coreboot ## Vendor +- [Verified Boot](vboot/index.md) - [Measured Boot](vboot/measured_boot.md) diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md new file mode 100644 index 00000000000..97420893e57 --- /dev/null +++ b/Documentation/security/vboot/index.md @@ -0,0 +1,324 @@ +# vboot - Verified Boot Support + +Google's verified boot support consists of: + +* A root of trust +* Special firmware layout +* Firmware verification +* Firmware measurements +* A firmware update mechanism +* Specific build flags +* Signing the coreboot image + +Google's vboot verifies the firmware and places measurements within the TPM. + +*** + +## Root of Trust + +When using vboot, the root-of-trust is basically the read-only portion of the +SPI flash. The following items factor into the trust equation: + +* The GCC compiler must reliably translate the code into machine code + without inserting any additional code (virus, backdoor, etc.) +* The CPU must reliably execute the reset sequence and instructions as + documented by the CPU manufacturer. +* The SPI flash must provide only the code programmed into it to the CPU + without providing any alternative reset vector or code sequence. +* The SPI flash must honor the write-protect input and protect the specified + portion of the SPI flash from all erase and write accesses. + +The firmware is typically protected using the write-protect pin on the SPI +flash part and setting some of the write-protect bits in the status register +during manufacturing. The protected area is platform specific and for x86 +platforms is typically 1/4th of the SPI flash part size. +Because this portion of the SPI flash is hardware write protected, it is not +possible to update this portion of the SPI flash in the field, without altering +the system to eliminate the ground connection to the SPI flash write-protect pin. +Without hardware modifications, this portion of the SPI flash maintains the +manufactured state during the system's lifetime. + +*** + +## Firmware Layout + +Several sections are added to the firmware layout to support vboot: + +* Read-only section +* Google Binary Blob (GBB) area +* Read/write section A +* Read/write section B + +The following sections describe the various portions of the flash layout. + +### Read-Only Section + +The read-only section contains a coreboot file system (CBFS) that contains all +of the boot firmware necessary to perform recovery for the system. This firmware +is typically protected using the write-protect pin on the SPI flash part and +setting some of the write-protect bits in the status register during +manufacturing. +The protected area is typically 1/4th of the SPI flash part size and must cover +the entire read-only section which consists of: + +* Vital Product Data (VPD) area +* Firmware ID area +* Google Binary Blob (GBB) area +* coreboot file system containing read-only recovery firmware + +### Google Binary Blob (GBB) Area + +The GBB area is part of the read-only section. This area contains a 4096 or 8192 +bit public root RSA key that is used to verify the *VBLOCK* area to obtain the +firmware signing key. + +### Recovery Firmware + +The recovery firmware is contained within a coreboot file system and consists of: + +* reset vector +* bootblock +* verstage +* romstage +* postcar +* ramstage +* payload +* flash map file +* config file +* processor specific files: + * Microcode + * fspm.bin + * fsps.bin + +The recovery firmware is written during manufacturing and typically contains +code to write the storage device (eMMC device or hard disk). The recovery image +is usually contained on a socketed device such as a USB flash drive or an +SD card. Depending upon the payload firmware doing the recovery, it may be +possible for the user to interact with the system to specify the recovery +image path. Part of the recovery is also to write the A and B areas of the SPI +flash device to boot the system. + +### Read/Write Section + +The read/write sections contain an area which contains the firmware signing +key and signature and an area containing a coreboot file system with a subset +of the firmware. The firmware files in *FW_MAIN_A* and *FW_MAIN_B* are: + +* romstage +* postcar +* ramstage +* payload +* config file +* processor specific files: + * Microcode + * fspm.bin + * fsps.bin + +The firmware subset enables most issues to be fixed in the field with firmware +updates. The firmware files handle memory and most of silicon initialization. +These files also produce the tables which get passed to the operating system. + +*** + +## Firmware Updates + +The read/write sections exist in one of three states: + +* Invalid +* Ready to boot +* Successfully booted + + +Firmware updates are handled by the operating system by writing any read/write +section that is not in the "successfully booted" state. Upon the next reboot, +vboot determines the section to boot. If it finds one in the "ready to boot" +state then it attempts to boot using that section. If the boot fails then +vboot marks the section as invalid and attempts to fall back to a read/write +section in the "successfully booted" state. If vboot is not able to find a +section in the "successfully booted" state then vboot enters recovery mode. + +Only the operating system is able to transition a section from the +"ready to boot" state to the "successfully booted" state. +The transition is typically done after the operating system has been running +for a while indicating that successful boot was possible and the operating +system is stable. + +Note that as long as the SPI write protection is in place then the system +is always recoverable. If the flash update fails then the system will continue +to boot using the previous read/write area. The same is true if coreboot passes +control to the payload or the operating system and then the boot fails. In the +worst case, the SPI flash gets totally corrupted in which case vboot fails the +signature checks and enters recovery mode. There are no times where the SPI +flash is exposed and the reset vector or part of the recovery firmware gets +corrupted. + +*** + +## Build Flags + +The following *Kconfig* values need to be selected to enable vboot: + +* COLLECT_TIMESTAMPS +* VBOOT + +The starting stage needs to be specified by selecting either +VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE. + +If vboot starts in bootblock then vboot may be built as a separate stage by +selecting `VBOOT_SEPARATE_VERSTAGE`. Additionally, if static RAM is too small +to fit both verstage and romstage then selecting `VBOOT_RETURN_FROM_VERSTAGE` +enables bootblock to reuse the RAM occupied by verstage for romstage. + +Non-volatile flash is needed for vboot operation. This flash area may be in +CMOS, the EC, or in a read/write area of the SPI flash device. +Select one of the following: + +* `VBOOT_VBNV_CMOS` +* `VBOOT_VBNV_EC` +* `VBOOT_VBNV_FLASH` + +More non-volatile storage features may be found in `security/vboot/Kconfig`. + +A TPM is also required for vboot operation. +TPMs are available in `drivers/i2c/tpm` and `drivers/pc80/tpm`. + +In addition to adding the coreboot files into the read-only region, +enabling vboot causes the build script to add the read/write files into +coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*. + +*** + +## Signing the coreboot Image + +The following command script is an example of how to sign the coreboot image +file. This script is used on the Intel Galileo board and creates the *GBB* area +and inserts it into the coreboot image. It also updates the *VBLOCK* areas with +the firmware signing key and the signature for the *FW_MAIN* firmware. +More details are available in `3rdparty/vboot/README`. + +```bash +#!/bin/sh +# +# The necessary tools were built and installed using the following commands: +# +# pushd 3rdparty/vboot +# make +# sudo make install +# popd +# +# The keys were made using the following command +# +# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \ +# --4k --4k-root --output $PWD/keys +# +# +# The "magic" numbers below are derived from the GBB section in +# src/mainboard/intel/galileo/vboot.fmd. +# +# GBB Header Size: 0x80 +# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611) +# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f) +# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690) +# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170) +# +# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000 +# +# Create the GBB area blob +# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size +# +gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob + +# +# Copy from the start of the flash to the GBB region into the signed flash +# image. +# +# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB +# +dd conv=fdatasync ibs=4096 obs=4096 count=1553 \ +if=build/coreboot.rom of=build/coreboot.signed.rom + +# +# Append the empty GBB area to the coreboot.rom image. +# +# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB +# +dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \ +of=build/coreboot.signed.rom + +# +# Append the rest of the read-only region into the signed flash image. +# +# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area +# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area +# +dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \ +if=build/coreboot.rom of=build/coreboot.signed.rom + +# +# Insert the HWID and public root and recovery RSA keys into the GBB area. +# +gbb_utility \ +--set --hwid='Galileo' \ +-r $PWD/keys/recovery_key.vbpubk \ +-k $PWD/keys/root_key.vbpubk \ +build/coreboot.signed.rom + +# +# Sign the read/write firmware areas with the private signing key and update +# the VBLOCK_A and VBLOCK_B regions. +# +3rdparty/vboot/scripts/image_signing/sign_firmware.sh \ +build/coreboot.signed.rom \ +$PWD/keys \ + build/coreboot.signed.rom +``` + +*** + +## Boot Flow + +The reset vector exist in the read-only area and points to the bootblock +entry point. The only copy of the bootblock exists in the read-only area +of the SPI flash. Verstage may be part of the bootblock or a separate stage. +If separate then the bootblock loads verstage from the read-only area and +transfers control to it. + +Upon first boot, verstage attempts to verify the read/write section A. +It gets the public root key from the GBB area and uses that to verify the +*VBLOCK* area in read-write section A. If the *VBLOCK* area is valid then it +extracts the firmware signing key (1024-8192 bits) and uses that to verify +the *FW_MAIN_A* area of read/write section A. If the verification is successful +then verstage instructs coreboot to use the coreboot file system in read/write +section A for the contents of the remaining boot firmware (romstage, postcar, +ramstage and the payload). + +If verification fails for the read/write area and the other read/write area is +not valid vboot falls back to the read-only area to boot into system recovery. + +*** + +## Chromebook Special Features + +Google's Chromebooks have some special features: + +* Developer mode +* Write-protect screw + +### Developer Mode + +Developer mode allows the user to use coreboot to boot another operating system. +This may be a another (beta) version of Chrome OS, or another flavor of +GNU/Linux. Use of developer mode does not void the system warranty. Upon entry +into developer mode, all locally saved data on the system is lost. +This prevents someone from entering developer mode to subvert the system +security to access files on the local system or cloud. + +### Write Protect Screw + +Chromebooks have a write-protect screw which provides the ground to the +write-protect pin of the SPI flash. +Google specifically did this to allow the manufacturing line and advanced +developers to re-write the entire SPI flash part. Once the screw is removed, +any firmware may be placed on the device. +However, accessing this screw requires opening the case and voids the +system warranty! diff --git a/Documentation/soc/intel/fit.dia b/Documentation/soc/intel/fit.dia new file mode 100644 index 00000000000..7e07978f710 Binary files /dev/null and b/Documentation/soc/intel/fit.dia differ diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md new file mode 100644 index 00000000000..8b638f04332 --- /dev/null +++ b/Documentation/soc/intel/fit.md @@ -0,0 +1,60 @@ +# Intel Firmware Interface Table + +The FIT allows to run code before the actual IA32 reset vector is executed +by the CPU. The FIT resides in the BIOS region (usually near the reset vector) +and is pointed to by the FIT pointer residing at `0xFFFFFFC0`. + +## Table layout +The table consists of blocks each 16 bytes in size. +The first is called *FIT header* the other are called *FIT entry*. + +![FIT in x86 memory map][fit] + +[fit]: fit.svg + +## Fit types + +Each entry has a *type* that give the other bits in the entry a different +meaning. The following types are known: + +```eval_rst ++-----------+------------------------------------------------------------------+ +| no. | Description | ++===========+==================================================================+ +| 0x0 | HEADER. | ++-----------+------------------------------------------------------------------+ +| 0x1 | MICROCODE. | ++-----------+------------------------------------------------------------------+ +| 0x2 | STARTUP_ACM. | ++-----------+------------------------------------------------------------------+ +| 0x7 | BIOS_STARTUP_MODULE. | ++-----------+------------------------------------------------------------------+ +| 0x8 | TPM_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0x9 | BIOS_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0xa | TXT_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0xb | KEY_MANIFEST. | ++-----------+------------------------------------------------------------------+ +| 0xc | BOOT_POLICY_MANIFEST. | ++-----------+------------------------------------------------------------------+ +| 0x10 | CSE_SECURE_BOOT. | ++-----------+------------------------------------------------------------------+ +| 0x2d | TXTSX_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0x2f | JMP_DEBUG_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0x7f | SKIP. | ++-----------+------------------------------------------------------------------+ +``` + +## Usage in coreboot + +The most common usage of FIT is to use *Type1* to update microcode before +execution of the IA32 reset vector happens. + +## References + +* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) +* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf) diff --git a/Documentation/soc/intel/fit.svg b/Documentation/soc/intel/fit.svg new file mode 100644 index 00000000000..eb6c696bb78 --- /dev/null +++ b/Documentation/soc/intel/fit.svg @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + bootblock + + + + + + + + + + + + + + + 4 GiB + + + 4 GiB - 10h + + + 4 GiB - x + + + 4 GiB - 40 h + + + + FIT Ptr + + + IA32 reset vec + + + + + + + + + + + + 4 GiB - z + + + + + + + + + + + 4 GiB - y + + + ACM + + + BOOTBLOCK + CODE + + + uCode + + + + + + + + + + + + + + + + FIT header + + + Type1 entry + + + Type2 entry + + + Type7 entry + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 4f6b4f21b6b..86f4de71559 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -8,3 +8,4 @@ This section contains documentation about coreboot on specific Intel SOCs. - [FSP](fsp/index.md) - [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) +- [Firmware Interface Table](fit.md) diff --git a/Documentation/vendorcode/eltan/index.md b/Documentation/vendorcode/eltan/index.md new file mode 100644 index 00000000000..4484798a23c --- /dev/null +++ b/Documentation/vendorcode/eltan/index.md @@ -0,0 +1,8 @@ +# Eltan vendorcode-specific documentation + +This section contains documentation about coreboot on Eltan specific +vendorcode. + +## Sections + +- [Security](security.md) diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md new file mode 100644 index 00000000000..04537df23ca --- /dev/null +++ b/Documentation/vendorcode/eltan/security.md @@ -0,0 +1,39 @@ +# Eltan Security + +## Security +This code enables measured boot and verified boot support. +Verified boot is available in coreboot, but based on ChromeOS. This vendorcode +uses a small encryption library and leave much more space in flash for the +payload. + +## Hashing Library +The library suppports SHA-1, SHA-256 and SHA-512. The required routines of +`3rdparty/vboot/firmware/2lib` are used. + +## Measured boot +measured boot support will use TPM2 device if available. The items specified +in `mb_log_list[]` will be measured. + +## Verified boot +verified boot support will use TPM2 device if available. The items specified +in the next table will be verified: +* `bootblock_verify_list[]` +* `verify_item_t romstage_verify_list[]` +* `ram_stage_additional_list[]` +* `ramstage_verify_list[]` +* `payload_verify_list[]` +* `oprom_verify_list[]` + +## Enabling support + +* Measured boot can be enabled using **CONFIG_MBOOT** +* Create mb_log_list table with list of item to measure +* Create tables bootblock_verify_list[], verify_item_t romstage_verify_list[], + ram_stage_additional_list[], ramstage_verify_list[], payload_verify_list[], + oprom_verify_list[] +* Verified boot can be enabled using **CONFIG_VERIFIED_BOOT** +* Added Kconfig values for verbose console output + +## Debugging + +You can enable verbose console output in *menuconfig*. diff --git a/MAINTAINERS b/MAINTAINERS index 04f784f8899..f1ae0769373 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -382,6 +382,12 @@ M: Tristan Corrick S: Maintained F: src/mainboard/supermicro/x10slm-f/ +FACEBOOK FBG1701 MAINBOARD +M: Frans Hendriks +M: Wim Vervoorn +S: Maintained +F: src/mainboard/facebook/fbg1701/ + AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE M: Timothy Pearson S: Supported diff --git a/Makefile.inc b/Makefile.inc index 36c05dbac47..d4f7597e82d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -31,7 +31,7 @@ CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE)) # misleadingly named, this is the coreboot version ifeq ($(KERNELVERSION),) ifeq ($(BUILD_TIMELESS),1) -KERNELVERSION := TIMELESS +KERNELVERSION := -TIMELESS--LESSTIME- else KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --dirty --always || git describe),\ @@ -196,15 +196,12 @@ ifeq ($(CONFIG_USE_BLOBS),y) # this is necessary because 3rdparty/blobs is update=none, and so is ignored # unless explicitly requested and enabled through --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) -endif -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y) -ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) +ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y) +# this is necessary because 3rdparty/fsp is update=none, and so is ignored +# unless explicitly requested and enabled through --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) endif endif -endif UPDATED_SUBMODULES:=1 COREBOOT_EXPORTS += UPDATED_SUBMODULES endif @@ -267,7 +264,14 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $(obj)/$(1).asl cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $(1).asl - if [ -z "$$$$($(IASL) -d $$@ 2>&1 | grep 'ACPI Warning')" ]; then echo " IASL $$@ disassembled correctly."; true; else echo "Error: Could not correctly disassemble $$@"; $(IASL) -d $$@; false; fi + if ! $(IASL) -d $$@ 2>&1 | grep -Eq 'ACPI (Warning|Error)'; then \ + echo " IASL $$@ disassembled correctly."; \ + true; \ + else \ + echo "Error: Could not correctly disassemble $$@"; \ + $(IASL) -d $$@; \ + false; \ + fi endef ####################################################################### @@ -397,7 +401,7 @@ endif CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time +CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) diff --git a/configs/config.lenovo_t420_static_option_table_no_mem_fuses b/configs/config.lenovo_t420_static_option_table_no_mem_fuses index a268d88b78d..0a3513cfac4 100644 --- a/configs/config.lenovo_t420_static_option_table_no_mem_fuses +++ b/configs/config.lenovo_t420_static_option_table_no_mem_fuses @@ -4,4 +4,6 @@ CONFIG_VENDOR_LENOVO=y CONFIG_BOARD_LENOVO_T420=y CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y +CONFIG_VBOOT=y +CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y # CONFIG_INTEL_CHIPSET_LOCKDOWN is not set diff --git a/configs/config.lenovo_x220_mrc_bin b/configs/config.lenovo_x220_mrc_bin new file mode 100644 index 00000000000..a51c4989049 --- /dev/null +++ b/configs/config.lenovo_x220_mrc_bin @@ -0,0 +1,3 @@ +CONFIG_VENDOR_LENOVO=y +CONFIG_BOARD_LENOVO_X220=y +# CONFIG_USE_NATIVE_RAMINIT is not set diff --git a/mmax.config b/mmax.config new file mode 100644 index 00000000000..cde9d01b503 --- /dev/null +++ b/mmax.config @@ -0,0 +1,762 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_NO_RELOCATABLE_RAMSTAGE=y +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_RAMPAYLOAD is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="intel/minnowmax" +CONFIG_MAINBOARD_PART_NUMBER="Minnow Max" +CONFIG_MAX_CPUS=16 +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp.fd" +CONFIG_CBFS_SIZE=0x00600000 +CONFIG_ENABLE_FSP_FAST_BOOT=y +CONFIG_VIRTUAL_ROM_SIZE=0x800000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_VGA_BIOS_ID="8086,0f31" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vga.dat" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x4000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set +# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set +# CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set +# CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set +# CONFIG_BOARD_INTEL_CANNONLAKE_RVPU is not set +# CONFIG_BOARD_INTEL_CANNONLAKE_RVPY is not set + +# +# Coffeelake RVP +# +# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set +# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set +# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set +# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set +# CONFIG_BOARD_INTEL_COMETLAKE_RVP is not set +# CONFIG_BOARD_INTEL_D510MO is not set +# CONFIG_BOARD_INTEL_D945GCLF is not set +# CONFIG_BOARD_INTEL_DCP847SKE is not set +# CONFIG_BOARD_INTEL_DG41WV is not set +# CONFIG_BOARD_INTEL_DG43GT is not set +# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set +# CONFIG_BOARD_INTEL_GALILEO is not set +# CONFIG_BOARD_INTEL_GLKRVP is not set +# CONFIG_BOARD_INTEL_HARCUVAR is not set +# CONFIG_BOARD_INTEL_ICELAKE_RVPU is not set +# CONFIG_BOARD_INTEL_ICELAKE_RVPY is not set +# CONFIG_BOARD_INTEL_KBLRVP3 is not set +# CONFIG_BOARD_INTEL_KBLRVP7 is not set +# CONFIG_BOARD_INTEL_KBLRVP8 is not set +# CONFIG_BOARD_INTEL_KBLRVP11 is not set +# CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LEAFHILL is not set +# CONFIG_BOARD_INTEL_LITTLEPLAINS is not set +# CONFIG_BOARD_INTEL_MINNOW3 is not set +CONFIG_BOARD_INTEL_MINNOWMAX=y +# CONFIG_BOARD_INTEL_MOHONPEAK is not set +# CONFIG_BOARD_INTEL_SKLSDLBRK is not set +# CONFIG_BOARD_INTEL_STRAGO is not set +# CONFIG_BOARD_INTEL_WTM2 is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Minnow Max" +# CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/txe.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_FSP_LOC=0xfffc0000 +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/fsp_baytrail/bootblock/bootblock.c" +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="" +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_ENABLE_BUILTIN_COM1=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_TTYS0_BASE=0x3f8 +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_SOC_INTEL_FSP_BAYTRAIL=y +# CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD is not set +CONFIG_CPU_MICROCODE_HEADER_FILES="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/M0130673324.h 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/M0130679901.h" +CONFIG_BAYTRAIL_FSP_SPECIFIC_OPTIONS=y +CONFIG_CONSOLE_CBMEM=y +CONFIG_FSP_SRC_PATH="" +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_QC_SDI_ENABLE is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_ENABLE_MRC_CACHE=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +# CONFIG_PARALLEL_MP_AP_WORK is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +CONFIG_PLATFORM_USES_FSP1_0=y +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USES_MICROCODE_HEADER_FILES=y +CONFIG_MICROCODE_BLOB_NOT_HOOKED_UP=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +CONFIG_FSP_VENDORCODE_HEADER_PATH="fsp1_0/baytrail" +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +# CONFIG_ARCH_POSTCAR_X86_32 is not set +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_NO_GFX_INIT=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +CONFIG_HAVE_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set + +# +# Intel FSP +# +CONFIG_HAVE_FSP_BIN=y +CONFIG_MRC_CACHE_FMAP=y +CONFIG_USE_GENERIC_FSP_CAR_INC=y +CONFIG_FSP_USES_UPD=y +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +# CONFIG_HAVE_ACPI_RESUME is not set +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +# CONFIG_IOAPIC is not set +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +# CONFIG_PXE_ROM is not set +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_STABLE=y +# CONFIG_IPXE_MASTER is not set +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_PXE_SERIAL_CONSOLE=y +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +CONFIG_BAREFLANK_SECONDARY_PAYLOAD=y +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set +CONFIG_MEMTEST_STABLE=y +# CONFIG_MEMTEST_MASTER is not set +# CONFIG_MEMTEST_REVISION is not set + +# +# Reserve RAM for payload +# +CONFIG_CUSTOM_RAM_RES_ADDR=0x21000000 +CONFIG_CUSTOM_RAM_RES_SIZE=0x20920000 + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_NO_STAGE_CACHE=y +CONFIG_BOOTBLOCK_CUSTOM=y diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a440800..d339cfeb34b 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -124,6 +124,13 @@ config COREINFO_SECONDARY_PAYLOAD coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads. +config BAREFLANK_SECONDARY_PAYLOAD + bool "Load Bareflank as a secondary payload" + default n + depends on ARCH_X86 + help + Bareflank can be loaded before primary payload. + config MEMTEST_SECONDARY_PAYLOAD bool "Load Memtest86+ as a secondary payload" default n @@ -151,4 +158,20 @@ config TINT_SECONDARY_PAYLOAD source "payloads/external/*/Kconfig.secondary" endmenu # "Secondary Payloads" + +menu "Reserve RAM for payload" + +config CUSTOM_RAM_RES_ADDR + hex "Base address for reserved memory" + default 0 + help + If a payload needs some preallocated memory this field specifies + starting address of reserved memory region. + +config CUSTOM_RAM_RES_SIZE + hex "Size of reserved memory" + default 0 + help + Size (in bytes) of reserved memory region. +endmenu endmenu diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 83d3910ce06..3f77fe432e8 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -13,6 +13,11 @@ ## GNU General Public License for more details. ## +cbfs-files-$(CONFIG_BAREFLANK_SECONDARY_PAYLOAD) += $(CONFIG_CBFS_PREFIX)/payload +$(CONFIG_CBFS_PREFIX)/payload-file := payloads/bareflank/build/bareflank.elf +$(CONFIG_CBFS_PREFIX)/payload-type := payload +$(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG) + cbfs-files-$(CONFIG_COREINFO_SECONDARY_PAYLOAD) += img/coreinfo img/coreinfo-file := payloads/coreinfo/build/coreinfo.elf img/coreinfo-type := payload @@ -24,6 +29,7 @@ img/nvramcui-type := payload img/nvramcui-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG) PAYLOADS_LIST=\ +payloads/bareflank \ payloads/coreinfo \ payloads/nvramcui \ payloads/libpayload \ @@ -38,6 +44,9 @@ payloads/external/GRUB2 \ payloads/external/LinuxBoot \ payloads/external/Yabits \ +payloads/bareflank/build/bareflank.elf bareflank: + $(MAKE) -C payloads/bareflank defaultbuild CONFIG_CBFS_PREFIX=$(CONFIG_CBFS_PREFIX) + payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild diff --git a/payloads/bareflank/Kconfig b/payloads/bareflank/Kconfig new file mode 100644 index 00000000000..8cee21381db --- /dev/null +++ b/payloads/bareflank/Kconfig @@ -0,0 +1,17 @@ +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# +# For a description of the syntax of this configuration file, +# see http://lxr.linux.no/source/Documentation/kbuild/kconfig-language.txt. +# + +mainmenu "Bareflank Configuration" diff --git a/payloads/bareflank/Makefile b/payloads/bareflank/Makefile new file mode 100644 index 00000000000..c19fcb79dd6 --- /dev/null +++ b/payloads/bareflank/Makefile @@ -0,0 +1,144 @@ +## +## This file is part of the coreinfo project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## Copyright (C) 2008 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +src := $(CURDIR) +srctree := $(src) +srck := $(src)/../../util/kconfig +coreinfo_obj := $(src)/build +objk := $(src)/build/util/kconfig + +ifeq ($(filter %clean,$(MAKECMDGOALS)),) +export KERNELVERSION := 0.1.0 +export KCONFIG_AUTOHEADER := $(coreinfo_obj)/config.h +export KCONFIG_AUTOCONFIG := $(coreinfo_obj)/auto.conf +export KCONFIG_DEPENDENCIES := $(coreinfo_obj)/auto.conf.cmd +export KCONFIG_SPLITCONFIG := $(coreinfo_obj)/config +export KCONFIG_TRISTATE := $(coreinfo_obj)/tristate.conf +export KCONFIG_CONFIG := $(CURDIR)/.config +export KCONFIG_NEGATIVES := 1 +export Kconfig := Kconfig + +export V := $(V) + +CONFIG_SHELL := sh +KBUILD_DEFCONFIG := configs/defconfig +UNAME_RELEASE := $(shell uname -r) +HAVE_DOTCONFIG := $(wildcard .config) +MAKEFLAGS += -rR --no-print-directory + +# Make is silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +.SILENT: +endif + +HOSTCC ?= gcc +HOSTCXX ?= g++ +HOSTCFLAGS := -I$(srck) -I$(objk) +HOSTCXXFLAGS := -I$(srck) -I$(objk) + +LIBPAYLOAD_PATH := $(realpath ../libpayload) +LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload +HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a) +LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses-64 +OBJCOPY ?= objcopy + +INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_OBJ)/include/kconfig.h -I$(src)/../../src/commonlib/include -I$(src)/include -I$(src) +OBJECTS = common.o entry.o platform.o +OBJS = $(patsubst %,$(coreinfo_obj)/%,$(OBJECTS)) +TARGET = $(coreinfo_obj)/bareflank.elf + +all: real-all + +# in addition to the dependency below, create the file if it doesn't exist +# to silence warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) +.xcompile: ../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@ + +CONFIG_COMPILER_GCC := y +ARCH-y := x86_64 + +include .xcompile + +CC := $(CC_$(ARCH-y)) +AS := $(AS_$(ARCH-y)) +OBJCOPY := $(OBJCOPY_$(ARCH-y)) + +LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc +LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas + +CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) + +ifneq ($(strip $(HAVE_DOTCONFIG)),) +include $(src)/.config +real-all: $(TARGET) + +$(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload + printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" + $(LPCC) -o $@ $(OBJS) + $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ + +$(coreinfo_obj)/%.S.o: $(src)/%.S libpayload + printf " LPAS $(subst $(CURDIR)/,,$(@))\n" + $(LPAS) -o $@ $< + +$(coreinfo_obj)/%.o: $(src)/%.c libpayload + printf " LPCC $(subst $(CURDIR)/,,$(@))\n" + $(LPCC) $(CFLAGS) -c -o $@ $< -DCONFIG_CBFS_PREFIX=\"$(CONFIG_CBFS_PREFIX)\" + +else +real-all: config +endif + +defaultbuild: + $(MAKE) olddefconfig + $(MAKE) all + +ifneq ($(strip $(HAVE_LIBPAYLOAD)),) +libpayload: + printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n" +else +LPOPTS=obj="$(CURDIR)/lpbuild" DOTCONFIG="$(CURDIR)/lp.config" +libpayload: + printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n" + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) distclean coreinfo_obj=$(coreinfo_obj)/libptmp + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG) + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) install DESTDIR=$(coreinfo_obj) +endif + +$(coreinfo_obj)/config.h: + $(MAKE) oldconfig + +$(shell mkdir -p $(coreinfo_obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) + +include $(srck)/Makefile + +.PHONY: $(PHONY) prepare + +else + +clean: + rm -rf build/*.elf build/*.o .xcompile + +distclean: clean + rm -rf build lpbuild + rm -f .config* lp.config* + +.PHONY: clean distclean +endif diff --git a/payloads/bareflank/common.c b/payloads/bareflank/common.c new file mode 100755 index 00000000000..2e1d55ab6bb --- /dev/null +++ b/payloads/bareflank/common.c @@ -0,0 +1,521 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +/* -------------------------------------------------------------------------- */ +/* Global */ +/* -------------------------------------------------------------------------- */ + +int64_t g_num_modules = 0; +struct bfelf_binary_t g_modules[MAX_NUM_MODULES]; + +_start_t _start_func = 0; +struct crt_info_t g_info; +struct bfelf_loader_t g_loader; + +int64_t g_num_cpus_started = 0; +int64_t g_vmm_status = VMM_UNLOADED; + +void *g_tls = 0; +void *g_stack = 0; + +uint64_t g_tls_size = 0; +uint64_t g_stack_size = 0; +uint64_t g_stack_top = 0; + +void *g_rsdp = 0; + +/* -------------------------------------------------------------------------- */ +/* Helpers */ +/* -------------------------------------------------------------------------- */ + +int64_t +private_setup_stack(void) +{ + g_stack_size = STACK_SIZE * 2; + + g_stack = platform_alloc_rw(g_stack_size); + if (g_stack == 0) { + return BF_ERROR_OUT_OF_MEMORY; + } + + g_stack_top = (uint64_t)g_stack + g_stack_size; + g_stack_top = (g_stack_top & ~(STACK_SIZE - 1)) - 1; + + platform_memset(g_stack, 0, g_stack_size); + return BF_SUCCESS; +} + +int64_t +private_setup_tls(void) +{ + g_tls_size = THREAD_LOCAL_STORAGE_SIZE * (uint64_t)platform_num_cpus(); + + g_tls = platform_alloc_rw(g_tls_size); + if (g_tls == 0) { + return BF_ERROR_OUT_OF_MEMORY; + } + + platform_memset(g_tls, 0, g_tls_size); + return BF_SUCCESS; +} + +int64_t +private_setup_rsdp(void) +{ + g_rsdp = platform_get_rsdp(); + return BF_SUCCESS; +} + +int64_t +private_add_raw_md_to_memory_manager(uint64_t virt, uint64_t type) +{ + int64_t ret = 0; + struct memory_descriptor md = {0, 0, 0}; + + md.virt = virt; + md.phys = (uint64_t)platform_virt_to_phys((void *)md.virt); + md.type = type; + + ret = platform_call_vmm_on_core( + 0, BF_REQUEST_ADD_MDL, (uintptr_t)&md, 0); + + if (ret != MEMORY_MANAGER_SUCCESS) { + return ret; + } + + return BF_SUCCESS; +} + +int64_t +private_add_md_to_memory_manager(struct bfelf_binary_t *module) +{ + bfelf64_word s = 0; + + for (s = 0; s < bfelf_file_get_num_load_instrs(&module->ef); s++) { + + int64_t ret = 0; + + uint64_t exec_s = 0; + uint64_t exec_e = 0; + const struct bfelf_load_instr *instr = 0; + + ret = bfelf_file_get_load_instr(&module->ef, s, &instr); + bfignored(ret); + + exec_s = (uint64_t)module->exec + instr->mem_offset; + exec_e = (uint64_t)module->exec + instr->mem_offset + instr->memsz; + exec_s &= ~(BAREFLANK_PAGE_SIZE - 1); + exec_e &= ~(BAREFLANK_PAGE_SIZE - 1); + + for (; exec_s <= exec_e; exec_s += BAREFLANK_PAGE_SIZE) { + if ((instr->perm & bfpf_x) != 0) { + ret = private_add_raw_md_to_memory_manager( + exec_s, MEMORY_TYPE_R | MEMORY_TYPE_E); + } + else { + ret = private_add_raw_md_to_memory_manager( + exec_s, MEMORY_TYPE_R | MEMORY_TYPE_W); + } + + if (ret != MEMORY_MANAGER_SUCCESS) { + return ret; + } + } + } + + return BF_SUCCESS; +} + +int64_t +private_add_tss_mdl(void) +{ + uint64_t i = 0; + + for (i = 0; i < g_tls_size; i += BAREFLANK_PAGE_SIZE) { + + int64_t ret = private_add_raw_md_to_memory_manager( + (uint64_t)g_tls + i, MEMORY_TYPE_R | MEMORY_TYPE_W); + + if (ret != BF_SUCCESS) { + return ret; + } + } + + return BF_SUCCESS; +} + +int64_t +private_add_modules_mdl(void) +{ + int64_t i = 0; + + for (i = 0; i < g_num_modules; i++) { + int64_t ret = private_add_md_to_memory_manager(&g_modules[i]); + if (ret != BF_SUCCESS) { + return ret; + } + } + + return BF_SUCCESS; +} + +/* -------------------------------------------------------------------------- */ +/* Implementation */ +/* -------------------------------------------------------------------------- */ + +int64_t +common_vmm_status(void) +{ return g_vmm_status; } + +void +common_reset(void) +{ + int64_t i; + + for (i = 0; i < g_num_modules; i++) { + if (g_modules[i].exec != 0) { + platform_free_rwe(g_modules[i].exec, g_modules[i].exec_size); + } + } + + platform_memset(&g_modules, 0, sizeof(g_modules)); + platform_memset(&g_loader, 0, sizeof(struct bfelf_loader_t)); + platform_memset(&g_info, 0, sizeof(struct crt_info_t)); + platform_memset(&g_loader, 0, sizeof(struct bfelf_loader_t)); + + _start_func = 0; + + g_num_modules = 0; + g_num_cpus_started = 0; + g_vmm_status = VMM_UNLOADED; + + if (g_tls != 0) { + platform_free_rw(g_tls, g_tls_size); + } + + if (g_stack != 0) { + platform_free_rw(g_stack, g_stack_size); + } + + g_tls = 0; + g_stack = 0; + g_stack_top = 0; + + g_rsdp = 0; +} + +int64_t +common_init(void) +{ + int64_t ret = platform_init(); + if (ret != BF_SUCCESS) { + return ret; + } + + common_reset(); + + return BF_SUCCESS; +} + +int64_t +common_fini(void) +{ + if (common_vmm_status() == VMM_RUNNING) { + if (common_stop_vmm() != BF_SUCCESS) { + BFALERT("common_fini: failed to stop vmm\n"); + } + } + + if (common_vmm_status() == VMM_LOADED) { + if (common_unload_vmm() != BF_SUCCESS) { + BFALERT("common_fini: failed to unload vmm\n"); + } + } + + if (common_vmm_status() == VMM_CORRUPT) { + return BF_ERROR_VMM_CORRUPTED; + } + + if (g_num_modules > 0) { + common_reset(); + } + + return BF_SUCCESS; +} + +int64_t +common_add_module(const char *file, uint64_t fsize) +{ + if (file == 0 || fsize == 0) { + return BF_ERROR_INVALID_ARG; + } + + switch (common_vmm_status()) { + case VMM_CORRUPT: + return BF_ERROR_VMM_CORRUPTED; + case VMM_LOADED: + return BF_ERROR_VMM_INVALID_STATE; + case VMM_RUNNING: + return BF_ERROR_VMM_INVALID_STATE; + default: + break; + } + + if (g_num_modules >= MAX_NUM_MODULES) { + return BF_ERROR_MAX_MODULES_REACHED; + } + + g_modules[g_num_modules].file = file; + g_modules[g_num_modules].file_size = fsize; + + g_num_modules++; + return BF_SUCCESS; +} + +int64_t +common_load_vmm(void) +{ + int64_t ret = 0; + int64_t ignore_ret = 0; + + switch (common_vmm_status()) { + case VMM_CORRUPT: + return BF_ERROR_VMM_CORRUPTED; + case VMM_LOADED: + return BF_SUCCESS; + case VMM_RUNNING: + return BF_ERROR_VMM_INVALID_STATE; + default: + break; + } + + if (g_num_modules == 0) { + return BF_ERROR_NO_MODULES_ADDED; + } + + ret = private_setup_stack(); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = private_setup_tls(); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = private_setup_rsdp(); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = bfelf_load(g_modules, (uint64_t)g_num_modules,(void **)&_start_func, &g_info, &g_loader); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = platform_call_vmm_on_core(0, BF_REQUEST_INIT, 0, 0); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = platform_call_vmm_on_core(0, BF_REQUEST_SET_RSDP, (uint64_t)g_rsdp, 0); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = private_add_modules_mdl(); + if (ret != BF_SUCCESS) { + goto failure; + } + + ret = private_add_tss_mdl(); + if (ret != BF_SUCCESS) { + goto failure; + } + + g_vmm_status = VMM_LOADED; + return BF_SUCCESS; + +failure: + + ignore_ret = common_unload_vmm(); + bfignored(ignore_ret); + + return ret; +} + +int64_t +common_unload_vmm(void) +{ + int64_t ret = 0; + + switch (common_vmm_status()) { + case VMM_CORRUPT: + return BF_ERROR_VMM_CORRUPTED; + case VMM_RUNNING: + return BF_ERROR_VMM_INVALID_STATE; + case VMM_UNLOADED: + goto unloaded; + default: + break; + } + + ret = platform_call_vmm_on_core(0, BF_REQUEST_FINI, 0, 0); + if (ret != BF_SUCCESS) { + goto corrupted; + } + +unloaded: + + common_reset(); + + g_vmm_status = VMM_UNLOADED; + return BF_SUCCESS; + +corrupted: + + g_vmm_status = VMM_CORRUPT; + return ret; +} + +int64_t +common_start_vmm(void) +{ + int64_t ret = 0; + int64_t cpuid = 0; + int64_t ignore_ret = 0; + + switch (common_vmm_status()) { + case VMM_CORRUPT: + return BF_ERROR_VMM_CORRUPTED; + case VMM_RUNNING: + return BF_SUCCESS; + case VMM_UNLOADED: + return BF_ERROR_VMM_INVALID_STATE; + default: + break; + } + + for (cpuid = 0, g_num_cpus_started = 0; cpuid < platform_num_cpus(); cpuid++) { + ret = platform_call_vmm_on_core( + (uint64_t)cpuid, BF_REQUEST_VMM_INIT, (uint64_t)cpuid, 0); + + if (ret != BF_SUCCESS) { + goto failure; + } + + g_num_cpus_started++; + } + + g_vmm_status = VMM_RUNNING; + return BF_SUCCESS; + +failure: + + ignore_ret = common_stop_vmm(); + bfignored(ignore_ret); + + return ret; +} + +int64_t +common_stop_vmm(void) +{ + int64_t ret = 0; + int64_t cpuid = 0; + + switch (common_vmm_status()) { + case VMM_CORRUPT: + return BF_ERROR_VMM_CORRUPTED; + case VMM_UNLOADED: + return BF_ERROR_VMM_INVALID_STATE; + default: + break; + } + + for (cpuid = g_num_cpus_started - 1; cpuid >= 0 ; cpuid--) { + ret = platform_call_vmm_on_core( + (uint64_t)cpuid, BF_REQUEST_VMM_FINI, (uint64_t)cpuid, 0); + + if (ret != BFELF_SUCCESS) { + goto corrupted; + } + + g_num_cpus_started--; + } + + g_vmm_status = VMM_LOADED; + return BF_SUCCESS; + +corrupted: + + g_vmm_status = VMM_CORRUPT; + return ret; +} + +int64_t +common_dump_vmm(struct debug_ring_resources_t **drr, uint64_t vcpuid) +{ + int64_t ret = 0; + + if (drr == 0) { + return BF_ERROR_INVALID_ARG; + } + + if (common_vmm_status() == VMM_UNLOADED) { + return BF_ERROR_VMM_INVALID_STATE; + } + + ret = platform_call_vmm_on_core( + 0, BF_REQUEST_GET_DRR, (uint64_t)vcpuid, (uint64_t)drr); + + if (ret != BFELF_SUCCESS) { + return ret; + } + + return BF_SUCCESS; +} + +typedef struct thread_context_t tc_t; + +int64_t +common_call_vmm( + uint64_t cpuid, uint64_t request, uintptr_t arg1, uintptr_t arg2) +{ + int64_t ignored_ret = 0; + tc_t *tc = (tc_t *)(g_stack_top - sizeof(tc_t)); + + ignored_ret = bfelf_set_integer_args(&g_info, request, arg1, arg2, 0); + bfignored(ignored_ret); + + tc->cpuid = cpuid; + tc->tlsptr = (uint64_t *)((uint64_t)g_tls + (THREAD_LOCAL_STORAGE_SIZE * (uint64_t)cpuid)); + + return _start_func((void *)(g_stack_top - sizeof(tc_t) - 1), &g_info); +} diff --git a/payloads/bareflank/entry.c b/payloads/bareflank/entry.c new file mode 100644 index 00000000000..fc24858d0b3 --- /dev/null +++ b/payloads/bareflank/entry.c @@ -0,0 +1,205 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include // TODO: read file from CBFS? +#include + +#include +#include +#include +#include + +#include +#include +#include + +extern void i386_do_exec(void* addr, int argc, char **argv, int *ret); + +/* -------------------------------------------------------------------------- */ +/* Global */ +/* -------------------------------------------------------------------------- */ + +uint64_t g_vcpuid = 0; + +struct pmodule_t { + const char *data; + uint64_t size; +}; + +uint64_t g_num_pmodules = 0; +struct pmodule_t pmodules[MAX_NUM_MODULES] = {{0}}; + +/* -------------------------------------------------------------------------- */ +/* Misc Device */ +/* -------------------------------------------------------------------------- */ + +static int64_t +ioctl_add_module(const char *file, uint64_t len) +{ + char *buf; + int64_t ret; + + if (g_num_pmodules >= MAX_NUM_MODULES) { + BFALERT("IOCTL_ADD_MODULE: too many modules have been loaded\n"); + return BF_IOCTL_FAILURE; + } + + buf = platform_alloc_rw(len); + if (buf == NULL) { + BFALERT("IOCTL_ADD_MODULE: failed to allocate memory for the module\n"); + return BF_IOCTL_FAILURE; + } + + platform_memcpy(buf, file, len); + + ret = common_add_module(buf, len); + if (ret != BF_SUCCESS) { + BFALERT("IOCTL_ADD_MODULE: common_add_module failed: %p - %s\n", (void *)ret, ec_to_str(ret)); + goto failed; + } + + pmodules[g_num_pmodules].data = buf; + pmodules[g_num_pmodules].size = len; + + g_num_pmodules++; + + return BF_IOCTL_SUCCESS; + +failed: + + platform_free_rw(buf, len); + + BFALERT("IOCTL_ADD_MODULE: failed\n"); + return BF_IOCTL_FAILURE; +} + +static long +ioctl_load_vmm(void) +{ + int64_t ret; + + ret = common_load_vmm(); + if (ret != BF_SUCCESS) { + BFALERT("IOCTL_LOAD_VMM: common_load_vmm failed: %p - %s\n", (void *)ret, ec_to_str(ret)); + goto failure; + } + + return BF_IOCTL_SUCCESS; + +failure: + + BFDEBUG("IOCTL_LOAD_VMM: failed\n"); + return BF_IOCTL_FAILURE; +} + +static long +ioctl_start_vmm(void) +{ + int64_t ret; + + ret = common_start_vmm(); + if (ret != BF_SUCCESS) { + BFALERT("IOCTL_START_VMM: common_start_vmm failed: %p - %s\n", (void *)ret, ec_to_str(ret)); + goto failure; + } + + return BF_IOCTL_SUCCESS; + +failure: + + BFDEBUG("IOCTL_START_VMM: failed\n"); + return BF_IOCTL_FAILURE; +} + +static void cbfs_run_payload(struct cbfs_payload *pay) +{ + struct cbfs_payload_segment *seg = &pay->segments; + for (;;) { + void *src = (void*)pay + ntohl(seg->offset); + void *dest = (void*)ntohll(seg->load_addr); + u32 src_len = ntohl(seg->len); + u32 dest_len = ntohl(seg->mem_len); + switch (seg->type) { + case PAYLOAD_SEGMENT_BSS: + printf("BSS segment %d@%p\n", dest_len, dest); + memset(dest, 0, dest_len); + break; + case PAYLOAD_SEGMENT_ENTRY: { + printf("Calling addr %p\n", dest); + i386_do_exec(dest, 0, NULL, NULL); + return; + } + default: + printf("Segment %x %d@%p -> %d@%p\n", seg->type, src_len, src, + dest_len, dest); + if (seg->compression == ntohl(CBFS_COMPRESS_NONE)) { + if (src_len > dest_len) + src_len = dest_len; + memcpy(dest, src, src_len); + } else if (CONFIG_LP_LZMA + && seg->compression == ntohl(CBFS_COMPRESS_LZMA)) { + int ret = ulzman(src, src_len, dest, dest_len); + if (ret < 0) + return; + src_len = ret; + } else { + printf("No support for compression type %x\n", seg->compression); + return; + } + if (dest_len > src_len) + memset(dest + src_len, 0, dest_len - src_len); + break; + } + seg++; + } +} + +/* -------------------------------------------------------------------------- */ +/* Entry / Exit */ +/* -------------------------------------------------------------------------- */ + +int main(void) +{ + void *payload = NULL; + + printf("\n"); + printf(" ___ __ _ _ \n"); + printf(" | _ ) __ _ _ _ ___ / _| |__ _ _ _ | |__\n"); + printf(" | _ \\/ _` | '_/ -_) _| / _` | ' \\| / /\n"); + printf(" |___/\\__,_|_| \\___|_| |_\\__,_|_||_|_\\_\\\n"); + printf("\n"); + printf(" Please give us a star on: https://github.com/Bareflank/hypervisor\n"); + printf("\n"); + + if (common_init() != BF_SUCCESS) { + return -1; + } + + ioctl_add_module((char *)vmm, vmm_len); + ioctl_load_vmm(); + ioctl_start_vmm(); + + payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/realpayload"); + + cbfs_run_payload(payload); + + printf("Should not get here...\n"); + + return 0; +} diff --git a/payloads/bareflank/include/bfaffinity.h b/payloads/bareflank/include/bfaffinity.h new file mode 100644 index 00000000000..1fb98f38e51 --- /dev/null +++ b/payloads/bareflank/include/bfaffinity.h @@ -0,0 +1,61 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfbuffer.h +/// +/// + +#ifdef WIN64 + +#include + +inline int +set_affinity(uint64_t core) +{ + if (SetProcessAffinityMask(GetCurrentProcess(), 1ULL << core) == 0) { + return -1; + } + + return 0; +} + +#else + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + +#include + +inline int +set_affinity(uint64_t core) +{ + cpu_set_t mask; + + CPU_ZERO(&mask); + CPU_SET(core, &mask); + + if (sched_setaffinity(0, sizeof(mask), &mask) != 0) { + return -1; + } + + return 0; +} + +#endif diff --git a/payloads/bareflank/include/bfarch.h b/payloads/bareflank/include/bfarch.h new file mode 100644 index 00000000000..17c6ea47e3a --- /dev/null +++ b/payloads/bareflank/include/bfarch.h @@ -0,0 +1,49 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2017 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFARCH_H +#define BFARCH_H + +#ifndef BF_ARCH + +#if defined(_MSC_VER) +# if defined(_M_X64) +# define BF_ARCH "intel_x64" +# define BF_X64 +# define BF_INTEL_X64 +# else +# error "bfarch.h: unsupported architecture" +# endif +#elif defined(__GNUC__) || defined(__clang__) +# if defined(__x86_64__) +# define BF_ARCH "intel_x64" +# define BF_X64 +# define BF_INTEL_X64 +# elif defined(__aarch64__) +# define BF_ARCH "aarch64" +# define BF_AARCH64 +# else +# error "bfarch.h: unsupported architecture" +# endif +#else +# error "bfarch.h: unsupported compiler" +#endif + +#endif +#endif diff --git a/payloads/bareflank/include/bfbenchmark.h b/payloads/bareflank/include/bfbenchmark.h new file mode 100644 index 00000000000..6d78980accb --- /dev/null +++ b/payloads/bareflank/include/bfbenchmark.h @@ -0,0 +1,114 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULLAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +#ifndef BFBENCHMARK_H +#define BFBENCHMARK_H + +#if defined(__clang__) || defined(__GNUC__) +#pragma GCC system_header +#endif + +#include +#include + +#include + +template +uint64_t benchmark(T func) +{ + auto s = std::chrono::high_resolution_clock::now(); + func(); + auto e = std::chrono::high_resolution_clock::now(); + + return static_cast((e - s).count()); +} + +size_t g_page_allocs = 0; +size_t g_nonpage_allocs = 0; + +inline void * +custom_new(std::size_t size) +{ + if ((size & 0xFFF) == 0) { + g_page_allocs += size; + } + else { + g_nonpage_allocs += size; + } + + return malloc(size); +} + +inline void +custom_delete(void *ptr, std::size_t size) +{ + bfignored(size); + free(ptr); +} + +void * +operator new[](std::size_t size) +{ return custom_new(size); } + +void * +operator new (std::size_t size) +{ return custom_new(size); } + +void * +operator new (std::size_t count, const std::nothrow_t &) +{ return custom_new(count); } + +void * +operator new[](std::size_t count, const std::nothrow_t &) +{ return custom_new(count); } + +void +operator delete (void *ptr, std::size_t size) throw() +{ custom_delete(ptr, size); } + +void +operator delete (void *ptr) throw() +{ operator delete (ptr, static_cast(0)); } + +void +operator delete[](void *ptr, std::size_t size) throw() +{ custom_delete(ptr, size); } + +void +operator delete[](void *ptr) throw() +{ operator delete[](ptr, static_cast(0)); } + +inline void +print_memory_stats() +{ + auto page_allocs = g_page_allocs; + auto nonpage_allocs = g_nonpage_allocs; + + bfdebug_nhex(0, "bytes allocated", page_allocs + nonpage_allocs); + bfdebug_subnhex(0, "page aligned bytes allocated", page_allocs); + bfdebug_subnhex(0, "non-page aligned bytes allocated", nonpage_allocs); +} + +inline void +clear_memory_stats() +{ + g_page_allocs = 0; + g_nonpage_allocs = 0; +} + +#endif diff --git a/payloads/bareflank/include/bfbitmanip.h b/payloads/bareflank/include/bfbitmanip.h new file mode 100644 index 00000000000..528ddbb9ec3 --- /dev/null +++ b/payloads/bareflank/include/bfbitmanip.h @@ -0,0 +1,274 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULLAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfbitmanip.h +/// + +#ifndef BFBITMANIP_H +#define BFBITMANIP_H + +#include + +#include +#include + +/// Set Bit +/// +/// Sets a bit given the bit position and an integer. +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bit is to be set +/// @param b bit position +/// @return t with bit set at position b +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +set_bit(T t, B b) noexcept +{ + return t | (0x1ULL << b); +} + +/// Set Bit +/// +/// Sets a bit given the bit position and an integer. +/// +/// @expects +/// @ensures +/// +/// @param view view whose bit is to be set +/// @param b bit position +/// @return t with bit set at position b +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +set_bit(gsl::span &view, B b) +{ + auto byte_view = gsl::as_writeable_bytes(view); + byte_view.at(b >> 3) |= gsl::narrow_cast((1 << (b & 7))); +} + +/// Clear Bit +/// +/// Clears a bit given the bit position and an integer. +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bit is to be cleared +/// @param b bit position +/// @return t with bit cleared at position b +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +clear_bit(T t, B b) noexcept +{ + return t & ~(0x1ULL << b); +} + +/// Clear Bit +/// +/// Clears a bit given the bit position and an integer. +/// +/// @expects +/// @ensures +/// +/// @param view view whose bit is to be cleared +/// @param b bit position +/// @return t with bit cleared at position b +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +clear_bit(gsl::span &view, B b) +{ + auto byte_view = gsl::as_writeable_bytes(view); + byte_view.at(b >> 3) &= gsl::narrow_cast(~(1 << (b & 7))); +} + +/// Get Bit +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bit is to be gotten +/// @param b bit position +/// @return value of bit b for integer t +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +get_bit(T t, B b) noexcept +{ + return (t & (0x1ULL << b)) >> b; +} + +/// Get Bit +/// +/// @expects +/// @ensures +/// +/// @param view view whose bit is to be gotten +/// @param b bit position +/// @return value of bit b for integer t +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +get_bit(const gsl::span &view, B b) +{ + auto byte_view = gsl::as_writeable_bytes(view); + return byte_view.at(b >> 3) & gsl::narrow_cast((1 << (b & 7))); +} + +/// Is Bit Set +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bit is to be tested +/// @param b bit position +/// @return true if bit b in t is set, false otherwise +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +is_bit_set(T t, B b) noexcept +{ + return static_cast(get_bit(t, b)) != static_cast(0); +} + +/// Is Bit Cleared +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bit is to be tested +/// @param b bit position +/// @return true if bit b in t is cleared, false otherwise +/// +template < + typename T, + typename B, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +is_bit_cleared(T t, B b) noexcept +{ + return static_cast(get_bit(t, b)) == static_cast(0); +} + +/// Number of Bits Set +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bit is to be tested +/// @return the number of bits set in t +/// +template < + typename T, + typename = std::enable_if::value> + > +auto +num_bits_set(T t) noexcept +{ + std::bitset<64> b{t}; + return b.count(); +} + +/// Get Bits +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bits are to be gotten +/// @param m the bit mask +/// @return t & m +/// +template < + typename T, + typename M, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +get_bits(T t, M m) noexcept +{ + return t & m; +} + +/// Set Bits +/// +/// @expects +/// @ensures +/// +/// @param t integer whose bits are to be set +/// @param m the bit mask +/// @param v the bits to set +/// @return t with bits set to v masked by m +/// +template < + typename T, + typename M, + typename V, + typename = std::enable_if::value>, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +constexpr auto +set_bits(T t, M m, V v) noexcept +{ + return (t & ~m) | (v & m); +} + +#endif diff --git a/payloads/bareflank/include/bfbuffer.h b/payloads/bareflank/include/bfbuffer.h new file mode 100644 index 00000000000..7ca1c0a5944 --- /dev/null +++ b/payloads/bareflank/include/bfbuffer.h @@ -0,0 +1,309 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfbuffer.h +/// + +#ifndef BFBUFFER_H +#define BFBUFFER_H + +#include +#include + +namespace bfn +{ + +/// Buffer +/// +/// Simple character buffer class that stores both a buffer and its size. +/// This class is a hybrid between std::array, and std::unique_ptr. It's +/// dynamic, doesn't have support for iterators or random memory access, +/// and cannot be copied. +/// +class buffer +{ +public: + + using size_type = std::size_t; ///< Size type of buffer + using data_type = char; ///< Data type of buffer + + /// Default Constructor + /// + /// @expects none + /// @ensures none + /// + buffer() = default; + + /// Allocate Buffer Constructor + /// + /// @expects none + /// @ensures none + /// + /// @param size the size of the buffer to allocate + /// + /// @throws std::bad_alloc if this constructor is unable to allocate memory for the buffer + /// + buffer(size_type size) : + m_size(size), + m_data(std::make_unique(m_size)) + { + expects(size != 0); + } + + /// Pre-Allocated Buffer Constructor + /// + /// @note Takes ownership of data, and frees the provided buffer when the + /// buffer goes out of scope + /// + /// @expects none + /// @ensures none + /// + /// @param data a pointer to the buffer to store. + /// @param size the size of the provided buffer + /// + buffer(void *data, size_type size) : + m_size(size), + m_data(static_cast(data)) + { + expects(size != 0 || data == nullptr); + expects(data != nullptr || size == 0); + } + + /// Initializer List Constructor + /// + /// @expects none + /// @ensures none + /// + /// @param list initial list to create the buffer + /// + /// @throws std::bad_alloc if this constructor is unable to allocate memory for the buffer + /// + buffer(std::initializer_list list) : + m_size(list.size()), + m_data(std::make_unique(list.size())) + { + auto _i = 0LL; + auto _span = span(); + + for (const auto &elem : list) { + _span[_i++] = elem; + } + } + + /// Default Destructor + /// + /// @expects none + /// @ensures none + /// + ~buffer() = default; + + /// Get Data + /// + /// @expects none + /// @ensures none + /// + /// @return returns a pointer to the buffer + /// + data_type *get() noexcept + { return m_data.get(); } + + /// Get Data + /// + /// @expects none + /// @ensures none + /// + /// @return returns a pointer to the buffer + /// + data_type *data() noexcept + { return m_data.get(); } + + /// Get Data + /// + /// @expects none + /// @ensures none + /// + /// @return returns a pointer to the buffer + /// + const data_type *data() const noexcept + { return m_data.get(); } + + /// Is Empty + /// + /// @expects none + /// @ensures none + /// + /// @return returns true if size() == 0, false otherwise + /// + bool empty() const noexcept + { return m_size == 0; } + + /// Valid + /// + /// @return returns true if the buffer is valid, false otherwise + /// + operator bool() const noexcept + { return m_data.operator bool(); } + + /// Size + /// + /// @expects none + /// @ensures none + /// + /// @return returns the size of the buffer + /// + size_type size() const noexcept + { return m_size; } + + /// Release + /// + /// @expects none + /// @ensures none + /// + void + release() noexcept + { + m_size = 0; + m_data.release(); + } + + /// Swap + /// + /// @expects none + /// @ensures none + /// + /// @param other the other buffer to swap with + /// + void + swap(buffer &other) noexcept + { + std::swap(m_size, other.m_size); + std::swap(m_data, other.m_data); + } + + /// Span + /// + /// @expects none + /// @ensures none + /// + /// @return returns a gsl::span that can be used to access the buffer. + /// + gsl::span + span() const + { return gsl::make_span(m_data.get(), gsl::narrow_cast(m_size)); } + + /// Resize + /// + /// Resize the buffer. If count is smaller than the original size, the + /// data is truncated. If count is larger than the original size, the + /// remaining data is undefined. + /// + /// @expects none + /// @ensures none + /// + /// @param count the number of bytes to resize the buffer to + /// + /// @throws std::bad_alloc if this method is unable to allocate memory for the buffer + /// + void + resize(size_type count) + { + auto new_data = std::make_unique(count); + memcpy(new_data.get(), m_data.get(), std::min(m_size, count)); + + m_size = count; + m_data = std::move(new_data); + } + +private: + + size_type m_size{0}; + std::unique_ptr m_data; + +public: + + /// @cond + + buffer(buffer &&) noexcept = default; + buffer &operator=(buffer &&) noexcept = default; + + buffer(const buffer &) = delete; + buffer &operator=(const buffer &) = delete; + + /// @endcond +}; + +/// Swap +/// +/// @expects none +/// @ensures none +/// +/// @param lhs buffer to swap +/// @param rhs buffer to swap +/// +inline void +swap(buffer &lhs, buffer &rhs) noexcept +{ lhs.swap(rhs); } + +/// Equals +/// +/// @expects none +/// @ensures none +/// +/// @param lhs buffer to compare +/// @param rhs buffer to compare +/// @return true if ==, false otherwise +/// +inline bool +operator==(const buffer &lhs, const buffer &rhs) noexcept +{ + if (lhs.size() != rhs.size()) { + return false; + } + + return memcmp(lhs.data(), rhs.data(), lhs.size()) == 0; +} + +/// Not Equals +/// +/// @expects none +/// @ensures none +/// +/// @param lhs buffer to compare +/// @param rhs buffer to compare +/// @return true if !=, false otherwise +/// +inline bool +operator!=(const buffer &lhs, const buffer &rhs) noexcept +{ return !(lhs == rhs); } + +/// Default Out Stream Operator +/// +/// @expects none +/// @ensures none +/// +/// @param os the out stream object +/// @return os +/// +inline std::ostream & +operator<<(std::ostream &os, const buffer &) +{ return os; } + +} + +#endif diff --git a/payloads/bareflank/include/bfcallonce.h b/payloads/bareflank/include/bfcallonce.h new file mode 100644 index 00000000000..05a7776bb39 --- /dev/null +++ b/payloads/bareflank/include/bfcallonce.h @@ -0,0 +1,56 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULLAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +#ifndef BFCALLONCE +#define BFCALLONCE + +/// @cond + +#include + +// TODO +// +// This code is only needed because there seems to be a bug with GCC that +// causes a system error when --coverage is enabled. The following was written +// to have the same names and implementation as std::call_once so that at +// some point this code can easily be removed. +// +namespace bfn +{ + +struct once_flag { + bool m_value{false}; + mutable std::mutex m_mutex{}; +}; + +template +void call_once(once_flag &flag, FUNC func) +{ + std::lock_guard lock(flag.m_mutex); + + if (!flag.m_value) { + func(); + flag.m_value = true; + } +} + +} + +/// @endcond + +#endif diff --git a/payloads/bareflank/include/bfconstants.h b/payloads/bareflank/include/bfconstants.h new file mode 100755 index 00000000000..f3334e21176 --- /dev/null +++ b/payloads/bareflank/include/bfconstants.h @@ -0,0 +1,277 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFCONSTANTS_H +#define BFCONSTANTS_H + +#include +#include + +/* + * Max Physical Address + * + * Defines the maximum physical address the system can access. This can be + * used by CR3 and EPT to define the memory map used by the VMM. Note that + * if this value is too large, its possible additional memory would be needed + * by the VMM to setup CR3 or EPT depending on the granulairty used. + * + * Note: defined in bytes + */ +#ifndef MAX_PHYS_ADDR +#define MAX_PHYS_ADDR 0x1000000000 +#endif + +/* + * Bareflank Page Size + * + * Defines the page size that is supported by the VMM. For now, this is + * set to a value that is likely supported by most hardware. + * + * Note: defined in bytes + */ +#ifndef BAREFLANK_PAGE_SIZE +#define BAREFLANK_PAGE_SIZE (0x1000ULL) +#endif + +/* + * Page Pool K + * + * Defines the size of the initial page pool used by the VMM. If more memory + * is needed by the VMM initially, this value may be increased. Note that + * increasing "K" by 1 will double the amount of memory. + */ +#ifndef PAGE_POOL_K +#define PAGE_POOL_K (15ULL) +#endif + +/* +* Huge Pool K +* +* Defines the size of the initial huge pool used by the VMM. If more memory +* is needed by the VMM initially, this value may be increased. Note that +* increasing "K" by 1 will double the amount of memory. +*/ + +#ifndef HUGE_POOL_K +#define HUGE_POOL_K (15ULL) +#endif +/* +* Memory Map Pool K +* +* Defines the size of the initial mem map pool used by the VMM. If more memory +* is needed by the VMM for mapping, this value may be increased. Note that +* increasing "K" by 1 will double the amount of memory. +*/ +#ifndef MEM_MAP_POOL_K +#define MEM_MAP_POOL_K (15ULL) +#endif + +/* + * Memory Map Pool Start + * + * This defines the starting location of the virtual memory that is used + * for memory mapping. Note that on some systems, this might need to be + * changed to prevent collisions. + * + * Note: defined in bytes (defaults to 2MB) + */ +#ifndef MEM_MAP_POOL_START +#define MEM_MAP_POOL_START 0x200000ULL +#endif + +/* + * Max Supported Modules + * + * The maximum number of modules supported by the VMM. If you VMM has a large + * number of dynamic libraries to load, this value might need to be increased + */ +#ifndef MAX_NUM_MODULES +#define MAX_NUM_MODULES (75LL) +#endif + +/* + * Debug Ring Size + * + * Defines the size of the debug ring. Note that the memory manager is used to + * allocate memory for the debug ring, so if you need more than one ring, + * which is supported, make sure the memory manager has enough memory in + * the huge pool to support your needs. + * + * Note: Must be defined using a bit shift as this prevents the debug ring from + * allocating memory that generates fragmentation in the memory manager + * + * Note: defined in bytes + */ +#define DEBUG_RING_SIZE (1 << 15ULL) + +/* + * Stack Size + * + * Each entry function is guarded with a custom stack to prevent stack + * overflows from corrupting the kernel, as well as providing a larger stack + * that's common in userspace code, but not in the kernel. If stack corruption + * is occuring, this function likely needs to be increased. Note one stack + * frame is allocated per CPU, so only increase this if needed. + * + * Note: Must be defined using a bit shift as we will mask to get the + * bottom of the stack if needed. + * + * Note: This is hard coded in the thread_context.asm as there is no way to + * use this include in NASM. If you change this, you must change the + * value in that file as well. + * + * Note: defined in bytes + */ +#ifndef STACK_SIZE +#define STACK_SIZE (1ULL << 15ULL) +#endif + +/* + * Thread Local Storage (TLS) Size + * + * Bareflank don't support threads, but it does support Multi-Core, and + * we need a way to store CPU specific information. Certain libc++ + * operations (for example, std::uncaught_exceptions) need to use this CPU + * specific storage so that the cores are not interfering with each other. + * So as far as the code is concerned, TLS is being used, even if a "thread" + * in the traditional sense isn't. + * + * Note: Defined in bytes + */ +#ifndef THREAD_LOCAL_STORAGE_SIZE +#define THREAD_LOCAL_STORAGE_SIZE (0x1000ULL) +#endif + +/* + * Default Serial COM Port + * + * On x64, possible values include (but not limited to): + * - 0x03F8U // COM1 + * - 0x02F8U // COM2 + * - 0x03E8U // COM3 + * - 0x02E8U // COM4 + * - 0xE000U + * - 0xE010U + * + * On aarch64, the value is the serial peripheral's physical base address. + * + * Note: See bfvmm/serial/serial_ns16550a.h + */ +#ifndef DEFAULT_COM_PORT +#if defined(BF_AARCH64) +# define DEFAULT_COM_PORT 0x09000000 +#else +# define DEFAULT_COM_PORT 0x03F8U +# define DEFAULT_COM_DRIVER serial_ns16550a +#endif +#endif + +/* + * Serial Port Driver + * + * Possible values include: + * - serial_ns16550a + * - serial_pl011 + * + * On x64, this should always be serial_ns16550a. + */ +#ifndef DEFAULT_COM_DRIVER +#if defined(BF_AARCH64) +# define DEFAULT_COM_DRIVER serial_pl011 +#else +# define DEFAULT_COM_DRIVER serial_ns16550a +#endif +#endif + +/* + * Serial port memory length (aarch64 only) + * + * This is the length of the memory region occupied by the memory-mapped + * serial port. + */ +#if !defined(DEFAULT_COM_LENGTH) && defined(BF_AARCH64) +#define DEFAULT_COM_LENGTH 0x1000 +#endif + +/* + * Default Serial Baud Rate + * + * Note: See bfvmm/serial/serial_ns16550a.h + */ +#ifndef DEFAULT_BAUD_RATE +#define DEFAULT_BAUD_RATE baud_rate_115200 +#endif + +/* + * Default serial baud rate divisor, integer part (for PL011) + * + * Note: See bfvmm/serial/serial_pl011.h + */ +#ifndef DEFAULT_BAUD_RATE_INT +#define DEFAULT_BAUD_RATE_INT 0x4 +#endif + +/* + * Default serial baud rate divisor, fractional part (for PL011) + * + * Note: See bfvmm/serial/serial_pl011.h + */ +#ifndef DEFAULT_BAUD_RATE_FRAC +#define DEFAULT_BAUD_RATE_FRAC 0x0 +#endif + +/* + * Default Serial Data Bits + * + * Note: See bfvmm/serial/serial_ns16550a.h + */ +#ifndef DEFAULT_DATA_BITS +#define DEFAULT_DATA_BITS char_length_8 +#endif + +/* + * Default Serial Stop Bits + * + * Note: See bfvmm/serial/serial_ns16550a.h + */ +#ifndef DEFAULT_STOP_BITS +#define DEFAULT_STOP_BITS stop_bits_1 +#endif + +/* + * Default Serial Parity Bits + * + * Note: See bfvmm/serial/serial_ns16550a.h + */ +#ifndef DEFAULT_PARITY_BITS +#define DEFAULT_PARITY_BITS parity_none +#endif + +/* + * Debug Level + * + * Defines how noisy Bareflank is. This defaults to 0 which only prints status + * information. Raise this level to include additional verbosity. Note that + * as you increase this level, performance will degrade. + */ +#ifndef DEBUG_LEVEL +#define DEBUG_LEVEL 0 +#endif + +#endif diff --git a/payloads/bareflank/include/bfdebug.h b/payloads/bareflank/include/bfdebug.h new file mode 100644 index 00000000000..03cf53b2214 --- /dev/null +++ b/payloads/bareflank/include/bfdebug.h @@ -0,0 +1,1137 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFDEBUG_H +#define BFDEBUG_H + +#include + +/** @cond */ + +/* -------------------------------------------------------------------------- */ +/* C++ Debugging */ +/* -------------------------------------------------------------------------- */ + +#ifdef __cplusplus + +#include +#include + +#include + +#ifdef _MSC_VER +#define bfcolor_black "" +#define bfcolor_red "" +#define bfcolor_green "" +#define bfcolor_yellow "" +#define bfcolor_blue "" +#define bfcolor_magenta "" +#define bfcolor_cyan "" +#define bfcolor_end "" +#else +#define bfcolor_black "\033[1;30m" +#define bfcolor_red "\033[1;31m" +#define bfcolor_green "\033[1;32m" +#define bfcolor_yellow "\033[1;33m" +#define bfcolor_blue "\033[1;34m" +#define bfcolor_magenta "\033[1;35m" +#define bfcolor_cyan "\033[1;36m" +#define bfcolor_end "\033[0m" +#endif + +#define bfcolor_debug bfcolor_green +#define bfcolor_alert bfcolor_yellow +#define bfcolor_error bfcolor_red + +using cstr_t = const char *; + +#ifdef UNIX +#define __BFFUNC__ static_cast(__PRETTY_FUNCTION__) +#else +#define __BFFUNC__ static_cast(__FUNCTION__) +#endif + +#ifdef VMM +extern "C" uint64_t thread_context_cpuid(void); +extern "C" uint64_t write_str(const std::string &str); +#else +#include +#endif + +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable : 4312) +#endif + +template < + typename T, + typename = std::enable_if_t < + std::is_pointer::value || + std::is_integral::value + > + > +const void * +view_as_pointer(const T val) +{ return reinterpret_cast(val); } + +#ifdef _MSC_VER +#pragma warning(pop) +#endif + +extern "C" uint64_t +unsafe_write_cstr(const char *cstr, size_t len); + +/* ---------------------------------------------------------------------------*/ +/* Low Level Debugging */ +/* ---------------------------------------------------------------------------*/ + +inline char * +bfitoa(size_t value, char *str, size_t base) +{ + const char digits[] = "0123456789abcdefghijklmnopqrstuvwxyz"; + int i = 0, j = 0; + size_t remainder; + + do { + remainder = value % base; + str[i++] = digits[remainder]; + value = value / base; + } + while (value != 0); + + str[i] = '\0'; + + for (j = 0, i--; j < i; j++, i--) { + char c = str[j]; + str[j] = str[i]; + str[i] = c; + } + + return str; +} + +#define CALLED() \ + { \ + const auto *str_text = "\033[1;32mDEBUG\033[0m: function called = "; \ + const auto *str_func = __BFFUNC__; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(str_func, strlen(str_func)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +#define WARNING(a) \ + { \ + const auto *str_text = "\033[1;33mWARNING\033[0m: " a " = "; \ + const auto *str_func = __BFFUNC__; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(str_func, strlen(str_func)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +#define UNHANDLED() \ + { \ + const auto *str_text = "\033[1;33mWARNING\033[0m: unsupported function called = "; \ + const auto *str_func = __BFFUNC__; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(str_func, strlen(str_func)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +#define ARG_UNSUPPORTED(a) \ + { \ + const auto *str_text = "\033[1;33mWARNING\033[0m: " a " not supported for function called = "; \ + const auto *str_func = __BFFUNC__; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(str_func, strlen(str_func)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + + +#define DEBUG_STR(a,b) \ + { \ + const auto *str_text = "\033[1;32mDEBUG\033[0m: " a " = "; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(b, strlen(b)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +#define DEBUG_DEC(a,b) \ + { \ + char numstr[64]; \ + bfitoa(b, numstr, 10); \ + const auto *str_text = "\033[1;32mDEBUG\033[0m: " a " = "; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(numstr, strlen(numstr)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +#define DEBUG_HEX(a,b) \ + { \ + char numstr[64]; \ + bfitoa(b, numstr, 16); \ + const auto *str_text = "\033[1;32mDEBUG\033[0m: " a " = "; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(numstr, strlen(numstr)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +#define DEBUG_LINE() \ + { \ + char numstr[64]; \ + bfitoa(__LINE__, numstr, 10); \ + const auto *str_text = "\033[1;32mDEBUG\033[0m: "; \ + const auto *str_func = __BFFUNC__; \ + const auto *str_next = " = "; \ + const auto *str_endl = "\n"; \ + unsafe_write_cstr(str_text, strlen(str_text)); \ + unsafe_write_cstr(str_func, strlen(str_func)); \ + unsafe_write_cstr(str_next, strlen(str_next)); \ + unsafe_write_cstr(numstr, strlen(numstr)); \ + unsafe_write_cstr(str_endl, strlen(str_endl)); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Helpers (Private) */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_core(gsl::not_null msg) +{ + *msg += bfcolor_cyan; + *msg += "["; + *msg += bfcolor_yellow; +#ifdef VMM + *msg += std::to_string(thread_context_cpuid()); +#else + *msg += '0'; +#endif + *msg += bfcolor_cyan; + *msg += "] "; + *msg += bfcolor_end; +} + +inline void +__bfdebug_type(gsl::not_null msg, cstr_t color, cstr_t type) +{ + *msg += color; + *msg += type; + *msg += bfcolor_end; + *msg += ": "; +} + +inline void +__bfdebug_jtfy(gsl::not_null msg, uint64_t width, cstr_t title, cstr_t indent) +{ + if (title != nullptr) { + auto len = width - strlen(title); + + if (indent != nullptr) { + len -= strlen(indent); + *msg += indent; + } + + *msg += title; + *msg += std::string(len, ' '); + } + else { + *msg += std::string(width, ' '); + } +} + +template +void __bfdebug_transaction(F func) +{ + std::string msg; + msg.reserve(0x1000); + func(&msg); + +#ifdef VMM + write_str(msg); +#else + std::cout << msg; +#endif +} + +template +void __bfdebug_add_line(std::string *msg, F func) +{ + if (msg == nullptr) { + __bfdebug_transaction([&](std::string * tmsg) { + func(tmsg); + }); + } + else { + std::string ln; + ln.reserve(0x1000); + + func(&ln); + + if (msg->size() + ln.size() > msg->capacity()) { + msg->reserve(msg->capacity() + 0x1000); + } + + *msg += ln; + } +} + +#define bfdebug_transaction(level,func) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_transaction(func); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Get Macro Magic */ +/* ---------------------------------------------------------------------------*/ + +/* + * This is a cleaned up version of the following: + * https://stackoverflow.com/questions/11761703/overloading-macro-on-number-of-arguments + * + * This is needed because some of the debug macros only take a single argument, + * which means __VA_ARGS__ gets mad because it's not used. For macros with more + * than one arg, this is not needed. Also, if this becomes needed for other + * things in the future, we should move this to it's own header + * + * The bug fix for MSVC comes from the following: + * https://stackoverflow.com/questions/5134523/msvc-doesnt-expand-va-args-correctly + */ + +#define __BUGFX(x) x + +#define __NARG2(...) __BUGFX(__NARG1(__VA_ARGS__,__RSEQN())) +#define __NARG1(...) __BUGFX(__ARGSN(__VA_ARGS__)) +#define __ARGSN(_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,N,...) N +#define __RSEQN() 10,9,8,7,6,5,4,3,2,1,0 + +#define __FUNC2(name,n) name ## n +#define __FUNC1(name,n) __FUNC2(name,n) +#define GET_MACRO(func,...) __FUNC1(func,__BUGFX(__NARG2(__VA_ARGS__))) (__VA_ARGS__) + +/* ---------------------------------------------------------------------------*/ +/* Info */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_info_core(cstr_t color, cstr_t type, cstr_t title, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + + if (title != nullptr) { + *msg += std::string(title); + } + + *msg += '\n'; +} + +inline void +__bfdebug_info(cstr_t color, cstr_t type, cstr_t title, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_info_core(color, type, title, ln); + }); +} + +#define bfdebug_info(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_info(bfcolor_debug, "DEBUG", __VA_ARGS__); \ + } + +#define bfalert_info(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_info(bfcolor_alert, "ALERT", __VA_ARGS__); \ + } + +#define bferror_info(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_info(bfcolor_error, "ERROR", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Line Break */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_lnbr_core(cstr_t color, cstr_t type, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + + *msg += '\n'; +} + +inline void +__bfdebug_lnbr(cstr_t color, cstr_t type, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_lnbr_core(color, type, ln); + }); +} + +#define bfdebug_lnbr1(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_lnbr(bfcolor_debug, "DEBUG"); \ + } + +#define bfalert_lnbr1(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_lnbr(bfcolor_alert, "ALERT"); \ + } + +#define bferror_lnbr1(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_lnbr(bfcolor_error, "ERROR"); \ + } + +#define bfdebug_lnbr2(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_lnbr(bfcolor_debug, "DEBUG", msg); \ + } + +#define bfalert_lnbr2(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_lnbr(bfcolor_alert, "ALERT", msg); \ + } + +#define bferror_lnbr2(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_lnbr(bfcolor_error, "ERROR", msg); \ + } + +#define bfdebug_lnbr(...) GET_MACRO(bfdebug_lnbr, __VA_ARGS__) +#define bfalert_lnbr(...) GET_MACRO(bfalert_lnbr, __VA_ARGS__) +#define bferror_lnbr(...) GET_MACRO(bferror_lnbr, __VA_ARGS__) + +/* ---------------------------------------------------------------------------*/ +/* Horizontal Line Break1 */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_brk1_core(cstr_t color, cstr_t type, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + + *msg += "======================================================================"; + *msg += '\n'; +} + +inline void +__bfdebug_brk1(cstr_t color, cstr_t type, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_brk1_core(color, type, ln); + }); +} + +#define bfdebug_brk11(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk1(bfcolor_debug, "DEBUG"); \ + } + +#define bfalert_brk11(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk1(bfcolor_alert, "ALERT"); \ + } + +#define bferror_brk11(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk1(bfcolor_error, "ERROR"); \ + } + +#define bfdebug_brk12(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk1(bfcolor_debug, "DEBUG", msg); \ + } + +#define bfalert_brk12(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk1(bfcolor_alert, "ALERT", msg); \ + } + +#define bferror_brk12(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk1(bfcolor_error, "ERROR", msg); \ + } + +#define bfdebug_brk1(...) GET_MACRO(bfdebug_brk1, __VA_ARGS__) +#define bfalert_brk1(...) GET_MACRO(bfalert_brk1, __VA_ARGS__) +#define bferror_brk1(...) GET_MACRO(bferror_brk1, __VA_ARGS__) + +/* ---------------------------------------------------------------------------*/ +/* Horizontal Line Break2 */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_brk2_core(cstr_t color, cstr_t type, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + + *msg += "----------------------------------------------------------------------"; + *msg += '\n'; +} + +inline void +__bfdebug_brk2(cstr_t color, cstr_t type, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_brk2_core(color, type, ln); + }); +} + +#define bfdebug_brk21(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk2(bfcolor_debug, "DEBUG"); \ + } + +#define bfalert_brk21(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk2(bfcolor_alert, "ALERT"); \ + } + +#define bferror_brk21(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk2(bfcolor_error, "ERROR"); \ + } + +#define bfdebug_brk22(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk2(bfcolor_debug, "DEBUG", msg); \ + } + +#define bfalert_brk22(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk2(bfcolor_alert, "ALERT", msg); \ + } + +#define bferror_brk22(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk2(bfcolor_error, "ERROR", msg); \ + } + +#define bfdebug_brk2(...) GET_MACRO(bfdebug_brk2, __VA_ARGS__) +#define bfalert_brk2(...) GET_MACRO(bfalert_brk2, __VA_ARGS__) +#define bferror_brk2(...) GET_MACRO(bferror_brk2, __VA_ARGS__) + +/* ---------------------------------------------------------------------------*/ +/* Horizontal Line Break3 */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_brk3_core(cstr_t color, cstr_t type, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + + *msg += "......................................................................"; + *msg += '\n'; +} + +inline void +__bfdebug_brk3(cstr_t color, cstr_t type, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_brk3_core(color, type, ln); + }); +} + +#define bfdebug_brk31(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk3(bfcolor_debug, "DEBUG"); \ + } + +#define bfalert_brk31(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk3(bfcolor_alert, "ALERT"); \ + } + +#define bferror_brk31(level) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk3(bfcolor_error, "ERROR"); \ + } + +#define bfdebug_brk32(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk3(bfcolor_debug, "DEBUG", msg); \ + } + +#define bfalert_brk32(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk3(bfcolor_alert, "ALERT", msg); \ + } + +#define bferror_brk32(level,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_brk3(bfcolor_error, "ERROR", msg); \ + } + +#define bfdebug_brk3(...) GET_MACRO(bfdebug_brk3, __VA_ARGS__) +#define bfalert_brk3(...) GET_MACRO(bfalert_brk3, __VA_ARGS__) +#define bferror_brk3(...) GET_MACRO(bferror_brk3, __VA_ARGS__) + +/* ---------------------------------------------------------------------------*/ +/* Hex Number */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_nhex_core( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, uint64_t nhex, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + __bfdebug_jtfy(msg, 52, title, indent); + + *msg += bfn::to_string(nhex, 16); + *msg += '\n'; +} + +inline void +__bfdebug_nhex( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, uint64_t nhex, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_nhex_core(color, type, indent, title, nhex, ln); + }); +} + +inline void +__bfdebug_nhex( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, void *nhex, std::string *msg = nullptr) +{ __bfdebug_nhex(color, type, indent, title, reinterpret_cast(nhex), msg); } + +#define bfdebug_nhex(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_nhex(bfcolor_debug, "DEBUG", nullptr, __VA_ARGS__); \ + } + +#define bfalert_nhex(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_nhex(bfcolor_alert, "ALERT", nullptr, __VA_ARGS__); \ + } + +#define bferror_nhex(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_nhex(bfcolor_error, "ERROR", nullptr, __VA_ARGS__); \ + } + +#define bfdebug_subnhex(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_nhex(bfcolor_debug, "DEBUG", " - ", __VA_ARGS__); \ + } + +#define bfalert_subnhex(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_nhex(bfcolor_alert, "ALERT", " - ", __VA_ARGS__); \ + } + +#define bferror_subnhex(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_nhex(bfcolor_error, "ERROR", " - ", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Decimal Number */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_ndec_core( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, uint64_t ndec, gsl::not_null msg) +{ + auto str = bfn::to_string(ndec, 10); + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + __bfdebug_jtfy(msg, 70 - str.length(), title, indent); + + *msg += str; + *msg += '\n'; +} + +inline void +__bfdebug_ndec( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, uint64_t ndec, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_ndec_core(color, type, indent, title, ndec, ln); + }); +} + +#define bfdebug_ndec(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_ndec(bfcolor_debug, "DEBUG", nullptr, __VA_ARGS__); \ + } + +#define bfalert_ndec(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_ndec(bfcolor_alert, "ALERT", nullptr, __VA_ARGS__); \ + } + +#define bferror_ndec(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_ndec(bfcolor_error, "ERROR", nullptr, __VA_ARGS__); \ + } + +#define bfdebug_subndec(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_ndec(bfcolor_debug, "DEBUG", " - ", __VA_ARGS__); \ + } + +#define bfalert_subndec(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_ndec(bfcolor_alert, "ALERT", " - ", __VA_ARGS__); \ + } + +#define bferror_subndec(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_ndec(bfcolor_error, "ERROR", " - ", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Boolean */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_bool_core( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, bool val, gsl::not_null msg) +{ + auto str = val ? "true" : "false"; + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + __bfdebug_jtfy(msg, 70 - strlen(str), title, indent); + + *msg += str; + *msg += '\n'; +} + +inline void +__bfdebug_bool( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, bool val, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_bool_core(color, type, indent, title, val, ln); + }); +} + +#define bfdebug_bool(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_bool(bfcolor_debug, "DEBUG", nullptr, __VA_ARGS__); \ + } + +#define bfalert_bool(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_bool(bfcolor_alert, "ALERT", nullptr, __VA_ARGS__); \ + } + +#define bferror_bool(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_bool(bfcolor_error, "ERROR", nullptr, __VA_ARGS__); \ + } + +#define bfdebug_subbool(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_bool(bfcolor_debug, "DEBUG", " - ", __VA_ARGS__); \ + } + +#define bfalert_subbool(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_bool(bfcolor_alert, "ALERT", " - ", __VA_ARGS__); \ + } + +#define bferror_subbool(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_bool(bfcolor_error, "ERROR", " - ", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Text */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_text_core( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, cstr_t text, gsl::not_null msg) +{ + auto str = text == nullptr ? std::string{} : std::string{text}; + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + __bfdebug_jtfy(msg, 70 - str.length(), title, indent); + + *msg += str; + *msg += '\n'; +} + +inline void +__bfdebug_text( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, cstr_t text, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_text_core(color, type, indent, title, text, ln); + }); +} + +#define bfdebug_text(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_text(bfcolor_debug, "DEBUG", nullptr, __VA_ARGS__); \ + } + +#define bfalert_text(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_text(bfcolor_alert, "ALERT", nullptr, __VA_ARGS__); \ + } + +#define bferror_text(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_text(bfcolor_error, "ERROR", nullptr, __VA_ARGS__); \ + } + +#define bfdebug_subtext(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_text(bfcolor_debug, "DEBUG", " - ", __VA_ARGS__); \ + } + +#define bfalert_subtext(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_text(bfcolor_alert, "ALERT", " - ", __VA_ARGS__); \ + } + +#define bferror_subtext(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_text(bfcolor_error, "ERROR", " - ", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Pass */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_pass_core( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + __bfdebug_jtfy(msg, 66, title, indent); + + *msg += bfcolor_green "pass" bfcolor_end; + *msg += '\n'; +} + +inline void +__bfdebug_pass( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_pass_core(color, type, indent, title, ln); + }); +} + +#define bfdebug_pass(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_pass(bfcolor_debug, "DEBUG", nullptr, __VA_ARGS__); \ + } + +#define bfalert_pass(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_pass(bfcolor_alert, "ALERT", nullptr, __VA_ARGS__); \ + } + +#define bferror_pass(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_pass(bfcolor_error, "ERROR", nullptr, __VA_ARGS__); \ + } + +#define bfdebug_subpass(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_pass(bfcolor_debug, "DEBUG", " - ", __VA_ARGS__); \ + } + +#define bfalert_subpass(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_pass(bfcolor_alert, "ALERT", " - ", __VA_ARGS__); \ + } + +#define bferror_subpass(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_pass(bfcolor_error, "ERROR", " - ", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Fail */ +/* ---------------------------------------------------------------------------*/ + +inline void +__bfdebug_fail_core( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, gsl::not_null msg) +{ + __bfdebug_core(msg); + __bfdebug_type(msg, color, type); + __bfdebug_jtfy(msg, 66, title, indent); + + *msg += bfcolor_red "fail <----" bfcolor_end; + *msg += '\n'; +} + +inline void +__bfdebug_fail( + cstr_t color, cstr_t type, cstr_t indent, cstr_t title, std::string *msg = nullptr) +{ + __bfdebug_add_line(msg, [&](std::string * ln) { + __bfdebug_fail_core(color, type, indent, title, ln); + }); +} + +#define bfdebug_fail(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_fail(bfcolor_debug, "DEBUG", nullptr, __VA_ARGS__); \ + } + +#define bfalert_fail(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_fail(bfcolor_alert, "ALERT", nullptr, __VA_ARGS__); \ + } + +#define bferror_fail(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_fail(bfcolor_error, "ERROR", nullptr, __VA_ARGS__); \ + } + +#define bfdebug_subfail(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_fail(bfcolor_debug, "DEBUG", " - ", __VA_ARGS__); \ + } + +#define bfalert_subfail(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_fail(bfcolor_alert, "ALERT", " - ", __VA_ARGS__); \ + } + +#define bferror_subfail(level, ...) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + __bfdebug_fail(bfcolor_error, "ERROR", " - ", __VA_ARGS__); \ + } + +/* ---------------------------------------------------------------------------*/ +/* Test */ +/* ---------------------------------------------------------------------------*/ + +#define bfdebug_test3(level,title,val) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfdebug_pass(level,title); \ + } \ + else { \ + bfdebug_fail(level,title); \ + } \ + } + +#define bfdebug_subtest3(level,title,val) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfdebug_subpass(level,title); \ + } \ + else { \ + bfdebug_subfail(level,title); \ + } \ + } + +#define bfalert_test3(level,title,val) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfalert_pass(level,title); \ + } \ + else { \ + bfalert_fail(level,title); \ + } \ + } + +#define bfalert_subtest3(level,title,val) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfalert_subpass(level,title); \ + } \ + else { \ + bfalert_subfail(level,title); \ + } \ + } + +#define bferror_test3(level,title,val) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bferror_pass(level,title); \ + } \ + else { \ + bferror_fail(level,title); \ + } \ + } + +#define bferror_subtest3(level,title,val) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bferror_subpass(level,title); \ + } \ + else { \ + bferror_subfail(level,title); \ + } \ + } + +#define bfdebug_test4(level,title,val,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfdebug_pass(level,title,msg); \ + } \ + else { \ + bfdebug_fail(level,title,msg); \ + } \ + } + +#define bfdebug_subtest4(level,title,val,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfdebug_subpass(level,title,msg); \ + } \ + else { \ + bfdebug_subfail(level,title,msg); \ + } \ + } + +#define bfalert_test4(level,title,val,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfalert_pass(level,title,msg); \ + } \ + else { \ + bfalert_fail(level,title,msg); \ + } \ + } + +#define bfalert_subtest4(level,title,val,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bfalert_subpass(level,title,msg); \ + } \ + else { \ + bfalert_subfail(level,title,msg); \ + } \ + } + +#define bferror_test4(level,title,val,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bferror_pass(level,title,msg); \ + } \ + else { \ + bferror_fail(level,title,msg); \ + } \ + } + +#define bferror_subtest4(level,title,val,msg) \ + if (GSL_UNLIKELY(level <= DEBUG_LEVEL)) { \ + if ((val)) { \ + bferror_subpass(level,title,msg); \ + } \ + else { \ + bferror_subfail(level,title,msg); \ + } \ + } + +#define bfdebug_test(...) GET_MACRO(bfdebug_test, __VA_ARGS__) +#define bfdebug_subtest(...) GET_MACRO(bfdebug_subtest, __VA_ARGS__) +#define bfalert_test(...) GET_MACRO(bfalert_test, __VA_ARGS__) +#define bfalert_subtest(...) GET_MACRO(bfalert_subtest, __VA_ARGS__) +#define bferror_test(...) GET_MACRO(bferror_test, __VA_ARGS__) +#define bferror_subtest(...) GET_MACRO(bferror_subtest, __VA_ARGS__) + +/* ---------------------------------------------------------------------------*/ +/* Line / Field */ +/* ---------------------------------------------------------------------------*/ + +#define bfline bfdebug_ndec(0, "line", __LINE__); +#define __bffield1(a,b) bfdebug_ndec(0, "[" #b "] " #a, a); +#define __bffield2(a,b) __bffield1(a,b); +#define bffield(a) __bffield2(a,__LINE__) +#define __bffield_hex1(a,b) bfdebug_nhex(0, "[" #b "] " #a, a); +#define __bffield_hex2(a,b) __bffield_hex1(a,b); +#define bffield_hex(a) __bffield_hex2(a,__LINE__) + +#endif + +/* -------------------------------------------------------------------------- */ +/* C Debugging */ +/* -------------------------------------------------------------------------- */ + +#ifndef KERNEL +#ifdef __cplusplus +#include +#else +#include +#endif +#define BFDEBUG(...) printf("[BAREFLANK DEBUG]: " __VA_ARGS__) +#define BFALERT(...) printf("[BAREFLANK ALERT]: " __VA_ARGS__) +#define BFERROR(...) printf("[BAREFLANK ERROR]: " __VA_ARGS__) +#endif + +/* -------------------------------------------------------------------------- */ +/* Linux Debugging */ +/* -------------------------------------------------------------------------- */ + +#ifdef KERNEL +#ifdef __linux__ +#include +#define BFDEBUG(...) printk(KERN_INFO "[BAREFLANK DEBUG]: " __VA_ARGS__) +#define BFALERT(...) printk(KERN_INFO "[BAREFLANK ALERT]: " __VA_ARGS__) +#define BFERROR(...) printk(KERN_ALERT "[BAREFLANK ERROR]: " __VA_ARGS__) +#endif +#endif + +/* -------------------------------------------------------------------------- */ +/* Windows Debugging */ +/* -------------------------------------------------------------------------- */ + +#ifdef KERNEL +#ifdef _WIN32 +#include +#define BFDEBUG(...) DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_INFO_LEVEL, "[BAREFLANK DEBUG]: " __VA_ARGS__) +#define BFALERT(...) DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_INFO_LEVEL, "[BAREFLANK ALERT]: " __VA_ARGS__) +#define BFERROR(...) DbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL, "[BAREFLANK ERROR]: " __VA_ARGS__) +#endif +#endif + +/* -------------------------------------------------------------------------- */ +/* EFI Debugging */ +/* -------------------------------------------------------------------------- */ + +#ifdef KERNEL +#ifdef EFI +#include "efi.h" +#include "efilib.h" +#define BFDEBUG(...) Print(L"[BAREFLANK DEBUG]: " __VA_ARGS__) +#define BFALERT(...) Print(L"[BAREFLANK ALERT]: " __VA_ARGS__) +#define BFERROR(...) Print(L"[BAREFLANK ERROR]: " __VA_ARGS__) +#endif +#endif + + +/** @endcond */ + +#endif diff --git a/payloads/bareflank/include/bfdebugringinterface.h b/payloads/bareflank/include/bfdebugringinterface.h new file mode 100644 index 00000000000..6aedf3b8f58 --- /dev/null +++ b/payloads/bareflank/include/bfdebugringinterface.h @@ -0,0 +1,163 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfdebug.h + */ + +#ifndef BFDEBUGRINGINTERFACE_H +#define BFDEBUGRINGINTERFACE_H + +#include +#include +#include +#include + +#pragma pack(push, 1) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Get Debug Ring Resource Typedef + * + * @expects none + * @ensures none + * + * This is used by the driver entry to as the function signature for + * getting it's internal debug ring + */ +typedef struct debug_ring_resources_t *(*get_drr_t)(uint64_t vcpuid); + +/** + * @struct debug_ring_resources_t + * + * Debug Ring Resources + * + * Each driver entry needs to allocate some memory for the debug ring, and + * then cast this structure over the allocated memory to access the bits used + * by the ring. + * + * Prior to providing this structure to the debug ring, the memory should be + * cleared, and the len of the buffer should be set to the total length of + * memory allocated minus the size of debug_ring_resources_t. + * + * @code + * + * int len = PAGE_SIZE * 100; + * struct debug_ring_resources_t *drr = valloc(len); + * + * memset(drr, 0, len); + * drr->len = len - sizeof(debug_ring_resources_t); + * + * + * + * int ret; + * char read_buf[len] + * + * ret = debug_ring_read(drr, read_buf, len); + * if(ret < 0) + * + * + * @endcode + * + * Note there are many different designs for cicular buffers, but all of the + * designs have to face the same problem. How to detect when the buffer is + * full vs when it is empty. This design uses two counters the grow + * forever. The current position in the buffer is then pos % len. If the + * counters are 64bit, it would take a life time for the counters to + * overflow. + * + * @var debug_ring_resources_t::epos + * the end position in the circular buffer + * @var debug_ring_resources_t::spos + * the start position in the circular buffer + * @var debug_ring_resources_t::tag1 + * used to identify the debug ring from a memory dump + * @var debug_ring_resources_t::buf + * the circular buffer that stores the debug strings. + * @var debug_ring_resources_t::tag2 + * used to identify the debug ring from a memory dump + */ +struct debug_ring_resources_t { + uint64_t epos; + uint64_t spos; + + uint64_t tag1; + char buf[DEBUG_RING_SIZE]; + uint64_t tag2; +}; + +/** + * Debug Ring Read + * + * Reads strings that have been written to the debug ring. Although you can + * provide any buffer size you want, it's advised to provide a buffer that + * is the same size as the buffer that was originally allocated. + * + * @expects none + * @ensures none + * + * @param drr the debug_ring_resource that was used to create the + * debug ring + * @param str the buffer to read the string into. should be the same size + * as drr in bytes + * @param len the length of the str buffer in bytes + * @return the number of bytes read from the debug ring, 0 + * on error + */ +static inline uint64_t +debug_ring_read(struct debug_ring_resources_t *drr, char *str, uint64_t len) +{ + uint64_t i; + uint64_t spos; + uint64_t count; + uint64_t content; + + if (drr == 0 || str == 0 || len == 0) { + return 0; + } + + if (drr->spos > drr->epos) { + return 0; + } + + spos = drr->spos % DEBUG_RING_SIZE; + content = drr->epos - drr->spos; + + for (i = 0, count = 0; i < content && i < len - 1; i++) { + if (drr->buf[spos] != '\0') { + str[count++] = drr->buf[spos]; + } + + spos = ((spos + 1) % DEBUG_RING_SIZE); + } + + str[i] = '\0'; + return count; +} + +#ifdef __cplusplus +} +#endif + +#pragma pack(pop) + +#endif diff --git a/payloads/bareflank/include/bfdelegate.h b/payloads/bareflank/include/bfdelegate.h new file mode 100644 index 00000000000..7e661f82678 --- /dev/null +++ b/payloads/bareflank/include/bfdelegate.h @@ -0,0 +1,282 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULLAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfdelegate.h +/// + +#ifndef BFDELEGATE_H +#define BFDELEGATE_H + +#include + +// ----------------------------------------------------------------------------- +// Delegate Definition +// ----------------------------------------------------------------------------- + +template < + typename T, + typename = std::enable_if::value> + > +class delegate; + +// ----------------------------------------------------------------------------- +// Delegate Partial Specialization +// ----------------------------------------------------------------------------- + +/// Delegate +/// +/// This delegate class provides the ability to register a call back function +/// that originates from: +/// - A free function +/// - A member function +/// - A lambda function (including capture lists) +/// +/// It should be noted that this class attempts to provide the most effcient +/// implementation without the need for malloc / free, or inheritance, at +/// the expense of a very specific syntax requirement. +/// +template < + typename RET, + typename ...PARAMS + > +class delegate +{ + using stub_t = RET(*)(void *, PARAMS...); ///< Stub function type + +public: + + /// Default Constructor + /// + /// Creates a nullptr delegate. Note that attempts to execute a nullptr + /// delegate will result in a crash as we do not perform a check for + /// null + /// + delegate() noexcept = default; + + /// Default Destructor + /// + ~delegate() noexcept = default; + + /// Is Valid + /// + /// @return true if valid, false otherwise + /// + constexpr bool is_valid() const noexcept + { return m_stub != nullptr; } + + /// Is Valid + /// + /// @return true if valid, false otherwise + /// + constexpr explicit operator bool() const noexcept + { return is_valid(); } + + /// Create (Member Function Pointer) + /// + /// Example usage: + /// @code + /// test_class t; + /// auto d = delegate::create(&t); + /// std::cout << "d: " << d(1) << '\n'; + /// @endcode + /// + /// @param obj a pointer to the class who's member function will + /// be executed. + /// @return resulting delegate + /// + template < + typename T, + RET(T::*FUNC)(PARAMS...), + typename = std::enable_if::value> + > + constexpr static delegate create(T &obj) noexcept + { return delegate(std::addressof(obj), member_stub); } + + /// Create (Member Function Pointer Class Pointer) + /// + /// Example usage: + /// @code + /// test_class t; + /// auto d = delegate::create(&t); + /// std::cout << "d: " << d(1) << '\n'; + /// @endcode + /// + /// @param obj a pointer to the class who's member function will + /// be executed. + /// @return resulting delegate + /// + template < + typename T, + RET(T::*FUNC)(PARAMS...), + typename = std::enable_if::value> + > + constexpr static delegate create(T *obj) noexcept + { return delegate(obj, member_stub); } + + /// Create (Member Function Unique Pointer) + /// + /// Example usage: + /// @code + /// auto t = make_unique(); + /// auto d = delegate::create(t); + /// std::cout << "d: " << d(1) << '\n'; + /// @endcode + /// + /// @param obj a pointer to the class who's member function will + /// be executed. + /// @return resulting delegate + /// + template < + typename T, + RET(T::*FUNC)(PARAMS...), + typename = std::enable_if::value> + > + constexpr static delegate create(const std::unique_ptr &obj) noexcept + { return delegate(obj.get(), member_stub); } + + /// Create (Const Member Function Pointer) + /// + /// Example usage: + /// @code + /// test_class t; + /// auto d = delegate::create(&t); + /// std::cout << "d: " << d(1) << '\n'; + /// @endcode + /// + /// @note this function has to have _const appended to it's name because + /// MSVC doesn't understand the template overload and fails to + /// compile. + /// + /// @param obj a pointer to the class who's member function will + /// be executed. + /// @return resulting delegate + /// + template < + typename T, + RET(T::*FUNC)(PARAMS...) const, + typename = std::enable_if::value> + > + constexpr static delegate create_const(const T &obj) noexcept + { return delegate(const_cast(std::addressof(obj)), const_member_stub); } + + /// Create (Function Pointer) + /// + /// Example usage: + /// @code + /// auto d = delegate::create<&foo>(); + /// std::cout << "d: " << d(1) << '\n'; + /// @endcode + /// + /// @return resulting delegate + /// + template + constexpr static delegate create() noexcept + { return delegate(nullptr, function_stub); } + + /// Create (Lambda Pointer) + /// + /// Example usage: + /// @code + /// test_class t; + /// auto d = delegate::create([](int val) -> int { return val; }); + /// std::cout << "d: " << d(1) << '\n'; + /// @endcode + /// + /// @param ptr a pointer to the lambda function that will + /// be executed. + /// @return resulting delegate + /// + template + constexpr static delegate create(const LAMBDA &ptr) noexcept + { return delegate(reinterpret_cast(const_cast(std::addressof(ptr))), lambda_stub); } + + /// Operator () + /// + /// @param params the parameters to pass to the delegate function. + /// @return the result of executing the delegate function + /// + constexpr RET operator()(PARAMS... params) const + { return (*m_stub)(m_obj, std::forward(params)...); } + +private: + + /// @cond + + // Note: + // + // The only public constructor is the default constructor. To create a + // delegate, use the delegate::create function. + // + + constexpr explicit delegate(void *obj, stub_t stub) noexcept : + m_obj(obj), + m_stub(stub) + { } + + /// @endcond + +private: + + /// @cond + + template < + typename T, + RET(T::*FUNC)(PARAMS...), + typename = std::enable_if::value> + > + constexpr static RET member_stub(void *obj, PARAMS... params) + { return (static_cast(obj)->*FUNC)(std::forward(params)...); } + + template < + typename T, + RET(T::*FUNC)(PARAMS...) const, + typename = std::enable_if::value> + > + constexpr static RET const_member_stub(void *obj, PARAMS... params) + { return (static_cast(obj)->*FUNC)(std::forward(params)...); } + + template + constexpr static RET function_stub(void *, PARAMS... params) + { return (FUNC)(std::forward(params)...); } + + template + constexpr static RET lambda_stub(void *ptr, PARAMS... params) + { return (static_cast(ptr)->operator())(std::forward(params)...); } + + /// @endcond + +private: + + void *m_obj{nullptr}; ///< Object containing member function + stub_t m_stub{nullptr}; ///< Stub that executes the delegate function + +public: + + /// @cond + + delegate(const delegate &other) noexcept = default; + delegate &operator=(const delegate &other) noexcept = default; + + delegate(delegate &&other) noexcept = default; + delegate &operator=(delegate &&other) noexcept = default; + + /// @endcond +}; + +#endif diff --git a/payloads/bareflank/include/bfdriverinterface.h b/payloads/bareflank/include/bfdriverinterface.h new file mode 100644 index 00000000000..af07deb8ee7 --- /dev/null +++ b/payloads/bareflank/include/bfdriverinterface.h @@ -0,0 +1,116 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFDRIVERINTERFACE_H +#define BFDRIVERINTERFACE_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* -------------------------------------------------------------------------- */ +/* Common */ +/* -------------------------------------------------------------------------- */ + +#define VMM_UNLOADED 10 +#define VMM_LOADED 11 +#define VMM_RUNNING 12 +#define VMM_CORRUPT 100 + +#ifndef BAREFLANK_NAME +#define BAREFLANK_NAME "bareflank" +#endif + +#ifndef BAREFLANK_MAJOR +#define BAREFLANK_MAJOR 150 +#endif + +#ifndef BAREFLANK_DEVICETYPE +#define BAREFLANK_DEVICETYPE 0xF00D +#endif + +#define IOCTL_ADD_MODULE_LENGTH_CMD 0x801 +#define IOCTL_ADD_MODULE_CMD 0x802 +#define IOCTL_LOAD_VMM_CMD 0x803 +#define IOCTL_UNLOAD_VMM_CMD 0x804 +#define IOCTL_START_VMM_CMD 0x805 +#define IOCTL_STOP_VMM_CMD 0x806 +#define IOCTL_DUMP_VMM_CMD 0x807 +#define IOCTL_VMM_STATUS_CMD 0x808 +#define IOCTL_SET_VCPUID_CMD 0x80A + +/* -------------------------------------------------------------------------- */ +/* Linux Interfaces */ +/* -------------------------------------------------------------------------- */ + +#ifdef __linux__ + +#define IOCTL_ADD_MODULE_LENGTH _IOW(BAREFLANK_MAJOR, IOCTL_ADD_MODULE_LENGTH_CMD, uint64_t *) +#define IOCTL_ADD_MODULE _IOW(BAREFLANK_MAJOR, IOCTL_ADD_MODULE_CMD, char *) +#define IOCTL_LOAD_VMM _IO(BAREFLANK_MAJOR, IOCTL_LOAD_VMM_CMD) +#define IOCTL_UNLOAD_VMM _IO(BAREFLANK_MAJOR, IOCTL_UNLOAD_VMM_CMD) +#define IOCTL_START_VMM _IO(BAREFLANK_MAJOR, IOCTL_START_VMM_CMD) +#define IOCTL_STOP_VMM _IO(BAREFLANK_MAJOR, IOCTL_STOP_VMM_CMD) +#define IOCTL_DUMP_VMM _IOR(BAREFLANK_MAJOR, IOCTL_DUMP_VMM_CMD, struct debug_ring_resources_t *) +#define IOCTL_VMM_STATUS _IOR(BAREFLANK_MAJOR, IOCTL_VMM_STATUS_CMD, int64_t *) +#define IOCTL_SET_VCPUID _IOW(BAREFLANK_MAJOR, IOCTL_SET_VCPUID_CMD, uint64_t *) + +#endif + +/* -------------------------------------------------------------------------- */ +/* Windows Interfaces */ +/* -------------------------------------------------------------------------- */ + +#if defined(_WIN32) || defined(__CYGWIN__) + +#include + +DEFINE_GUID( + GUID_DEVINTERFACE_bareflank, + 0x1d9c9218, + 0x3c88, + 0x4b81, + 0x8e, + 0x81, + 0xb4, + 0x62, + 0x2a, + 0x4d, + 0xcb, + 0x44); + +#define IOCTL_ADD_MODULE CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_ADD_MODULE_CMD, METHOD_IN_DIRECT, FILE_WRITE_DATA) +#define IOCTL_LOAD_VMM CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_LOAD_VMM_CMD, METHOD_BUFFERED, 0) +#define IOCTL_UNLOAD_VMM CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_UNLOAD_VMM_CMD, METHOD_BUFFERED, 0) +#define IOCTL_START_VMM CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_START_VMM_CMD, METHOD_BUFFERED, 0) +#define IOCTL_STOP_VMM CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_STOP_VMM_CMD, METHOD_BUFFERED, 0) +#define IOCTL_DUMP_VMM CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_DUMP_VMM_CMD, METHOD_OUT_DIRECT, FILE_READ_DATA) +#define IOCTL_VMM_STATUS CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_VMM_STATUS_CMD, METHOD_BUFFERED, FILE_READ_DATA) +#define IOCTL_SET_VCPUID CTL_CODE(BAREFLANK_DEVICETYPE, IOCTL_SET_VCPUID_CMD, METHOD_IN_DIRECT, FILE_WRITE_DATA) + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/payloads/bareflank/include/bfdwarf.h b/payloads/bareflank/include/bfdwarf.h new file mode 100644 index 00000000000..b13bc99b7bd --- /dev/null +++ b/payloads/bareflank/include/bfdwarf.h @@ -0,0 +1,96 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfdwarf.h + */ + +#ifndef BFDWARF_H +#define BFDWARF_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @struct dwarf_sections_t + * + * Struct to hold pointers to all the used DWARF sections + * + * @var dwarf_sections_t::debug_info_addr + * the virtual address of ".debug_info" after relocation + * @var dwarf_sections_t::debug_info_size + * the size of ".debug_info" + * @var dwarf_sections_t::debug_abbrev_addr + * the virtual address of ".debug_abbrev" after relocation + * @var dwarf_sections_t::debug_abbrev_size + * the size of ".debug_abbrev" + * @var dwarf_sections_t::debug_line_addr + * the virtual address of ".debug_line" after relocation + * @var dwarf_sections_t::debug_line_size + * the size of ".debug_line" + * @var dwarf_sections_t::debug_str_addr + * the virtual address of ".debug_str" after relocation + * @var dwarf_sections_t::debug_str_size + * the size of ".debug_str" + * @var dwarf_sections_t::debug_ranges_addr + * the virtual address of ".debug_ranges" after relocation + * @var dwarf_sections_t::debug_ranges_size + * the size of ".debug_ranges" + */ +struct dwarf_sections_t { + void *debug_info_addr; + uint64_t debug_info_size; + + void *debug_abbrev_addr; + uint64_t debug_abbrev_size; + + void *debug_line_addr; + uint64_t debug_line_size; + + void *debug_str_addr; + uint64_t debug_str_size; + + void *debug_ranges_addr; + uint64_t debug_ranges_size; +}; + +/** + * Get DWARF sections + * + * @expects none + * @ensures ret != nullptr + * + * Returns a list containing pointers to the found DWARF sections. These + * sections are used to map instruction pointers to function names in the + * unwinder. + * + * @return dwarf_sections_t pointer + */ +struct dwarf_sections_t * +get_dwarf_sections() noexcept; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/payloads/bareflank/include/bfehframelist.h b/payloads/bareflank/include/bfehframelist.h new file mode 100644 index 00000000000..5d9be204303 --- /dev/null +++ b/payloads/bareflank/include/bfehframelist.h @@ -0,0 +1,68 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfehframelist.h + */ + +#ifndef BFEHFRAMELIST_H +#define BFEHFRAMELIST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @struct eh_frame_t + * + * Defines a ".eh_frame" section. + * + * @var eh_frame_t::addr + * the starting address of the the .eh_frame section + * @var eh_frame_t::size + * the size of the .eh_frame section + */ +struct eh_frame_t { + void *addr; + uint64_t size; +}; + +/** + * Get EH Framework List + * + * @expects none + * @ensures ret != nullptr + * + * Returns a list of ".eh_frame" sections, containing their start address, + * and size. This is used by the unwind library to find stack frames. The + * list should have one .eh_frame section for each module that is loaded. + * + * @return eh_frame list (of size MAX_NUM_MODULES) + */ +struct eh_frame_t * +get_eh_frame_list() noexcept; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/payloads/bareflank/include/bfelf_loader.h b/payloads/bareflank/include/bfelf_loader.h new file mode 100644 index 00000000000..7e0113fe540 --- /dev/null +++ b/payloads/bareflank/include/bfelf_loader.h @@ -0,0 +1,2531 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfelf_loader.h + */ + +#ifndef BFELF_LOADER_H +#define BFELF_LOADER_H + +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(push, 1) + +#ifdef __cplusplus +extern "C" { +#endif + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Defines */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +#ifndef BFELF_MAX_NEEDED +#define BFELF_MAX_NEEDED (25) +#endif + +#ifndef BFELF_MAX_SEGMENTS +#define BFELF_MAX_SEGMENTS (4) +#endif + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Data Types */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * Data Representation + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 2 + */ + +/* @cond */ + +#ifndef __cplusplus +typedef uint64_t bfelf64_addr; +typedef uint64_t bfelf64_off; +typedef uint16_t bfelf64_half; +typedef uint32_t bfelf64_word; +typedef int32_t bfelf64_sword; +typedef uint64_t bfelf64_xword; +typedef int64_t bfelf64_sxword; +#else +using bfelf64_addr = uint64_t; +using bfelf64_off = uint64_t; +using bfelf64_half = uint16_t; +using bfelf64_word = uint32_t; +using bfelf64_sword = int32_t; +using bfelf64_xword = uint64_t; +using bfelf64_sxword = int64_t; +#endif + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Error Codes */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +static inline int64_t +private_error(const char *header, const char *msg, const char *func, int line, int64_t code) +{ + BFALERT("%s [%d] %s: %s\n", func, line, header, msg); + return code; +} + +#define bfinvalid_argument(a) \ + private_error("invalid argument", a, __func__, __LINE__, BFELF_ERROR_INVALID_ARG); + +#define bfinvalid_file(a) \ + private_error("invalid file", a, __func__, __LINE__, BFELF_ERROR_INVALID_FILE); + +#define bfinvalid_index(a) \ + private_error("invalid index", a, __func__, __LINE__, BFELF_ERROR_INVALID_INDEX); + +#define bfinvalid_signature(a) \ + private_error("invalid signature", a, __func__, __LINE__, BFELF_ERROR_INVALID_SIGNATURE); + +#define bfunsupported_file(a) \ + private_error("unsupported elf file", a, __func__, __LINE__, BFELF_ERROR_UNSUPPORTED_FILE); + +#define bfloader_full(a) \ + private_error("loader full", a, __func__, __LINE__, BFELF_ERROR_LOADER_FULL); + +#define bfno_such_symbol(a) \ + private_error("no such symbol", a, __func__, __LINE__, BFELF_ERROR_NO_SUCH_SYMBOL); + +#define bfunsupported_rel(a) \ + private_error("unsupported relocation", a, __func__, __LINE__, BFELF_ERROR_UNSUPPORTED_RELA); + +#define bfout_of_memory(a) \ + private_error("out of memory", a, __func__, __LINE__, BFELF_ERROR_OUT_OF_MEMORY); + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Helpers */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +static inline int64_t +private_strcmp(const char *s1, const char *s2) +{ + while ((*s1 != 0) && (*s1 == *s2)) { + s1++, s2++; + } + + return *s1 == *s2 ? BFELF_SUCCESS : BFELF_ERROR_MISMATCH; +} + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF File Definition */ +/* ---------------------------------------------------------------------------------------------- */ + +struct bfelf_dyn; +struct bfelf_sym; +struct bfelf_rela; +struct bfelf_shdr; +struct bfelf_phdr; +struct bfelf_ehdr; + +/** + * @struct bfelf_load_instr + * + * ELF Load Segment + * + * The load instructions that each segment provides is missing some helpful + * info. This structure provides the info that is needed, in a cleaned up + * format. + * + * Note that there are two different char * buffers that you need to know about + * when loading a segment. There is the char * for the ELF file, and the char * + * for the memory that the ELF file is being loaded into. The ELF file does + * not equal memory. The best example is the BSS section, which is empty in the + * ELF file. Also, the RE vs RW sections are usually aligned. To use this + * information use the following steps: + * - get the total size of memory + * - allocate RW memory for the total size + * - get the number of load instructions + * - loop through each load instruction and copy the file char * to the mem + * char * using the file/mem offset/size. + * - map memory using the virt_addr and mem_size + * + * @var bfelf_load_instr::perm + * defines the permissions (read/write/execute) for this segment + * @var bfelf_load_instr::mem_offset + * defines the segment offset in memory + * @var bfelf_load_instr::file_offset + * defines the segment offset in the ELF file + * @var bfelf_load_instr::memsz + * defines the segment size in memory + * @var bfelf_load_instr::filesz + * defines the segment size in the ELF file + * @var bfelf_load_instr::virt_addr + * defines the assumed virtual address of the segment if PIC == false + */ +struct bfelf_load_instr { + bfelf64_word perm; + bfelf64_off mem_offset; + bfelf64_off file_offset; + bfelf64_xword memsz; + bfelf64_xword filesz; + bfelf64_addr virt_addr; +}; + +/* + * ELF File + * + * The following is used by this API to store information about the ELF file + * being used. + * + * @cond + */ +struct bfelf_file_t { + uint64_t filesz; + const char *file; + + char *exec_addr; + char *exec_virt; + + bfelf64_off entry; + + bfelf64_xword num_load_instr; + struct bfelf_load_instr load_instr[BFELF_MAX_SEGMENTS]; + + bfelf64_xword num_loadable_segments; + const struct bfelf_phdr *loadable_segments[BFELF_MAX_SEGMENTS]; + + bfelf64_addr start_addr; + bfelf64_xword total_memsz; + + bfelf64_xword num_needed; + bfelf64_xword needed[BFELF_MAX_NEEDED]; + + const struct bfelf_ehdr *ehdr; + const struct bfelf_phdr *phdrtab; + const struct bfelf_shdr *shdrtab; + + bfelf64_addr dynoff; + + const char *strtab; + const char *strtab_offset; + const char *shstrtab; + + bfelf64_word nbucket; + bfelf64_word nchain; + const bfelf64_word *bucket; + const bfelf64_word *chain; + const bfelf64_word *hash; + + bfelf64_xword dynnum; + const struct bfelf_dyn *dyntab; + + bfelf64_xword symnum; + const struct bfelf_sym *symtab; + + bfelf64_xword relanum_dyn; + const struct bfelf_rela *relatab_dyn; + + bfelf64_xword relanum_plt; + const struct bfelf_rela *relatab_plt; + + bfelf64_addr init; + bfelf64_addr fini; + + bfelf64_addr init_array; + bfelf64_xword init_arraysz; + + bfelf64_addr fini_array; + bfelf64_xword fini_arraysz; + + bfelf64_addr eh_frame; + bfelf64_xword eh_framesz; + + bfelf64_xword flags_1; + bfelf64_xword stack_flags; + + bfelf64_addr relaro_vaddr; + bfelf64_xword relaro_memsz; + + bfelf64_word added; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF File Header */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * e_ident indexes + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 3 + * + * @cond + */ +#define bfei_mag0 bfscast(bfelf64_sword, 0) +#define bfei_mag1 bfscast(bfelf64_sword, 1) +#define bfei_mag2 bfscast(bfelf64_sword, 2) +#define bfei_mag3 bfscast(bfelf64_sword, 3) +#define bfei_class bfscast(bfelf64_sword, 4) +#define bfei_data bfscast(bfelf64_sword, 5) +#define bfei_version bfscast(bfelf64_sword, 6) +#define bfei_osabi bfscast(bfelf64_sword, 7) +#define bfei_abiversion bfscast(bfelf64_sword, 8) +#define bfei_pad bfscast(bfelf64_sword, 9) +#define bfei_nident bfscast(bfelf64_sword, 16) + +/* @endcond */ + +/* + * ELF Class Types + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 5 + * + * @cond + */ +#define bfelfclass32 bfscast(unsigned char, 1) +#define bfelfclass64 bfscast(unsigned char, 2) + +/* @endcond */ + +/* + * ELF Data Types + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 5 + * + * @cond + */ +#define bfelfdata2lsb bfscast(unsigned char, 1) +#define bfelfdata2msb bfscast(unsigned char, 2) + +/* @endcond */ + +/* + * ELF Version + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 4 + * + * @cond + */ +#define bfev_current bfscast(unsigned char, 1) + +/* @endcond */ + +/* + * ELF OS / ABI Types + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 5 + * + * @cond + */ +#define bfelfosabi_sysv bfscast(unsigned char, 0) +#define bfelfosabi_hpux bfscast(unsigned char, 1) +#define bfelfosabi_standalone bfscast(unsigned char, 255) + +/* @endcond */ + +/* + * ELF Types + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 5 + * + * @cond + */ +#define bfet_none bfscast(bfelf64_half, 0) +#define bfet_rel bfscast(bfelf64_half, 1) +#define bfet_exec bfscast(bfelf64_half, 2) +#define bfet_dyn bfscast(bfelf64_half, 3) +#define bfet_core bfscast(bfelf64_half, 4) +#define bfet_loos bfscast(bfelf64_half, 0xFE00) +#define bfet_hios bfscast(bfelf64_half, 0xFEFF) +#define bfet_loproc bfscast(bfelf64_half, 0xFF00) +#define bfet_hiproc bfscast(bfelf64_half, 0xFFFF) + +/* @endcond */ + +/* + * ELF Machine Codes + * + * The following is defined in the Linux kernel sources: + * linux/include/uapi/linux/elf-em.h + * + * @cond + */ +#define bfem_none bfscast(bfelf64_half, 0) +#define bfem_m32 bfscast(bfelf64_half, 1) +#define bfem_sparc bfscast(bfelf64_half, 2) +#define bfem_386 bfscast(bfelf64_half, 3) +#define bfem_68k bfscast(bfelf64_half, 4) +#define bfem_88k bfscast(bfelf64_half, 5) +#define bfem_486 bfscast(bfelf64_half, 6) +#define bfem_860 bfscast(bfelf64_half, 7) +#define bfem_mips bfscast(bfelf64_half, 8) +#define bfem_mips_rs3_le bfscast(bfelf64_half, 10) +#define bfem_mips_rs4_be bfscast(bfelf64_half, 11) +#define bfem_parisc bfscast(bfelf64_half, 15) +#define bfem_sparc32plus bfscast(bfelf64_half, 18) +#define bfem_ppc bfscast(bfelf64_half, 20) +#define bfem_ppc64 bfscast(bfelf64_half, 21) +#define bfem_spu bfscast(bfelf64_half, 23) +#define bfem_arm bfscast(bfelf64_half, 40) +#define bfem_sh bfscast(bfelf64_half, 42) +#define bfem_sparcv9 bfscast(bfelf64_half, 43) +#define bfem_h8_300 bfscast(bfelf64_half, 46) +#define bfem_ia_64 bfscast(bfelf64_half, 50) +#define bfem_x86_64 bfscast(bfelf64_half, 62) +#define bfem_s390 bfscast(bfelf64_half, 22) +#define bfem_cris bfscast(bfelf64_half, 76) +#define bfem_v850 bfscast(bfelf64_half, 87) +#define bfem_m32r bfscast(bfelf64_half, 88) +#define bfem_mn10300 bfscast(bfelf64_half, 89) +#define bfem_openrisc bfscast(bfelf64_half, 92) +#define bfem_blackfin bfscast(bfelf64_half, 106) +#define bfem_altera_nios2 bfscast(bfelf64_half, 113) +#define bfem_ti_c6000 bfscast(bfelf64_half, 140) +#define bfem_aarch64 bfscast(bfelf64_half, 183) +#define bfem_frv bfscast(bfelf64_half, 0x5441) +#define bfem_avr32 bfscast(bfelf64_half, 0x18AD) +#define bfem_alpha bfscast(bfelf64_half, 0x9026) +#define bfem_cygnus_v850 bfscast(bfelf64_half, 0x9080) +#define bfem_cygnus_m32r bfscast(bfelf64_half, 0x9041) +#define bfem_s390_old bfscast(bfelf64_half, 0xA390) +#define bfem_cygnus_mn10300 bfscast(bfelf64_half, 0xBEEF) + +/* @endcond */ + +/* + * ELF File Header + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 3 + * + * The file header is located at the beginning of the file, and is used to + * locate the other parts of the file. + * + * @cond + */ +struct bfelf_ehdr { + unsigned char e_ident[bfei_nident]; + bfelf64_half e_type; + bfelf64_half e_machine; + bfelf64_word e_version; + bfelf64_addr e_entry; + bfelf64_off e_phoff; + bfelf64_off e_shoff; + bfelf64_word e_flags; + bfelf64_half e_ehsize; + bfelf64_half e_phentsize; + bfelf64_half e_phnum; + bfelf64_half e_shentsize; + bfelf64_half e_shnum; + bfelf64_half e_shstrndx; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Section Header Table */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * ELF Section Type + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 7 + * + * @cond + */ +#define bfsht_null bfscast(bfelf64_word, 0) +#define bfsht_progbits bfscast(bfelf64_word, 1) +#define bfsht_symtab bfscast(bfelf64_word, 2) +#define bfsht_strtab bfscast(bfelf64_word, 3) +#define bfsht_rela bfscast(bfelf64_word, 4) +#define bfsht_hash bfscast(bfelf64_word, 5) +#define bfsht_dynamic bfscast(bfelf64_word, 6) +#define bfsht_note bfscast(bfelf64_word, 7) +#define bfsht_nobits bfscast(bfelf64_word, 8) +#define bfsht_rel bfscast(bfelf64_word, 9) +#define bfsht_shlib bfscast(bfelf64_word, 10) +#define bfsht_dynsym bfscast(bfelf64_word, 11) +#define bfsht_init_array bfscast(bfelf64_word, 14) +#define bfsht_fini_array bfscast(bfelf64_word, 15) +#define bfsht_loos bfscast(bfelf64_word, 0x60000000) +#define bfsht_hios bfscast(bfelf64_word, 0x6FFFFFFF) +#define bfsht_loproc bfscast(bfelf64_word, 0x70000000) +#define bfsht_x86_64_unwind bfscast(bfelf64_word, 0x70000001) +#define bfsht_hiproc bfscast(bfelf64_word, 0x7FFFFFFF) + +/* @endcond */ + +/* + * ELF Section Attributes + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 8 + * + * @cond + */ +#define bfshf_write bfscast(bfelf64_xword, 0x1) +#define bfshf_alloc bfscast(bfelf64_xword, 0x2) +#define bfshf_execinstr bfscast(bfelf64_xword, 0x4) +#define bfshf_maskos bfscast(bfelf64_xword, 0x0F000000) +#define bfshf_maskproc bfscast(bfelf64_xword, 0xF0000000) +#define bfshf_undocumneted bfscast(bfelf64_xword, 0x00000060) + +#define bfshf_a (bfshf_alloc) +#define bfshf_wa (bfshf_write | bfshf_alloc) +#define bfshf_ai (bfshf_alloc | bfshf_write | bfshf_undocumneted) + +/* @endcond */ + +/* + * ELF Section Header Entry + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 6 + * + * Sections contain all the information in an ELF file, except for the ELF + * header, program header table, and section header table. Sections are + * identified by an index into the section header table. + * + * @cond + */ +struct bfelf_shdr { + bfelf64_word sh_name; + bfelf64_word sh_type; + bfelf64_xword sh_flags; + bfelf64_addr sh_addr; + bfelf64_off sh_offset; + bfelf64_xword sh_size; + bfelf64_word sh_link; + bfelf64_word sh_info; + bfelf64_xword sh_addralign; + bfelf64_xword sh_entsize; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Dynamic Section */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * ELF Dynamic Table Entry Tags + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 14 + * + * @cond + */ +#define bfdt_null bfscast(bfelf64_xword, 0) +#define bfdt_needed bfscast(bfelf64_xword, 1) +#define bfdt_pltrelsz bfscast(bfelf64_xword, 2) +#define bfdt_pltgot bfscast(bfelf64_xword, 3) +#define bfdt_hash bfscast(bfelf64_xword, 4) +#define bfdt_strtab bfscast(bfelf64_xword, 5) +#define bfdt_symtab bfscast(bfelf64_xword, 6) +#define bfdt_rela bfscast(bfelf64_xword, 7) +#define bfdt_relasz bfscast(bfelf64_xword, 8) +#define bfdt_relaent bfscast(bfelf64_xword, 9) +#define bfdt_strsz bfscast(bfelf64_xword, 10) +#define bfdt_syment bfscast(bfelf64_xword, 11) +#define bfdt_init bfscast(bfelf64_xword, 12) +#define bfdt_fini bfscast(bfelf64_xword, 13) +#define bfdt_soname bfscast(bfelf64_xword, 14) +#define bfdt_rpath bfscast(bfelf64_xword, 15) +#define bfdt_symbolic bfscast(bfelf64_xword, 16) +#define bfdt_rel bfscast(bfelf64_xword, 17) +#define bfdt_relsz bfscast(bfelf64_xword, 18) +#define bfdt_relent bfscast(bfelf64_xword, 19) +#define bfdt_pltrel bfscast(bfelf64_xword, 20) +#define bfdt_debug bfscast(bfelf64_xword, 21) +#define bfdt_textrel bfscast(bfelf64_xword, 22) +#define bfdt_jmprel bfscast(bfelf64_xword, 23) +#define bfdt_bind_now bfscast(bfelf64_xword, 24) +#define bfdt_init_array bfscast(bfelf64_xword, 25) +#define bfdt_fini_array bfscast(bfelf64_xword, 26) +#define bfdt_init_arraysz bfscast(bfelf64_xword, 27) +#define bfdt_fini_arraysz bfscast(bfelf64_xword, 28) +#define bfdt_loos bfscast(bfelf64_xword, 0x60000000) +#define bfdt_relacount bfscast(bfelf64_xword, 0x6ffffff9) +#define bfdt_relcount bfscast(bfelf64_xword, 0x6ffffffa) +#define bfdt_flags_1 bfscast(bfelf64_xword, 0x6ffffffb) +#define bfdt_hios bfscast(bfelf64_xword, 0x6FFFFFFF) +#define bfdt_loproc bfscast(bfelf64_xword, 0x70000000) +#define bfdt_hiproc bfscast(bfelf64_xword, 0x7FFFFFFF) + +#define bfdf_1_now bfscast(bfelf64_xword, 0x00000001) +#define bfdf_1_global bfscast(bfelf64_xword, 0x00000002) +#define bfdf_1_group bfscast(bfelf64_xword, 0x00000004) +#define bfdf_1_nodelete bfscast(bfelf64_xword, 0x00000008) +#define bfdf_1_loadfltr bfscast(bfelf64_xword, 0x00000010) +#define bfdf_1_initfirst bfscast(bfelf64_xword, 0x00000020) +#define bfdf_1_noopen bfscast(bfelf64_xword, 0x00000040) +#define bfdf_1_origin bfscast(bfelf64_xword, 0x00000080) +#define bfdf_1_direct bfscast(bfelf64_xword, 0x00000100) +#define bfdf_1_trans bfscast(bfelf64_xword, 0x00000200) +#define bfdf_1_interpose bfscast(bfelf64_xword, 0x00000400) +#define bfdf_1_nodeflib bfscast(bfelf64_xword, 0x00000800) +#define bfdf_1_nodump bfscast(bfelf64_xword, 0x00001000) +#define bfdf_1_confalt bfscast(bfelf64_xword, 0x00002000) +#define bfdf_1_endfiltee bfscast(bfelf64_xword, 0x00004000) +#define bfdf_1_dispreldne bfscast(bfelf64_xword, 0x00008000) +#define bfdf_1_disprelpnd bfscast(bfelf64_xword, 0x00010000) +#define bfdf_1_nodirect bfscast(bfelf64_xword, 0x00020000) +#define bfdf_1_ignmuldef bfscast(bfelf64_xword, 0x00040000) +#define bfdf_1_noksyms bfscast(bfelf64_xword, 0x00080000) +#define bfdf_1_nohdr bfscast(bfelf64_xword, 0x00100000) +#define bfdf_1_edited bfscast(bfelf64_xword, 0x00200000) +#define bfdf_1_noreloc bfscast(bfelf64_xword, 0x00400000) +#define bfdf_1_symintpose bfscast(bfelf64_xword, 0x00800000) +#define bfdf_1_globaudit bfscast(bfelf64_xword, 0x01000000) +#define bfdf_1_singleton bfscast(bfelf64_xword, 0x02000000) +#define bfdf_1_pie bfscast(bfelf64_xword, 0x08000000) + +/* @endcond */ + +/* + * ELF Dynamic Table + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 14 + * + * NOTE: The spec actually uses a union, but the use of a union goes against + * the C++ Core Guidelines, and Windows seems to get really mad. There really + * is not need for a union since the type size if the same. For this reason, + * we simply use d_val and cast when needed. + * + * @cond + */ +struct bfelf_dyn { + bfelf64_sxword d_tag; + bfelf64_xword d_val; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Symbol Table */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * ELF Symbol Bindings + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 10 + * + * @cond + */ +#define bfstb_local bfscast(unsigned char, 0) +#define bfstb_global bfscast(unsigned char, 1) +#define bfstb_weak bfscast(unsigned char, 2) +#define bfstb_loos bfscast(unsigned char, 10) +#define bfstb_hios bfscast(unsigned char, 12) +#define bfstb_loproc bfscast(unsigned char, 13) +#define bfstb_hiproc bfscast(unsigned char, 15) + +/* @endcond */ + +/* + * ELF Symbol Types + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 10 + * + * @cond + */ +#define bfstt_notype bfscast(unsigned char, 0) +#define bfstt_object bfscast(unsigned char, 1) +#define bfstt_func bfscast(unsigned char, 2) +#define bfstt_section bfscast(unsigned char, 3) +#define bfstt_file bfscast(unsigned char, 4) +#define bfstt_loos bfscast(unsigned char, 10) +#define bfstt_hios bfscast(unsigned char, 12) +#define bfstt_loproc bfscast(unsigned char, 13) +#define bfstt_hiproc bfscast(unsigned char, 15) + +/* @endcond */ + +/* + * ELF Symbol Info Algorithms + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 11 + * + * @cond + */ +#define BFELF_SYM_BIND(x) ((x) >> 4) +#define BFELF_SYM_TYPE(x) ((x)&0xF) + +/* @endcond */ + +/* + * ELF Undefined Symbol Index + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 9 + * + * @cond + */ +#define STN_UNDEF 0 + +/* @endcond */ + +/* + * ELF Symbol + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 9 + * + * @cond + */ +struct bfelf_sym { + bfelf64_word st_name; + unsigned char st_info; + unsigned char st_other; + bfelf64_half st_shndx; + bfelf64_addr st_value; + bfelf64_xword st_size; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Relocations */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * ELF Relocation + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 11 + * + * @cond + */ +struct bfelf_rel { + bfelf64_addr r_offset; + bfelf64_xword r_info; +}; + +/* @endcond */ + +/* + * ELF Relocation Addend + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 11 + * + * @cond + */ +struct bfelf_rela { + bfelf64_addr r_offset; + bfelf64_xword r_info; + bfelf64_sxword r_addend; +}; + +/* @endcond */ + +/* + * ELF Relocation Info Algorithms + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 11 + * + * @cond + */ +#define BFELF_REL_SYM(i) ((i) >> 32) +#define BFELF_REL_TYPE(i) ((i)&0xFFFFFFFFL) + +/* @endcond */ + + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Program Header */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * ELF Section Attributes + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 12 + * + * @cond + */ +#define bfpt_null bfscast(bfelf64_word, 0) +#define bfpt_load bfscast(bfelf64_word, 1) +#define bfpt_dynamic bfscast(bfelf64_word, 2) +#define bfpt_interp bfscast(bfelf64_word, 3) +#define bfpt_note bfscast(bfelf64_word, 4) +#define bfpt_shlib bfscast(bfelf64_word, 5) +#define bfpt_phdr bfscast(bfelf64_word, 6) +#define bfpt_loos bfscast(bfelf64_word, 0x60000000) +#define bfpt_gnu_eh_frame bfscast(bfelf64_word, 0x6474e550) +#define bfpt_gnu_stack bfscast(bfelf64_word, 0x6474e551) +#define bfpt_gnu_relro bfscast(bfelf64_word, 0x6474e552) +#define bfpt_hios bfscast(bfelf64_word, 0x6FFFFFFF) +#define bfpt_loproc bfscast(bfelf64_word, 0x70000000) +#define bfpt_hiproc bfscast(bfelf64_word, 0x7FFFFFFF) + +/* @endcond */ + +/* + * ELF Section Attributes + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 13 + * + * @cond + */ +#define bfpf_x bfscast(bfelf64_xword, 0x1) +#define bfpf_w bfscast(bfelf64_xword, 0x2) +#define bfpf_r bfscast(bfelf64_xword, 0x4) +#define bfpf_maskos bfscast(bfelf64_xword, 0x00FF0000) +#define bfpf_maskproc bfscast(bfelf64_xword, 0xFF000000) + +/* @endcond */ + +/* + * ELF Program Header Entry + * + * The following is defined in the ELF 64bit file format specification: + * http://www.uclibc.org/docs/elf-64-gen.pdf, page 12 + * + * In executable and shared object files, sections are grouped into segments for + * loading. The program header table contains a list of entries describing + * each segment. This information is needed when using the ELF loader to + * load each segment into memory allocated by the user. For more information + * on how to do this, please see the unit tests. + * + * @cond + */ +struct bfelf_phdr { + bfelf64_word p_type; + bfelf64_word p_flags; + bfelf64_off p_offset; + bfelf64_addr p_vaddr; + bfelf64_addr p_paddr; + bfelf64_xword p_filesz; + bfelf64_xword p_memsz; + bfelf64_xword p_align; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Loader Definition */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * ELF Loader + * + * The following structure is used to create an ELF loader, which groups up + * all of the ELF files used by a single program, mainly needed for global + * symbol searching. + * + * @cond + */ +struct bfelf_loader_t { + bfelf64_word num; + bfelf64_word relocated; + struct bfelf_file_t *efs[MAX_NUM_MODULES]; +}; + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Symbol Table Implementation */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +static inline unsigned long +private_hash(const char *name) +{ + unsigned long h = 0; + + while (*name != 0) { + char c = *name++; + unsigned long g; + unsigned char uc = bfscast(unsigned char, c); + + if (c >= 0) { + h = (h << 4) + uc; + } + else { + h = (h << 4) - uc; + } + + if ((g = (h & 0xf0000000)) != 0) { + h ^= g >> 24; + } + + h &= 0x0fffffff; + } + + return h; +} + +static inline int64_t +private_get_sym_by_hash( + struct bfelf_file_t *ef, const char *name, const struct bfelf_sym **sym) +{ + bfelf64_word i = 0; + unsigned long x = private_hash(name); + + i = ef->bucket[x % ef->nbucket]; + while (i > STN_UNDEF && i < ef->nchain) { + int64_t ret = 0; + const char *str = nullptr; + + *sym = &(ef->symtab[i]); + str = &(ef->strtab[(*sym)->st_name]); + + ret = private_strcmp(name, str); + if (ret == BFELF_ERROR_MISMATCH) { + i = ef->chain[i]; + continue; + } + + return BFELF_SUCCESS; + } + + return BFELF_ERROR_NO_SUCH_SYMBOL; +} + +static inline int64_t +private_get_sym_by_name( + struct bfelf_file_t *ef, const char *name, const struct bfelf_sym **sym) +{ + bfelf64_word i = 0; + + if (ef->hash != nullptr) { + return private_get_sym_by_hash(ef, name, sym); + } + + for (i = 0; i < ef->symnum; i++) { + int64_t ret = 0; + const char *str = nullptr; + + *sym = &(ef->symtab[i]); + str = &(ef->strtab[(*sym)->st_name]); + + ret = private_strcmp(name, str); + if (ret == BFELF_ERROR_MISMATCH) { + continue; + } + + return BFELF_SUCCESS; + } + + return BFELF_ERROR_NO_SUCH_SYMBOL; +} + +static inline int64_t +private_get_sym_global( + const struct bfelf_loader_t *loader, const char *name, + struct bfelf_file_t **ef_found, const struct bfelf_sym **sym) +{ + int64_t ret = 0; + bfelf64_word i = 0; + struct bfelf_file_t *ef_ignore = *ef_found; + const struct bfelf_sym *found_sym = nullptr; + + *sym = nullptr; + *ef_found = nullptr; + + for (i = 0; i < loader->num; i++) { + if (loader->efs[i] == ef_ignore) { + continue; + } + + ret = private_get_sym_by_name(loader->efs[i], name, &found_sym); + if (ret == BFELF_ERROR_NO_SUCH_SYMBOL) { + continue; + } + + if (found_sym->st_value == 0) { + continue; + } + + *sym = found_sym; + *ef_found = loader->efs[i]; + + if (BFELF_SYM_BIND(found_sym->st_info) == bfstb_weak) { + continue; + } + + return BFELF_SUCCESS; + } + + if (*sym != nullptr) { + return BFELF_SUCCESS; + } + + return bfno_such_symbol(name); +} + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Relocations Implementation */ +/* ---------------------------------------------------------------------------------------------- */ + +/* + * Forward declarations required by relocator + * + * @cond + */ + +static inline int64_t +private_get_sym_global( + const struct bfelf_loader_t *loader, const char *name, + struct bfelf_file_t **ef_found, const struct bfelf_sym **sym); + +/* @endcond */ + +/* + * Relocation definitions and relocators + * + * @cond + */ + +#if defined(BF_AARCH64) +# include +#elif defined(BF_X64) +# include +#else +# error "Unsupported architecture" +#endif + +/* @endcond */ + +/* @cond */ + +static inline int64_t +private_relocate_symbols(struct bfelf_loader_t *loader, struct bfelf_file_t *ef) +{ + int64_t ret = 0; + bfelf64_word i = 0; + + for (i = 0; i < ef->relanum_dyn; i++) { + const struct bfelf_rela *rela = &(ef->relatab_dyn[i]); + + ret = private_relocate_symbol(loader, ef, rela); + if (ret != BFELF_SUCCESS) { + return ret; + } + } + + for (i = 0; i < ef->relanum_plt; i++) { + const struct bfelf_rela *rela = &(ef->relatab_plt[i]); + + ret = private_relocate_symbol(loader, ef, rela); + if (ret != BFELF_SUCCESS) { + return ret; + } + } + + return BFELF_SUCCESS; +} + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF File Implementation */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +static inline int64_t +private_check_signature(struct bfelf_file_t *ef) +{ + if (ef->ehdr->e_ident[bfei_mag0] != 0x7F) { + return bfinvalid_signature("magic #0 has unexpected value"); + } + + if (ef->ehdr->e_ident[bfei_mag1] != 'E') { + return bfinvalid_signature("magic #1 has unexpected value"); + } + + if (ef->ehdr->e_ident[bfei_mag2] != 'L') { + return bfinvalid_signature("magic #2 has unexpected value"); + } + + if (ef->ehdr->e_ident[bfei_mag3] != 'F') { + return bfinvalid_signature("magic #3 has unexpected value"); + } + + return BFELF_SUCCESS; +} + +static inline int64_t +private_check_support(struct bfelf_file_t *ef) +{ + if (ef->ehdr->e_ident[bfei_class] != bfelfclass64) { + return bfunsupported_file("file is not 64bit"); + } + + if (ef->ehdr->e_ident[bfei_data] != bfelfdata2lsb) { + return bfunsupported_file("file is not little endian"); + } + + if (ef->ehdr->e_ident[bfei_version] != bfev_current) { + return bfunsupported_file("unsupported version"); + } + + if (ef->ehdr->e_ident[bfei_osabi] != bfelfosabi_sysv) { + return bfunsupported_file("file does not use the system v abi"); + } + + if (ef->ehdr->e_ident[bfei_abiversion] != 0) { + return bfunsupported_file("unsupported abi version"); + } + + if (ef->ehdr->e_type != bfet_dyn && ef->ehdr->e_type != bfet_exec) { + return bfunsupported_file("file must be an executable or shared library"); + } + +#ifdef BF_AARCH64 + if (ef->ehdr->e_machine != bfem_aarch64) { + return bfunsupported_file("file must be compiled for aarch64"); + } +#endif + +#ifdef BF_X64 + if (ef->ehdr->e_machine != bfem_x86_64) { + return bfunsupported_file("file must be compiled for x86_64"); + } +#endif + + if (ef->ehdr->e_version != bfev_current) { + return bfunsupported_file("unsupported version"); + } + + if (ef->ehdr->e_flags != 0) { + return bfunsupported_file("unsupported flags"); + } + + return BFELF_SUCCESS; +} + +static inline void +private_process_segments(struct bfelf_file_t *ef) +{ + bfelf64_xword i = 0; + + for (i = 0; i < ef->ehdr->e_phnum; i++) { + const struct bfelf_phdr *phdr = &(ef->phdrtab[i]); + + switch (phdr->p_type) { + case bfpt_load: + + if (ef->num_loadable_segments < BFELF_MAX_SEGMENTS) { + ef->total_memsz = phdr->p_vaddr + phdr->p_memsz; + ef->loadable_segments[ef->num_loadable_segments++] = phdr; + } + + break; + + case bfpt_dynamic: + ef->dynoff = phdr->p_offset; + ef->dynnum = phdr->p_filesz / sizeof(struct bfelf_dyn); + break; + + case bfpt_gnu_stack: + ef->stack_flags = phdr->p_flags; + break; + + case bfpt_gnu_relro: + ef->relaro_vaddr = phdr->p_vaddr; + ef->relaro_memsz = phdr->p_memsz; + break; + } + } + + if (ef->num_loadable_segments > 0) { + ef->start_addr = ef->loadable_segments[0]->p_vaddr; + ef->total_memsz -= ef->start_addr; + } + + for (i = 0; i < ef->num_loadable_segments; i++) { + const struct bfelf_phdr *phdr = ef->loadable_segments[i]; + + ef->load_instr[i].perm = phdr->p_flags; + ef->load_instr[i].mem_offset = phdr->p_vaddr - ef->start_addr; + ef->load_instr[i].file_offset = phdr->p_offset; + ef->load_instr[i].memsz = phdr->p_memsz; + ef->load_instr[i].filesz = phdr->p_filesz; + ef->load_instr[i].virt_addr = phdr->p_vaddr; + + ef->num_load_instr++; + } +} + +static inline void +private_process_dynamic_section(struct bfelf_file_t *ef) +{ + bfelf64_xword i = 0; + + if (ef->dynnum == 0 || ef->dynoff == 0) { + return; + } + + ef->num_needed = 0; + ef->dyntab = bfrcast(const struct bfelf_dyn *, ef->file + ef->dynoff); + + for (i = 0; i < ef->dynnum; i++) { + const struct bfelf_dyn *dyn = &(ef->dyntab[i]); + + switch (dyn->d_tag) { + case bfdt_null: + return; + + case bfdt_needed: + + if (ef->num_needed < BFELF_MAX_NEEDED) { + ef->needed[ef->num_needed++] = dyn->d_val; + } + + break; + + case bfdt_pltrelsz: + ef->relanum_plt = dyn->d_val / sizeof(struct bfelf_rela); + break; + + case bfdt_hash: + ef->hash = bfrcast(bfelf64_word *, dyn->d_val); + break; + + case bfdt_strtab: + ef->strtab_offset = bfrcast(char *, dyn->d_val); + break; + + case bfdt_symtab: + ef->symtab = bfrcast(struct bfelf_sym *, dyn->d_val); + break; + + case bfdt_rela: + ef->relatab_dyn = bfrcast(struct bfelf_rela *, dyn->d_val); + break; + + case bfdt_relasz: + ef->relanum_dyn = dyn->d_val / sizeof(struct bfelf_rela); + break; + + case bfdt_init: + ef->init = dyn->d_val; + break; + + case bfdt_fini: + ef->fini = dyn->d_val; + break; + + case bfdt_jmprel: + ef->relatab_plt = bfrcast(struct bfelf_rela *, dyn->d_val); + break; + + case bfdt_init_array: + ef->init_array = dyn->d_val; + break; + + case bfdt_fini_array: + ef->fini_array = dyn->d_val; + break; + + case bfdt_init_arraysz: + ef->init_arraysz = dyn->d_val; + break; + + case bfdt_fini_arraysz: + ef->fini_arraysz = dyn->d_val; + break; + + case bfdt_flags_1: + ef->flags_1 = dyn->d_val; + break; + + default: + break; + } + } +} + +/* @endcond */ + +/** + * Initialize an ELF file + * + * This function initializes an ELF file structure given the file's contents + * in memory. The resulting structure will be used by all of the other + * functions. + * + * @expects file != nullptr + * @expects filesz != nullptr + * @expects ef != nullptr + * @ensures + * + * @param file a character buffer containing the contents of the ELF file to + * be loaded. + * @param filesz the size of the character buffer + * @param ef the ELF file structure to initialize. + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_file_init(const char *file, uint64_t filesz, struct bfelf_file_t *ef) +{ + int64_t ret = 0; + bfelf64_word i = 0; + + if (file == nullptr) { + return bfinvalid_argument("file == nullptr"); + } + + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (filesz < sizeof(struct bfelf_ehdr)) { + return bfinvalid_argument("filesz invalid"); + } + + ef->file = file; + ef->filesz = filesz; + + ef->ehdr = bfrcast(const struct bfelf_ehdr *, file); + ef->phdrtab = bfrcast(const struct bfelf_phdr *, file + ef->ehdr->e_phoff); + ef->shdrtab = bfrcast(const struct bfelf_shdr *, file + ef->ehdr->e_shoff); + + ret = private_check_signature(ef); + if (ret != BFELF_SUCCESS) { + return ret; + } + + ret = private_check_support(ef); + if (ret != BFELF_SUCCESS) { + return ret; + } + + private_process_segments(ef); + private_process_dynamic_section(ef); + + ef->entry = ef->ehdr->e_entry; + ef->shstrtab = bfrcast(const char *, file + ef->shdrtab[ef->ehdr->e_shstrndx].sh_offset); + + /* + * ld from binutils 2.27 only has rela.dyn, while ld.gold and ld.lld both + * have rela.dyn and rela.plt. ld from binutils 2.27 also uses + * .init_array / .fini_array instead of .ctors / .dtors, while ld.gold and + * ld.lld still use the old .ctors / .dtors, which do not seems to show + * up in the .dynamic section, so we need to manually search for them. + * Since you will likely only have one or the other, if we see the old + * .ctors / .dtors, we treat it like .init_array / .fini_array for now + * which keeps things simple. Also, ld from binutils 2.27 marks .eh_frame + * with bfsht_x86_64_unwind, while ld.gold and ld.lld both mark .eh_frame + * with bfsht_progbits, also requiring a manual string search. + * + * Note that the file provided in this function is assumed to be deleted + * after this function is called, and thus, we have to search for these + * sections now because the file will not be available later. + */ + + for (i = 0; i < ef->ehdr->e_shnum; i++) { + const struct bfelf_shdr *shdr = &(ef->shdrtab[i]); + const char *name = &ef->shstrtab[shdr->sh_name]; + + if (private_strcmp(name, ".eh_frame") == BFELF_SUCCESS) { + ef->eh_frame = shdr->sh_addr; + ef->eh_framesz = shdr->sh_size; + continue; + } + + if (private_strcmp(name, ".ctors") == BFELF_SUCCESS) { + ef->init_array = shdr->sh_addr; + ef->init_arraysz = shdr->sh_size; + continue; + } + + if (private_strcmp(name, ".dtors") == BFELF_SUCCESS) { + ef->fini_array = shdr->sh_addr; + ef->fini_arraysz = shdr->sh_size; + continue; + } + } + + /* + * The string table is located in both ELF file provided here, as well as + * in the exec provided to bfelf_loader_add. By the time bfelf_loader_add + * is called, we assume that the file provided to this function has been + * deleted, but up to this point, the user is free to use some of the + * functions (like bfelf_file_get_needed), and for these we need a valid + * string table, so we store the location of the string table relative + * to the provided file, and then overwrite this when the user adds the + * ELF file to the loader, in which case we reference the string table + * relative to the provided exec. + */ + ef->strtab = bfcadd(const char *, ef->strtab_offset, bfrcast(bfelf64_addr, file)); + + return BFELF_SUCCESS; +} + +/** + * Get number of load instructions + * + * Once an ELF file has been initialized, the next step is to load all of the + * program segments into memory, relocate them, and then execute the entry + * point. To assist this operation, this function returns the total number of + * load instructions. + * + * @expects ef != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file + * @return number of load instructions on success, negative on error + */ +static inline int64_t +bfelf_file_get_num_load_instrs(const struct bfelf_file_t *ef) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + return bfscast(int64_t, ef->num_load_instr); +} + +/** + * Get load instructions + * + * Once you know how many load instructions there are, you can use this + * function to get each instruction structure. + * + * @expects ef != nullptr + * @expects index < bfelf_file_get_num_load_instrs() + * @expects instr != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file + * @param index the index of the instructions to get + * @param instr where to store the load instructions + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_file_get_load_instr( + const struct bfelf_file_t *ef, uint64_t index, const struct bfelf_load_instr **instr) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (instr == nullptr) { + return bfinvalid_argument("phdr == nullptr"); + } + + if (index >= ef->num_load_instr) { + return bfinvalid_index("index >= number of load instructions"); + } + + *instr = &(ef->load_instr[index]); + return BFELF_SUCCESS; +} + +/** + * Get Info + * + * Once an ELF loader has had all of it's ELF files initialized and added, + * use the relocate ELF loader to setup the ELF files such that they can + * be executed. Once this is done, this function can be used to get the + * C runtime information for bootstrapping a binary / module. + * + * @expects ef != nullptr + * @expects info != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the info structure for + * @param info the info structure to store the results. + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_file_get_section_info( + const struct bfelf_file_t *ef, struct section_info_t *info) +{ + bfelf64_word i = 0; + + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (info == nullptr) { + return bfinvalid_argument("info == nullptr"); + } + + if (ef->added == 0) { + return bfinvalid_argument("ef must be added to a loader first"); + } + + for (i = 0; i < sizeof(struct section_info_t); i++) { + bfrcast(char *, info)[i] = 0; + } + + if (ef->init != 0) { + info->init_addr = ef->init + ef->exec_virt; + } + + if (ef->fini != 0) { + info->fini_addr = ef->fini + ef->exec_virt; + } + + if (ef->init_array != 0) { + info->init_array_addr = ef->init_array + ef->exec_virt; + info->init_array_size = ef->init_arraysz; + } + + if (ef->fini_array != 0) { + info->fini_array_addr = ef->fini_array + ef->exec_virt; + info->fini_array_size = ef->fini_arraysz; + } + + if (ef->eh_frame != 0) { + info->eh_frame_addr = ef->eh_frame + ef->exec_virt; + info->eh_frame_size = ef->eh_framesz; + } + + return BFELF_SUCCESS; +} + +/** + * Get Entry Point + * + * Returns the entry point of the ELF file. + * + * @expects ef != nullptr + * @expects addr != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the entry location from + * @param addr the resulting address of the entry point + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_file_get_entry(const struct bfelf_file_t *ef, void **addr) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (addr == nullptr) { + return bfinvalid_argument("addr == nullptr"); + } + + if (ef->added == 0) { + return bfinvalid_argument("ef must be added to a loader first"); + } + + *addr = bfrcast(void *, ef->entry + ef->exec_virt); + return BFELF_SUCCESS; +} + +/** + * Get Stack Permissions + * + * Returns the ELF file's stack permissions. + * + * @expects ef != nullptr + * @expects perm != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the stack permission info from + * @param perm the resulting permissions + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_file_get_stack_perm(const struct bfelf_file_t *ef, bfelf64_xword *perm) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (perm == nullptr) { + return bfinvalid_argument("perm == nullptr"); + } + + *perm = ef->stack_flags; + return BFELF_SUCCESS; +} + +/** + * Get Relocation Read-Only Info + * + * Returns the ELF file's RELRO information for + * re-mapping previously writable memory to read-only + * + * @expects ef != nullptr + * @expects addr != nullptr + * @expects size != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the relro info from + * @param addr the resulting address + * @param size the resulting size + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_file_get_relro( + const struct bfelf_file_t *ef, bfelf64_addr *addr, bfelf64_xword *size) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (addr == nullptr) { + return bfinvalid_argument("addr == nullptr"); + } + + if (size == nullptr) { + return bfinvalid_argument("size == nullptr"); + } + + if (ef->added == 0) { + return bfinvalid_argument("ef must be added to a loader first"); + } + + *addr = ef->relaro_vaddr + bfrcast(bfelf64_addr, ef->exec_virt); + *size = ef->relaro_memsz; + return BFELF_SUCCESS; +} + +/** + * Get Number of Needed Libraries + * + * Returns the number of DT_NEEDED entries in the ELF + * file + * + * @expects ef != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the number of needed files from + * @return number of needed entries on success, negative on error + */ +static inline int64_t +bfelf_file_get_num_needed(const struct bfelf_file_t *ef) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + return bfscast(int64_t, ef->num_needed); +} + +/** + * Get Needed Library + * + * Returns the name of a shared library that is needed by this + * ELF file + * + * @expects ef != nullptr + * @expects index < bfelf_file_get_num_needed() + * @expects needed != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the needed filename from + * @param index the shared library name to get + * @param needed the resulting needed library + * @return number of needed entries on success, negative on error + */ +static inline int64_t +bfelf_file_get_needed( + const struct bfelf_file_t *ef, uint64_t index, const char **needed) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (needed == nullptr) { + return bfinvalid_argument("needed == nullptr"); + } + + if (index >= ef->num_needed) { + return bfinvalid_index("index >= number of needed"); + } + + *needed = &(ef->strtab[ef->needed[index]]); + return BFELF_SUCCESS; +} + +/** + * Get Total Memory Size + * + * Returns the total number of bytes needed in memory for this ELF file + * when loading the ELF file + * + * @expects ef != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the total size from + * @return number of needed entries on success, negative on error + */ +static inline int64_t +bfelf_file_get_total_size(const struct bfelf_file_t *ef) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + return bfscast(int64_t, ef->total_memsz); +} + +/** + * Get PIC/PIE + * + * Returns 1 if this ELF file was compiled using PIC / PIE, or + * 0 otherwise + * + * @expects ef != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param ef the ELF file to get the pic/pie info from + * @return 1 if compiled with PIC/PIE, 0 otherwise + */ +static inline int64_t +bfelf_file_get_pic_pie(const struct bfelf_file_t *ef) +{ + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + return ef->start_addr == 0 ? 1 : 0; +} + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Loader Implementation */ +/* ---------------------------------------------------------------------------------------------- */ + +/** + * Add ELF file to an ELF loader + * + * Once an ELF loader has been initialized, use this function to add an + * ELF file to the ELF loader + * + * @expects loader != nullptr + * @expects ef != nullptr + * @expects exec_addr != nullptr + * @expects exec_virt != nullptr + * @ensures + * + * @param loader the ELF loader + * @param ef the ELF file to add + * @param exec_addr the address in memory where this ELF file was loaded. + * @param exec_virt the address in memory where this ELF file will be run. + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_loader_add( + struct bfelf_loader_t *loader, struct bfelf_file_t *ef, char *exec_addr, char *exec_virt) +{ + bfelf64_addr start; + + if (loader == nullptr) { + return bfinvalid_argument("loader == nullptr"); + } + + if (ef == nullptr) { + return bfinvalid_argument("ef == nullptr"); + } + + if (exec_addr == nullptr) { + return bfinvalid_argument("exec_addr == nullptr"); + } + + if (loader->num >= MAX_NUM_MODULES) { + return bfloader_full("increase MAX_NUM_MODULES"); + } + + if (ef->added++ != 0) { + return bfinvalid_argument("ef already added"); + } + + ef->exec_addr = exec_addr; + + if (ef->start_addr == 0) { + ef->exec_virt = exec_virt; + } + + start = bfrcast(bfelf64_addr, ef->exec_addr - ef->start_addr); + + ef->hash = bfcadd(const bfelf64_word *, ef->hash, start); + ef->strtab = bfcadd(const char *, ef->strtab_offset, start); + ef->symtab = bfcadd(const struct bfelf_sym *, ef->symtab, start); + ef->relatab_dyn = bfcadd(const struct bfelf_rela *, ef->relatab_dyn, start); + ef->relatab_plt = bfcadd(const struct bfelf_rela *, ef->relatab_plt, start); + + ef->nbucket = ef->hash[0]; + ef->nchain = ef->hash[1]; + ef->bucket = &(ef->hash[2]); + ef->chain = &(ef->hash[2 + ef->nbucket]); + + /* + * Sadly, the only way to determine the total size of the dynamic symbol + * table is to assume that the dynamic string table is always after the + * dynamic symbol table. :( + */ + ef->symnum = (bfrcast(bfelf64_addr, ef->strtab) - bfrcast(bfelf64_addr, ef->symtab)) / + sizeof(struct bfelf_sym); + + loader->efs[loader->num++] = ef; + return BFELF_SUCCESS; +} + +/** + * Relocate ELF Loader + * + * Relocates all of the ELF files that have been added to the ELF loader. + * Once all of the ELF files have been relocated, it's safe to resolve + * symbols for execution. + * + * @expects loader != nullptr + * @ensures + * + * @param loader the ELF loader + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_loader_relocate(struct bfelf_loader_t *loader) +{ + bfelf64_word i = 0; + + if (loader == nullptr) { + return bfinvalid_argument("loader == nullptr"); + } + + if (loader->relocated == 1) { + return BFELF_SUCCESS; + } + + for (i = 0; i < loader->num; i++) { + int64_t ret = private_relocate_symbols(loader, loader->efs[i]); + if (ret != BFELF_SUCCESS) { + return ret; + } + } + + loader->relocated = 1; + return BFELF_SUCCESS; +} + +/** + * Resolve Symbol + * + * Once an ELF loader has had all of it's ELF files initialized and added, + * use the relocate ELF loader to setup the ELF files such that they can + * be executed. If the ELF file is relocated into memory that is accessible + * via the ELF loader, the resolve symbol function can be used to get the + * address of a specific symbol so that it can be executed. + * + * @expects loader != nullptr + * @expects loader != name + * @expects loader != addr + * @ensures + * + * @param loader the ELF loader + * @param name the name of the symbol to resolve + * @param addr the resulting address if the symbol is successfully resolved + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_loader_resolve_symbol( + const struct bfelf_loader_t *loader, const char *name, void **addr) +{ + int64_t ret = 0; + + struct bfelf_file_t *found_ef = nullptr; + const struct bfelf_sym *found_sym = nullptr; + + if (loader == nullptr) { + return bfinvalid_argument("loader == nullptr"); + } + + if (name == nullptr) { + return bfinvalid_argument("name == nullptr"); + } + + if (addr == nullptr) { + return bfinvalid_argument("addr == nullptr"); + } + + ret = private_get_sym_global(loader, name, &found_ef, &found_sym); + if (ret != BFELF_SUCCESS) { + return ret; + } + + *addr = found_ef->exec_virt + found_sym->st_value; + return BFELF_SUCCESS; +} + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Loading APIs */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +struct bfelf_binary_t { + char *exec; + const char *file; + uint64_t exec_size; + uint64_t file_size; + struct bfelf_file_t ef; +}; + +static inline int64_t +private_load_binary(struct bfelf_binary_t *binary) +{ + int64_t i = 0; + int64_t ret = 0; + int64_t num_segments = 0; + + /* + * Note: + * + * This function expects that binary->file and binary->file_size have + * already been filled in before executing this function. It will + * allocate the exec, and then copy each program segment in the provided + * file into the exec + */ + + if (binary->ef.file == nullptr) { + ret = bfelf_file_init(binary->file, binary->file_size, &binary->ef); + if (ret != BF_SUCCESS) { + return ret; + } + } + + num_segments = bfelf_file_get_num_load_instrs(&binary->ef); + binary->exec_size = bfscast(uint64_t, bfelf_file_get_total_size(&binary->ef)); + + /* + * TODO: + * + * Currently we allocate RWE memory instead of W^E. This code is used in + * two different places, the hypervisor and guest applications. In both + * cases this memory is changed to W^E by either the hypervisor's memory + * manager, or by a set of hypercalls. The only time the memory is actually + * used as RWE is during the initialization of the hypervisor, and not it's + * normal operation. + * + * Since this has to be cross platform, most operating systems support some + * form of RWE so this is what we use today. The risk for attack is limited + * to the initialization of the hypervisor which in most cases will be + * performed by a root-of-trust, so the attack surface is low. Still, + * someday it would be nice to find an mprotect like function for all + * operating systems such that memory can be allocated RW, and changed + * to RE as needed. If this functionality is found, the code here will have + * to be changed to support this. + */ + + binary->exec = bfscast(char *, platform_alloc_rwe(binary->exec_size)); + if (binary->exec == nullptr) { + return bfout_of_memory("unable to allocate exec RWE memory"); + } + + platform_memset(binary->exec, 0, binary->exec_size); + + for (i = 0; i < num_segments; i++) { + const struct bfelf_load_instr *instr = nullptr; + + const char *src = nullptr; + char *dst = nullptr; + + ret = bfelf_file_get_load_instr(&binary->ef, bfscast(uint64_t, i), &instr); + bfignored(ret); + + if (instr != nullptr) { + dst = bfadd(char *, binary->exec, instr->mem_offset); + src = bfcadd(const char *, binary->file, instr->file_offset); + + platform_memcpy(dst, src, instr->filesz); + } + } + + return BF_SUCCESS; +} + +static inline int64_t +private_relocate_binaries( + struct bfelf_binary_t *binaries, uint64_t num_binaries, struct bfelf_loader_t *loader) +{ + uint64_t i = 0; + int64_t ret = 0; + + for (i = 0; i < num_binaries; i++) { + ret = bfelf_loader_add(loader, &binaries[i].ef, binaries[i].exec, binaries[i].exec); + bfignored(ret); + } + + ret = bfelf_loader_relocate(loader); + if (ret != BFELF_SUCCESS) { + return ret; + } + + return BF_SUCCESS; +} + +static inline int64_t +private_crt_info( + struct bfelf_binary_t *binaries, uint64_t num_binaries, struct crt_info_t *crt_info) +{ + uint64_t i = 0; + + for (i = 0; i < num_binaries; i++) { + + int64_t ret = 0; + struct section_info_t section_info; + + ret = bfelf_file_get_section_info(&binaries[i].ef, §ion_info); + bfignored(ret); + + crt_info->info[crt_info->info_num++] = section_info; + } + + return BF_SUCCESS; +} + +/* @endcond */ + +/** + * Load + * + * Takes an array of ELF binaries and loads them. The resulting output is an + * entry point that can be executed. The CRT info and the ELF loader are also + * provided as a result. + * + * @note This function gets the entry point of the last binary provided. + * For this reason, the main executable should ALWAYS be last in the list + * of ELF binaries provided + * + * @note It is assumed that file and file_size are already provided for each + * ELF binary. This function will loop through each binary, and use this + * information to actually load everything into ELF file specific + * structures. + * + * @expects binaries != null + * @expects num_binaries != 0 && num_binaries < MAX_NUM_MODULES + * @expects entry != null + * @expects crt_info != null + * @expects loader != null + * @ensures none + * + * @param binaries the list of ELF binaries to load + * @param num_binaries the number of binaries provided + * @param entry the resulting entry point + * @param crt_info the resulting CRT info + * @param loader the resulting ELF loader + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_load( + struct bfelf_binary_t *binaries, uint64_t num_binaries, void **entry, + struct crt_info_t *crt_info, struct bfelf_loader_t *loader) +{ + uint64_t i = 0; + int64_t ret = 0; + + if (binaries == nullptr) { + return bfinvalid_argument("binaries == nullptr"); + } + + if (num_binaries == 0 || num_binaries >= MAX_NUM_MODULES) { + return bfinvalid_argument("num_binaries == 0 || num_binaries >= MAX_NUM_MODULES"); + } + + if (entry == nullptr) { + return bfinvalid_argument("entry == nullptr"); + } + + if (crt_info == nullptr) { + return bfinvalid_argument("crt_info == nullptr"); + } + + if (loader == nullptr) { + return bfinvalid_argument("loader == nullptr"); + } + + for (i = 0; i < num_binaries; i++) { + ret = private_load_binary(&binaries[i]); + if (ret != BF_SUCCESS) { + return ret; + } + } + + ret = private_relocate_binaries(binaries, num_binaries, loader); + if (ret != BF_SUCCESS) { + return ret; + } + + ret = private_crt_info(binaries, num_binaries, crt_info); + bfignored(ret); + + ret = bfelf_file_get_entry(&binaries[num_binaries - 1].ef, entry); + bfignored(ret); + + return BF_SUCCESS; +} + +/** + * Set Args + * + * Tells the CRT info to use the standard main(arc, argv) function, and sets + * the values of these. This information will be passed to the resulting + * entry point + * + * @expects crt_info != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param crt_info the CRT info to fill where the args will be stored + * @param argc the total number of args + * @param argv the args + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_set_args(struct crt_info_t *crt_info, int argc, const char **argv) +{ + if (crt_info == nullptr) { + return bfinvalid_argument("crt_info == nullptr"); + } + + crt_info->argc = argc; + crt_info->argv = argv; + crt_info->arg_type = 0; + + return BF_SUCCESS; +} + +/** + * Set Integer Args + * + * There are two different types of main functions supported: the standard + * main(arc, argv) and then another form that uses 64bit integers in the + * form int64_t bfmain(int64_t, int64_t, int64_t, int64_t). This function tells + * the CRT info to use the integer version, and sets the values of these. + * This information will be passed to the resulting entry point + * + * @expects crt_info != nullptr + * @ensures returns BFELF_SUCCESS if params == valid + * + * @param crt_info the CRT info to fill where the args will be stored + * @param request the request id + * @param arg1 integer arg #1 + * @param arg2 integer arg #2 + * @param arg3 integer arg #3 + * @return BFELF_SUCCESS on success, negative on error + */ +static inline int64_t +bfelf_set_integer_args( + struct crt_info_t *crt_info, uintptr_t request, uintptr_t arg1, uintptr_t arg2, uintptr_t arg3) +{ + if (crt_info == nullptr) { + return bfinvalid_argument("crt_info == nullptr"); + } + + crt_info->request = request; + crt_info->arg1 = arg1; + crt_info->arg2 = arg2; + crt_info->arg3 = arg3; + crt_info->arg_type = 1; + + return BF_SUCCESS; +} + +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + +#include +#include +#include + +#include +#include +#include +#include + +/* @cond */ + +inline auto +private_read_binary( + gsl::not_null f, const std::string &filename, bfelf_binary_t &binary) +{ + auto buffer = f->read_binary(filename); + + binary.file = buffer.get(); + binary.file_size = buffer.size(); + + return buffer; +} + +inline auto +private_get_needed_list(const bfelf_file_t &ef) +{ + int64_t ret = 0; + std::vector list; + + for (auto i = 0LL; i < bfelf_file_get_num_needed(&ef); i++) { + const char *needed = nullptr; + + ret = bfelf_file_get_needed(&ef, static_cast(i), &needed); + bfignored(ret); + + list.emplace_back(needed); + } + + return list; +} + +/* @endcond */ + +/** + * Read Binary and Get Needed List + * + * This function takes a filename, and a list of paths to locate the + * provide file. If the ELF binary is located, the function then parses + * the ELF file and returns the list of binaries that are needed (i.e. + * have to be linked to this ELF binary to resolve needed symbols). If + * the binary cannot be located, an exception is thrown. + * + * @expects none + * @ensures none + * + * @param f the file object to read the located filename + * @param filename the name of the ELF binary to get the needed list from + * @param paths a list of paths to locate the ELF binary from + * @param buffer the buffer to read the ELF binary into + * @param binary the binary object + * @return list of needed binaries or throws + */ +inline auto +bfelf_read_binary_and_get_needed_list( + gsl::not_null f, const std::string &filename, + const std::vector &paths, bfn::buffer &buffer, bfelf_binary_t &binary) +{ + buffer = private_read_binary(f, filename, binary); + + auto ret = bfelf_file_init(buffer.data(), buffer.size(), &binary.ef); + if (ret != BFELF_SUCCESS) { + throw std::runtime_error("bfelf_file_init failed: " + std::to_string(ret)); + } + + auto list = f->find_files(private_get_needed_list(binary.ef), paths); + return list; +} + +/** + * Binaries Info + * + * Provides a C++ wrapper for all of the ELF structures that are needed to + * load an ELF binary. + */ +class binaries_info +{ +public: + + using index_type = std::size_t; ///< Index type + using info_type = crt_info_t; ///< CRT info type + using entry_type = void *; ///< Entry point address type + using loader_type = bfelf_loader_t; ///< ELF loader type + + /** + * Constructor + * + * Loads the file provided, and searches the needed list to identify + * any other files that are needed for symbol resolution. + * + * @expects none + * @ensures none + * + * @param f the file object to read the located filename + * @param filename the name of the ELF binary to load + * @param paths a list of paths to locate the ELF binary from + * @param load if true, loads the binaries + */ + binaries_info( + gsl::not_null f, const std::string &filename, const std::vector &paths, bool load = true) + { + bfn::buffer data; + bfelf_binary_t binary = {}; + + auto filenames = bfelf_read_binary_and_get_needed_list(f, filename, paths, data, binary); + + this->init_binaries(f, filenames); + this->push_binary(std::move(data), std::move(binary)); + + auto ___ = gsl::on_failure([&] { + this->unload_binaries(); + }); + + if (load) { + this->load_binaries(); + } + } + + /** + * Constructor + * + * Loads all of the files provided. This does not search the needed list + * and instead expects that the list of binaries provided is complete. + * + * @expects none + * @ensures none + * + * @param f the file object to read the located filename + * @param filenames the list of files to load + * @param load if true, loads the binaries + */ + binaries_info( + gsl::not_null f, const std::vector &filenames, bool load = true) + { + this->init_binaries(f, filenames); + + auto ___ = gsl::on_failure([&] { + this->unload_binaries(); + }); + + if (load) { + this->load_binaries(); + } + } + + /** + * Default Destructor + */ + ~binaries_info() + { this->unload_binaries(); } + + /** + * Set Args + * + * Sets the argc and argv for this binary. + * + * @expects none + * @ensures none + * + * @param argc the number of arguments to pass to this binary + * @param argv the arguments to pass to this binary + */ + void + set_args(int argc, const char **argv) + { + auto ret = bfelf_set_args(&m_info, argc, argv); + bfignored(ret); + } + + /** + * Get Main ELF Binary + * + * Returns the main ELF binary (i.e. does not return the shared libraries + * needed by the main binary) + * + * @expects none + * @ensures none + * + * @return main binary + */ + auto & + ef() + { return m_binaries.back().ef; } + + /** + * Get Specific ELF Binary + * + * Returns a specific ELF binary given an index + * + * @expects index is valid + * @ensures none + * + * @param index of the ELF binary to get + * @return main binary + */ + auto & + ef(index_type index) + { return m_binaries.at(index).ef; } + + /** + * Get A Specific Binary + * + * @expects none + * @ensures none + * + * @param index of the specific binary to get + * @return returns a specific binary + */ + auto & + at(index_type index) + { return m_binaries.at(index); } + + /** + * Get The First Binary + * + * @expects none + * @ensures none + * + * @return returns the first binary + */ + auto & + front() + { return m_binaries.front(); } + + /** + * Get The Last Binary + * + * @expects none + * @ensures none + * + * @return returns the last binary + */ + auto & + back() + { return m_binaries.back(); } + + /** + * Get Binaries + * + * @expects none + * @ensures none + * + * @return returns the Binaries + */ + auto & + binaries() + { return m_binaries; } + + /** + * Get CRT Info + * + * @expects none + * @ensures none + * + * @return returns CRT info + */ + const auto & + info() const + { return m_info; } + + /** + * Get Entry Point Address + * + * @expects none + * @ensures none + * + * @return returns entry point address + */ + auto + entry() const + { return m_entry; } + + /** + * Get ELF Loader + * + * @expects none + * @ensures none + * + * @return returns the ELF loader + */ + auto & + loader() + { return m_loader; } + +private: + + void + push_binary(bfn::buffer &&data, bfelf_binary_t &&binary) + { + m_datas.push_back(std::move(data)); + m_binaries.push_back(std::move(binary)); + } + + void + init_binaries(gsl::not_null f, const std::vector &filenames) + { + expects(!filenames.empty()); + + for (const auto &filename : filenames) { + bfelf_binary_t binary = {}; + this->push_binary(private_read_binary(f, filename, binary), std::move(binary)); + } + } + + void + load_binaries() + { + auto ret = bfelf_load(m_binaries.data(), m_binaries.size(), &m_entry, &m_info, &m_loader); + if (ret != BF_SUCCESS) { + throw std::runtime_error("bfelf_load failed: " + bfn::to_string(ret, 16)); + } + } + + void + unload_binaries() + { + for (const auto &binary : m_binaries) { + platform_free_rwe(binary.exec, binary.exec_size); + } + } + + info_type m_info{}; + entry_type m_entry{}; + loader_type m_loader{}; + + std::vector m_binaries; + std::vector m_datas; + +public: + + /** @cond */ + + binaries_info(binaries_info &&) noexcept = default; + binaries_info &operator=(binaries_info &&) noexcept = default; + + binaries_info(const binaries_info &) = delete; + binaries_info &operator=(const binaries_info &) = delete; + + /** @endcond */ +}; + +#endif + +#pragma pack(pop) +#endif diff --git a/payloads/bareflank/include/bfelf_loader_reloc_aarch64.h b/payloads/bareflank/include/bfelf_loader_reloc_aarch64.h new file mode 100644 index 00000000000..80155de61cb --- /dev/null +++ b/payloads/bareflank/include/bfelf_loader_reloc_aarch64.h @@ -0,0 +1,263 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2017 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfelf_loader_reloc_aarch64.h + */ + +/* + * AArch64 Relocations + * + * The following is defined in the "ELF for the ARM 64-bit architecture" + * specification: + * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056b/IHI0056B_aaelf64.pdf + * + * @cond + */ + +/* ---------------------------------------------------------------------------------------------- */ +/* Miscellaneous relocations */ +/* ---------------------------------------------------------------------------------------------- */ +#define BFR_AARCH64_NONE bfscast(bfelf64_xword, 0) + +/* ---------------------------------------------------------------------------------------------- */ +/* Static data relocations */ +/* ---------------------------------------------------------------------------------------------- */ +/* Data relocations */ +#define BFR_AARCH64_ABS64 bfscast(bfelf64_xword, 257) +#define BFR_AARCH64_ABS32 bfscast(bfelf64_xword, 258) +#define BFR_AARCH64_ABS16 bfscast(bfelf64_xword, 259) +#define BFR_AARCH64_PREL64 bfscast(bfelf64_xword, 260) +#define BFR_AARCH64_PREL32 bfscast(bfelf64_xword, 261) +#define BFR_AARCH64_PREL16 bfscast(bfelf64_xword, 262) + +/* ---------------------------------------------------------------------------------------------- */ +/* Static AArch64 relocations */ +/* ---------------------------------------------------------------------------------------------- */ +/* Group relocations to create an unsigned data value or address inline */ +#define BFR_AARCH64_MOVW_UABS_G0 bfscast(bfelf64_xword, 263) +#define BFR_AARCH64_MOVW_UABS_G0_NC bfscast(bfelf64_xword, 264) +#define BFR_AARCH64_MOVW_UABS_G1 bfscast(bfelf64_xword, 265) +#define BFR_AARCH64_MOVW_UABS_G1_NC bfscast(bfelf64_xword, 266) +#define BFR_AARCH64_MOVW_UABS_G2 bfscast(bfelf64_xword, 267) +#define BFR_AARCH64_MOVW_UABS_G2_NC bfscast(bfelf64_xword, 268) +#define BFR_AARCH64_MOVW_UABS_G3 bfscast(bfelf64_xword, 269) + +/* Group relocations to create a signed data or offset value inline */ +#define BFR_AARCH64_MOVW_SABS_G0 bfscast(bfelf64_xword, 270) +#define BFR_AARCH64_MOVW_SABS_G1 bfscast(bfelf64_xword, 271) +#define BFR_AARCH64_MOVW_SABS_G2 bfscast(bfelf64_xword, 272) + +/* Relocations to generate PC-relative addresses */ +#define BFR_AARCH64_LD_PREL_LO19 bfscast(bfelf64_xword, 273) +#define BFR_AARCH64_ADR_PREL_LO21 bfscast(bfelf64_xword, 274) +#define BFR_AARCH64_ADR_PREL_PG_HI21 bfscast(bfelf64_xword, 275) +#define BFR_AARCH64_ADR_PREL_PG_HI21_NC bfscast(bfelf64_xword, 276) +#define BFR_AARCH64_ADD_ABS_LO12_NC bfscast(bfelf64_xword, 277) +#define BFR_AARCH64_LDST8_ABS_LO12_NC bfscast(bfelf64_xword, 278) +#define BFR_AARCH64_LDST16_ABS_LO12_NC bfscast(bfelf64_xword, 284) +#define BFR_AARCH64_LDST32_ABS_LO12_NC bfscast(bfelf64_xword, 285) +#define BFR_AARCH64_LDST64_ABS_LO12_NC bfscast(bfelf64_xword, 286) +#define BFR_AARCH64_LDST128_ABS_LO12_NC bfscast(bfelf64_xword, 299) + +/* Relocations for control-flow instructions */ +#define BFR_AARCH64_TSTBR14 bfscast(bfelf64_xword, 279) +#define BFR_AARCH64_CONDBR19 bfscast(bfelf64_xword, 280) +#define BFR_AARCH64_JUMP26 bfscast(bfelf64_xword, 282) +#define BFR_AARCH64_CALL26 bfscast(bfelf64_xword, 283) + +/* Group relocations to create a PC-relative offset inline */ +#define BFR_AARCH64_MOVW_PREL_G0 bfscast(bfelf64_xword, 287) +#define BFR_AARCH64_MOVW_PREL_G0_NC bfscast(bfelf64_xword, 288) +#define BFR_AARCH64_MOVW_PREL_G1 bfscast(bfelf64_xword, 289) +#define BFR_AARCH64_MOVW_PREL_G1_NC bfscast(bfelf64_xword, 290) +#define BFR_AARCH64_MOVW_PREL_G2 bfscast(bfelf64_xword, 291) +#define BFR_AARCH64_MOVW_PREL_G2_NC bfscast(bfelf64_xword, 292) +#define BFR_AARCH64_MOVW_PREL_G3 bfscast(bfelf64_xword, 293) + +/* Group relocations to create a GOT-relative offset inline */ +#define BFR_AARCH64_MOVW_GOTOFF_G0 bfscast(bfelf64_xword, 300) +#define BFR_AARCH64_MOVW_GOTOFF_G0_NC bfscast(bfelf64_xword, 301) +#define BFR_AARCH64_MOVW_GOTOFF_G1 bfscast(bfelf64_xword, 302) +#define BFR_AARCH64_MOVW_GOTOFF_G1_NC bfscast(bfelf64_xword, 303) +#define BFR_AARCH64_MOVW_GOTOFF_G2 bfscast(bfelf64_xword, 304) +#define BFR_AARCH64_MOVW_GOTOFF_G2_NC bfscast(bfelf64_xword, 305) +#define BFR_AARCH64_MOVW_GOTOFF_G3 bfscast(bfelf64_xword, 306) + +/* GOT-relative data relocations */ +#define BFR_AARCH64_GOTREL64 bfscast(bfelf64_xword, 307) +#define BFR_AARCH64_GOTREL32 bfscast(bfelf64_xword, 308) + +/* GOT-relative instruction relocations */ +#define BFR_AARCH64_GOT_LD_PREL19 bfscast(bfelf64_xword, 309) +#define BFR_AARCH64_LD64_GOTOFF_LO15 bfscast(bfelf64_xword, 310) +#define BFR_AARCH64_ADR_GOT_PAGE bfscast(bfelf64_xword, 311) +#define BFR_AARCH64_LD64_GOT_LO12_NC bfscast(bfelf64_xword, 312) +#define BFR_AARCH64_LD64_GOTPAGE_LO15 bfscast(bfelf64_xword, 313) + +/* ---------------------------------------------------------------------------------------------- */ +/* Relocations for thread-local storage */ +/* ---------------------------------------------------------------------------------------------- */ +/* General dynamic TLS relocations */ +#define BFR_AARCH64_TLSGD_ADR_PREL21 bfscast(bfelf64_xword, 512) +#define BFR_AARCH64_TLSGD_ADR_PAGE21 bfscast(bfelf64_xword, 513) +#define BFR_AARCH64_TLSGD_ADD_LO12_NC bfscast(bfelf64_xword, 514) +#define BFR_AARCH64_TLSGD_MOVW_G1 bfscast(bfelf64_xword, 515) +#define BFR_AARCH64_TLSGD_MOVW_G0_NC bfscast(bfelf64_xword, 516) + +/* Local dynamic TLS relocations */ +#define BFR_AARCH64_TLSLD_ADR_PREL21 bfscast(bfelf64_xword, 517) +#define BFR_AARCH64_TLSLD_ADR_PAGE21 bfscast(bfelf64_xword, 518) +#define BFR_AARCH64_TLSLD_ADD_LO12_NC bfscast(bfelf64_xword, 519) +#define BFR_AARCH64_TLSLD_MOVW_G1 bfscast(bfelf64_xword, 520) +#define BFR_AARCH64_TLSLD_MOVW_G0_NC bfscast(bfelf64_xword, 521) +#define BFR_AARCH64_TLSLD_LD_PREL19 bfscast(bfelf64_xword, 522) +#define BFR_AARCH64_TLSLD_MOVW_DTPREL_G2 bfscast(bfelf64_xword, 523) +#define BFR_AARCH64_TLSLD_MOVW_DTPREL_G1 bfscast(bfelf64_xword, 524) +#define BFR_AARCH64_TLSLD_MOVW_DTPREL_G1_NC bfscast(bfelf64_xword, 525) +#define BFR_AARCH64_TLSLD_MOVW_DTPREL_G0 bfscast(bfelf64_xword, 526) +#define BFR_AARCH64_TLSLD_MOVW_DTPREL_G0_NC bfscast(bfelf64_xword, 527) +#define BFR_AARCH64_TLSLD_ADD_DTPREL_HI12 bfscast(bfelf64_xword, 528) +#define BFR_AARCH64_TLSLD_ADD_DTPREL_LO12 bfscast(bfelf64_xword, 529) +#define BFR_AARCH64_TLSLD_ADD_DTPREL_LO12_NC bfscast(bfelf64_xword, 530) +#define BFR_AARCH64_TLSLD_LDST8_DTPREL_LO12 bfscast(bfelf64_xword, 531) +#define BFR_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC bfscast(bfelf64_xword, 532) +#define BFR_AARCH64_TLSLD_LDST16_DTPREL_LO12 bfscast(bfelf64_xword, 533) +#define BFR_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC bfscast(bfelf64_xword, 534) +#define BFR_AARCH64_TLSLD_LDST32_DTPREL_LO12 bfscast(bfelf64_xword, 535) +#define BFR_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC bfscast(bfelf64_xword, 536) +#define BFR_AARCH64_TLSLD_LDST64_DTPREL_LO12 bfscast(bfelf64_xword, 537) +#define BFR_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC bfscast(bfelf64_xword, 538) +#define BFR_AARCH64_TLSLD_LDST128_DTPREL_LO12 bfscast(bfelf64_xword, 572) +#define BFR_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC bfscast(bfelf64_xword, 573) + +/* Initial exec TLS relocations */ +#define BFR_AARCH64_TLSIE_MOVW_GOTTPREP_G1 bfscast(bfelf64_xword, 539) +#define BFR_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC bfscast(bfelf64_xword, 540) +#define BFR_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 bfscast(bfelf64_xword, 541) +#define BFR_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC bfscast(bfelf64_xword, 542) +#define BFR_AARCH64_TLSIE_LD_GOTTPREL_PREL19 bfscast(bfelf64_xword, 543) + +/* Local exec TLS relocations */ +#define BFR_AARCH64_TLSLE_MOVW_TPREL_G2 bfscast(bfelf64_xword, 544) +#define BFR_AARCH64_TLSLE_MOVW_TPREL_G1 bfscast(bfelf64_xword, 545) +#define BFR_AARCH64_TLSLE_MOVW_TPREL_G1_NC bfscast(bfelf64_xword, 546) +#define BFR_AARCH64_TLSLE_MOVW_TPREL_G0 bfscast(bfelf64_xword, 547) +#define BFR_AARCH64_TLSLE_MOVW_TPREL_G0_NC bfscast(bfelf64_xword, 548) +#define BFR_AARCH64_TLSLE_ADD_TPREL_HI12 bfscast(bfelf64_xword, 549) +#define BFR_AARCH64_TLSLE_ADD_TPREL_LO12 bfscast(bfelf64_xword, 550) +#define BFR_AARCH64_TLSLE_ADD_TPREL_LO12_NC bfscast(bfelf64_xword, 551) +#define BFR_AARCH64_TLSLE_LDST8_TPREL_LO12 bfscast(bfelf64_xword, 552) +#define BFR_AARCH64_TLSLE_LDST8_TPREL_LO12_NC bfscast(bfelf64_xword, 553) +#define BFR_AARCH64_TLSLE_LDST16_TPREL_LO12 bfscast(bfelf64_xword, 554) +#define BFR_AARCH64_TLSLE_LDST16_TPREL_LO12_NC bfscast(bfelf64_xword, 555) +#define BFR_AARCH64_TLSLE_LDST32_TPREL_LO12 bfscast(bfelf64_xword, 556) +#define BFR_AARCH64_TLSLE_LDST32_TPREL_LO12_NC bfscast(bfelf64_xword, 557) +#define BFR_AARCH64_TLSLE_LDST64_TPREL_LO12 bfscast(bfelf64_xword, 558) +#define BFR_AARCH64_TLSLE_LDST64_TPREL_LO12_NC bfscast(bfelf64_xword, 559) +#define BFR_AARCH64_TLSLE_LDST128_TPREL_LO12 bfscast(bfelf64_xword, 570) +#define BFR_AARCH64_TLSLE_LDST128_TPREL_LO12_NC bfscast(bfelf64_xword, 571) + +/* TLS descriptor relocations */ +#define BFR_AARCH64_TLSDESC_LD_PREL19 bfscast(bfelf64_xword, 560) +#define BFR_AARCH64_TLSDESC_ADR_PREL21 bfscast(bfelf64_xword, 561) +#define BFR_AARCH64_TLSDESC_ADR_PAGE21 bfscast(bfelf64_xword, 562) +#define BFR_AARCH64_TLSDESC_LD64_LO12 bfscast(bfelf64_xword, 563) +#define BFR_AARCH64_TLSDESC_ADD_LO12 bfscast(bfelf64_xword, 564) +#define BFR_AARCH64_TLSDESC_OFF_G1 bfscast(bfelf64_xword, 656) +#define BFR_AARCH64_TLSDESC_OFF_G0_NC bfscast(bfelf64_xword, 566) +#define BFR_AARCH64_TLSDESC_LDR bfscast(bfelf64_xword, 567) +#define BFR_AARCH64_TLSDESC_ADD bfscast(bfelf64_xword, 568) +#define BFR_AARCH64_TLSDESC_CALL bfscast(bfelf64_xword, 569) + +/* ---------------------------------------------------------------------------------------------- */ +/* Dynamic relocations */ +/* ---------------------------------------------------------------------------------------------- */ +#define BFR_AARCH64_COPY bfscast(bfelf64_xword, 1024) +#define BFR_AARCH64_GLOB_DAT bfscast(bfelf64_xword, 1025) +#define BFR_AARCH64_JUMP_SLOT bfscast(bfelf64_xword, 1026) +#define BFR_AARCH64_RELATIVE bfscast(bfelf64_xword, 1027) +#define BFR_AARCH64_TLS_DTPREL64 bfscast(bfelf64_xword, 1028) +#define BFR_AARCH64_TLS_DTPMOD64 bfscast(bfelf64_xword, 1029) +#define BFR_AARCH64_TLS_TPREL64 bfscast(bfelf64_xword, 1030) +#define BFR_AARCH64_TLSDESC bfscast(bfelf64_xword, 1031) +#define BFR_AARCH64_IRELATIVE bfscast(bfelf64_xword, 1032) + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Relocations Implementation */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +static inline int64_t +private_relocate_symbol( + struct bfelf_loader_t *loader, struct bfelf_file_t *ef, const struct bfelf_rela *rela) +{ + const char *str = nullptr; + const struct bfelf_sym *found_sym = nullptr; + struct bfelf_file_t *found_ef = ef; + bfelf64_addr *ptr = bfrcast(bfelf64_addr *, ef->exec_addr + rela->r_offset - ef->start_addr); + + if (BFELF_REL_TYPE(rela->r_info) == BFR_AARCH64_RELATIVE) { + *ptr = bfrcast(bfelf64_addr, ef->exec_virt + rela->r_addend); + return BFELF_SUCCESS; + } + + found_sym = &(ef->symtab[BFELF_REL_SYM(rela->r_info)]); + + if (BFELF_SYM_BIND(found_sym->st_info) == bfstb_weak) { + found_ef = nullptr; + } + + if (found_sym->st_value == 0 || found_ef == nullptr) { + int64_t ret; + + str = &(ef->strtab[found_sym->st_name]); + ret = private_get_sym_global(loader, str, &found_ef, &found_sym); + + if (ret != BFELF_SUCCESS) { + return ret; + } + } + + switch (BFELF_REL_TYPE(rela->r_info)) { + case BFR_AARCH64_GLOB_DAT: + case BFR_AARCH64_JUMP_SLOT: + case BFR_AARCH64_ABS64: + *ptr = bfrcast(bfelf64_addr, found_ef->exec_virt + found_sym->st_value); + break; + + case BFR_AARCH64_ABS32: + *(uint32_t *) ptr = bfrcast(uint32_t, found_ef->exec_virt + found_sym->st_value); + break; + + case BFR_AARCH64_ABS16: + *(uint16_t *) ptr = bfrcast(uint16_t, found_ef->exec_virt + found_sym->st_value); + break; + + default: + return bfunsupported_rel(str); + } + + return BFELF_SUCCESS; +} + +/* @endcond */ diff --git a/payloads/bareflank/include/bfelf_loader_reloc_x64.h b/payloads/bareflank/include/bfelf_loader_reloc_x64.h new file mode 100644 index 00000000000..5127762ff76 --- /dev/null +++ b/payloads/bareflank/include/bfelf_loader_reloc_x64.h @@ -0,0 +1,93 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2017 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfelf_loader_reloc_x64.h + */ + +/* + * System V ABI 64bit Relocations + * + * The following is defined in the ELF 64bit file format specification: + * http://www.x86-64.org/documentation/abi.pdf, page 71 + * + * @cond + */ +#define BFR_X86_64_64 bfscast(bfelf64_xword, 1) +#define BFR_X86_64_GLOB_DAT bfscast(bfelf64_xword, 6) +#define BFR_X86_64_JUMP_SLOT bfscast(bfelf64_xword, 7) +#define BFR_X86_64_RELATIVE bfscast(bfelf64_xword, 8) + +/* @endcond */ + +/* ---------------------------------------------------------------------------------------------- */ +/* ELF Relocations Implementation */ +/* ---------------------------------------------------------------------------------------------- */ + +/* @cond */ + +static inline int64_t +private_relocate_symbol( + struct bfelf_loader_t *loader, struct bfelf_file_t *ef, const struct bfelf_rela *rela) +{ + const char *str = nullptr; + const struct bfelf_sym *found_sym = nullptr; + struct bfelf_file_t *found_ef = ef; + bfelf64_addr *ptr = bfrcast(bfelf64_addr *, ef->exec_addr + rela->r_offset - ef->start_addr); + + if (BFELF_REL_TYPE(rela->r_info) == BFR_X86_64_RELATIVE) { + *ptr = bfrcast(bfelf64_addr, ef->exec_virt + rela->r_addend); + return BFELF_SUCCESS; + } + + found_sym = &(ef->symtab[BFELF_REL_SYM(rela->r_info)]); + + if (BFELF_SYM_BIND(found_sym->st_info) == bfstb_weak) { + found_ef = nullptr; + } + + if (found_sym->st_value == 0 || found_ef == nullptr) { + int64_t ret = 0; + str = &(ef->strtab[found_sym->st_name]); + + ret = private_get_sym_global(loader, str, &found_ef, &found_sym); + if (ret != BFELF_SUCCESS) { + return ret; + } + } + + *ptr = bfrcast(bfelf64_addr, found_ef->exec_virt + found_sym->st_value); + + switch (BFELF_REL_TYPE(rela->r_info)) { + case BFR_X86_64_64: + *ptr += bfscast(bfelf64_addr, rela->r_addend); + break; + + case BFR_X86_64_GLOB_DAT: + case BFR_X86_64_JUMP_SLOT: + break; + + default: + return bfunsupported_rel(str); + } + + return BFELF_SUCCESS; +} + +/* @endcond */ diff --git a/payloads/bareflank/include/bferrorcodes.h b/payloads/bareflank/include/bferrorcodes.h new file mode 100644 index 00000000000..647a13a1d6b --- /dev/null +++ b/payloads/bareflank/include/bferrorcodes.h @@ -0,0 +1,174 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFERROR_CODES_H +#define BFERROR_CODES_H + +#include + +/* -------------------------------------------------------------------------- */ +/* Success */ +/* -------------------------------------------------------------------------- */ + +#define SUCCESS 0 + +/* -------------------------------------------------------------------------- */ +/* Entry Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define ENTRY_SUCCESS bfscast(int64_t, SUCCESS) +#define ENTRY_ERROR_STACK_OVERFLOW bfscast(int64_t, 0x8000000000000010) +#define ENTRY_ERROR_VMM_INIT_FAILED bfscast(int64_t, 0x8000000000000020) +#define ENTRY_ERROR_VMM_START_FAILED bfscast(int64_t, 0x8000000000000030) +#define ENTRY_ERROR_VMM_STOP_FAILED bfscast(int64_t, 0x8000000000000040) +#define ENTRY_ERROR_UNKNOWN bfscast(int64_t, 0x8000000000000050) + +/* -------------------------------------------------------------------------- */ +/* C Runtime Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define CRT_SUCCESS bfscast(int64_t, SUCCESS) +#define CRT_FAILURE bfscast(int64_t, 0x8000000000000100) + +/* -------------------------------------------------------------------------- */ +/* Unwinder Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define REGISTER_EH_FRAME_SUCCESS bfscast(int64_t, SUCCESS) +#define REGISTER_EH_FRAME_FAILURE bfscast(int64_t, 0x8000000000001000) + +/* -------------------------------------------------------------------------- */ +/* Debug Ring Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define GET_DRR_SUCCESS bfscast(int64_t, SUCCESS) +#define GET_DRR_FAILURE bfscast(int64_t, 0x8000000000010000) + +/* -------------------------------------------------------------------------- */ +/* ELF Loader Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define BFELF_SUCCESS bfscast(int64_t, SUCCESS) +#define BFELF_ERROR_INVALID_ARG bfscast(int64_t, 0x8000000000100000) +#define BFELF_ERROR_INVALID_FILE bfscast(int64_t, 0x8000000000200000) +#define BFELF_ERROR_INVALID_INDEX bfscast(int64_t, 0x8000000000300000) +#define BFELF_ERROR_INVALID_SIGNATURE bfscast(int64_t, 0x8000000000500000) +#define BFELF_ERROR_UNSUPPORTED_FILE bfscast(int64_t, 0x8000000000600000) +#define BFELF_ERROR_INVALID_SEGMENT bfscast(int64_t, 0x8000000000700000) +#define BFELF_ERROR_INVALID_SECTION bfscast(int64_t, 0x8000000000800000) +#define BFELF_ERROR_LOADER_FULL bfscast(int64_t, 0x8000000000900000) +#define BFELF_ERROR_NO_SUCH_SYMBOL bfscast(int64_t, 0x8000000000A00000) +#define BFELF_ERROR_MISMATCH bfscast(int64_t, 0x8000000000B00000) +#define BFELF_ERROR_UNSUPPORTED_RELA bfscast(int64_t, 0x8000000000C00000) +#define BFELF_ERROR_OUT_OF_ORDER bfscast(int64_t, 0x8000000000D00000) +#define BFELF_ERROR_OUT_OF_MEMORY bfscast(int64_t, 0x8000000000E00000) + +/* -------------------------------------------------------------------------- */ +/* Memory Manager Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define MEMORY_MANAGER_SUCCESS bfscast(int64_t, SUCCESS) +#define MEMORY_MANAGER_FAILURE bfscast(int64_t, 0x8000000001000000) + +/* -------------------------------------------------------------------------- */ +/* Common Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define BF_SUCCESS bfscast(int64_t, SUCCESS) +#define BF_ERROR_INVALID_ARG bfscast(int64_t, 0x8000000010000000) +#define BF_ERROR_INVALID_INDEX bfscast(int64_t, 0x8000000020000000) +#define BF_ERROR_NO_MODULES_ADDED bfscast(int64_t, 0x8000000030000000) +#define BF_ERROR_MAX_MODULES_REACHED bfscast(int64_t, 0x8000000040000000) +#define BF_ERROR_VMM_INVALID_STATE bfscast(int64_t, 0x8000000050000000) +#define BF_ERROR_FAILED_TO_ADD_FILE bfscast(int64_t, 0x8000000060000000) +#define BF_ERROR_FAILED_TO_DUMP_DR bfscast(int64_t, 0x8000000070000000) +#define BF_ERROR_OUT_OF_MEMORY bfscast(int64_t, 0x8000000080000000) +#define BF_ERROR_VMM_CORRUPTED bfscast(int64_t, 0x8000000090000000) +#define BF_ERROR_UNKNOWN bfscast(int64_t, 0x80000000A0000000) + +/* -------------------------------------------------------------------------- */ +/* IOCTL Error Codes */ +/* -------------------------------------------------------------------------- */ + +#define BF_IOCTL_SUCCESS bfscast(int64_t, SUCCESS) +#define BF_IOCTL_FAILURE bfscast(int64_t, -1) + +/* -------------------------------------------------------------------------- */ +/* Bad Alloc */ +/* -------------------------------------------------------------------------- */ + +#define BF_BAD_ALLOC bfscast(int64_t, 0x8000000100000000) + +/* -------------------------------------------------------------------------- */ +/* VMCall */ +/* -------------------------------------------------------------------------- */ + +#define BF_VMCALL_SUCCESS bfscast(int64_t, SUCCESS) +#define BF_VMCALL_FAILURE bfscast(int64_t, 0x8000001000000000) + +/* -------------------------------------------------------------------------- */ +/* Stringify Error Codes */ +/* -------------------------------------------------------------------------- */ + +static inline const char * +ec_to_str(int64_t value) +{ + switch (value) { + case SUCCESS: return "SUCCESS"; + case ENTRY_ERROR_STACK_OVERFLOW: return "ENTRY_ERROR_STACK_OVERFLOW"; + case ENTRY_ERROR_VMM_INIT_FAILED: return "ENTRY_ERROR_VMM_INIT_FAILED"; + case ENTRY_ERROR_VMM_START_FAILED: return "ENTRY_ERROR_VMM_START_FAILED"; + case ENTRY_ERROR_VMM_STOP_FAILED: return "ENTRY_ERROR_VMM_STOP_FAILED"; + case ENTRY_ERROR_UNKNOWN: return "ENTRY_ERROR_UNKNOWN"; + case CRT_FAILURE: return "CRT_FAILURE"; + case REGISTER_EH_FRAME_FAILURE: return "REGISTER_EH_FRAME_FAILURE"; + case GET_DRR_FAILURE: return "GET_DRR_FAILURE"; + case MEMORY_MANAGER_FAILURE: return "MEMORY_MANAGER_FAILURE"; + case BFELF_ERROR_INVALID_ARG: return "BFELF_ERROR_INVALID_ARG"; + case BFELF_ERROR_INVALID_FILE: return "BFELF_ERROR_INVALID_FILE"; + case BFELF_ERROR_INVALID_INDEX: return "BFELF_ERROR_INVALID_INDEX"; + case BFELF_ERROR_INVALID_SIGNATURE: return "BFELF_ERROR_INVALID_SIGNATURE"; + case BFELF_ERROR_UNSUPPORTED_FILE: return "BFELF_ERROR_UNSUPPORTED_FILE"; + case BFELF_ERROR_INVALID_SEGMENT: return "BFELF_ERROR_INVALID_SEGMENT"; + case BFELF_ERROR_INVALID_SECTION: return "BFELF_ERROR_INVALID_SECTION"; + case BFELF_ERROR_LOADER_FULL: return "BFELF_ERROR_LOADER_FULL"; + case BFELF_ERROR_NO_SUCH_SYMBOL: return "BFELF_ERROR_NO_SUCH_SYMBOL"; + case BFELF_ERROR_MISMATCH: return "BFELF_ERROR_MISMATCH"; + case BFELF_ERROR_UNSUPPORTED_RELA: return "BFELF_ERROR_UNSUPPORTED_RELA"; + case BFELF_ERROR_OUT_OF_ORDER: return "BFELF_ERROR_OUT_OF_ORDER"; + case BFELF_ERROR_OUT_OF_MEMORY: return "BFELF_ERROR_OUT_OF_MEMORY"; + case BF_ERROR_INVALID_ARG: return "BF_ERROR_INVALID_ARG"; + case BF_ERROR_INVALID_INDEX: return "BF_ERROR_INVALID_INDEX"; + case BF_ERROR_NO_MODULES_ADDED: return "BF_ERROR_NO_MODULES_ADDED"; + case BF_ERROR_MAX_MODULES_REACHED: return "BF_ERROR_MAX_MODULES_REACHED"; + case BF_ERROR_VMM_INVALID_STATE: return "BF_ERROR_VMM_INVALID_STATE"; + case BF_ERROR_FAILED_TO_ADD_FILE: return "BF_ERROR_FAILED_TO_ADD_FILE"; + case BF_ERROR_FAILED_TO_DUMP_DR: return "BF_ERROR_FAILED_TO_DUMP_DR"; + case BF_ERROR_OUT_OF_MEMORY: return "BF_ERROR_OUT_OF_MEMORY"; + case BF_ERROR_VMM_CORRUPTED: return "BF_ERROR_VMM_CORRUPTED"; + case BF_ERROR_UNKNOWN: return "BF_ERROR_UNKNOWN"; + case BF_BAD_ALLOC: return "BF_BAD_ALLOC"; + case BF_IOCTL_FAILURE: return "BF_IOCTL_FAILURE"; + + default: + return "UNDEFINED_ERROR_CODE"; + } +} + +#endif diff --git a/payloads/bareflank/include/bfexception.h b/payloads/bareflank/include/bfexception.h new file mode 100755 index 00000000000..0e7f12794fc --- /dev/null +++ b/payloads/bareflank/include/bfexception.h @@ -0,0 +1,144 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfexception.h +/// + +#ifndef BFEXCEPTION_H +#define BFEXCEPTION_H + +#include +#include + +#include +#include +#include + +/// Guard Exceptions +/// +/// Catches all exceptions and prints the exception that occurred. The point of +/// this function is to prevent any exception from bubbling beyond this point. +/// +/// @expects +/// @ensures +/// +/// @param error_code an error code to return if an exception occurs +/// @param func the function to run that is guarded +/// @param error_func the function to run when an exception occurs +/// @return error_code on failure, SUCCESS on success +/// +template < + typename FUNC, + typename ERROR_FUNC, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +int64_t +guard_exceptions(int64_t error_code, FUNC func, ERROR_FUNC error_func) +{ + try { + func(); + return SUCCESS; + } + catch (std::bad_alloc &) { + error_func(); + return BF_BAD_ALLOC; + } + catch (std::exception &e) { + bfdebug_transaction(0, [&](std::string * msg) { + bferror_lnbr(0, msg); + bferror_brk1(0, msg); + bferror_info(0, typeid(e).name(), msg); + bferror_brk1(0, msg); + bferror_info(0, e.what(), msg); + }); + } + catch (...) { + bfdebug_transaction(0, [&](std::string * msg) { + bferror_lnbr(0, msg); + bferror_brk1(0, msg); + bferror_info(0, "unknown exception", msg); + bferror_brk1(0, msg); + }); + } + + error_func(); + return error_code; +} + +/// Guard Exceptions +/// +/// Catches all exceptions and prints the exception that occurred. The point of +/// this function is to prevent any exception from bubbling beyond this point. +/// +/// @expects +/// @ensures +/// +/// @param error_code an error code to return if an exception occurs +/// @param func the function to run that is guarded +/// @return error_code on failure, SUCCESS on success +/// +template < + typename FUNC, + typename = std::enable_if::value> + > +int64_t +guard_exceptions(int64_t error_code, FUNC && func) +{ return guard_exceptions(error_code, std::forward(func), [] {}); } + +/// Guard Exceptions +/// +/// Catches all exceptions and prints the exception that occurred. The point of +/// this function is to prevent any exception from bubbling beyond this point. +/// +/// @expects +/// @ensures +/// +/// @param func the function to run that is guarded +/// +template < + typename FUNC, + typename = std::enable_if::value> + > +void +guard_exceptions(FUNC && func) +{ guard_exceptions(0L, std::forward(func), [] {}); } + +/// Guard Exceptions +/// +/// Catches all exceptions and prints the exception that occurred. The point of +/// this function is to prevent any exception from bubbling beyond this point. +/// +/// @expects +/// @ensures +/// +/// @param func the function to run that is guarded +/// @param error_func the function to run when an exception occurs +/// +template < + typename FUNC, + typename ERROR_FUNC, + typename = std::enable_if::value>, + typename = std::enable_if::value> + > +void +guard_exceptions(FUNC && func, ERROR_FUNC && error_func) +{ guard_exceptions(0L, std::forward(func), std::forward(error_func)); } + +#endif diff --git a/payloads/bareflank/include/bfexports.h b/payloads/bareflank/include/bfexports.h new file mode 100644 index 00000000000..1cc48ccce0f --- /dev/null +++ b/payloads/bareflank/include/bfexports.h @@ -0,0 +1,37 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFEXPORTS_H +#define BFEXPORTS_H + +#if defined(_WIN32) || defined(__CYGWIN__) +#define IMPORT_SYM __declspec(dllimport) +#define EXPORT_SYM __declspec(dllexport) +#else +#define IMPORT_SYM +#define EXPORT_SYM __attribute__ ((visibility ("default"))) +#endif + +#if defined(_WIN32) || defined(__CYGWIN__) +#define WEAK_SYM +#else +#define WEAK_SYM __attribute__((weak)) +#endif + +#endif diff --git a/payloads/bareflank/include/bffile.h b/payloads/bareflank/include/bffile.h new file mode 100644 index 00000000000..57a9e0939de --- /dev/null +++ b/payloads/bareflank/include/bffile.h @@ -0,0 +1,345 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bffile.h +/// + +#ifndef BFFILE_H +#define BFFILE_H + +#include + +#include +#include +#include + +#include +#include +#include +#include + +/// File +/// +/// This class is responsible for working with a file. Specifically, this +/// class wraps calls to ifstream and fstream to simplify their interface +/// as well as provide an implementation for the rest of the Bareflank +/// Manager, such that testing is easier. +/// +class file +{ +public: + + using text_data = std::string; ///< File format for text data + using binary_data = bfn::buffer; ///< File format for binary data + using filename_type = std::string; ///< File name type + using extension_type = std::string; ///< Extension name type + using path_list_type = std::vector; ///< Find files path type + using filesize_type = std::size_t; ///< File size type + + /// File Constructor + /// + /// @expects none + /// @ensures none + /// + /// Creates a file class that can be used to working with files. + /// + file() noexcept = default; + + /// File Destructor + /// + /// @expects none + /// @ensures none + /// + VIRTUAL ~file() noexcept = default; + + /// Read + /// + /// Reads the entire contents of a file, in text form + /// + /// @expects filename.empty() == false + /// @ensures none + /// + /// @param filename name of the file to read. + /// @return the contents of filename + /// + /// optimization notes: + /// - http://insanecoding.blogspot.it/2011/11/how-to-read-in-file-in-c.html + /// - since std::string has to initialize the backing array, reading in + /// a binary will always be faster. Thus, use read_binary if possible + /// + VIRTUAL text_data + read_text(const filename_type &filename) const + { + expects(!filename.empty()); + + std::fstream handle(filename, std::ios_base::in | std::ios_base::binary); + if (handle) { + + handle.seekg(0, std::ios::end); + auto size = handle.tellg(); + + if (size <= 0) { + return text_data{}; + } + + handle.seekg(0, std::ios::beg); + text_data buffer(static_cast(size), 0); + + handle.read(&buffer.front(), size); + return buffer; + } + + throw std::runtime_error("invalid filename: " + filename); + } + + /// Read + /// + /// Reads the entire contents of a file, in binary form + /// + /// @expects filename.empty() == false + /// @ensures none + /// + /// @param filename name of the file to read. + /// @return the contents of filename + /// + /// optimization notes: + /// - http://insanecoding.blogspot.it/2011/11/how-to-read-in-file-in-c.html + /// + VIRTUAL binary_data + read_binary(const filename_type &filename) const + { + expects(!filename.empty()); + + std::fstream handle(filename, std::ios_base::in | std::ios_base::binary); + if (handle) { + + handle.seekg(0, std::ios::end); + auto size = handle.tellg(); + + if (size <= 0) { + return binary_data{}; + } + + handle.seekg(0, std::ios::beg); + binary_data buffer(static_cast(size)); + + handle.read(buffer.data(), size); + return buffer; + } + + throw std::runtime_error("invalid filename: " + filename); + } + + /// Write + /// + /// Writes text data to the file provided + /// + /// @expects filename.empty() == false + /// @expects buffer.empty() == false + /// @ensures none + /// + /// @param filename name of the file to write to. + /// @param buffer data to write + /// + VIRTUAL void + write_text(const filename_type &filename, const text_data &buffer) const + { + expects(!filename.empty()); + + std::fstream handle(filename, std::ios_base::out | std::ios_base::binary); + if (handle) { + handle.write(buffer.data(), static_cast(buffer.size())); + return; + } + + throw std::runtime_error("invalid filename: " + filename); + } + + /// Write + /// + /// Writes binary data to the file provided + /// + /// @expects filename.empty() == false + /// @expects buffer.empty() == false + /// @ensures none + /// + /// @param filename name of the file to write to. + /// @param buffer data to write + /// + VIRTUAL void + write_binary(const filename_type &filename, const binary_data &buffer) const + { + expects(!filename.empty()); + + std::fstream handle(filename, std::ios_base::out | std::ios_base::binary); + if (handle) { + handle.write(buffer.data(), static_cast(buffer.size())); + return; + } + + throw std::runtime_error("invalid filename: " + filename); + } + + /// Get File Extension + /// + /// @expects none + /// @ensures none + /// + /// @param filename the file name to extract the extension + /// @return the filename's extension + /// + VIRTUAL extension_type + extension(const filename_type &filename) const + { + if (filename.empty()) { + return {}; + } + + auto index = filename.find_last_of('.'); + + if (index != filename_type::npos) { + return filename.substr(index); + } + + return {}; + } + + /// File Exists + /// + /// @expects none + /// @ensures none + /// + /// @param filename the file name to check + /// @return true if the file exists, false otherwise + /// + VIRTUAL bool + exists(const filename_type &filename) const + { + std::ifstream handle{filename}; + return handle.good(); + } + + /// File Size + /// + /// @expects filename.empty() == false + /// @ensures none + /// + /// @param filename to get the size of + /// @return size of filename + /// + VIRTUAL filesize_type + size(const filename_type &filename) const + { + expects(!filename.empty()); + + std::fstream handle(filename, std::ios_base::in | std::ios_base::binary); + if (handle) { + handle.seekg(0, std::ios::end); + return static_cast(handle.tellg()); + } + + throw std::runtime_error("invalid filename: " + filename); + } + + /// Find Files + /// + /// Loops through all of the provided files and file paths and + /// returns a list of each filename combined with the path and the filename + /// that was first found. If a filename cannot be found, an exception is + /// thrown. + /// + /// @note we use the '/' separator on both Windows and POSIX. The reason + /// is both support '/' for the versions we support. + /// + /// @expects files.empty() == false + /// @expects paths.empty() == false + /// @ensures ret: path_list_type.size() == files.size() + /// + /// @param files list of files to locate in the list of provided paths + /// @param paths list of paths to search for the provided list of files + /// @return pull paths for each file located, throws otherwise + /// + VIRTUAL path_list_type + find_files(const path_list_type &files, const path_list_type &paths) const + { + expects(!paths.empty()); + path_list_type results; + + for (const auto &filename : files) { + auto found = false; + + for (auto path : paths) { + path += '/'; + path += filename; + + if (exists(path)) { + results.push_back(path); + + found = true; + break; + } + } + + if (!found) { + throw std::runtime_error("unable to locate file: " + filename); + } + } + + return results; + } + + /// Get Home Directory + /// + /// @expects none + /// @expects none + /// + /// @return returns home directory + /// + VIRTUAL std::string + home() const + { + char *home; + + home = std::getenv("HOME"); + if (home != nullptr) { + return {home}; + } + + home = std::getenv("HOMEPATH"); + if (home != nullptr) { + return {home}; + } + + throw std::runtime_error("HOME or HOMEPATH not set"); + } + +public: + + /// @cond + + file(file &&) noexcept = default; + file &operator=(file &&) noexcept = default; + + file(const file &) = default; + file &operator=(const file &) = default; + + /// @endcond +}; + +#endif diff --git a/payloads/bareflank/include/bfgsl.h b/payloads/bareflank/include/bfgsl.h new file mode 100644 index 00000000000..4e8ee400ee2 --- /dev/null +++ b/payloads/bareflank/include/bfgsl.h @@ -0,0 +1,282 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfgsl.h +/// + +#ifndef BFGSL_H +#define BFGSL_H + +#if defined(__clang__) || defined(__GNUC__) +#pragma GCC system_header +#endif + +#include + +/// @cond + +#define concat1(a,b) a ## b +#define concat2(a,b) concat1(a,b) +#define ___ concat2(dont_care, __COUNTER__) + +/// @endcond + +#ifndef NEED_GSL_LITE + +#include + +namespace gsl +{ + +/// @cond + +#define expects(cond) Expects(cond) +#define ensures(cond) Ensures(cond) + +template +class final_act_success +{ +public: + explicit final_act_success(F f) noexcept : f_(std::move(f)), invoke_(true) {} + + final_act_success(final_act_success &&other) noexcept : f_(std::move(other.f_)), invoke_(other.invoke_) + { + other.invoke_ = false; + } + + final_act_success(const final_act_success &) = delete; + final_act_success &operator=(const final_act_success &) = delete; + + ~final_act_success() noexcept + { + if (std::uncaught_exception()) { + return; + } + + if (invoke_) { f_(); } + } + +private: + F f_; + bool invoke_; +}; + +template +class final_act_failure +{ +public: + explicit final_act_failure(F f) noexcept : f_(std::move(f)), invoke_(true) {} + + final_act_failure(final_act_failure &&other) noexcept : f_(std::move(other.f_)), invoke_(other.invoke_) + { + other.invoke_ = false; + } + + final_act_failure(const final_act_failure &) = delete; + final_act_failure &operator=(const final_act_failure &) = delete; + + ~final_act_failure() noexcept + { + if (!std::uncaught_exception()) { + return; + } + + if (invoke_) { f_(); } + } + +private: + F f_; + bool invoke_; +}; + +template +inline final_act_success on_success(const F &f) noexcept +{ + return final_act_success(f); +} + +template +inline final_act_success on_success(F &&f) noexcept +{ + return final_act_success(std::forward(f)); +} + +template +inline final_act_failure on_failure(const F &f) noexcept +{ + return final_act_failure(f); +} + +template +inline final_act_failure on_failure(F &&f) noexcept +{ + return final_act_failure(std::forward(f)); +} + +/// @endcond + +/// Memset +/// +/// Same as std::memset, but for spans +/// +/// @param dst The span to memset +/// @param val The value to set the span to +/// @return Returns dst +/// +template +auto memset(span dst, T val) +{ + expects(dst.size() > 0); + + return std::memset( + dst.data(), + static_cast(val), + static_cast(dst.size()) + ); +} + +} + +#else + +#ifdef NEED_STD_LITE +#include +#endif + +/// @cond + +#if defined(__clang__) || defined(__GNUC__) +#define gsl_likely(x) __builtin_expect(!!(x), 1) +#define gsl_unlikely(x) __builtin_expect(!!(x), 0) +#else +#define gsl_likely(x) (x) +#define gsl_unlikely(x) (x) +#endif + +#ifndef GSL_ABORT +#define GSL_ABORT abort +#endif + +#define expects(cond) \ + if (gsl_unlikely(!(cond))) { \ + GSL_ABORT(); \ + } +#define ensures(cond) \ + if (gsl_unlikely(!(cond))) { \ + GSL_ABORT(); \ + } + +/// @endcond + +namespace gsl +{ + +/// Narrow Cast +/// +/// A rename of static_cast to indicate a narrow (e.g. 64bit to 32bit) +/// +/// @param u the value to narrow +/// @return static_cast(u) +/// +template +inline constexpr T +narrow_cast(U &&u) noexcept +{ + return static_cast(std::forward(u)); +} + +/// At +/// +/// Returns a reference to an element in an array given an index. Unlike +/// the [] operator, if the indexis out-of-bounds, an exception is thrown, +/// or std::terminate() is called. +/// +/// @param arr the array +/// @param index the index of the element to retrieve. +/// @return a reference to +/// +template +constexpr T & +at(T(&arr)[N], I index) +{ + expects(index >= 0 && index < narrow_cast(N)); + return arr[static_cast(index)]; +} + +/// At +/// +/// Returns a reference to an element in an array given an index. Unlike +/// the [] operator, if the indexis out-of-bounds, an exception is thrown, +/// or std::terminate() is called. +/// +/// @param arr the array +/// @param index the index of the element to retrieve. +/// @return a reference to +/// +template +const constexpr T & +at(const T(&arr)[N], I index) +{ + expects(index >= 0 && index < narrow_cast(N)); + return arr[static_cast(index)]; +} + +/// At +/// +/// Returns a reference to an element in an array given an index. Unlike +/// the [] operator, if the indexis out-of-bounds, an exception is thrown, +/// or std::terminate() is called. +/// +/// @param arr the array +/// @param N the size of the array +/// @param index the index of the element to retrieve. +/// @return a reference to +/// +template +constexpr T & +at(T *arr, size_t N, I index) +{ + expects(index >= 0 && index < narrow_cast(N)); + return arr[static_cast(index)]; +} + +/// At +/// +/// Returns a reference to an element in an array given an index. Unlike +/// the [] operator, if the indexis out-of-bounds, an exception is thrown, +/// or std::terminate() is called. +/// +/// @param arr the array +/// @param N the size of the array +/// @param index the index of the element to retrieve. +/// @return a reference to +/// +template +const constexpr T & +at(const T *arr, size_t N, I index) +{ + expects(index >= 0 && index < narrow_cast(N)); + return arr[static_cast(index)]; +} + +} + +#endif + +#endif diff --git a/payloads/bareflank/include/bfjson.h b/payloads/bareflank/include/bfjson.h new file mode 100644 index 00000000000..62e4a9a393d --- /dev/null +++ b/payloads/bareflank/include/bfjson.h @@ -0,0 +1,113 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULLAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfjson.h +/// + +#ifndef BFJSON_H +#define BFJSON_H + +#include + +#include +using json = nlohmann::json; ///< Simply namespace + +/// JSON Hex or Dec +/// +/// Converts a JSON object's field to T. The field name can either be "" +/// or "_hex". If "_hex" is added to the field name, the value is +/// interpreted as a hex string, other wise it's interpreted as a dec number. +/// +/// @expects none +/// @ensures none +/// +/// @param obj the json object +/// @param field the field name +/// @return returns the converted number or throws +/// +template < + typename T, + typename J, + typename = std::enable_if::value> + > +auto +json_hex_or_dec(const J &obj, const std::string &field) +{ + auto val_hex = obj.value(field + "_hex", json(nullptr)); + + if (val_hex.is_string()) { + return gsl::narrow_cast(std::stoull(val_hex.template get(), 0, 16)); + } + + auto val_dec = obj.at(field); + + if (val_dec.is_number()) { + return gsl::narrow_cast(val_dec.template get()); + } + + throw std::runtime_error("json is neither a hex or dec"); +} + +/// JSON Hex or Dec Array +/// +/// Converts a JSON object's field to [T]. The field name can either be +/// "" or "_hex". If "_hex" is added to the field name, each value +/// is interpreted as a hex string, other wise they are interpreted as a dec +/// number. +/// +/// @expects none +/// @ensures none +/// +/// @param obj the json object +/// @param field the field name +/// @return returns std::vector with the converted numbers or throws +/// +template < + typename T, + typename J, + typename = std::enable_if::value> + > +auto +json_hex_or_dec_array(const J &obj, const std::string &field) +{ + std::vector result; + auto array_hex = obj.value(field + "_hex", json(nullptr)); + + if (array_hex.is_array()) { + for (auto val : array_hex) { + result.push_back(gsl::narrow_cast(std::stoull(val.template get(), 0, 16))); + } + + return result; + } + + auto array_dec = obj.at(field); + + if (array_dec.is_array()) { + for (auto val : array_dec) { + result.push_back(gsl::narrow_cast(val.template get())); + } + + return result; + } + + throw std::runtime_error("json is neither a hex or dec"); +} + +#endif diff --git a/payloads/bareflank/include/bfmanager.h b/payloads/bareflank/include/bfmanager.h new file mode 100644 index 00000000000..3e4f5a0716d --- /dev/null +++ b/payloads/bareflank/include/bfmanager.h @@ -0,0 +1,198 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +#ifndef BFMANAGER_H +#define BFMANAGER_H + +#include +#include +#include + +#include +#include + +/// Manager +/// +/// A generic class for creating, destroying, running and stopping T given a +/// T_factory to actually instantiate T, and a tid to identify which T to +/// interact with. +/// +template +class bfmanager +{ +public: + + /// Destructor + /// + /// @expects none + /// @ensures none + /// + ~bfmanager() = default; + + /// Get Singleton Instance + /// + /// @expects none + /// @ensures ret != nullptr + /// + /// @return a singleton instance of bfmanager + /// + static bfmanager *instance() noexcept + { + static bfmanager self; + return &self; + } + + /// Create T + /// + /// Creates T. Note that the T is actually created by the + /// T factory's make_t function. + /// + /// @expects none + /// @ensures none + /// + /// @param id the t to initialize + /// @param obj object that can be passed around as needed + /// by extensions of Bareflank + /// + void create(tid id, bfobject *obj = nullptr) + { + auto ___ = gsl::on_failure([&] { + std::lock_guard guard(m_mutex); + m_ts.erase(id); + }); + + if (auto &&t = add_t(id, obj)) { + t->init(obj); + } + } + + /// Destroy T + /// + /// Deletes T. + /// + /// @param id the t to destroy + /// @param obj object that can be passed around as needed + /// by extensions of Bareflank + /// + void destroy(tid id, bfobject *obj = nullptr) + { + auto ___ = gsl::finally([&] { + std::lock_guard guard(m_mutex); + m_ts.erase(id); + }); + + if (auto &&t = get_t(id)) { + t->fini(obj); + } + } + + /// Run T + /// + /// Executes T. + /// + /// @expects t exists + /// @ensures none + /// + /// @param id the t to run + /// @param obj object that can be passed around as needed + /// by extensions of Bareflank + /// + void run(tid id, bfobject *obj = nullptr) + { + if (auto &&t = get_t(id)) { + t->run(obj); + } + } + + /// Halt T + /// + /// Halts T. + /// + /// @expects none + /// @ensures none + /// + /// @param id the t to halt + /// @param obj object that can be passed around as needed + /// by extensions of Bareflank + /// + void hlt(tid id, bfobject *obj = nullptr) + { + if (auto &&t = get_t(id)) { + t->hlt(obj); + } + } + + /// Set Factory + /// + /// Should only be used by unit tests + /// + /// @expects none + /// @ensures none + /// + /// @param factory the new factory to use + /// + void set_factory(std::unique_ptr factory) + { m_T_factory = std::move(factory); } + +private: + + bfmanager() noexcept : + m_T_factory(std::make_unique()) + { } + + std::unique_ptr &add_t(tid id, bfobject *obj) + { + if (auto &&t = get_t(id)) { + return t; + } + + if (auto t = m_T_factory->make(id, obj)) { + std::lock_guard guard(m_mutex); + return m_ts[id] = std::move(t); + } + + throw std::runtime_error("make returned a nullptr"); + } + + std::unique_ptr &get_t(tid id) + { + std::lock_guard guard(m_mutex); + return m_ts[id]; + } + +private: + + std::unique_ptr m_T_factory; + std::map> m_ts; + + mutable std::mutex m_mutex; + +public: + + /// @cond + + bfmanager(bfmanager &&) noexcept = delete; + bfmanager &operator=(bfmanager &&) noexcept = delete; + + bfmanager(const bfmanager &) = delete; + bfmanager &operator=(const bfmanager &) = delete; + + /// @endcond +}; + +#endif diff --git a/payloads/bareflank/include/bfmemory.h b/payloads/bareflank/include/bfmemory.h new file mode 100644 index 00000000000..49d39029a03 --- /dev/null +++ b/payloads/bareflank/include/bfmemory.h @@ -0,0 +1,75 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfmemory.h + */ + +#ifndef BFMEMORY_H +#define BFMEMORY_H + +#include +#include +#include + +#pragma pack(push, 1) + +#ifdef __cplusplus +extern "C" { +#endif + +/* @cond */ + +#define MEMORY_TYPE_R 0x1U +#define MEMORY_TYPE_W 0x2U +#define MEMORY_TYPE_E 0x4U + +/* @endcond */ + +/** + * @struct memory_descriptor + * + * Memory Descriptor + * + * A memory descriptor provides information about a block of memory. + * Typically, each page of memory that the VMM uses will have a memory + * descriptor associated with it. The VMM will use this information to create + * its resources, as well as generate page tables as needed. + * + * @var memory_descriptor::phys + * the starting physical address of the block of memory + * @var memory_descriptor::virt + * the starting virtual address of the block of memory + * @var memory_descriptor::type + * the type of memory block. This is likely architecture specific as + * this holds information about access rights, etc... + */ +struct memory_descriptor { + uint64_t phys; + uint64_t virt; + uint64_t type; +}; + +#ifdef __cplusplus +} +#endif + +#pragma pack(pop) + +#endif diff --git a/payloads/bareflank/include/bfobject.h b/payloads/bareflank/include/bfobject.h new file mode 100644 index 00000000000..295c5fe25ab --- /dev/null +++ b/payloads/bareflank/include/bfobject.h @@ -0,0 +1,57 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfobject.h +/// + +#ifndef BFOBJECT_H +#define BFOBJECT_H + +/// User Data +/// +/// This defines the base class used for passing around subclasses. +/// This is mainly used so that dynamic_cast can be used if desired +/// for casting and deletion. +/// +class bfobject +{ +public: + + /// Default Constructor + /// + bfobject() = default; + + /// Default Destructor + /// + virtual ~bfobject() = default; + +public: + + /// @cond + + bfobject(bfobject &&) noexcept = delete; + bfobject &operator=(bfobject &&) noexcept = delete; + + bfobject(const bfobject &) = delete; + bfobject &operator=(const bfobject &) = delete; + + /// @endcond +}; + +#endif diff --git a/payloads/bareflank/include/bfplatform.h b/payloads/bareflank/include/bfplatform.h new file mode 100755 index 00000000000..657622734f1 --- /dev/null +++ b/payloads/bareflank/include/bfplatform.h @@ -0,0 +1,177 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfplatform.h + */ + +#ifndef BFPLATFORM_H +#define BFPLATFORM_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initalize Platform Logic + * + * @expects none + * @ensures none + * + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t platform_init(void); + +/** + * Allocate Memory + * + * @expects none + * @ensures none + * + * @note: If this function is used in userspace, it must be assumed that free() + * can be used to free this memory. In the kernel, it can be assumed that + * platform_free_rw is used instead, which provides the length field. + * + * @param len the size of memory to allocate in bytes. + * @return returns the address of the newly allocated memory + */ +void *platform_alloc_rw(uint64_t len); + +/** + * Allocate Executable Memory + * + * @expects none + * @ensures none + * + * @note: memory allocated from this function must be 4k aligned. If this + * function is used in userspace, it must be assumed that free() can be + * used to free this memory. In the kernel, it can be assumed that + * platform_free_rwe is used instead, which provides the length field. + * + * @param len the size of memory to allocate in bytes. + * @return returns the address of the newly allocated, executable memory + */ +void *platform_alloc_rwe(uint64_t len); + +/** + * Free Memory + * + * @expects none + * @ensures none + * + * @param addr the address of memory allocated using platform_alloc_rw + * @param len the size of the memory allocated using platform_alloc_rw + */ +void platform_free_rw(const void *addr, uint64_t len); + +/** + * Free Executable Memory + * + * @expects none + * @ensures none + * + * @param addr the address of memory allocated using platform_alloc_rwe + * @param len the size of the memory allocated using platform_alloc_rwe + */ +void platform_free_rwe(const void *addr, uint64_t len); + +/** + * Convert Virtual Address to Physical Address + * + * @expects none + * @ensures none + * + * @param virt the virtual address to convert + * @return the physical address associated with the provided virtual address + */ +void *platform_virt_to_phys(void *virt); + +/** + * Memset + * + * @expects none + * @ensures none + * + * @param ptr a pointer to the memory to set + * @param value the value to set each byte to + * @param num the number of bytes to set + */ +void *platform_memset(void *ptr, char value, uint64_t num); + +/** + * Memcpy + * + * @expects none + * @ensures none + * + * @param dst a pointer to the memory to copy to + * @param src a pointer to the memory to copy from + * @param num the number of bytes to copy + */ +void *platform_memcpy(void *dst, const void *src, uint64_t num); + +/** + * Get Number of CPUs + * + * @expects none + * @ensures none + * + * @return returns the total number of CPUs available. + */ +int64_t platform_num_cpus(void); + +/** + * Call VMM on Core + * + * Executes the VMM. The VMM has a single entry point, with a switch statement + * that executes the provided "request". When this occurs, arg1 and arg2 are + * provided to the requested function. Note that the first arg takes a cpuid, + * which is the core number want to execute the VMM on. If a -1 is provided, + * the currently executing core will be used. + * + * @param cpuid the core id this code is to be execute on + * @param request the requested function in the VMM to execute + * @param arg1 arg #1 + * @param arg2 arg #2 + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t platform_call_vmm_on_core( + uint64_t cpuid, uint64_t request, uintptr_t arg1, uintptr_t arg2); + +/** + * Get RSDP + * + * Returns the address of the Root System Description Pointer for ACPI. + * If ACPI is not supported, return 0. + * + * @expects none + * @ensures none + * + * @return returns the RSDP or 0 if ACPI is not supported + */ +void *platform_get_rsdp(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/payloads/bareflank/include/bfshuffle.h b/payloads/bareflank/include/bfshuffle.h new file mode 100644 index 00000000000..bda3fc27971 --- /dev/null +++ b/payloads/bareflank/include/bfshuffle.h @@ -0,0 +1,49 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfshuffle.h +/// + +#ifndef BFSHUFFLE_H +#define BFSHUFFLE_H + +#include +#include +#include + +namespace bfn +{ + +/// Shuffle Vector +/// +/// @expects none +/// @ensures none +/// +/// @param list the vector to shuffle +/// +template void +shuffle(std::vector &list) +{ + std::random_device rd; + std::shuffle(list.begin(), list.end(), std::mt19937{rd()}); +} + +} + +#endif diff --git a/payloads/bareflank/include/bfstd.h b/payloads/bareflank/include/bfstd.h new file mode 100644 index 00000000000..eea919d3188 --- /dev/null +++ b/payloads/bareflank/include/bfstd.h @@ -0,0 +1,118 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfstd.h +/// + +#ifndef BFSTD_H +#define BFSTD_H + +#if defined(__clang__) || defined(__GNUC__) +#pragma GCC system_header +#endif + +#include +#include + +// Note: +// +// This file exists for code that cannot include libc++ +// + +namespace std +{ +/// Remove Reference +/// +/// Returns T regardless of lvalue / rvalue type +/// +template struct remove_reference { + typedef T type; ///< Type T +}; + +/// Remove Reference +/// +/// Returns T regardless of lvalue / rvalue type +/// +template struct remove_reference { + typedef T type; ///< Type T +}; + +/// Remove Reference +/// +/// Returns T regardless of lvalue / rvalue type +/// +template struct remove_reference < T && > { + typedef T type; ///< Type T +}; + +/// Forward +/// +/// Preserves lvalue / rvalue reference +/// +/// @param t the object to be forwarded +/// @return static_cast(t) +/// +template +constexpr T && +forward(typename std::remove_reference::type &t) noexcept +{ + return static_cast < T && >(t); +} + +/// Forward +/// +/// Preserves lvalue / rvalue reference +/// +/// @param t the object to be forwarded +/// @return static_cast(t) +/// +template +constexpr T && +forward(typename std::remove_reference::type &&t) noexcept +{ + return static_cast < T && >(t); +} + +/// Move +/// +/// Produces a rvalue reference +/// +/// @param t the object to be moved +/// @return static_cast::type&&>(t) +/// +template +constexpr typename std::remove_reference::type && +move(T &&t) noexcept +{ + return static_cast < typename std::remove_reference::type && >(t); +} + +/// Terminate +/// +/// A C++ wrapper around C's abort(). +/// +[[noreturn]] inline void +terminate() noexcept +{ + printf("FATAL ERROR: std::terminate() called!!!\n"); + abort(); +} +} + +#endif diff --git a/payloads/bareflank/include/bfstring.h b/payloads/bareflank/include/bfstring.h new file mode 100644 index 00000000000..4212fcdcd1e --- /dev/null +++ b/payloads/bareflank/include/bfstring.h @@ -0,0 +1,142 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfstring.h +/// + +#ifndef BFSTRING_H +#define BFSTRING_H + +#include +#include +#include +#include +#include + +/// std::string literal +/// +/// @param str string to convert to std::string +/// @param len len of str +/// @return std::string(str, len) +/// +inline auto operator""_s(const char *str, std::size_t len) +{ + return std::string(str, len); +} + +namespace bfn +{ + +/// Convert to String (with base) +/// +/// Same thing as std::to_string, but adds the ability to state the base for +/// conversion. +/// +/// @expects none +/// @ensures none +/// +/// @param val the value to convert +/// @param base the base for conversion. +/// @return string version of val converted to the provided base +/// +template < + typename T, + typename = std::enable_if::value> + > +std::string +to_string(const T val, const int base) +{ + // TODO: + // + // C++17 has a new set of functions that called to_chars which gets rid + // of the allocation. We should use this in the VMM when compiled with + // our cross compiler. When not compiled with our cross compiler, we + // should use this code to emulate it so that we do not need C++17 on all + // systems. This optimization would reduce the debugging code to just + // page allocations as needed which is ideal + // + + std::stringstream stream; + + switch (base) { + case 16: + stream << std::setfill('0') << std::setw(18) << std::internal; + break; + + default: + break; + }; + + stream << std::setbase(base) << std::showbase << val; + return stream.str(); +} + +/// Split String +/// +/// Splits a string into a string vector based on a provided +/// delimiter +/// +/// @expects none +/// @ensures none +/// +/// @param str the string to split +/// @param delimiter the delimiter to split the string with +/// @return std::vector version of str, split using delimiter +/// +inline std::vector +split(const std::string &str, char delimiter) +{ + std::istringstream ss{str}; + std::vector result; + + while (!ss.eof()) { + std::string field; + std::getline(ss, field, delimiter); + + result.push_back(field); + } + + return result; +} + +/// Split String +/// +/// Splits a string into a string vector based on a provided +/// delimiter +/// +/// @expects none +/// @ensures none +/// +/// @param str the string to split +/// @param delimiter the delimiter to split the string with +/// @return std::vector version of str, split using delimiter +/// +inline std::vector +split(const char *str, char delimiter) +{ + if (str == nullptr) { + return {}; + } + + return split(std::string(str), delimiter); +} + +} + +#endif diff --git a/payloads/bareflank/include/bfsupport.h b/payloads/bareflank/include/bfsupport.h new file mode 100755 index 00000000000..496e114ed31 --- /dev/null +++ b/payloads/bareflank/include/bfsupport.h @@ -0,0 +1,196 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfsupport.h + */ + +#ifndef BFSUPPORT_H +#define BFSUPPORT_H + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @struct section_info_t + * + * Provides information about the ELF file that is used to init/fini the + * file. + * + * @var section_info_t::init_addr + * the virtual address of ".init" after relocation + * @var section_info_t::fini_addr + * the virtual address of ".fini" after relocation + * @var section_info_t::init_array_addr + * the virtual address of ".init_array" after relocation + * @var section_info_t::init_array_size + * the size of ".init_array" + * @var section_info_t::fini_array_addr + * the virtual address of ".fini_array" after relocation + * @var section_info_t::fini_array_size + * the size of ".fini_array" + * @var section_info_t::eh_frame_addr + * the virtual address of ".eh_frame" after relocation + * @var section_info_t::eh_frame_size + * the size of ".eh_frame" + * @var section_info_t::debug_info_addr + * the virtual address of ".debug_info" after relocation + * @var section_info_t::debug_info_size + * the size of ".debug_info" + * @var section_info_t::debug_abbrev_addr + * the virtual address of ".debug_abbrev" after relocation + * @var section_info_t::debug_abbrev_size + * the size of ".debug_abbrev" + * @var section_info_t::debug_line_addr + * the virtual address of ".debug_line" after relocation + * @var section_info_t::debug_line_size + * the size of ".debug_line" + * @var section_info_t::debug_str_addr + * the virtual address of ".debug_str" after relocation + * @var section_info_t::debug_str_size + * the size of ".debug_str" + * @var section_info_t::debug_ranges_addr + * the virtual address of ".debug_ranges" after relocation + * @var section_info_t::debug_ranges_size + * the size of ".debug_ranges" + */ +struct section_info_t { + void *init_addr; + void *fini_addr; + + void *init_array_addr; + uint64_t init_array_size; + + void *fini_array_addr; + uint64_t fini_array_size; + + void *eh_frame_addr; + uint64_t eh_frame_size; + + void *debug_info_addr; + uint64_t debug_info_size; + + void *debug_abbrev_addr; + uint64_t debug_abbrev_size; + + void *debug_line_addr; + uint64_t debug_line_size; + + void *debug_str_addr; + uint64_t debug_str_size; + + void *debug_ranges_addr; + uint64_t debug_ranges_size; +}; + +/** + * @struct crt_info_t + * + * Provides information for executing an application including section + * information, the program break and arguments. + * + * @var crt_info_t::arg_type + * 0 = argc/argv, 1 == arg#, undefined otherwise + * @var crt_info_t::argc + * the number of arguments + * @var crt_info_t::argv + * the arguments +* @var crt_info_t::request + * - + * @var crt_info_t::arg1 + * integer argument #1 + * @var crt_info_t::arg2 + * integer argument #2 + * @var crt_info_t::arg3 + * integer argument #3 + * @var crt_info_t::info_num + * the number of modules + * @var crt_info_t::info + * the section info for each module + * @var crt_info_t::func + * (optional) function to call + * @var crt_info_t::vcpuid + * (optional) vcpuid the executable is running on + * @var crt_info_t::program_break + * (optional) the executable's program break + */ +struct crt_info_t { + + int arg_type; + + int argc; + const char **argv; + + uintptr_t request; + uintptr_t arg1; + uintptr_t arg2; + uintptr_t arg3; + + int info_num; + struct section_info_t info[MAX_NUM_MODULES]; + + uintptr_t func; + uintptr_t vcpuid; + uintptr_t program_break; +}; + +/** + * Request IDs + * + * The following defines the different types of requests that can be made + * when calling bfmain instead of main. Note that these are simply the + * currently defined requests, users can add to this as needed. + * + * @cond + */ + +#define BF_REQUEST_INIT 0 +#define BF_REQUEST_FINI 1 +#define BF_REQUEST_VMM_INIT 2 +#define BF_REQUEST_VMM_FINI 3 +#define BF_REQUEST_ADD_MDL 4 +#define BF_REQUEST_GET_DRR 5 +#define BF_REQUEST_SET_RSDP 6 +#define BF_REQUEST_END 0xFFFF + +/* @endcond */ + +/** + * Start + * + * Defines the function signature for the _start function + */ +#ifdef __cplusplus +using _start_t = int64_t (*)(char *stack, const struct crt_info_t *); +#else +typedef int64_t (*_start_t)(char *stack, const struct crt_info_t *); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/payloads/bareflank/include/bfthreadcontext.h b/payloads/bareflank/include/bfthreadcontext.h new file mode 100644 index 00000000000..3fa562e92bd --- /dev/null +++ b/payloads/bareflank/include/bfthreadcontext.h @@ -0,0 +1,115 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file bfthreadcontext.h + */ + +#ifndef BFTHREADCONTEXT +#define BFTHREADCONTEXT + +#include +#include + +#pragma pack(push, 1) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Return CPUID + * + * @return returns the CPUID for the currently executing thread + */ +uint64_t thread_context_cpuid(void); + +/** + * Return TLS data + * + * @return returns the TLS data for the currently executing thread + */ +uint64_t *thread_context_tlsptr(void); + +/** + * @struct thread_context_t + * + * Thread Context + * + * On the top of every stack pointer sits one of these structures, which is + * used to identify thread specific information. For more information on + * how this works, please see the following post: + * + * https://github.com/Bareflank/hypervisor/issues/213 + * + * Note: If this struct changes, assembly code in the misc module will + * likely have to change as well since we don't have a clean way to bridge + * between C and NASM + * + * @var thread_context_t::cpuid + * the cpuid of the thread + * @var thread_context_t::tlsptr + * the TLS pointer of the thread + * @var thread_context_t::reserved1 + * reserved + * @var thread_context_t::reserved2 + * reserved + */ +struct thread_context_t { + uint64_t cpuid; + uint64_t *tlsptr; + uint64_t reserved1; + uint64_t reserved2; +}; + +/** + * Setup Stack + * + * The following function sets up the stack to match the algorithm defined + * in the following issue: + * + * https://github.com/Bareflank/hypervisor/issues/213 + * + * @param stack the stack pointer + * @return the stack pointer (in interger form) + */ +static inline uint64_t +setup_stack(void *stack) +{ + struct thread_context_t *tc; + uint64_t stack_int = bfrcast(uint64_t, stack); + + uint64_t stack_top = stack_int + (STACK_SIZE * 2); + stack_top = (stack_top & ~(STACK_SIZE - 1)) - 1; + stack_int = stack_top - sizeof(struct thread_context_t) - 1; + + tc = bfrcast(struct thread_context_t *, stack_top - sizeof(struct thread_context_t)); + tc->cpuid = thread_context_cpuid(); + tc->tlsptr = thread_context_tlsptr(); + + return stack_int; +} + +#ifdef __cplusplus +} +#endif + +#pragma pack(pop) + +#endif diff --git a/payloads/bareflank/include/bftypes.h b/payloads/bareflank/include/bftypes.h new file mode 100644 index 00000000000..13d0671b8c0 --- /dev/null +++ b/payloads/bareflank/include/bftypes.h @@ -0,0 +1,138 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BFTYPES_H +#define BFTYPES_H + +/* -------------------------------------------------------------------------- */ +/* Helper Macros */ +/* -------------------------------------------------------------------------- */ + +#ifdef __cplusplus +#define bfscast(a, b) (static_cast(b)) +#else +#define bfscast(a, b) ((a)(b)) +#endif + +#ifdef __cplusplus +#define bfrcast(a, b) (reinterpret_cast(b)) +#else +#define bfrcast(a, b) ((a)(b)) +#endif + +#ifdef __cplusplus +#define bfadd(a, b, c) (reinterpret_cast(reinterpret_cast(b) + (c))) +#else +#define bfadd(a, b, c) ((a)((char *)(b) + (c))) +#endif + +#ifdef __cplusplus +#define bfcadd(a, b, c) (reinterpret_cast(reinterpret_cast(b) + (c))) +#else +#define bfcadd(a, b, c) ((a)((const char *)(b) + (c))) +#endif + +#define bfignored(a) (void)a + +/* -------------------------------------------------------------------------- */ +/* Stringify */ +/* -------------------------------------------------------------------------- */ + +#define bfstringify(a) __bfstringify(a) +#define __bfstringify(a) #a + +/* -------------------------------------------------------------------------- */ +/* NULL */ +/* -------------------------------------------------------------------------- */ + +#if !defined(__cplusplus) && !defined(nullptr) +#define nullptr 0 +#endif + +/* -------------------------------------------------------------------------- */ +/* Debug */ +/* -------------------------------------------------------------------------- */ + +#ifdef NDEBUG +#define ndebug 1 +#else +#define ndebug 0 +#endif + +/* -------------------------------------------------------------------------- */ +/* Testing */ +/* -------------------------------------------------------------------------- */ + +#ifdef ENABLE_BUILD_TEST +#define VIRTUAL virtual +#else +#define VIRTUAL +#endif + +/* -------------------------------------------------------------------------- */ +/* Userspace */ +/* -------------------------------------------------------------------------- */ + +#if !defined(KERNEL) && !defined(_WIN32) +#if defined(__cplusplus) && __has_include("cstdint") +#include +#else +#include +#endif +#endif + +/* -------------------------------------------------------------------------- */ +/* Linux Types */ +/* -------------------------------------------------------------------------- */ + +#if defined(KERNEL) && defined(__linux__) +#include +#define PRId64 "lld" +#endif + +/* -------------------------------------------------------------------------- */ +/* Windows Types */ +/* -------------------------------------------------------------------------- */ + +#if defined(_WIN32) +#include +typedef INT8 int8_t; +typedef INT16 int16_t; +typedef INT32 int32_t; +typedef INT64 int64_t; +typedef UINT8 uint8_t; +typedef UINT16 uint16_t; +typedef UINT32 uint32_t; +typedef UINT64 uint64_t; +typedef UINT_PTR uintptr_t; +typedef INT_PTR intptr_t; +#define PRId64 "lld" +#endif + +/* -------------------------------------------------------------------------- */ +/* EFI Types */ +/* -------------------------------------------------------------------------- */ + +#if defined(KERNEL) && defined(EFI) +#include "efi.h" +#include "efilib.h" +#define PRId64 "lld" +#endif + +#endif diff --git a/payloads/bareflank/include/bfupperlower.h b/payloads/bareflank/include/bfupperlower.h new file mode 100644 index 00000000000..dd7161bd565 --- /dev/null +++ b/payloads/bareflank/include/bfupperlower.h @@ -0,0 +1,146 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfupperlower.h +/// + +#ifndef BFUPPERLOWER_H +#define BFUPPERLOWER_H + +#include +#include + +namespace bfn +{ + +/// Lower +/// +/// @param val the pointer to mask +/// @return the lower 12 bits of val +/// +template < + typename T, + typename = std::enable_if::value> + > +auto +lower(T val) noexcept +{ + return static_cast(static_cast(val) & (0xFFFULL)); +} + +/// Lower +/// +/// @param val the pointer to mask +/// @return the lower 12 bits of val +/// +template +auto +lower(T *val) noexcept +{ + return reinterpret_cast(reinterpret_cast(val) & (0xFFFULL)); +} + +/// Lower +/// +/// @param val the pointer to mask +/// @param from the number of bits to mask +/// @return the lower "from" bits of val +/// +template < + typename T, + typename = std::enable_if::value> + > +auto +lower(T val, uintptr_t from) noexcept +{ + return static_cast(static_cast(val) & ((0x1ULL << from) - 1)); +} + +/// Lower +/// +/// @param val the pointer to mask +/// @param from the number of bits to mask +/// @return the lower "from" bits of val +/// +template +auto +lower(T *val, uintptr_t from) noexcept +{ + return reinterpret_cast(reinterpret_cast(val) & ((0x1ULL << from) - 1)); +} + +/// Upper +/// +/// @param val the pointer to mask +/// @return the upper 12 bits of val +/// +template < + typename T, + typename = std::enable_if::value> + > +auto +upper(T val) noexcept +{ + return static_cast(static_cast(val) & ~(0xFFFULL)); +} + +/// Upper +/// +/// @param val the pointer to mask +/// @return the upper 12 bits of val +/// +template +auto +upper(T *val) noexcept +{ + return reinterpret_cast(reinterpret_cast(val) & ~(0xFFFULL)); +} + +/// Upper +/// +/// @param val the pointer to mask +/// @param from the number of bits to mask +/// @return the upper "from" bits of val +/// +template < + typename T, + typename = std::enable_if::value> + > +auto +upper(T val, uintptr_t from) noexcept +{ + return static_cast(static_cast(val) & ~((0x1ULL << from) - 1)); +} + +/// Upper +/// +/// @param val the pointer to mask +/// @param from the number of bits to mask +/// @return the upper "from" bits of val +/// +template +auto +upper(T *val, uintptr_t from) noexcept +{ + return reinterpret_cast(reinterpret_cast(val) & ~((0x1ULL << from) - 1)); +} + +} + +#endif diff --git a/payloads/bareflank/include/bfvcpuid.h b/payloads/bareflank/include/bfvcpuid.h new file mode 100644 index 00000000000..23e7f8cf89b --- /dev/null +++ b/payloads/bareflank/include/bfvcpuid.h @@ -0,0 +1,64 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +#ifndef BFVCPUID_H +#define BFVCPUID_H + +#include + +// *INDENT-OFF* + +namespace vcpuid +{ + using type = uint64_t; + + constexpr const auto reserved = 0x8000000000000000UL; + + constexpr const auto invalid = 0xFFFFFFFFFFFFFFFFUL; + constexpr const auto current = 0xFFFFFFFFFFFFFFF0UL; + + constexpr const auto guest_mask = 0xFFFFFFFFFFFF0000UL; + constexpr const auto guest_from = 16; + + /// Is Bootstrap vCPU + /// + /// @expects none + /// @ensures none + /// + /// @param id the id to check + /// @return true if this vCPU is the bootstrap vCPU, false otherwise + /// + constexpr inline bool is_bootstrap_vcpu(type id) + { return id == 0; } + + /// Is Host VM vCPU + /// + /// @expects none + /// @ensures none + /// + /// @param id the id to check + /// @return true if this vCPU belongs to the host VM, false otherwise + /// + constexpr inline bool is_hvm_vcpu(type id) + { return (id & (vcpuid::guest_mask & ~vcpuid::reserved)) == 0; } + +} + +// *INDENT-ON* + +#endif diff --git a/payloads/bareflank/include/bfvector.h b/payloads/bareflank/include/bfvector.h new file mode 100644 index 00000000000..7e76f28828f --- /dev/null +++ b/payloads/bareflank/include/bfvector.h @@ -0,0 +1,140 @@ +// +// Bareflank Hypervisor +// Copyright (C) 2015 Assured Information Security, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/// +/// @file bfvector.h +/// + +#ifndef BFVECTOR +#define BFVECTOR + +#include +#include + +namespace bfn +{ + +/// Find +/// +/// Get the iterator from the provided vector, given an index. +/// +/// @expects index >= 0 +/// @expects index < v.size() +/// @ensures ret != v.end() +/// +/// @param v std::vector to get iterator from +/// @param index the iterator to locate +/// @return returns the iterator at pos == index, or throws gsl::fail_fast +/// +template < + typename T, + typename A + > +auto +find(std::vector &v, const std::ptrdiff_t index) +{ + // [[ensures ret: ret != v.end()]] + expects(index >= 0 && index < gsl::narrow_cast(v.size())); + + return v.begin() + index; +} + +/// Find (const) +/// +/// Get the iterator from the provided vector, given an index. +/// +/// @expects index >= 0 +/// @expects index < v.size() +/// @ensures ret != v.end() +/// +/// @param v std::vector to get iterator from +/// @param index the iterator to locate +/// @return returns the iterator at pos == index, or throws gsl::fail_fast +/// +template < + typename T, + typename A + > +auto +cfind(const std::vector &v, const std::ptrdiff_t index) +{ + // [[ensures ret: ret != v.end()]] + expects(index >= 0 && index < gsl::narrow_cast(v.size())); + + return v.cbegin() + index; +} + +/// Remove +/// +/// Removes an element from the provided vector. This function uses +/// std::vector::erase, and thus, all iterators are invalidated after this +/// function call is made. +/// +/// @expects index >= 0 +/// @expects index < v.size() +/// @ensures +/// +/// @param v std::vector to get iterator from +/// @param index the iterator to locate +/// +template < + typename T, + typename A, + typename I, + typename = std::enable_if::value> + > +void +remove(std::vector &v, const I index) +{ + v.erase(cfind(v, index)); +} + +/// Take +/// +/// Takes an element from the provided vector. This function uses +/// std::vector::erase, and thus, all iterators are invalidated after this +/// function call is made. +/// +/// @expects index >= 0 +/// @expects index < v.size() +/// @ensures +/// +/// @param v std::vector to get iterator from +/// @param index the iterator to locate +/// @return returns the element that was removed +/// +template < + typename T, + typename A, + typename I, + typename = std::enable_if::value> + > +auto +take(std::vector &v, const I index) +{ + const auto iter = cfind(v, index); + auto val = *iter; + + v.erase(iter); + + return val; +} + +} + +#endif diff --git a/payloads/bareflank/include/common.h b/payloads/bareflank/include/common.h new file mode 100644 index 00000000000..f0d314ec60b --- /dev/null +++ b/payloads/bareflank/include/common.h @@ -0,0 +1,176 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef COMMON_H +#define COMMON_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * VMM Status + * + * @return returns the current status of the VMM. + */ +int64_t +common_vmm_status(void); + +/** + * Reset + * + * This function should not be called directly. Instead, use common_unload. + * This is only exposed publically for unit testing. + */ +void +common_reset(void); + +/** + * Initialize Driver Entry + * + * This code should be run as part of the driver entry's init code. This + * sets up some resources that are needed throughout the lifetime of the + * driver entry. + */ +int64_t +common_init(void); + +/** + * Finalize Driver Entry + * + * This code should be run as part of the driver entry's fini code. This + * cleans up some resources that were needed throughout the lifetime of the + * driver entry. + * + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_fini(void); + +/** + * Add Module + * + * Add's a module into memory to be executed once start_vmm is run. This + * function uses the platform functions to allocate memory for the executable. + * The file that is provided should not be removed until after stop_vmm is + * run. Removing the file from memory could cause a crash, as the start_vmm + * function uses the file that is being added to search for symbols that are + * needed, as well as the stop_vmm function. Once stop_vmm is run, it's safe + * to remove the files. Also, this function cannot be run if the vmm has + * already been started. + * + * @param file the file to add to memory + * @param fsize the size of the file in bytes + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_add_module(const char *file, uint64_t fsize); + +/** + * Load VMM + * + * This function loads the vmm (assuming that the modules that were + * loaded are actually a vmm). Once a VMM is loaded, it is placed in memory, + * and all of the modules are properly reloacted such that, code within each + * module is now capable of executing. + * + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_load_vmm(void); + +/** + * Unload VMM + * + * This function unloads the vmm. Once the VMM is unloaded, all of the symbols + * for the VMM are removed from memory, and are no longer accessible. The VMM + * cannot be unloaded unless the VMM is already loaded, but is not running. + * + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_unload_vmm(void); + +/** + * Start VMM + * + * This function starts the vmm. Before the VMM can be started, it must first + * be loaded. + * + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_start_vmm(void); + +/** + * Stop VMM + * + * This function stops the vmm. Before a VMM can be stopped, it must first be + * loaded, and running. + * + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_stop_vmm(void); + +/** + * Dump VMM + * + * This grabs the conents of the debug ring, and dumps the contents to the + * driver entry's console. This is one of a couple of ways to get feedback + * from the VMM. Note that the VMM must at least be loaded for this function + * to work as it has to do a symbol lookup + * + * @param drr a pointer to the drr provided by the user + * @param vcpuid indicates which drr to get as each vcpu has its own drr + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_dump_vmm(struct debug_ring_resources_t **drr, uint64_t vcpuid); + +/** + * Call VMM + * + * Executes the VMM. The VMM has a single entry point, with a switch statement + * that executes the provided "request". When this occurs, arg1 and arg2 are + * provided to the requested function. Note that the first arg takes a cpuid, + * which is the core number you are currently executing on. This is needed + * because this function needs to set up the proper stack before executing + * the VMM, and it needs to know which core you are on to use the proper stack + * which in turn also executes with the proper TLS region. + * + * @param cpuid the core id this code is currently being executed on + * @param request the requested function in the VMM to execute + * @param arg1 arg #1 + * @param arg2 arg #2 + * @return BF_SUCCESS on success, negative error code on failure + */ +int64_t +common_call_vmm(uint64_t cpuid, uint64_t request, uintptr_t arg1, uintptr_t arg2); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/payloads/bareflank/platform.c b/payloads/bareflank/platform.c new file mode 100755 index 00000000000..27197fe55a9 --- /dev/null +++ b/payloads/bareflank/platform.c @@ -0,0 +1,86 @@ +/* + * Bareflank Hypervisor + * Copyright (C) 2015 Assured Information Security, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +#include +#include +#include + + +int platform_info_should_fail = 0; + +int64_t +platform_init(void) +{ return BF_SUCCESS; } + +void * +platform_alloc_rw(uint64_t len) +{ + return memalign(BAREFLANK_PAGE_SIZE, len); +} + +void * +platform_alloc_rwe(uint64_t len) +{ + return memalign(BAREFLANK_PAGE_SIZE, len); +} + +void +platform_free_rw(const void *addr, uint64_t len) +{ + bfignored(len); + free((void *)addr); +} + +void +platform_free_rwe(const void *addr, uint64_t len) +{ + bfignored(len); + free((void *)addr); +} + +void * +platform_virt_to_phys(void *virt) +{ return virt; } + +void * +platform_memset(void *ptr, char value, uint64_t num) +{ return memset(ptr, value, num); } + +void * +platform_memcpy(void *dst, const void *src, uint64_t num) +{ return memcpy(dst, src, num); } + +int64_t +platform_num_cpus(void) +{ return 1; } + +int64_t +platform_call_vmm_on_core( + uint64_t cpuid, uint64_t request, uintptr_t arg1, uintptr_t arg2) +{ + return common_call_vmm(cpuid, request, arg1, arg2); +} + +void * +platform_get_rsdp(void) +{ return 0; } diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index ff042af65d8..3060161fe03 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -103,15 +103,10 @@ static void show_config_space(WINDOW *win, int row, int col, int index) static int pci_module_redraw(WINDOW *win) { unsigned int bus, slot, func; - int i, last; + int i; print_module_title(win, "PCI Device List"); - last = menu_first + MENU_VISIBLE; - - if (last > devices_index) - last = devices_index; - for (i = 0; i < MENU_VISIBLE; i++) { int item = menu_first + i; diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index ccf62b82371..84af49ccc0a 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -123,7 +123,7 @@ config LINUXBOOT_KERNEL_CONFIGFILE Note: this can be a defconfig file or a complete .config file. -choice LINUXBOOT_KERNEL_FORMAT +choice prompt "Kernel binary format" default LINUXBOOT_KERNEL_BZIMAGE if LINUXBOOT_X86 || LINUXBOOT_X86_64 default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 5632a0b9231..e32ad1e21be 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## +SHELL := /bin/bash ARCH-$(CONFIG_LINUXBOOT_X86_64)=x86_64 ARCH-$(CONFIG_LINUXBOOT_X86)=x86 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5edbb81b187..902454e731a 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -47,6 +47,17 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))),) ADDITIONAL_PAYLOAD_CONFIG+=$(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))) endif +ifeq ($(CONFIG_BAREFLANK_SECONDARY_PAYLOAD),y) +cbfs-files-y += $(CONFIG_CBFS_PREFIX)/realpayload +$(CONFIG_CBFS_PREFIX)/realpayload-file := $(CONFIG_PAYLOAD_FILE) +ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) +$(CONFIG_CBFS_PREFIX)/realpayload-type := flat-binary +else +$(CONFIG_CBFS_PREFIX)/realpayload-type := payload +endif +$(CONFIG_CBFS_PREFIX)/realpayload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG) +$(CONFIG_CBFS_PREFIX)/realpayload-options := $(ADDITIONAL_PAYLOAD_CONFIG) +else cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload $(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) @@ -56,6 +67,7 @@ $(CONFIG_CBFS_PREFIX)/payload-type := payload endif $(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG) $(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG) +endif cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_config payload_config-file := $(PAYLOAD_CONFIG) @@ -229,7 +241,9 @@ endif ifeq ($(CONFIG_BUILD_IPXE),y) PXE_ROM_FILE:=payloads/external/iPXE/ipxe/ipxe.rom endif - +ifeq ($(CONFIG_PXE_ADD_SCRIPT),y) +PXE_CONFIG_SCRIPT:=$(abspath $(patsubst "%",%,$(CONFIG_PXE_SCRIPT))) +endif ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) IPXE_UART=COM$(call int-add,$(CONFIG_UART_FOR_CONSOLE) 1) endif @@ -244,7 +258,7 @@ cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE) pci$(CONFIG_PXE_ROM_ID).rom-type := raw -payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) +payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT) $(MAKE) -C payloads/external/iPXE all \ CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \ PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ @@ -253,6 +267,9 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \ IPXE_UART=$(IPXE_UART) \ CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \ + CONFIG_SCRIPT=$(PXE_CONFIG_SCRIPT) \ + CONFIG_HAS_SCRIPT=$(CONFIG_PXE_ADD_SCRIPT) \ + CONFIG_PXE_NO_PROMT=$(CONFIG_PXE_NO_PROMT) \ MFLAGS= MAKEFLAGS= # LinuxBoot diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c6b76..fd05c0c12a5 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=a698c8995ffb2838296ec284fe3c4ad33dfca307 +TAG-$(CONFIG_SEABIOS_STABLE)=a5cab58e9a3fb6e168aba919c5669bea406573b4 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index 2afe1cd5e11..a2bc512395f 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -9,7 +9,7 @@ choice default UBOOT_STABLE config UBOOT_STABLE - bool "v2016.1" + bool "v2019.4" help Stable U-Boot version diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 67c60c15355..5cd89569d75 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -13,8 +13,8 @@ ## GNU General Public License for more details. ## -# 2016-1 tag -STABLE_COMMIT_ID=fa85e826c16b9ce1ad302a57e9c4b24db0d8b930 +# 2019-4 tag +STABLE_COMMIT_ID=3c99166441bf3ea325af2da83cfe65430b49c066 TAG-$(CONFIG_UBOOT_MASTER)=origin/master TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID) @@ -30,6 +30,7 @@ unexport KCONFIG_DEPENDENCIES unexport KCONFIG_SPLITCONFIG unexport KCONFIG_TRISTATE unexport KCONFIG_NEGATIVES +unexport $(COREBOOT_EXPORTS) all: build @@ -50,11 +51,11 @@ else touch $(project_dir)/$(STABLE_COMMIT_ID) endif -$(project_dir)/tag-$(TAG-y): fetch +checkout: fetch echo " Checking out $(project_name) revision $(TAG-y)" cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) -config: $(project_dir)/$(TAG-y) +config: checkout rm -f $(project_config_file) ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),) ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","") @@ -64,7 +65,7 @@ else false endif else - cat $(project_dir)/configs/coreboot-x86_defconfig >> $(project_config_file) + cat $(project_dir)/configs/coreboot_defconfig >> $(project_config_file) endif $(MAKE) -C $(project_dir) olddefconfig @@ -82,4 +83,4 @@ distclean: print-repo-info: echo "$(project_git_repo) $(project_dir)" -.PHONY: config build clean distclean fetch print-repo-info +.PHONY: checkout config build clean distclean fetch print-repo-info diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index ce0a7aea14e..7cb0d1e2497 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -42,12 +42,12 @@ choice depends on BUILD_IPXE config IPXE_STABLE - bool "2017.3" + bool "2019.3" help iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the 'stable' version. - This is iPXE from the end of March, 2017. + This is iPXE from the end of March, 2019. config IPXE_MASTER bool "master" @@ -87,5 +87,31 @@ config PXE_SERIAL_CONSOLE Unselect to let only SeaBIOS handle printing output. +config PXE_NO_PROMT + bool "Do not show prompt to boot from PXE" + default n + depends on BUILD_IPXE + help + Don't wait for the user to press Ctrl-B. + The PXE still can be run as it shows up in SeaBIOS's payload list. + +config PXE_ADD_SCRIPT + bool "Embed an iPXE script for automated provisioning" + depends on BUILD_IPXE + default n + help + Enable to embed a script that is run instead of an iPXE shell. + +config PXE_SCRIPT + string "Embedded iPXE script path and filename" + depends on PXE_ADD_SCRIPT + default "" + help + Path to a script that is embedded into the iPXE binary. + Example: startup.ipxe + + Uses the ipxe script instead showing the prompt: + "Press Ctrl-B to start iPXE..." + endmenu endif diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245ca5f..0c071fa13bb 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -13,9 +13,9 @@ ## GNU General Public License for more details. ## -# 2017.3 - Last commit of March 2017 +# 2019.3 - Last commit of March 2019 # When updating, change the name both here and in payloads/external/iPXE/Kconfig -STABLE_COMMIT_ID=fd6d1f4660a37d75acba1c64e2e5f137307bbc31 +STABLE_COMMIT_ID=ebf2eaf515e46abd43bc798e7e4ba77bfe529218 TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) @@ -54,15 +54,34 @@ ifeq ($(CONSOLE_SERIAL),yy) sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif +ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_PXE_NO_PROMT)),) + cp "$(project_dir)/src/config/general.h" "$(project_dir)/src/config/general.h.cb" +endif +ifeq ($(CONFIG_HAS_SCRIPT),y) + sed 's|//#define\s*IMAGE_SCRIPT.*|#define IMAGE_SCRIPT|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" + mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h" +endif +ifeq ($(CONFIG_PXE_NO_PROMT),y) + sed 's|#define\s*BANNER_TIMEOUT.*|#define BANNER_TIMEOUT 0|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" + mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h" +endif -build: config +build: config $(CONFIG_SCRIPT) +ifeq ($(CONFIG_HAS_SCRIPT),y) + echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)" + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) +else echo " MAKE $(project_name) $(TAG-y)" $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom +endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h" cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h" endif +ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_PXE_NO_PROMT)),) + cp "$(project_dir)/src/config/general.h.cb" "$(project_dir)/src/config/general.h" +endif clean: test -d $(project_dir) && $(MAKE) -C $(project_dir)/src veryclean || exit 0 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 5dce89ae6f2..03c5e52ee4a 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -109,6 +109,11 @@ config ARCH_X86 help Support the x86 architecture +config ARCH_X86_64 + bool "x86_64" + help + Support the x86_64 architecture + config ARCH_ARM64 bool "ARM64" help @@ -123,7 +128,7 @@ endchoice config MULTIBOOT bool "Multiboot header support" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_X86_64 default y if !CHROMEOS config HEAP_SIZE @@ -149,6 +154,7 @@ config BASE_ADDRESS default 0x80100000 if ARCH_ARM64 default 0x00000000 if ARCH_MIPS default 0x00100000 if ARCH_X86 + default 0x21000000 if ARCH_X86_64 help This is the base address for the payload. @@ -241,7 +247,7 @@ config SERIAL_CONSOLE config 8250_SERIAL_CONSOLE bool "8250-compatible serial port driver (including IO and MMIO)" depends on SERIAL_CONSOLE - default y if ARCH_X86 + default y if ARCH_X86 || ARCH_X86_64 config S5P_SERIAL_CONSOLE bool "Exynos SOC, S5P compatible serial port driver" @@ -258,6 +264,11 @@ config IPQ40XX_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config QCS405_SERIAL_CONSOLE + bool "QCS405 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE @@ -266,7 +277,7 @@ config PL011_SERIAL_CONSOLE config SERIAL_IOBASE ## This default is currently not used on non-x86 systems. hex "Default I/O base for the serial port (default 0x3f8)" - depends on SERIAL_CONSOLE && ARCH_X86 + depends on SERIAL_CONSOLE && (ARCH_X86 || ARCH_X86_64) default 0x3f8 config SERIAL_SET_SPEED @@ -299,12 +310,12 @@ config VIDEO_CONSOLE config VGA_VIDEO_CONSOLE bool "VGA video console driver" - depends on ARCH_X86 && VIDEO_CONSOLE + depends on (ARCH_X86 || ARCH_X86_64) && VIDEO_CONSOLE default y if !CHROMEOS config GEODELX_VIDEO_CONSOLE bool "Geode LX video console driver" - depends on ARCH_X86 && VIDEO_CONSOLE + depends on (ARCH_X86 || ARCH_X86_64) && VIDEO_CONSOLE default n config COREBOOT_VIDEO_CONSOLE @@ -334,14 +345,14 @@ config PC_I8042 config PC_MOUSE bool "Allow input from a PC mouse" default n if CHROMEOS - default y if ARCH_X86 # uses IO + default y if ARCH_X86 || ARCH_X86_64 # uses IO default n help PS/2 mouse driver on top of PC_I8042. config PC_KEYBOARD bool "Allow input from a PC keyboard" - default y if ARCH_X86 # uses IO + default y if ARCH_X86 || ARCH_X86_64 # uses IO default n config PC_KEYBOARD_IGNORE_INIT_FAILURE @@ -364,12 +375,12 @@ menu "Drivers" config PCI bool "Support for PCI devices" - depends on ARCH_X86 # for now + depends on ARCH_X86 || ARCH_X86_64 # for now default y config NVRAM bool "Support for reading/writing NVRAM bytes" - depends on ARCH_X86 # for now + depends on ARCH_X86 || ARCH_X86_64 # for now default y config MOUSE_CURSOR @@ -401,7 +412,7 @@ config RTC_PORT_EXTENDED_VIA config SPEAKER bool "Support for PC speaker" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_X86_64 default y if !CHROMEOS source "drivers/timer/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1a0acf1781b..891b0c41357 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -97,6 +97,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 +ARCHDIR-$(CONFIG_LP_ARCH_X86_64) := x86 ARCH-y := $(ARCHDIR-y) @@ -105,6 +106,7 @@ ARCH-y := $(ARCHDIR-y) ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_X86_64) := x86_64 ARCH-$(CONFIG_LP_ARCH_MIPS) := mips # Three cases where we don't need fully populated $(obj) lists: diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 7787762b43c..9f4de391116 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -35,6 +35,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 +ARCHDIR-$(CONFIG_LP_ARCH_X86_64) := x86 DESTDIR ?= install real-target: lib @@ -93,7 +94,7 @@ $(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o printf " CP $(subst $(CURDIR)/,,$(@))\n" cp $^ $@ -install: real-target +install: real-target arch/$(ARCHDIR-y)/libpayload.ldscript printf " INSTALL $(DESTDIR)/libpayload/lib\n" install -m 755 -d $(DESTDIR)/libpayload/lib for lib in $(library-targets); do \ diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index 129ff5f6821..4e6415f881a 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -27,7 +27,7 @@ ## SUCH DAMAGE. ## -if ARCH_X86 +if ARCH_X86 || ARCH_X86_64 config ARCH_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 0cc477399af..8b63fb77f26 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -27,16 +27,29 @@ ## SUCH DAMAGE. ## + +ifeq ($(CONFIG_LP_ARCH_X86_64),y) +# x64 needs at least 16-byte aligned stack (PSB=4) +CFLAGS += -mpreferred-stack-boundary=4 -mno-red-zone +else CFLAGS += -mpreferred-stack-boundary=2 +endif head.o-y += head.S + libc-y += main.c sysinfo.c libc-y += timer.c coreboot.c util.S -libc-y += exec.S virtual.c +libc-y += virtual.c libc-y += selfboot.c -libc-y += exception_asm.S exception.c +libc-y += exception.c libc-y += delay.c +ifeq ($(CONFIG_LP_ARCH_X86_64),y) +libc-y += exec64.S exception_asm64.S +else +libc-y += exec.S exception_asm.S +endif + # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed. libc-$(CONFIG_LP_GPL) += string.c @@ -48,3 +61,7 @@ libcbfs-$(CONFIG_LP_CBFS) += rom_media.c libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c libc-$(CONFIG_LP_ENABLE_APIC) += apic.c + +arch/$(ARCHDIR-y)/libpayload.ldscript: $(obj)/libpayload-config.h FORCE + gcc -E -x c -Iinclude -I$(obj) arch/$(ARCHDIR-y)/libpayload.ldscript.in | grep -v "^#" > arch/$(ARCHDIR-y)/libpayload.ldscript +FORCE: diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index db81ea1163b..d8db6052f7e 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -87,12 +87,12 @@ int apic_initialized(void) static inline uint32_t apic_read32(uint32_t offset) { - return read32((void *)(apic_bar + offset)); + return read32((void *)(size_t)(apic_bar + offset)); } static inline void apic_write32(uint32_t offset, uint32_t value) { - write32((void *)(apic_bar + offset), value); + write32((void *)(size_t)(apic_bar + offset), value); } uint8_t apic_id(void) @@ -204,6 +204,7 @@ static void apic_reset_all_lvts(void) { uint8_t max = apic_max_lvt_entries(); for (int i = 0; i <= max; ++i) { + if (i == 3) continue; // FIXME: LVT LINT0 Register (FEE0 0350H), hack for SeaBIOS uint32_t offset = APIC_LVT_TIMER + APIC_LVT_SIZE * i; apic_write32(offset, APIC_MASKED_BIT); } diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 13ff58ccbe4..2bac4aefa95 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -35,7 +35,7 @@ #define IF_FLAG (1 << 9) -u32 exception_stack[0x400] __attribute__((aligned(8))); +size_t exception_stack[0x400] __attribute__((aligned(8))); static interrupt_handler handlers[256]; @@ -61,9 +61,9 @@ static const char *names[EXC_COUNT] = { [EXC_SX] = "Security", }; -static void print_segment_error_code(u32 code) +static void print_segment_error_code(size_t code) { - printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1FFF); + printf("%#zx - descriptor %#zx in the ", code, (code >> 3) & 0x1FFF); if (code & (0x1 << 1)) { printf("IDT"); } else { @@ -78,9 +78,9 @@ static void print_segment_error_code(u32 code) printf(", internal to the CPU"); } -static void print_page_fault_error_code(u32 code) +static void print_page_fault_error_code(size_t code) { - printf("%#x -", code); + printf("%#zx -", code); if (code & (0x1 << 0)) printf(" page protection"); else @@ -99,22 +99,22 @@ static void print_page_fault_error_code(u32 code) printf(", instruction fetch"); } -static void print_raw_error_code(u32 code) +static void print_raw_error_code(size_t code) { - printf("%#x", code); + printf("%#zx", code); } static void dump_stack(uintptr_t addr, size_t bytes) { int i, j; - const int line = 8; - uint32_t *ptr = (uint32_t *)(addr & ~(line * sizeof(*ptr) - 1)); + const int line = 32 / sizeof(size_t); + size_t *ptr = (size_t *)(addr & ~(line * sizeof(*ptr) - 1)); printf("Dumping stack:\n"); for (i = bytes / sizeof(*ptr); i >= 0; i -= line) { printf("%p: ", ptr + i); for (j = i; j < i + line; j++) - printf("%08x ", *(ptr + j)); + printf("%0*zx ", (int)(2*sizeof(size_t)), *(ptr + j)); printf("\n"); } } @@ -144,28 +144,55 @@ static void dump_exception_state(void) break; } printf("\n"); - printf("EIP: 0x%08x\n", exception_state->regs.eip); - printf("CS: 0x%04x\n", exception_state->regs.cs); - printf("EFLAGS: 0x%08x\n", exception_state->regs.eflags); - printf("EAX: 0x%08x\n", exception_state->regs.eax); - printf("ECX: 0x%08x\n", exception_state->regs.ecx); - printf("EDX: 0x%08x\n", exception_state->regs.edx); - printf("EBX: 0x%08x\n", exception_state->regs.ebx); - printf("ESP: 0x%08x\n", exception_state->regs.esp); - printf("EBP: 0x%08x\n", exception_state->regs.ebp); - printf("ESI: 0x%08x\n", exception_state->regs.esi); - printf("EDI: 0x%08x\n", exception_state->regs.edi); - printf("DS: 0x%04x\n", exception_state->regs.ds); - printf("ES: 0x%04x\n", exception_state->regs.es); - printf("SS: 0x%04x\n", exception_state->regs.ss); - printf("FS: 0x%04x\n", exception_state->regs.fs); - printf("GS: 0x%04x\n", exception_state->regs.gs); +#if CONFIG(LP_ARCH_X86_64) + printf("RIP: 0x%016zx\n", exception_state->regs.rip); + printf("CS: 0x%04zx\n", exception_state->regs.cs); + printf("RFLAGS: 0x%016zx\n", exception_state->regs.rflags); + printf("RAX: 0x%016zx\n", exception_state->regs.rax); + printf("RCX: 0x%016zx\n", exception_state->regs.rcx); + printf("RDX: 0x%016zx\n", exception_state->regs.rdx); + printf("RBX: 0x%016zx\n", exception_state->regs.rbx); + printf("RSP: 0x%016zx\n", exception_state->regs.rsp); + printf("RBP: 0x%016zx\n", exception_state->regs.rbp); + printf("RSI: 0x%016zx\n", exception_state->regs.rsi); + printf("RDI: 0x%016zx\n", exception_state->regs.rdi); + printf("R8: 0x%016zx\n", exception_state->regs.r8); + printf("R9: 0x%016zx\n", exception_state->regs.r9); + printf("R10: 0x%016zx\n", exception_state->regs.r10); + printf("R11: 0x%016zx\n", exception_state->regs.r11); + printf("R12: 0x%016zx\n", exception_state->regs.r12); + printf("R13: 0x%016zx\n", exception_state->regs.r13); + printf("R14: 0x%016zx\n", exception_state->regs.r14); + printf("R15: 0x%016zx\n", exception_state->regs.r15); + printf("DS: 0x%04zx\n", exception_state->regs.ds); + printf("ES: 0x%04zx\n", exception_state->regs.es); + printf("SS: 0x%04zx\n", exception_state->regs.ss); + printf("FS: 0x%04zx\n", exception_state->regs.fs); + printf("GS: 0x%04zx\n", exception_state->regs.gs); +#else + printf("EIP: 0x%08zx\n", exception_state->regs.eip); + printf("CS: 0x%04zx\n", exception_state->regs.cs); + printf("EFLAGS: 0x%08zx\n", exception_state->regs.eflags); + printf("EAX: 0x%08zx\n", exception_state->regs.eax); + printf("ECX: 0x%08zx\n", exception_state->regs.ecx); + printf("EDX: 0x%08zx\n", exception_state->regs.edx); + printf("EBX: 0x%08zx\n", exception_state->regs.ebx); + printf("ESP: 0x%08zx\n", exception_state->regs.esp); + printf("EBP: 0x%08zx\n", exception_state->regs.ebp); + printf("ESI: 0x%08zx\n", exception_state->regs.esi); + printf("EDI: 0x%08zx\n", exception_state->regs.edi); + printf("DS: 0x%04zx\n", exception_state->regs.ds); + printf("ES: 0x%04zx\n", exception_state->regs.es); + printf("SS: 0x%04zx\n", exception_state->regs.ss); + printf("FS: 0x%04zx\n", exception_state->regs.fs); + printf("GS: 0x%04zx\n", exception_state->regs.gs); +#endif } void exception_dispatch(void) { die_if(exception_state->vector >= ARRAY_SIZE(handlers), - "Invalid vector %u\n", exception_state->vector); + "Invalid vector %zu\n", exception_state->vector); u8 vec = exception_state->vector; @@ -185,7 +212,11 @@ void exception_dispatch(void) vec); dump_exception_state(); +#if CONFIG(LP_ARCH_X86_64) + dump_stack(exception_state->regs.rsp, 1024); +#else dump_stack(exception_state->regs.esp, 512); +#endif /* We don't call apic_eoi because we don't want to ack the interrupt and allow another interrupt to wake the processor. */ halt(); @@ -207,14 +238,14 @@ void set_interrupt_handler(u8 vector, interrupt_handler handler) handlers[vector] = handler; } -static uint32_t eflags(void) +static size_t flags(void) { - uint32_t eflags; + size_t flags; asm volatile( "pushf\n\t" "pop %0\n\t" - : "=rm" (eflags)); - return eflags; + : "=rm" (flags)); + return flags; } void enable_interrupts(void) @@ -234,5 +265,5 @@ void disable_interrupts(void) int interrupts_enabled(void) { - return !!(eflags() & IF_FLAG); + return !!(flags() & IF_FLAG); } diff --git a/payloads/libpayload/arch/x86/exception_asm64.S b/payloads/libpayload/arch/x86/exception_asm64.S new file mode 100644 index 00000000000..a14742870a3 --- /dev/null +++ b/payloads/libpayload/arch/x86/exception_asm64.S @@ -0,0 +1,317 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + .align 16 + .global exception_stack_end +exception_stack_end: + .quad 0 + .global exception_state +exception_state: + .quad 0 + +/* Some temporary variables which are used while saving exception state. */ +vector: + .quad 0 +error_code: + .quad 0 +old_rsp: + .quad 0 +old_rax: + .quad 0 +old_rdx: + .quad 0 + + .align 16 + +.code64 + +/* + * Each exception vector has a small stub associated with it which sets aside + * the error code, if any, records which vector we entered from, and calls + * the common exception entry point. Some exceptions have error codes and some + * don't, so we have a macro for each type. + */ + + .macro stub num +exception_stub_\num: + movq $0, error_code + movq $\num, vector + jmp exception_common + .endm + + .macro stub_err num +exception_stub_\num: + popq error_code + movq $\num, vector + jmp exception_common + .endm + + .altmacro + .macro user_defined_stubs from, to + stub \from + .if \to-\from + user_defined_stubs %(from+1),\to + .endif + .endm + + stub 0 + stub 1 + stub 2 + stub 3 + stub 4 + stub 5 + stub 6 + stub 7 + stub_err 8 + stub 9 + stub_err 10 + stub_err 11 + stub_err 12 + stub_err 13 + stub_err 14 + stub 15 + stub 16 + stub_err 17 + stub 18 + stub 19 + stub 20 + stub 21 + stub 22 + stub 23 + stub 24 + stub 25 + stub 26 + stub 27 + stub 28 + stub 29 + stub_err 30 + stub 31 + /* Split the macro so we avoid a stack overflow. */ + user_defined_stubs 32, 63 + user_defined_stubs 64, 127 + user_defined_stubs 128, 191 + user_defined_stubs 192, 255 + +exception_common: + /* + * Save off the stack pointer and old eax value and install the + * exception stack. eax points to the old stack which has the + * exception ip, cs, and flags. + */ + movq %rax, old_rax + movq 24(%rsp), %rax + movq %rax, old_rsp + movq %rdx, old_rdx + movq %rsp, %rax + movq exception_stack_end, %rsp + + /* + * Push values onto the top of the exception stack to form an + * exception state structure. + */ + pushq vector + pushq error_code + mov %gs, %rdx + pushq %rdx + mov %fs, %rdx + pushq %rdx + mov %es, %rdx + pushq %rdx + mov %ds, %rdx + pushq %rdx + mov %ss, %rdx + pushq %rdx + pushq 8(%rax) + pushq 16(%rax) + pushq (%rax) + pushq %r15 + pushq %r14 + pushq %r13 + pushq %r12 + pushq %r11 + pushq %r10 + pushq %r9 + pushq %r8 + pushq %rdi + pushq %rsi + pushq %rbp + pushq old_rsp + pushq %rbx + pushq old_rdx + pushq %rcx + pushq old_rax + + /* + * Call the C exception handler. It will find the exception state + * using the exception_state global pointer. Not + * passing parameters means we don't have to worry about what ABI + * is being used. + */ + movq %rsp, exception_state + call exception_dispatch + + /* + * Restore state from the exception state structure, including any + * changes that might have been made. + */ + popq old_rax + popq %rcx + popq old_rdx + popq %rbx + popq old_rsp + + movq old_rsp, %rax + andq $~(0xf), %rax + subq $40, %rax + + popq %rbp + popq %rsi + popq %rdi + popq %r8 + popq %r9 + popq %r10 + popq %r11 + popq %r12 + popq %r13 + popq %r14 + popq %r15 + popq (%rax) + popq 16(%rax) + popq 8(%rax) + popq %rdx + mov %rdx, %ss + popq %rdx + mov %rdx, %ds + popq %rdx + mov %rdx, %es + popq %rdx + mov %rdx, %fs + popq %rdx + mov %rdx, %gs + + movq %rax, %rsp + movq old_rax, %rax + movq old_rdx, %rdx + + /* Return from the exception. */ + iretq + + /* + * Record the target and construct the actual entry at init time. This + * is necessary because the linker doesn't want to construct the entry + * for us. + */ + .macro interrupt_gate target + .quad \target + .quad \target + .endm + + .altmacro + .macro user_defined_gates from, to + interrupt_gate exception_stub_\from + .if \to-\from + user_defined_gates %(from+1),\to + .endif + .endm + + .align 8 + .global idt +idt: + interrupt_gate exception_stub_0 + interrupt_gate exception_stub_1 + interrupt_gate exception_stub_2 + interrupt_gate exception_stub_3 + interrupt_gate exception_stub_4 + interrupt_gate exception_stub_5 + interrupt_gate exception_stub_6 + interrupt_gate exception_stub_7 + interrupt_gate exception_stub_8 + interrupt_gate exception_stub_9 + interrupt_gate exception_stub_10 + interrupt_gate exception_stub_11 + interrupt_gate exception_stub_12 + interrupt_gate exception_stub_13 + interrupt_gate exception_stub_14 + interrupt_gate exception_stub_15 + interrupt_gate exception_stub_16 + interrupt_gate exception_stub_17 + interrupt_gate exception_stub_18 + interrupt_gate exception_stub_19 + interrupt_gate exception_stub_20 + interrupt_gate exception_stub_21 + interrupt_gate exception_stub_22 + interrupt_gate exception_stub_23 + interrupt_gate exception_stub_24 + interrupt_gate exception_stub_25 + interrupt_gate exception_stub_26 + interrupt_gate exception_stub_27 + interrupt_gate exception_stub_28 + interrupt_gate exception_stub_29 + interrupt_gate exception_stub_30 + interrupt_gate exception_stub_31 + user_defined_gates 32, 63 + user_defined_gates 64, 127 + user_defined_gates 128, 191 + user_defined_gates 192, 255 +idt_end: + +/* IDT pointer for use with lidt */ +idt_ptr: + .word idt_end - idt - 1 + .quad idt + + .global exception_init_asm +exception_init_asm: + /* + * Loop over the entries which start out as two copies of the target + * address. We can turn them into real interrupt gates by selectively + * replacing certain bit fields. + */ + movq $idt, %rax + movq $0x00008e0000180000, %rcx +1: + movq (%rax), %rdi + movq %rdi, %rsi + movq %rdi, %rdx + andl $0xffff0000, %esi + shlq $32, %rsi + andq $0x0000ffff, %rdx + orq %rdx, %rsi + orq %rcx, %rsi + movq %rsi, (%rax) + shrq $32, %rdi + movq %rdi, 8(%rax) + addq $16, %rax + cmpq $idt_end, %rax + jne 1b + + /* Install the IDT. */ + lidt idt_ptr + + ret diff --git a/payloads/libpayload/arch/x86/exec64.S b/payloads/libpayload/arch/x86/exec64.S new file mode 100644 index 00000000000..48c418f7b7d --- /dev/null +++ b/payloads/libpayload/arch/x86/exec64.S @@ -0,0 +1,134 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* calling syntax: i386_do_exec(long addr, int argc, char **argv, int *ret) */ + +/* This implements the payload API detailed here: + * https://www.coreboot.org/Payload_API + */ + +.align 4 +.text + +.code64 +.global i386_do_exec + .type i386_do_exec,@function + +i386_do_exec: + pushq %rbx + pushq %rbp + pushq %rdx + pushq %rcx + + movq $0x08, %rcx + call SetCodeSelector + +.code32 + pushl %ebp + movl %esp, %ebp + + /* Save the remaining callee preserved registers */ + pushl %ebx + pushl %esi + pushl %edi + + /* Disable paging */ + movl %cr0, %eax + andl $0x7FFFFFFF, %eax + movl %eax, %cr0 + + /* Disable long mode */ + movl $0xC0000080, %ecx + rdmsr + btrl $8, %eax + wrmsr + + /* Push argc and argv on to the stack. + * + * We need to put a dummy value inbetween, as argc should be at offset + * 0x10, according to the payload API. + */ + pushl %esi /* argc */ + pushl $0 + pushl 12(%ebp) /* argv, saved on stack */ + + /* Push a "magic" number on the stack - the other payload will use this + * as a clue that the argc and argv values on the stack are sane. + */ + pushl $0x12345678 + + /* Jump to the code */ + call *%edi + /* %eax has the return value */ + + /* Skip over the argc/argv stuff still on the stack. + * Don't assume %ebp is sane, here. Restore it from the stack. + */ + addl $0x10, %esp + + /* Restore the saved registers */ + popl %edi + popl %esi + popl %ebx + popl %ebp + + /* Get pointer to return value and save the return value in it. */ + movl (%esp), %ecx + movl %eax, (%ecx) + + /* Use long jump to switch to 64-bit code segment */ + ljmp $0x18, $1f +.code64 +1: + popq %rcx + popq %rdx + popq %rbp + popq %rbx + + ret + +SetCodeSelector: + # pop the return address from stack + pop %rbx + + # save rsp because we need to push it after ss + mov %rsp, %rdx + + # use iret to jump to a 32-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov %ss, %ax # need to push ss.. + push %rax # push ss instuction not valid in x64 mode, + # so use ax + push %rdx # the rsp to load + pushfq # push rflags + push %rcx # cx is code segment selector from caller + push %rbx # push the IP for the next instruction + + # the iretq will behave like ret, with the new cs/ss value loaded + iretq diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S index 0575dbe8cc4..04a4ad4f0f5 100644 --- a/payloads/libpayload/arch/x86/head.S +++ b/payloads/libpayload/arch/x86/head.S @@ -61,6 +61,7 @@ mb_header: #define CB_ARGV 0x08 #define CB_ARGC 0x10 +#if !CONFIG(LP_ARCH_X86_64) /* * This function saves off the previous stack and switches us to our * own execution environment. @@ -142,3 +143,324 @@ _leave: /* Return to the original context. */ ret + + +#else +/* + * This function saves off the previous stack and switches us to our + * own execution environment. + */ +_init: + /* No interrupts, please. */ + cli + cld + + /* Store EAX and EBX */ + movl %eax, loader_eax + movl %ebx, loader_ebx + + /* Copy argv[] and argc as demanded by the Payload API, + * see https://www.coreboot.org/Payload_API and exec.S. + */ + cmpl $CB_MAGIC_VALUE, CB_MAGIC(%esp) + jne 1f + + movl CB_ARGV(%esp), %eax + movl %eax, main_argv + movl $0, (main_argv+4) + + movl CB_ARGC(%esp), %eax + movl %eax, main_argc +1: + /* Store current stack pointer and set up new stack. */ + movl %esp, %ebx + movl $_stack, %esp + andl $0xfffffff0, %esp + + pushl $0 /* keep stack aligned for x64 calls (SysV ABI) */ + pushl $0 + pushl $0 + pushl %ebx + + /* Enable special x86 functions if present. */ + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + + movl $0, %eax + cpuid + /* Test if CPUID(eax=1) is available. */ + test %eax, %eax + je cpuid_done + + /* Get CPU features. */ + movl $1, %eax + cpuid + +cpuid_fpu: + /* Test if x87 FPU is present */ + test $1, %edx + je cpuid_sse + + fninit + movl %cr0, %eax + andl $0xFFFFFFFB, %eax /* clear EM */ + orl $0x00000022, %eax /* set MP, NE */ + movl %eax, %cr0 + +cpuid_sse: + /* Test if SSE is available */ + test $0x02000000, %edx + je cpuid_done + + movl %cr4, %eax + orl $0x00000600, %eax /* set OSFXSR, OSXMMEXCPT */ + movl %eax, %cr4 + +cpuid_done: + popl %edx + popl %ecx + popl %ebx + popl %eax + + /* Prepare GDT for 64-bit operation */ + lgdt %cs:gdtptr + ljmp $0x08, $1f +1: + movl $0x10, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + call _gen_long_mode_pgtbl32 + + /* Load identity mapped page tables */ + movl $(_pagetables), %eax + movl %eax, %cr3 + + /* Enable PAE */ + movl %cr4, %eax + btsl $5, %eax + movl %eax, %cr4 + + /* Enable long mode */ + movl $0xC0000080, %ecx /* 0xC0000080 = IA32_EFER */ + rdmsr + btsl $8, %eax + wrmsr + + /* Enable paging */ + movl %cr0, %eax + btsl $31, %eax + movl %eax, %cr0 + + /* Use long jump to switch to 64-bit code segment */ + ljmp $0x18, $1f +.code64 +1: + + /* Clear bss */ + movq $_edata, %rdi + addq $7, %rdi + andq $(~7), %rdi + movq %rsp, %rcx + subq %rdi, %rcx + shrq $3, %rcx + xorq %rax, %rax + rep stosq + + /* Let's rock. */ + call start_main + + /* %eax has the return value - pass it on unmolested */ +_leave: + /* Just in case */ + cli + + /* Ensure cache is clean. */ + invd + + push %rax + + /* Set 32-bit code segment and ss */ + mov $0x08, %rcx + call SetCodeSelector + +.code32 + /* Running in 32-bit compatibility mode */ + + /* Use flat 32-bit data segment. */ + movl $0x10, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + /* Disable paging */ + movl %cr0, %eax + andl $0x7FFFFFFF, %eax + movl %eax, %cr0 + + /* Disable long mode */ + movl $0xC0000080, %ecx + rdmsr + btrl $8, %eax + wrmsr + + /* Disable PAE */ + movl %cr4, %eax + andl $(~0x20), %eax + movl %eax, %cr4 + + popl %eax + addl $4, %esp /* we pushed %rax, but poped %eax */ + + /* Restore old stack. */ + popl %esp + + /* Return to the original context. */ + ret + + .align 4 +.globl gdtptr +gdtptr: + .word gdt_end - gdt -1 /* compute the table limit */ + .long gdt /* we know the offset */ + + .align 4 +gdt: + /* selgdt 0, unused */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes + for limit */ + + /* selgdt 0x10,flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + + /* selgdt 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 + +gdt_end: + + +/* Page table attributes: WB, Supervisor, Present, Writeable */ +#define PAGE_ATTRIBUTES 0x003 + +/* + * Creates identity mapped page entries. + * Identity maps 0 - 4GiB using arbitraty page size. + * Use offset: + * 12 for 4 KiB pages + * 12 + 9 for 2 MiB pages + * 12 + 9 + 9 for 1 GiB pages + * + * edi: The destination (in _pagetables) + * Clobers: esi, edi, ebx + */ +.code32 +.macro gen_page_entries32 offset + xorl %esi, %esi + xorl %ebx, %ebx +1: + movl $(PAGE_ATTRIBUTES | (1 << 7)), 0x00(%edi) + orl %esi, 0x00(%edi) + movl %ebx, 0x04(%edi) + addl $(1 << (\offset)), %esi + addl $8, %edi + cmpl %ebx, %esi + ja 1b +.endm + +_gen_long_mode_pgtbl32: + + /* Setup long mode: identity map 0-4GiB */ + + movl $(_pagetables), %ecx + xorl %eax, %eax + + /* Generate one PM4LE entry - point to PDPE */ + leal (0x1000)(%ecx), %edi + movl %edi, (%ecx) + orl $(PAGE_ATTRIBUTES), (%ecx) + movl %eax, 4(%ecx) + + /* Read CPUID(eax=0x80000001) EDX BIT26 */ + movl $0x80000001, %eax + cpuid + btsl $26, %edx + jc paging_1g_pages +paging_2m_pages: + + /* With 2 MiB hugepages we need 6 pages of 4096 byte */ + + movl $(PAGE_ATTRIBUTES), %ebx + + /* edi points to PDPE table, point esi to PDE tables */ + movl %edi, %esi + addl $0x1000, %esi + + movl $4, %eax + /* Point to the to be generated PDE tables */ +1: + mov %ebx, 0x0(%edi) + or %esi, 0x0(%edi) + movl $0, 0x4(%edi) + add $0x1000, %esi + add $8, %edi + dec %eax + jnz 1b + + /* point edi to PDE tables */ + movl $(_pagetables), %ecx + leal (0x2000)(%ecx), %edi + + /* Fill the PDE tables : Generate 4 * 512 PDE entries */ + gen_page_entries32 (12 + 9) + + ret + +paging_1g_pages: + /* With 1 GiB hugepages we need 2 pages of 4096 byte */ + + /* edi points to PDPE table already */ + + /* Fill the PDPE table : Generate 4 PDPE entries */ + gen_page_entries32 (12 + 9 + 9) + + ret + +.code64 +SetCodeSelector: + # pop the return address from stack + pop %rbx + + # save rsp because we need to push it after ss + mov %rsp, %rdx + + # use iret to jump to a 32-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov %ss, %ax # need to push ss.. + push %rax # push ss instuction not valid in x64 mode, + # so use ax + push %rdx # the rsp to load + pushfq # push rflags + push %rcx # cx is code segment selector from caller + push %rbx # push the IP for the next instruction + + # the iretq will behave like ret, with the new cs/ss value loaded + iretq + +.align 4096 +_pagetables: + .fill 4096 * 6 +#endif diff --git a/payloads/libpayload/arch/x86/libpayload.ldscript b/payloads/libpayload/arch/x86/libpayload.ldscript.in similarity index 94% rename from payloads/libpayload/arch/x86/libpayload.ldscript rename to payloads/libpayload/arch/x86/libpayload.ldscript.in index bcb2165a2fc..00696838746 100644 --- a/payloads/libpayload/arch/x86/libpayload.ldscript +++ b/payloads/libpayload/arch/x86/libpayload.ldscript.in @@ -27,8 +27,14 @@ * SUCH DAMAGE. */ +#include +#if CONFIG(LP_ARCH_X86_64) +OUTPUT_FORMAT(elf64-x86-64) +OUTPUT_ARCH(i386:x86-64) +#else OUTPUT_FORMAT(elf32-i386) OUTPUT_ARCH(i386) +#endif ENTRY(_entry) diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c index d9c27fa8b42..99b65e74c79 100644 --- a/payloads/libpayload/arch/x86/rom_media.c +++ b/payloads/libpayload/arch/x86/rom_media.c @@ -51,10 +51,10 @@ static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) // mapped location. To workaround that, we handle >0xf0000000 as real // memory pointer. - if ((uint32_t)offset > (uint32_t)0xf0000000) + if ((size_t)offset > (size_t)0xf0000000) ptr = (void*)offset; else - ptr = (void*)(0 - (uint32_t)media->context + offset); + ptr = (void*)(size_t)(0x100000000ULL - (size_t)media->context + offset); return ptr; } @@ -80,7 +80,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { // 0xfffffffc, and the pointer is still a memory-mapped address. // Since the CBFS core always use ROM offset, we need to figure out // header->romsize even before media is initialized. - struct cbfs_header *header = (struct cbfs_header*) + struct cbfs_header *header = (struct cbfs_header*)(size_t) *(uint32_t*)(0xfffffffc); if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { #if CONFIG(LP_ROM_SIZE) @@ -91,7 +91,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { #endif } else { uint32_t romsize = ntohl(header->romsize); - media->context = (void*)romsize; + media->context = (void*)(size_t)romsize; #if CONFIG(LP_ROM_SIZE) if (CONFIG_LP_ROM_SIZE != romsize) printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", diff --git a/payloads/libpayload/arch/x86/virtual.c b/payloads/libpayload/arch/x86/virtual.c index 59768dbd66b..5fb3151ced7 100644 --- a/payloads/libpayload/arch/x86/virtual.c +++ b/payloads/libpayload/arch/x86/virtual.c @@ -28,9 +28,9 @@ */ #include +#include -unsigned long virtual_offset = 0; - +uintptr_t virtual_offset = 0; int getpagesize(void) { diff --git a/payloads/libpayload/bin/lpas b/payloads/libpayload/bin/lpas index a82570ceb05..dd56de52022 100755 --- a/payloads/libpayload/bin/lpas +++ b/payloads/libpayload/bin/lpas @@ -64,13 +64,6 @@ CMDLINE= while [ $# -gt 0 ]; do case $1 in - --32) - shift - continue - ;; - --64) - error "Invalid option --64 - only 32 bit architectures are supported" - ;; -debug-wrapper) DEBUGME=1 shift @@ -84,7 +77,7 @@ while [ $# -gt 0 ]; do shift done -_ASFLAGS="--32 -I$_INCDIR" +_ASFLAGS="-I$_INCDIR" if [ $DEBUGME -eq 1 ]; then echo "$DEFAULT_AS $_ASFLAGS $CMDLINE" diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342ff28..8a2d139787a 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -92,6 +92,12 @@ if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHEXTRA="-m32 " _ARCH=x86 fi +if [ "$CONFIG_LP_ARCH_X86_64" = "y" ]; then + _ARCHINCDIR=$_INCDIR/x86 + _ARCHLIBDIR=$_LIBDIR/x86 + _ARCHEXTRA="-m64 " + _ARCH=x86_64 +fi if [ -f $_LIBDIR/libpayload.ldscript ]; then _LDDIR=$_LIBDIR @@ -120,9 +126,6 @@ while [ $# -gt 0 ]; do shift continue ;; - -m64) - error "Invalid option --64 - only 32 bit architectures are supported" - ;; -c) DOLINK=0 ;; diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral index 5f60392fdb4..e305fb67000 100644 --- a/payloads/libpayload/configs/config.mistral +++ b/payloads/libpayload/configs/config.mistral @@ -1,3 +1,5 @@ CONFIG_LP_CHROMEOS=y CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QCS405_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/configs/defconfig-tinycurses-64 b/payloads/libpayload/configs/defconfig-tinycurses-64 new file mode 100644 index 00000000000..52f79bc000a --- /dev/null +++ b/payloads/libpayload/configs/defconfig-tinycurses-64 @@ -0,0 +1,12 @@ +CONFIG_LP_ARCH_X86_64=y +CONFIG_LP_ENABLE_APIC=y +# CONFIG_LP_MULTIBOOT is not set +CONFIG_LP_TINYCURSES=y +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_UHCI=y +CONFIG_LP_USB_OHCI=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y +CONFIG_LP_HEAP_SIZE=536870912 +CONFIG_LP_STACK_SIZE=8388608 diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 40e587c2237..b4e75943f39 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -37,6 +37,7 @@ libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c serial/serial.c libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c +libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/qcs405.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 643167ef409..e864ac92638 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -63,6 +63,7 @@ #define I8042_KBCMD_EN 0xf4 #define I8042_KBCMD_DEFAULT_DIS 0xf5 #define I8042_KBCMD_SET_DEFAULT 0xf6 +#define I8042_KBCMD_ACK 0xfa #define I8042_KBCMD_RESEND 0xfe #define I8042_KBCMD_RESET 0xff diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 1035bf2791a..240385ce6dc 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -172,7 +172,7 @@ static unsigned char keyboard_cmd(unsigned char cmd) { i8042_write_data(cmd); - return i8042_wait_read_ps2() == 0xfa; + return i8042_wait_read_ps2() == I8042_KBCMD_ACK; } int keyboard_havechar(void) @@ -258,6 +258,7 @@ int keyboard_getchar(void) /* vulcan nerve pinch */ if ((modifier & KB_MOD_ALT) && reset_handler) reset_handler(); + /* fallthrough */ default: ret = 0; } @@ -296,7 +297,8 @@ int keyboard_set_layout(char *country) static struct console_input_driver cons = { .havekey = keyboard_havechar, - .getchar = keyboard_getchar + .getchar = keyboard_getchar, + .input_type = CONSOLE_INPUT_TYPE_EC, }; void keyboard_init(void) @@ -315,19 +317,42 @@ void keyboard_init(void) /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); + /* Reset keyboard and self test (keyboard side) */ + ret = keyboard_cmd(I8042_KBCMD_RESET); + if (!ret) { + printf("ERROR: Keyboard reset failed!\n"); + return; + } + /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard set scancode failed!\n"); return; + } ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard scancode set#1 failed!\n"); return; + } + + /* + * Set default parameters. + * Fix for broken QEMU ps/2 make scancodes. + */ + ret = keyboard_cmd(0xf6); + if (!ret) { + printf("ERROR: Keyboard set default params failed!\n"); + return; + } /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard enable scanning failed!\n"); return; + } console_add_input_driver(&cons); } diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index f503bdb1245..9502d4b147e 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -98,7 +98,8 @@ static void serial_hardware_init(int speed, int word_bits, static struct console_input_driver consin = { .havekey = &serial_havechar, - .getchar = &serial_getchar + .getchar = &serial_getchar, + .input_type = CONSOLE_INPUT_TYPE_UART, }; static struct console_output_driver consout = { diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 52d71b8ac8a..7656ad73e0b 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -560,6 +560,7 @@ void serial_console_init(void) consin.havekey = serial_havechar; consin.getchar = serial_getchar; + consin.input_type = CONSOLE_INPUT_TYPE_UART; consout.putchar = serial_putchar; diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index 912893d7e23..183ada6563f 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -352,6 +352,7 @@ void serial_console_init(void) consin.havekey = serial_havechar; consin.getchar = serial_getchar; + consin.input_type = CONSOLE_INPUT_TYPE_UART; consout.putchar = serial_putchar; diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c new file mode 100644 index 00000000000..9f02e172634 --- /dev/null +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2010-2012, 2014, 2016, 2019, The Linux Foundation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +#define PERIPH_BLK_BLSP 1 + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \ + (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +#define UART1_DM_BASE ((void *)0x078af000) +#define UART2_DM_BASE ((void *)0x078b1000) + +enum { + BLSP1_UART1, + BLSP1_UART2, +}; + +#define FIFO_DATA_SIZE 4 + +struct uart_params_t { + void *uart_dm_base; + unsigned int blsp_uart; +}; + +static struct console_input_driver consin = { + .havekey = serial_havechar, + .getchar = serial_getchar, +}; + +static struct console_output_driver consout = { + .putchar = serial_putchar, +}; + +static struct uart_params_t uart_board_param = {}; + +/** + * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); + + /* Enable receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); + + /* Clear stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + /* Enable stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); + + return 0; +} + +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +static int valid_data = 0; + +static unsigned int word = 0; + +/** + * msm_boot_uart_dm_read - reads a word from the RX FIFO. + * @data: location where the read data is stored + * @count: no of valid data in the FIFO + * + * Reads a word from the RX FIFO. If no data is available + * returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. + */ +static unsigned int +msm_boot_uart_dm_read(unsigned int *data, int *count) +{ + static int total_rx_data = 0; + static int rx_data_read = 0; + void *base; + uint32_t status_reg; + + base = uart_board_param.uart_dm_base; + + if (data == NULL) + return MSM_BOOT_UART_DM_E_INVAL; + + status_reg = read32(MSM_BOOT_UART_DM_MISR(base)); + + /* Check for DM_RXSTALE for RX transfer to finish */ + while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { + status_reg = read32(MSM_BOOT_UART_DM_MISR(base)); + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Check for Overrun error. We'll just reset Error Status */ + if (read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_UART_OVERRUN) { + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + total_rx_data = rx_data_read = 0; + msm_boot_uart_dm_init(base); + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ + if (total_rx_data == 0) + total_rx_data = read32(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); + + /* Data available in FIFO; read a word. */ + *data = read32(MSM_BOOT_UART_DM_RF(base, 0)); + + /* increment the total count of chars we've read so far */ + rx_data_read += FIFO_DATA_SIZE; + + /* actual count of valid data in word */ + *count = ((total_rx_data < rx_data_read) ? + (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : + FIFO_DATA_SIZE); + + /* If there are still data left in FIFO we'll read them before + * initializing RX Transfer again + */ + if (rx_data_read < total_rx_data) + return 0; + + msm_boot_uart_dm_init_rx_transfer(base); + total_rx_data = rx_data_read = 0; + + return 0; +} + +void serial_putchar(unsigned int data) +{ + int num_of_chars = 1; + void *base = uart_board_param.uart_dm_base; + + if (data == '\n') { + num_of_chars++; + data = (data << 8) | '\r'; + } + + /* Wait until transmit FIFO is empty. */ + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); + + /* And now write the character(s) */ + write32(MSM_BOOT_UART_DM_TF(base, 0), data); +} + +/* + * msm_boot_uart_dm_reset - resets UART controller + * @base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + return 0; +} + +/* + * msm_boot_uart_dm_init - initilaizes UART controller + * @uart_dm_base: UART controller base address + */ +unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); + + /* Configure Interrupt Mask register IMR */ + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); + + /* RX watermark value */ + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); + + /* Enable transmitter */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * serial_havechar - checks if data available for reading + * + * Returns 1 if data available, 0 otherwise + */ +int serial_havechar(void) +{ + /* Return if data is already read */ + if (valid_data) + return 1; + + /* Read data from the FIFO */ + if (msm_boot_uart_dm_read(&word, &valid_data) != 0) + return 0; + + return 1; +} + +/** + * qcs405_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +int serial_getchar(void) +{ + uint8_t byte; + + while (!serial_havechar()) + ; /* wait for incoming data */ + + byte = (uint8_t)(word & 0xff); + word = word >> 8; + valid_data--; + + return byte; +} + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + struct cb_serial *sc_ptr = lib_sysinfo.serial; + + if (!sc_ptr) + return; + + uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr; + + /* TODO: We should rely on coreboot init. */ + msm_boot_uart_dm_init(uart_board_param.uart_dm_base); + + console_add_output_driver(&consout); + console_add_input_driver(&consin); +} diff --git a/payloads/libpayload/drivers/serial/s5p.c b/payloads/libpayload/drivers/serial/s5p.c index 1d23352ec49..6ca5dc4717f 100644 --- a/payloads/libpayload/drivers/serial/s5p.c +++ b/payloads/libpayload/drivers/serial/s5p.c @@ -84,7 +84,8 @@ static struct console_output_driver s5p_serial_output = static struct console_input_driver s5p_serial_input = { .havekey = &serial_havechar, - .getchar = &serial_getchar + .getchar = &serial_getchar, + .input_type = CONSOLE_INPUT_TYPE_UART, }; void serial_init(void) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 40e1008cf45..f74adafd752 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -108,6 +108,9 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, const int ncs = HBA_CAPS_DECODE_NCS(ctrl->caps); + if (ahci_cmdengine_stop(port)) + return 1; + /* Allocate command list, one command table and received FIS. */ cmd_t *const cmdlist = memalign(1024, ncs * sizeof(cmd_t)); cmdtable_t *const cmdtable = memalign(128, sizeof(cmdtable_t)); @@ -121,12 +124,10 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis)); /* Set command list base and received FIS base. */ - if (ahci_cmdengine_stop(port)) - return 1; port->cmdlist_base = virt_to_phys(cmdlist); port->frameinfo_base = virt_to_phys(rcvd_fis); if (ahci_cmdengine_start(port)) - return 1; + goto _cleanup_ret; /* Put port into active state. */ port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE; @@ -178,6 +179,8 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, /* Clean up (not reached for initialized devices). */ if (dev) free(dev); + /* Only free if stopping succeeds, since otherwise the controller may + still use the resources for DMA. */ if (!ahci_cmdengine_stop(port)) { port->cmdlist_base = 0; port->frameinfo_base = 0; diff --git a/payloads/libpayload/drivers/storage/ahci_common.c b/payloads/libpayload/drivers/storage/ahci_common.c index ef9d43d3068..20e6dfdf89b 100644 --- a/payloads/libpayload/drivers/storage/ahci_common.c +++ b/payloads/libpayload/drivers/storage/ahci_common.c @@ -69,7 +69,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev, u8 *const user_buf, const size_t len, const int out) { - if ((u32)user_buf & 1) { + if ((size_t)user_buf & 1) { printf("ahci: Odd buffer pointer (%p).\n", user_buf); if (dev->buf) /* orphaned buffer */ free(dev->buf - *(dev->buf - 1)); @@ -79,7 +79,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev, dev->user_buf = user_buf; dev->write_back = !out; dev->buflen = len; - if ((u32)dev->buf & 1) { + if ((size_t)dev->buf & 1) { dev->buf[0] = 1; dev->buf += 1; } else { diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 5a61dfab51b..ba4976f7ccd 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -12,12 +12,12 @@ choice prompt "Timer driver" - default TIMER_NONE if !ARCH_X86 - default TIMER_RDTSC if ARCH_X86 + default TIMER_NONE if !(ARCH_X86 || ARCH_X86_64) + default TIMER_RDTSC if ARCH_X86 || ARCH_X86_64 config TIMER_RDTSC bool "x86 rdtsc" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_X86_64 config TIMER_NONE bool "None" diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 92e3f26180c..8e5cec04bf4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -287,6 +287,21 @@ struct cb_macs { struct mac_address mac_addrs[0]; }; +#define CB_TAG_MMC_INFO 0x0035 +struct cb_mmc_info { + uint32_t tag; + uint32_t size; + /* + * Passes the early mmc status to payload to indicate if firmware + * successfully sent CMD0, CMD1 to the card or not. In case of + * success, the payload can skip the first step of the initialization + * sequence which is to send CMD0, and instead start by sending CMD1 + * as described in Jedec Standard JESD83-B1 section 6.4.3. + * passes 1 on success + */ + int32_t early_cmd1_status; +}; + #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 3a84b3b0382..57a3afc6b1d 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -350,6 +350,9 @@ int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_op typedef enum { CONSOLE_INPUT_TYPE_UNKNOWN = 0, CONSOLE_INPUT_TYPE_USB, + CONSOLE_INPUT_TYPE_EC, + CONSOLE_INPUT_TYPE_UART, + CONSOLE_INPUT_TYPE_GPIO, } console_input_type; void console_init(void); @@ -431,9 +434,12 @@ void hexdump(const void *memory, size_t length); void fatal(const char *msg) __attribute__((noreturn)); /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ -static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +static inline int clz(u32 x) +{ + return x ? __builtin_clz(x) : (int)sizeof(x) * 8; +} /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ -static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 7e6e74809dd..03df76de598 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -100,7 +100,7 @@ struct sysinfo_t { void *vboot_workbuf; uint32_t vboot_workbuf_size; -#if CONFIG(LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86) || CONFIG(LP_ARCH_X86_64) int x86_rom_var_mtrr_index; #endif @@ -129,6 +129,7 @@ struct sysinfo_t { uint64_t mtc_start; uint32_t mtc_size; void *chromeos_vpd; + int mmc_early_wake_status; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/include/x86/arch/exception.h b/payloads/libpayload/include/x86/arch/exception.h index a6c2afcf0d7..9fede2d0c05 100644 --- a/payloads/libpayload/include/x86/arch/exception.h +++ b/payloads/libpayload/include/x86/arch/exception.h @@ -31,6 +31,7 @@ #define _ARCH_EXCEPTION_H #include +#include void exception_init_asm(void); void exception_dispatch(void); @@ -42,31 +43,60 @@ int interrupts_enabled(void); struct exception_state { /* Careful: x86/gdb.c currently relies on the size and order of regs. */ +#if CONFIG(LP_ARCH_X86_64) struct { - u32 eax; - u32 ecx; - u32 edx; - u32 ebx; - u32 esp; - u32 ebp; - u32 esi; - u32 edi; - u32 eip; - u32 eflags; - u32 cs; - u32 ss; - u32 ds; - u32 es; - u32 fs; - u32 gs; + size_t rax; + size_t rcx; + size_t rdx; + size_t rbx; + size_t rsp; + size_t rbp; + size_t rsi; + size_t rdi; + size_t r8; + size_t r9; + size_t r10; + size_t r11; + size_t r12; + size_t r13; + size_t r14; + size_t r15; + size_t rip; + size_t rflags; + size_t cs; + size_t ss; + size_t ds; + size_t es; + size_t fs; + size_t gs; } regs; - u32 error_code; - u32 vector; +#else + struct { + size_t eax; + size_t ecx; + size_t edx; + size_t ebx; + size_t esp; + size_t ebp; + size_t esi; + size_t edi; + size_t eip; + size_t eflags; + size_t cs; + size_t ss; + size_t ds; + size_t es; + size_t fs; + size_t gs; + } regs; +#endif + size_t error_code; + size_t vector; } __packed; extern struct exception_state *exception_state; -extern u32 exception_stack[]; -extern u32 *exception_stack_end; +extern uintptr_t exception_stack[]; +extern uintptr_t *exception_stack_end; enum { EXC_DE = 0, /* Divide by zero */ diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index c417ce0c667..7482eaaddf0 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void write32(volatile void *addr, u static inline unsigned int inl(int port) { unsigned long val; - __asm__ __volatile__("inl %w1, %0" : "=a"(val) : "Nd"(port)); + __asm__ __volatile__("inl %w1, %k0" : "=a"(val) : "Nd"(port)); return val; } @@ -102,7 +102,7 @@ static inline unsigned char inb(int port) static inline void outl(unsigned int val, int port) { - __asm__ __volatile__("outl %0, %w1" : : "a"(val), "Nd"(port)); + __asm__ __volatile__("outl %k0, %w1" : : "a"(val), "Nd"(port)); } static inline void outw(unsigned short val, int port) diff --git a/payloads/libpayload/include/x86/arch/rdtsc.h b/payloads/libpayload/include/x86/arch/rdtsc.h index ef23e0e247c..041c55386d4 100644 --- a/payloads/libpayload/include/x86/arch/rdtsc.h +++ b/payloads/libpayload/include/x86/arch/rdtsc.h @@ -34,9 +34,15 @@ static u64 rdtsc(void) { +#if CONFIG(LP_ARCH_X86_64) + u32 low, high; + __asm__ __volatile__ ("rdtsc" : "=a" (low), "=d" (high)); + return ((u64)high << 32) | low; +#else u64 val; __asm__ __volatile__ ("rdtsc" : "=A" (val)); return val; +#endif } #endif diff --git a/payloads/libpayload/include/x86/arch/virtual.h b/payloads/libpayload/include/x86/arch/virtual.h index 328c3aa34ef..779bd59fcb4 100644 --- a/payloads/libpayload/include/x86/arch/virtual.h +++ b/payloads/libpayload/include/x86/arch/virtual.h @@ -30,10 +30,12 @@ #ifndef _ARCH_VIRTUAL_H #define _ARCH_VIRTUAL_H -extern unsigned long virtual_offset; +#include -#define virt_to_phys(virt) ((unsigned long) (virt) + virtual_offset) -#define phys_to_virt(phys) ((void *) ((unsigned long) (phys) - virtual_offset)) +extern uintptr_t virtual_offset; + +#define virt_to_phys(virt) ((size_t) (virt) + virtual_offset) +#define phys_to_virt(phys) ((void *) ((size_t) (phys) - virtual_offset)) #define virt_to_bus(addr) virt_to_phys(addr) #define bus_to_virt(addr) phys_to_virt(addr) diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 3982e47ec26..26a3a48c232 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -102,6 +102,13 @@ static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) info->vbnv_size = vbnv->range_size; } +static void cb_parse_mmc_info(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_mmc_info *mmc_info = (struct cb_mmc_info *)ptr; + + info->mmc_early_wake_status = mmc_info->early_cmd1_status; +} + static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) { int i; @@ -399,6 +406,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_SPI_FLASH: cb_parse_spi_flash(ptr, info); break; + case CB_TAG_MMC_INFO: + cb_parse_mmc_info(ptr, info); + break; case CB_TAG_MTC: cb_parse_mtc(ptr, info); break; diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 75834486b5b..50a1a6deb72 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -34,7 +34,7 @@ #include #include -#if CONFIG(LP_ARCH_X86) && CONFIG(LP_NVRAM) +#if (CONFIG(LP_ARCH_X86) || CONFIG(LP_ARCH_X86_64)) && CONFIG(LP_NVRAM) #include #endif diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index e94e1e76baf..1343fca99cb 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -119,7 +119,7 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, // Logical offset (for source media) of first file. *offset = ntohl(header->offset); *cbfs_end = ntohl(header->romsize); -#if CONFIG(LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86) || CONFIG(LP_ARCH_X86_64) // resolve actual length of ROM used for CBFS components // the bootblock size was not taken into account *cbfs_end -= ntohl(header->bootblocksize); diff --git a/src/Kconfig b/src/Kconfig index 62b3818fe49..d30aa99f06f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,6 +277,21 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. +config RAMPAYLOAD + bool "Enable coreboot flow without executing ramstage" + default n + depends on ARCH_X86 + help + If this option is enabled, coreboot flow will skip ramstage + loading and execution of ramstage to load payload. + + Instead it is expected to load payload from postcar stage itself. + + In this flow coreboot will perform basic x86 initialization + (DRAM resource allocation), MTRR programming, + Skip PCI enumeration logic and only allocate BAR for fixed devices + (bootable devices, TPM over GSPI). + endmenu menu "Mainboard" @@ -370,8 +385,6 @@ source "src/superio/*/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" -# FIXME move to vendorcode -source "src/drivers/intel/fsp1_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" @@ -428,6 +441,7 @@ config RTC config HEAP_SIZE hex + default 0x100000 if FLATTENED_DEVICE_TREE default 0x4000 config STACK_SIZE @@ -1144,32 +1158,6 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. -config GENERIC_SPD_BIN - bool - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - depends on GENERIC_SPD_BIN - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config SPD_READ_BY_WORD - bool - config BOOTBLOCK_CUSTOM # To be selected by arch, SoC or mainboard if it does not want use the normal # src/lib/bootblock.c#main() C entry point. diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 7cf173b5bb4..291e4eef3ee 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -18,9 +18,9 @@ #include #include #include -#include #include #include +#include #include /* diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d17a20d6286..7fbc525a18b 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -38,7 +38,6 @@ static void run_payload(struct prog *prog) void arch_prog_run(struct prog *prog) { void (*doit)(void *); - void *arg; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { run_payload(prog); @@ -46,7 +45,6 @@ void arch_prog_run(struct prog *prog) } doit = prog_entry(prog); - arg = prog_entry_arg(prog); doit(prog_entry_arg(prog)); } diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af7594..25a398068a0 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,8 +24,8 @@ config ARCH_RISCV_M # one implementation that will not have it due # to security concerns. bool - default n if ARCH_RISCV_M_DISABLED - default y + default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED + default n config ARCH_RISCV_S # S (supervisor) mode is for kernels. It is optional. diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 29064b1dc10..edf5295d79f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index a5f3fd40654..e0d7c60e5f6 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -20,7 +20,6 @@ #include #include #include -#include #include static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 242a7cfa1f9..827c1cba028 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -265,6 +265,14 @@ config SKIP_MAX_REBOOT_CNT_CLEAR Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successful boot. +config ACPI_NO_PCAT_8259 + bool + help + Selected by platforms that don't expose a PC/AT 8259 PIC pair. + +config ACPI_HAVE_PCAT_8259 + def_bool y if !ACPI_NO_PCAT_8259 + config ACPI_CPU_STRING string default "\\_PR.CP%02d" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6e4ee76c55f..7e518d8c93e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -193,7 +193,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c +verstage-y += cpu_common.c verstage-y += memset.c verstage-y += memcpy.c verstage-y += memmove.c @@ -230,7 +230,7 @@ romstage-y += boot.c romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S romstage-y += cbmem.c romstage-y += cbfs_and_run.c -romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c +romstage-y += cpu_common.c romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401a6e4..bf9813cbfe2 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -218,6 +218,9 @@ void acpi_create_madt(acpi_madt_t *madt) memset((void *)madt, 0, sizeof(acpi_madt_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -229,7 +232,8 @@ void acpi_create_madt(acpi_madt_t *madt) header->revision = get_acpi_table_revision(MADT); madt->lapic_addr = LOCAL_APIC_ADDR; - madt->flags = 0x1; /* PCAT_COMPAT */ + if (CONFIG(ACPI_HAVE_PCAT_8259)) + madt->flags |= 1; current = acpi_fill_madt(current); @@ -247,6 +251,9 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -301,6 +308,9 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa) if (!lasa) return; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TCPA", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -360,6 +370,9 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2) if (!lasa) tpm2_log_len = 0; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TPM2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -480,6 +493,9 @@ void acpi_create_srat(acpi_srat_t *srat, memset((void *)srat, 0, sizeof(acpi_srat_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SRAT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -507,6 +523,9 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, memset((void *)dmar, 0, sizeof(acpi_dmar_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "DMAR", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -568,6 +587,33 @@ unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, return atsr->length; } +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, + u32 proximity_domain) +{ + dmar_rhsa_entry_t *rhsa = (dmar_rhsa_entry_t *)current; + memset(rhsa, 0, sizeof(*rhsa)); + rhsa->type = DMAR_RHSA; + rhsa->length = sizeof(*rhsa); + rhsa->base_address = base_addr; + rhsa->proximity_domain = proximity_domain; + + return rhsa->length; +} + +unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, + const char *device_name) +{ + dmar_andd_entry_t *andd = (dmar_andd_entry_t *)current; + int andd_len = sizeof(dmar_andd_entry_t) + strlen(device_name) + 1; + memset(andd, 0, andd_len); + andd->type = DMAR_ANDD; + andd->length = andd_len; + andd->device_number = device_number; + memcpy(&andd->device_name, device_name, strlen(device_name)); + + return andd->length; +} + void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current) { dmar_entry_t *drhd = (dmar_entry_t *)base; @@ -641,6 +687,9 @@ void acpi_create_slit(acpi_slit_t *slit, memset((void *)slit, 0, sizeof(acpi_slit_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SLIT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -666,6 +715,9 @@ void acpi_create_hpet(acpi_hpet_t *hpet) memset((void *)hpet, 0, sizeof(acpi_hpet_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -700,6 +752,9 @@ void acpi_create_vfct(struct device *device, memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "VFCT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -726,6 +781,9 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, memset((void *)ivrs, 0, sizeof(acpi_ivrs_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "IVRS", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -779,6 +837,10 @@ void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, current = (uintptr_t)dbg2; memset(dbg2, 0, sizeof(acpi_dbg2_header_t)); header = &(dbg2->header); + + if (!header) + return; + header->revision = get_acpi_table_revision(DBG2); memcpy(header->signature, "DBG2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -898,6 +960,9 @@ static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(rsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -918,6 +983,9 @@ static void acpi_write_xsdt(acpi_xsdt_t *xsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(xsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -1018,7 +1086,8 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, memcpy(pos, data, data_len); len += data_len; - header->length += len; + if (header) + header->length += len; return len; } @@ -1031,6 +1100,9 @@ void acpi_write_hest(acpi_hest_t *hest, memset(hest, 0, sizeof(acpi_hest_t)); + if (!header) + return; + memcpy(header->signature, "HEST", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1052,6 +1124,9 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) memset(bert, 0, sizeof(acpi_bert_t)); + if (!header) + return; + memcpy(header->signature, "BERT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1073,6 +1148,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) acpi_header_t *header = &(fadt->header); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + + if (!header) + return; + memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index c57ba480941..57fbc89064a 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -377,7 +377,7 @@ void acpi_device_write_i2c(const struct acpi_i2c *i2c) desc_length = acpi_device_write_zero_len(); /* Byte 3: Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_I2C_SERIAL_BUS_REVISION_ID); /* Byte 4: Resource Source Index is Reserved */ acpigen_emit_byte(0); @@ -401,7 +401,7 @@ void acpi_device_write_i2c(const struct acpi_i2c *i2c) acpigen_emit_word(i2c->mode_10bit); /* Byte 9: Type Specific Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_I2C_TYPE_SPECIFIC_REVISION_ID); /* Byte 10-11: I2C Type Data Length */ type_length = acpi_device_write_zero_len(); @@ -435,7 +435,7 @@ void acpi_device_write_spi(const struct acpi_spi *spi) desc_length = acpi_device_write_zero_len(); /* Byte 3: Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_SPI_SERIAL_BUS_REVISION_ID); /* Byte 4: Resource Source Index is Reserved */ acpigen_emit_byte(0); @@ -464,7 +464,7 @@ void acpi_device_write_spi(const struct acpi_spi *spi) acpigen_emit_word(flags); /* Byte 9: Type Specific Revision ID */ - acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID); + acpigen_emit_byte(ACPI_SPI_TYPE_SPECIFIC_REVISION_ID); /* Byte 10-11: SPI Type Data Length */ type_length = acpi_device_write_zero_len(); @@ -740,6 +740,9 @@ size_t acpi_dp_add_property_list(struct acpi_dp *dp, const struct acpi_dp *prop; size_t i, properties_added = 0; + if (!dp || !property_list) + return 0; + for (i = 0; i < property_count; i++) { prop = &property_list[i]; @@ -775,6 +778,9 @@ size_t acpi_dp_add_property_list(struct acpi_dp *dp, struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, uint64_t value) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_INTEGER, name); if (new) @@ -786,6 +792,9 @@ struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, const char *string) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_STRING, name); if (new) @@ -797,6 +806,9 @@ struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, const char *reference) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_REFERENCE, name); if (new) @@ -810,7 +822,7 @@ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, { struct acpi_dp *new; - if (!child || child->type != ACPI_DP_TYPE_TABLE) + if (!dp || !child || child->type != ACPI_DP_TYPE_TABLE) return NULL; new = acpi_dp_new(dp, ACPI_DP_TYPE_CHILD, name); @@ -826,7 +838,7 @@ struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array) { struct acpi_dp *new; - if (!array || array->type != ACPI_DP_TYPE_TABLE) + if (!dp || !array || array->type != ACPI_DP_TYPE_TABLE) return NULL; new = acpi_dp_new(dp, ACPI_DP_TYPE_ARRAY, array->name); @@ -842,7 +854,7 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, struct acpi_dp *dp_array; int i; - if (len <= 0) + if (!dp || len <= 0) return NULL; dp_array = acpi_dp_new_table(name); @@ -862,6 +874,9 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low) { + if (!dp) + return NULL; + struct acpi_dp *gpio = acpi_dp_new_table(name); if (!gpio) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 3f9f99422d6..e283f4da31a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 37fb087ebdb..29b3600bbe7 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -34,7 +34,9 @@ /* Vboot measured boot TCPA log measurements. * Needs to be transferred until CBMEM is available */ +#if CONFIG(VBOOT_MEASURED_BOOT) VBOOT2_TPM_LOG(., 2K) +#endif /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ @@ -89,8 +91,7 @@ _car_global_end = .; _car_relocatable_data_end = .; -#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \ - !CONFIG(USE_NATIVE_RAMINIT) +#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && !CONFIG(USE_NATIVE_RAMINIT) . = ABSOLUTE(0xff7e1000); _mrc_pool = .; . += 0x5000; diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 80d4d0da4ad..e6c94355033 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -219,6 +219,35 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } +/* Keep track of default apic ids for SMM. */ +static int cpus_default_apic_id[CONFIG_MAX_CPUS]; + +/* + * When CPUID executes with EAX set to 1, additional processor identification + * information is returned to EBX register: + * Default APIC ID: EBX[31-24] - this number is the 8 bit ID that is assigned + * to the local APIC on the processor during power on. + */ +static int initial_lapicid(void) +{ + return cpuid_ebx(1) >> 24; +} + +/* Function to keep track of cpu default apic_id */ +void cpu_add_map_entry(unsigned int index) +{ + cpus_default_apic_id[index] = initial_lapicid(); +} + +/* Returns default APIC id based on logical_cpu number or < 0 on failure. */ +int cpu_get_apic_id(int logical_cpu) +{ + if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) + return -1; + + return cpus_default_apic_id[logical_cpu]; +} + void cpu_initialize(unsigned int index) { /* Because we busy wait at the printk spinlock. @@ -308,3 +337,27 @@ void arch_bootstate_coreboot_exit(void) /* APs are waiting for work. Last thing to do is park them. */ mp_park_aps(); } + +/* + * Previously cpu_index() implementation assumes that cpu_index() + * function will always getting called from coreboot context + * (ESP stack pointer will always refer to coreboot). + * + * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * assumption might not be true, where FSP context (stack pointer refers + * to FSP) will request to get cpu_index(). + * + * Hence new logic to use cpuid to fetch lapic id and matches with + * cpus_default_apic_id[] variable to return correct cpu_index(). + */ +int cpu_index(void) +{ + int i; + int lapic_id = initial_lapicid(); + + for (i = 0; i < CONFIG_MAX_CPUS; i++) { + if (cpu_get_apic_id(i) == lapic_id) + return i; + } + return -1; +} diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b00777a4553..b88f4a7553e 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -502,7 +502,7 @@ void x86_exception(struct eregs *info) } #else /* !CONFIG_GDB_STUB */ #define MDUMP_SIZE 0x80 - unsigned int logical_processor = 0; + int logical_processor = 0; #if ENV_RAMSTAGE logical_processor = cpu_index(); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f4ed7440c5a..dbf46a9b1b0 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -56,11 +56,11 @@ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) -#include #include #include #include #include +#include #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ @@ -335,9 +335,9 @@ enum { }; enum dmar_flags { - DMAR_INTR_REMAP = 1, - DMAR_X2APIC_OPT_OUT = 2, - DMA_CTRL_PLATFORM_OPT_IN_FLAG = 3, + DMAR_INTR_REMAP = 1 << 0, + DMAR_X2APIC_OPT_OUT = 1 << 1, + DMA_CTRL_PLATFORM_OPT_IN_FLAG = 1 << 2, }; typedef struct dmar_entry { @@ -366,6 +366,22 @@ typedef struct dmar_atsr_entry { u16 segment; } __packed dmar_atsr_entry_t; +typedef struct dmar_rhsa_entry { + u16 type; + u16 length; + u32 reserved; + u64 base_address; + u32 proximity_domain; +} __packed dmar_rhsa_entry_t; + +typedef struct dmar_andd_entry { + u16 type; + u16 length; + u8 reserved[3]; + u8 device_number; + u8 device_name[]; +} __packed dmar_andd_entry_t; + /* DMAR (DMA Remapping Reporting Structure) */ typedef struct acpi_dmar { struct acpi_table_header header; @@ -822,14 +838,12 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(struct device *device); -#endif void acpi_create_mcfg(acpi_mcfg_t *mcfg); @@ -850,6 +864,10 @@ unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit); unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment); +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, + u32 proximity_domain); +unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, + const char *device_name); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index d26f3306957..35695467cbd 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -309,9 +309,12 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio); * ACPI Descriptors for Serial Bus interfaces */ -#define ACPI_SERIAL_BUS_TYPE_I2C 1 -#define ACPI_SERIAL_BUS_TYPE_SPI 2 -#define ACPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_SERIAL_BUS_TYPE_I2C 1 +#define ACPI_SERIAL_BUS_TYPE_SPI 2 +#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ +#define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1 +#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1 /* * ACPI I2C Bus diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 9e5769304b8..6114667c6c7 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -18,7 +18,6 @@ #ifndef LIBACPI_H #define LIBACPI_H -#include #include #include #include diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 61b17a6d2a9..078ea1748b0 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -261,13 +261,6 @@ static inline struct cpu_info *cpu_info(void) ); return ci; } - -static inline unsigned long cpu_index(void) -{ - struct cpu_info *ci; - ci = cpu_info(); - return ci->index; -} #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases @@ -374,4 +367,18 @@ uint32_t cpu_get_feature_flags_ecx(void); */ uint32_t cpu_get_feature_flags_edx(void); +/* + * Previously cpu_index() implementation assumes that cpu_index() + * function will always getting called from coreboot context + * (ESP stack pointer will always refer to coreboot). + * + * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * assumption might not be true, where FSP context (stack pointer refers + * to FSP) will request to get cpu_index(). + * + * Hence new logic to use cpuid to fetch lapic id and matches with + * cpus_default_apic_id[] variable to return correct cpu_index(). + */ +int cpu_index(void); + #endif /* ARCH_CPU_H */ diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d62487ef882..e5d0ceab4de 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -141,13 +141,16 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) }; if (prog_locate(prog)) - die("Failed to locate after CAR program.\n"); + die_with_post_code(POST_INVALID_ROM, + "Failed to locate after CAR program.\n"); if (rmodule_stage_load(&rsl)) - die("Failed to load after CAR program.\n"); + die_with_post_code(POST_INVALID_ROM, + "Failed to load after CAR program.\n"); /* Set the stack pointer within parameters of the program loaded. */ if (rsl.params == NULL) - die("No parameters found in after CAR program.\n"); + die_with_post_code(POST_INVALID_ROM, + "No parameters found in after CAR program.\n"); finalize_load(rsl.params, pcf->stack); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 1aa5be927de..bf627f280fd 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,9 @@ #include #include #include +#include +#include +#include #if CONFIG(CHROMEOS) #include #endif @@ -50,6 +53,41 @@ static u8 smbios_checksum(u8 *p, u32 length) return -ret; } +/* Get the device type 41 from the dev struct */ +static u8 smbios_get_device_type_from_dev(struct device *dev) +{ + u16 pci_basesubclass = (dev->class >> 8) & 0xFFFF; + + switch (pci_basesubclass) { + case PCI_CLASS_NOT_DEFINED: + return SMBIOS_DEVICE_TYPE_OTHER; + case PCI_CLASS_DISPLAY_VGA: + case PCI_CLASS_DISPLAY_XGA: + case PCI_CLASS_DISPLAY_3D: + case PCI_CLASS_DISPLAY_OTHER: + return SMBIOS_DEVICE_TYPE_VIDEO; + case PCI_CLASS_STORAGE_SCSI: + return SMBIOS_DEVICE_TYPE_SCSI; + case PCI_CLASS_NETWORK_ETHERNET: + return SMBIOS_DEVICE_TYPE_ETHERNET; + case PCI_CLASS_NETWORK_TOKEN_RING: + return SMBIOS_DEVICE_TYPE_TOKEN_RING; + case PCI_CLASS_MULTIMEDIA_VIDEO: + case PCI_CLASS_MULTIMEDIA_AUDIO: + case PCI_CLASS_MULTIMEDIA_PHONE: + case PCI_CLASS_MULTIMEDIA_OTHER: + return SMBIOS_DEVICE_TYPE_SOUND; + case PCI_CLASS_STORAGE_ATA: + return SMBIOS_DEVICE_TYPE_PATA; + case PCI_CLASS_STORAGE_SATA: + return SMBIOS_DEVICE_TYPE_SATA; + case PCI_CLASS_STORAGE_SAS: + return SMBIOS_DEVICE_TYPE_SAS; + default: + return SMBIOS_DEVICE_TYPE_UNKNOWN; + } +} + int smbios_add_string(u8 *start, const char *str) { @@ -140,7 +178,7 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t) { switch (mod_id) { - case 0x2c80: + case 0x9b85: t->manufacturer = smbios_add_string(t->eos, "Crucial"); break; @@ -172,9 +210,9 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, t->manufacturer = smbios_add_string(t->eos, "Hynix/Hyundai"); break; - case 0xb502: + case 0x3486: t->manufacturer = smbios_add_string(t->eos, - "SuperTalent"); + "Super Talent"); break; case 0xcd04: t->manufacturer = smbios_add_string(t->eos, @@ -188,7 +226,7 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, t->manufacturer = smbios_add_string(t->eos, "Elpida"); break; - case 0xff2c: + case 0x2c80: t->manufacturer = smbios_add_string(t->eos, "Micron"); break; @@ -833,6 +871,41 @@ static int smbios_write_type7_cache_parameters(unsigned long *current, return len; } +int smbios_write_type9(unsigned long *current, int *handle, + const char *name, const enum misc_slot_type type, + const enum slot_data_bus_bandwidth bandwidth, + const enum misc_slot_usage usage, + const enum misc_slot_length length, + u8 slot_char1, u8 slot_char2, u8 bus, u8 dev_func) +{ + struct smbios_type9 *t = (struct smbios_type9 *)*current; + int len = sizeof(struct smbios_type9); + + memset(t, 0, sizeof(struct smbios_type9)); + t->type = SMBIOS_SYSTEM_SLOTS; + t->handle = *handle; + t->length = len - 2; + if (name) + t->slot_designation = smbios_add_string(t->eos, name); + else + t->slot_designation = smbios_add_string(t->eos, "SLOT"); + t->slot_type = type; + /* TODO add slot_id supoort, will be "_SUN" for ACPI devices */ + t->slot_data_bus_width = bandwidth; + t->current_usage = usage; + t->slot_length = length; + t->slot_characteristics_1 = slot_char1; + t->slot_characteristics_2 = slot_char2; + t->segment_group_number = 0; + t->bus_number = bus; + t->device_function_number = dev_func; + t->data_bus_width = SlotDataBusWidthOther; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} static int smbios_write_type11(unsigned long *current, int *handle) { @@ -927,7 +1000,7 @@ int smbios_write_type38(unsigned long *current, int *handle, int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, - u8 bus, u8 device, u8 function) + u8 bus, u8 device, u8 function, u8 device_type) { struct smbios_type41 *t = (struct smbios_type41 *)*current; int len = sizeof(struct smbios_type41); @@ -937,7 +1010,7 @@ int smbios_write_type41(unsigned long *current, int *handle, t->handle = *handle; t->length = len - 2; t->reference_designation = smbios_add_string(t->eos, name); - t->device_type = SMBIOS_DEVICE_TYPE_OTHER; + t->device_type = device_type; t->device_status = 1; t->device_type_instance = instance; t->segment_group_number = segment; @@ -964,6 +1037,88 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } +/* Generate Type41 entries from devicetree */ +static int smbios_walk_device_tree_type41(struct device *dev, int *handle, + unsigned long *current) +{ + static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; + + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + if (!dev->on_mainboard) + return 0; + + u8 device_type = smbios_get_device_type_from_dev(dev); + + if (device_type == SMBIOS_DEVICE_TYPE_OTHER || + device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + return 0; + + if (device_type > SMBIOS_DEVICE_TYPE_COUNT) + return 0; + + const char *name = get_pci_subclass_name(dev); + + return smbios_write_type41(current, handle, + name, // name + type41_inst_cnt[device_type]++, // inst + 0, // segment + dev->bus->secondary, //bus + PCI_SLOT(dev->path.pci.devfn), // device + PCI_FUNC(dev->path.pci.devfn), // func + device_type); +} + +/* Generate Type9 entries from devicetree */ +static int smbios_walk_device_tree_type9(struct device *dev, int *handle, + unsigned long *current) +{ + enum misc_slot_usage usage; + enum slot_data_bus_bandwidth bandwidth; + enum misc_slot_type type; + enum misc_slot_length length; + + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + + if (!dev->smbios_slot_type && !dev->smbios_slot_data_width && + !dev->smbios_slot_designation && !dev->smbios_slot_length) + return 0; + + if (dev_is_active_bridge(dev)) + usage = SlotUsageInUse; + else if (dev->enabled) + usage = SlotUsageAvailable; + else + usage = SlotUsageUnknown; + + if (dev->smbios_slot_data_width) + bandwidth = dev->smbios_slot_data_width; + else + bandwidth = SlotDataBusWidthUnknown; + + if (dev->smbios_slot_type) + type = dev->smbios_slot_type; + else + type = SlotTypeUnknown; + + if (dev->smbios_slot_length) + length = dev->smbios_slot_length; + else + length = SlotLengthUnknown; + + return smbios_write_type9(current, handle, + dev->smbios_slot_designation, + type, + bandwidth, + usage, + length, + 1, + 0, + dev->bus->secondary, + dev->path.pci.devfn); +} + static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { @@ -976,6 +1131,8 @@ static int smbios_walk_device_tree(struct device *tree, int *handle, dev_name(dev)); len += dev->ops->get_smbios_data(dev, handle, current); } + len += smbios_walk_device_tree_type9(dev, handle, current); + len += smbios_walk_device_tree_type41(dev, handle, current); } return len; } diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 4379099ffe0..a509bc9f61a 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -18,6 +18,7 @@ #include #include #include +#include #if !defined(ERROR) #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index af79a590755..535ba3394c1 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -39,6 +39,7 @@ #define CBMEM_ID_IMD_SMALL 0x53a11439 #define CBMEM_ID_MEMINFO 0x494D454D #define CBMEM_ID_MMA_DATA 0x4D4D4144 +#define CBMEM_ID_MMC_STATUS 0x4d4d4353 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_VAR_MRCDATA 0x4d524345 @@ -100,6 +101,7 @@ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_MMA_DATA, "MMA DATA " }, \ + { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 198ad27b876..277b7467fba 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -291,9 +291,9 @@ struct lb_gpios { }; #define LB_TAG_VBNV 0x0019 -#define LB_TAB_VBOOT_HANDOFF 0x0020 -#define LB_TAB_VBOOT_WORKBUF 0x0034 -#define LB_TAB_DMA 0x0022 +#define LB_TAG_VBOOT_HANDOFF 0x0020 +#define LB_TAG_VBOOT_WORKBUF 0x0034 +#define LB_TAG_DMA 0x0022 #define LB_TAG_RAM_OOPS 0x0023 #define LB_TAG_MTC 0x002b struct lb_range { @@ -310,7 +310,7 @@ void lb_ramoops(struct lb_header *header); #define LB_TAG_CBMEM_CONSOLE 0x0017 #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 -#define LB_TAG_TCPA_LOG 0x0034 +#define LB_TAG_TCPA_LOG 0x0036 #define LB_TAG_WIFI_CALIBRATION 0x0027 #define LB_TAG_VPD 0x002c struct lb_cbmem_ref { @@ -385,6 +385,21 @@ struct mac_address { uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ }; +#define LB_TAG_MMC_INFO 0x0035 +struct lb_mmc_info { + uint32_t tag; + uint32_t size; + /* + * Passes the early mmc status to payload to indicate if firmware + * successfully sent CMD0, CMD1 to the card or not. In case of + * success, the payload can skip the first step of the initialization + * sequence which is to send CMD0, and instead start by sending CMD1 + * as described in Jedec Standard JESD83-B1 section 6.4.3. + * passes 1 on success + */ + int32_t early_cmd1_status; +}; + struct lb_macs { uint32_t tag; uint32_t size; diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h index 1a05eebd55d..4a3671c7ab8 100644 --- a/src/commonlib/include/commonlib/stdlib.h +++ b/src/commonlib/include/commonlib/stdlib.h @@ -38,11 +38,11 @@ #if CONFIG(COREBOOT_BUILD) #include #include -#define printf(...) printk(BIOS_ERR, __VA_ARGS__) #define HALT(x) halt() #else #include -#define HALT(x) +#define printk(level, ...) printf(__VA_ARGS__) +#define HALT(x) abort() #endif static inline void *xmalloc_work(size_t size, const char *file, @@ -50,7 +50,7 @@ static inline void *xmalloc_work(size_t size, const char *file, { void *ret = malloc(size); if (!ret && size) { - printf("%s/%s/line %d: Failed to malloc %zu bytes\n", + printk(BIOS_ERR, "%s/%s/line %d: Failed to malloc %zu bytes\n", file, func, line, size); while (1) HALT(1); diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index a2d30949b35..1798c2cac7e 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -18,7 +18,6 @@ #endif #include -#include #include #include #include diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 2e1ae85f06e..06f0156c82e 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -19,7 +19,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index fd59bd0b6fc..348d3fe17d7 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -20,7 +20,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 5c85e99655d..19daa2ee7eb 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include "bouncebuf.h" #include #include diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 1bae3fbff2d..e3209734bab 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -17,9 +17,9 @@ * GNU General Public License for more details. */ -#include #include #include +#include #include #include #include diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index d8ff4bc729d..f434a6c0b69 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -21,7 +21,6 @@ * GNU General Public License for more details. */ -#include #include #include "sd_mmc.h" #include "storage.h" diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d5795d79296..4f0c2ef6139 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,6 +9,7 @@ endif smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +smm-$(CONFIG_SMM_TSEG) += post.c verstage-y += init.c verstage-y += printk.c diff --git a/src/console/die.c b/src/console/die.c index 769e65134f6..513d1c4097a 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -36,4 +36,11 @@ void __noreturn die(const char *msg) die_notify(); halt(); } + +/* Report a fatal error with a post code */ +void __noreturn die_with_post_code(uint8_t value, const char *msg) +{ + post_code(value); + die(msg); +} #endif diff --git a/src/console/post.c b/src/console/post.c index 236aa8cdaad..0719e5e7df8 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -44,7 +44,6 @@ void __weak mainboard_post(uint8_t value) DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE void cmos_post_log(void) { u8 code = 0; @@ -82,7 +81,7 @@ void cmos_post_log(void) default: printk(BIOS_WARNING, "POST: Unexpected post code " "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) +#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); #if CONFIG(CMOS_POST_EXTRA) if (extra) @@ -125,7 +124,6 @@ void post_log_clear(void) post_log_extra(0); } #endif /* CONFIG_CMOS_POST_EXTRA */ -#endif /* ENV_RAMSTAGE */ static void cmos_post_code(u8 value) { diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 043a1dae376..c429ac79e22 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -24,20 +24,6 @@ #define SUPPORT_64BIT_INTS #endif -/* haha, don't need ctype.c */ -#define isdigit(c) ((c) >= '0' && (c) <= '9') -#define is_digit isdigit -#define isxdigit(c) (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) - -static int skip_atoi(const char **s) -{ - int i = 0; - - while (is_digit(**s)) - i = i*10 + *((*s)++) - '0'; - return i; -} - #define ZEROPAD 1 /* pad with zero */ #define SIGN 2 /* unsigned/signed long */ #define PLUS 4 /* show plus */ @@ -56,8 +42,10 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), int count = 0; #ifdef SUPPORT_64BIT_INTS unsigned long long num = inum; + long long snum = num; #else - unsigned long num = (long)inum; + unsigned long num = (unsigned long)inum; + long snum = (long)num; if (num != inum) { /* Alert user to an incorrect result by printing #^!. */ @@ -76,9 +64,9 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), c = (type & ZEROPAD) ? '0' : ' '; sign = 0; if (type & SIGN) { - if ((signed long long)num < 0) { + if (snum < 0) { sign = '-'; - num = -num; + num = -snum; size--; } else if (type & PLUS) { sign = '+'; @@ -173,8 +161,8 @@ int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), /* get field width */ field_width = -1; - if (is_digit(*fmt)) { - field_width = skip_atoi(&fmt); + if (isdigit(*fmt)) { + field_width = skip_atoi((char **)&fmt); } else if (*fmt == '*') { ++fmt; /* it's the next argument */ @@ -189,8 +177,8 @@ int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), precision = -1; if (*fmt == '.') { ++fmt; - if (is_digit(*fmt)) { - precision = skip_atoi(&fmt); + if (isdigit(*fmt)) { + precision = skip_atoi((char **)&fmt); } else if (*fmt == '*') { ++fmt; /* it's the next argument */ diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c index 6e7f9e214a5..01ee5a5c6fa 100644 --- a/src/cpu/allwinner/a10/twi.c +++ b/src/cpu/allwinner/a10/twi.c @@ -20,12 +20,13 @@ * Largely based on the uboot-sunxi code. */ -#include "memmap.h" -#include "twi.h" - #include #include #include +#include + +#include "memmap.h" +#include "twi.h" #define TWI_BASE(n) (A1X_TWI0_BASE + 0x400 * (n)) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 579cae5d1de..2c6e08cf0a3 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,6 +89,7 @@ b.- prep_fid_change(...) */ +#include #include #include #include diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 76bc6d99e50..d6a4725e2ef 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -14,8 +14,11 @@ * GNU General Public License for more details. */ +#include #include #include +#include + #include "init_cpus.h" #if CONFIG(HAVE_OPTION_TABLE) @@ -983,7 +986,6 @@ void cpuSetAMDMSR(uint8_t node_id) uint8_t nvram; u32 platform; uint64_t revision; - uint8_t enable_c_states; uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1059,21 +1061,16 @@ void cpuSetAMDMSR(uint8_t node_id) } if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { - enable_c_states = 0; if (CONFIG(HAVE_ACPI_TABLES)) - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (enable_c_states) { - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); - c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */ - wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); - } + if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && + (nvram)) { + /* Set up the C-state base address */ + msr_t c_state_addr_msr; + c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); + c_state_addr_msr.lo = ACPI_CPU_P_LVL2; + wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); + } } -#else - enable_c_states = 0; #endif if (revision & AMD_FAM15_ALL) { diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index d09fc8241c5..5d653d123b0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -17,7 +17,6 @@ #define INIT_CPUS_H #include -#include #include #include #include diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index d024069e303..e648b717508 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include @@ -30,6 +29,7 @@ #include #include #include +#include static inline uint8_t is_fam15h(void) { diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index ad4a7ead6d1..125876badff 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -95,13 +95,13 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores) */ /* Wait for the first core of each compute unit to start... */ - uint32_t timeout; for (i = 1; i < cores + 1; i++) { if (!(i & 0x1)) { uint32_t ap_apicid = get_boot_apic_id(nodeid, i); - timeout = wait_cpu_state(ap_apicid, - F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); + /* Timeout */ + wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, + F10_APSTATE_ASLEEP); } } diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 73a8bf8474d..3f897407cf4 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -12,7 +12,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index b2b915fe76c..251714cb8f2 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -33,6 +33,11 @@ _cache_as_ram_setup: bootblock_pre_c_entry: +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) + movl $cache_as_ram, %esp /* return address */ + jmp check_mtrr /* Check if CPU properly reset */ +#endif + cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 3aadfdee5a6..5936953b526 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -23,10 +23,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP select CPU_INTEL_COMMON - -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/haswell/bootblock.c" + select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 1fa71c9521d..f83d5db9703 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -21,9 +21,15 @@ ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c endif -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S +bootblock-y += bootblock.c + postcar-y += ../car/non-evict/exit_car.S +verstage-y += tsc_freq.c + subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 722cc0102e0..7baa2a81ec6 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include @@ -23,41 +23,8 @@ #include #include "haswell.h" -#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) -/* Needed for RCBA access to set Soft Reset Data register */ #include -#else -#error "CPU must be paired with Intel LynxPoint southbridge" -#endif - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} +#include static void set_flex_ratio_to_tdp_nominal(void) { @@ -105,26 +72,8 @@ static void set_flex_ratio_to_tdp_nominal(void) halt(); } -static void check_for_clean_reset(void) -{ - msr_t msr; - msr = rdmsr(MTRR_DEF_TYPE_MSR); - - /* Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); - } -} - -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - check_for_clean_reset(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index e634f85fc33..3c3e53a8391 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -17,7 +17,6 @@ #include #include #include -#include #if CONFIG(PARALLEL_CPU_INIT) #error Intel hyper-threading requires serialized CPU init diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 9481917ff8d..d8c016867cb 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,9 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select NO_FIXED_XIP_ROM_SIZE + select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_CPU_INIT string @@ -28,8 +31,8 @@ config SMM_TSEG_SIZE hex default 0x800000 -config XIP_ROM_SIZE +config SMM_RESERVED_SIZE hex - default 0x20000 + default 0x100000 endif diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 043141ac188..39246c07082 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -19,6 +19,10 @@ ramstage-y += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +romstage-y += stage_cache.c +ramstage-y += stage_cache.c +postcar-y += stage_cache.c + cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 1e6a3119100..e7ba2a771b4 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,6 +20,7 @@ /* Nehalem bus clock is fixed at 133MHz */ #define NEHALEM_BCLK 133 +#define CORE_THREAD_COUNT_MSR 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) @@ -79,4 +80,22 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif +/* + * Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. + */ +#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE +#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE) + +/* Sanity check config options. */ +#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE" +#endif +#if (CONFIG_SMM_TSEG_SIZE < 0x800000) +# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" +#endif +#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) +# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#endif + #endif diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f08a058a57e..d8de7c055f1 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -109,29 +111,6 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -int cpu_get_apic_id_map(int *apic_id_map) -{ - int i; - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; ++i) { - apic_id_map[i] = (i % threads_per_core) - + ((i / threads_per_core) << 2); - } - - return threads_per_package; -} - - int cpu_config_tdp_levels(void) { msr_t platform_info; @@ -250,58 +229,6 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(struct device *cpu) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - struct device *new; - - /* Build the CPU device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + (i % threads_per_core) - + ((i / threads_per_core) << 2); - - /* Allocate the new CPU device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new CPU */ - if (is_smp_boot() && !start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - static void model_2065x_init(struct device *cpu) { char processor_name[49]; @@ -309,8 +236,6 @@ static void model_2065x_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - intel_update_microcode_from_cbfs(); - /* Clear out pending MCEs */ configure_mca(); @@ -320,10 +245,6 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid(), boot_cpu()); - /* Setup MTRRs based on physical address size */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT @@ -348,9 +269,75 @@ static void model_2065x_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); +} - /* Start up extra cores */ - intel_cores_init(cpu); +/* MP initialization support. */ +static const void *microcode_patch; + +static void pre_mp_init(void) +{ + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + msr_t msr; + int num_threads; + int num_cores; + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + return num_threads; +} + +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} + +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + southbridge_smm_init(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void bsp_init_and_start_aps(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c new file mode 100644 index 00000000000..ab8ac979c16 --- /dev/null +++ b/src/cpu/intel/model_2065x/stage_cache.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "model_2065x.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = RESERVED_SMM_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + RESERVED_SMM_OFFSET); +} diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 7f73da9ab4e..dbb89821215 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,10 +1,7 @@ config CPU_INTEL_MODEL_206AX bool -config CPU_INTEL_MODEL_306AX - bool - -if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX +if CPU_INTEL_MODEL_206AX config CPU_SPECIFIC_OPTIONS def_bool y @@ -25,15 +22,12 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP + select NO_FIXED_XIP_ROM_SIZE config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_206ax/bootblock.c" -config XIP_ROM_SIZE - hex - default 0x20000 if USE_NATIVE_RAMINIT - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 85b0937b9c9..524e49c5c60 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 6d08bb36844..05c507c09c2 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -17,11 +17,8 @@ void bsp_init_and_start_aps(struct bus *cpu_bus); /* These helpers are for performing SMM relocation. */ void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); u32 northbridge_get_tseg_base(void); u32 northbridge_get_tseg_size(void); -int cpu_get_apic_id_map(int *apic_id_map); void northbridge_write_smram(u8 smram); bool cpu_has_alternative_smrr(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index cc2a8952ca7..f3192bcd554 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -100,60 +100,6 @@ static void write_smrr(struct smm_relocation_params *relo_params) } } -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -static void asmlinkage cpu_smm_do_relocation(void *arg) -{ - em64t101_smm_state_save_area_t *save_state; - msr_t mtrr_cap; - struct smm_relocation_params *relo_params; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - relo_params = p->arg; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } - - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - - /* All threads need to set IEDBASE and SMBASE in the save state area. - * Since one thread runs at a time during the relocation the save state - * is the same for all cpus. */ - save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - save_state->smbase = relo_params->smram_base - - cpu * runtime->save_state_size; - if (CONFIG_IED_REGION_SIZE != 0) { - save_state->iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", - save_state->smbase, save_state->iedbase, save_state); - } else { - printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n", - save_state->smbase, save_state); - } - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0) - write_smrr(relo_params); - - southbridge_clear_smi_status(); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { /* All range registers are aligned to 4KiB */ @@ -202,33 +148,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) } } -static int install_relocation_handler(int *apic_id_map, int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* The default SMM entry happens serially at the default location. - * Therefore, there is only 1 concurrent save state area. Set the - * stack size to the save state size, and call into the - * do_relocation handler. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = &cpu_smm_do_relocation, - .handler_arg = (void *)relo_params, - }; - - default_smm_area = backup_default_smm_area(); - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - int i; - for (i = 0; i < num_cpus; i++) - smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - return 0; -} - static void setup_ied_area(struct smm_relocation_params *params) { char *ied_base; @@ -248,94 +167,6 @@ static void setup_ied_area(struct smm_relocation_params *params) memset(ied_base + (1 << 20), 0, (32 << 10)); } -static int install_permanent_handler(int *apic_id_map, int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); - if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) - return -1; - int i; - for (i = 0; i < num_cpus; i++) - smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - return 0; -} - -static int cpu_smm_setup(void) -{ - int num_cpus; - int apic_id_map[CONFIG_MAX_CPUS]; - - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - /* enable the SMM memory window */ - northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG); - - if (CONFIG_IED_REGION_SIZE != 0) - setup_ied_area(&smm_reloc_params); - - num_cpus = cpu_get_apic_id_map(apic_id_map); - if (num_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); - } - - if (install_relocation_handler(apic_id_map, num_cpus, - &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); - return -1; - } - - if (install_permanent_handler(apic_id_map, num_cpus, - &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); - return -1; - } - - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - /* TODO(adurbin): Is this really needed? */ - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - northbridge_write_smram(G_SMRAME | C_BASE_SEG); - - return 0; -} - -void smm_init(void) -{ - /* Return early if CPU SMM setup failed. */ - if (cpu_smm_setup()) - return; - - southbridge_smm_init(); - - /* Initiate first SMI to kick off SMM-context relocation. Note: this - * SMI being triggered here queues up an SMI in the APs which are in - * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI - * at the SMM_DEFAULT_BASE before jumping to startup vector. */ - southbridge_trigger_smi(); - - printk(BIOS_DEBUG, "Relocation complete.\n"); - - /* Lock down the SMRAM space. */ - smm_lock(); -} - void smm_init_completion(void) { restore_default_smm_area(default_smm_area); diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 6566a01cf81..d3af4ca3cc4 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS select MMX select SSE select CPU_HAS_L2_ENABLE_MSR + select NO_FIXED_XIP_ROM_SIZE config DCACHE_RAM_BASE hex @@ -20,4 +21,11 @@ config DCACHE_RAM_SIZE hex default 0x4000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + endif diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 868f6e56085..c95e135bb5f 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,9 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 5cff4125ae1..7111f5efd5e 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -40,29 +41,6 @@ static int determine_total_number_of_cores(void) return count; } -/** - * @brief Returns three times the FSB clock in MHz - * - * The result of calculations with the returned value shall be divided by 3. - * This helps to avoid rounding errors. - */ -static int get_fsb(void) -{ - const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; - switch (fsbcode) { - case 0: return 800; /* / 3 == 266 */ - case 1: return 400; /* / 3 == 133 */ - case 2: return 600; /* / 3 == 200 */ - case 3: return 500; /* / 3 == 166 */ - case 4: return 1000; /* / 3 == 333 */ - case 5: return 300; /* / 3 == 100 */ - case 6: return 1200; /* / 3 == 400 */ - } - printk(BIOS_WARNING, - "Warning: No supported FSB frequency. Assuming 200MHz\n"); - return 600; -} - static void gen_pstate_entries(const sst_table_t *const pstates, const int cpuID, const int cores_per_package, const uint8_t coordination) @@ -75,7 +53,12 @@ static void gen_pstate_entries(const sst_table_t *const pstates, cpuID, cores_per_package, coordination); acpigen_write_name("_PSS"); - const int fsb3 = get_fsb(); + int fsb3 = get_ia32_fsb_x3(); + if (fsb3 <= 0) { + printk(BIOS_ERR, "CPU or FSB not supported. Assuming 200MHz\n"); + fsb3 = 600; + } + const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO( pstates->states[pstates->num_states - 1]); const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 232fe63f32f..608afd7a28c 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -151,13 +151,6 @@ config X86_AMD_FIXED_MTRRS This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config PLATFORM_USES_FSP1_0 - bool - default n - help - Selected for Intel processors/platform combinations that use the - Intel Firmware Support Package (FSP) 1.0 for initialization. - config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S new file mode 100644 index 00000000000..ec015abe22e --- /dev/null +++ b/src/cpu/x86/early_reset.S @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * input %esp: return address (not pointer to return address!) + * clobber the content of eax, ecx, edx + */ + +#include + +.section .text +.global check_mtrr + +check_mtrr: + /* Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. */ + +check_for_clean_reset: + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jnz warm_reset + jmp *%esp + /* perform warm reset */ +warm_reset: + movw $0xcf9, %dx + movb $0x06, %al + outb %al, %dx + /* Should not reach this*/ +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 8cd3092b247..755fbe220d7 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -24,7 +24,7 @@ void do_lapic_init(void) * see the Intel mp1.4 spec, page A-3 */ - printk(BIOS_INFO, "Setting up local APIC..."); + printk(BIOS_INFO, "Setting up local APIC...\n"); /* Enable the local APIC */ enable_lapic(); diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 3ad1f0a0557..0f73e71331e 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -291,6 +291,7 @@ int start_cpu(struct device *cpu) info = (struct cpu_info *)stack_top; info->index = index; info->cpu = cpu; + cpu_add_map_entry(info->index); thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ @@ -549,6 +550,7 @@ void initialize_cpus(struct bus *cpu_bus) /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); + cpu_add_map_entry(info->index); // why here? In case some day we can start core1 in amd_sibling_init if (is_smp_boot()) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9d51b3e8b56..b7b8fe2afaf 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -135,20 +135,8 @@ struct mp_flight_plan { static int global_num_aps; static struct mp_flight_plan mp_info; -struct cpu_map { - struct device *dev; - /* Keep track of default apic ids for SMM. */ - int default_apic_id; -}; - -/* Keep track of APIC and device structure for each CPU. */ -static struct cpu_map cpus[CONFIG_MAX_CPUS]; - -static inline void add_cpu_map_entry(const struct cpu_info *info) -{ - cpus[info->index].dev = info->cpu; - cpus[info->index].default_apic_id = cpuid_ebx(1) >> 24; -} +/* Keep track of device structure for each CPU. */ +static struct device *cpus_dev[CONFIG_MAX_CPUS]; static inline void barrier_wait(atomic_t *b) { @@ -212,9 +200,9 @@ static void asmlinkage ap_init(unsigned int cpu) info = cpu_info(); info->index = cpu; - info->cpu = cpus[cpu].dev; + info->cpu = cpus_dev[cpu]; - add_cpu_map_entry(info); + cpu_add_map_entry(info->index); thread_init_cpu_info_non_bsp(info); /* Fix up APIC id with reality. */ @@ -411,7 +399,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) continue; } new->name = processor_name; - cpus[i].dev = new; + cpus_dev[i] = new; } return max_cpus; @@ -589,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); /* Track BSP in cpu_map structures. */ - add_cpu_map_entry(info); + cpu_add_map_entry(info->index); } /* @@ -667,15 +655,6 @@ static void mp_initialize_cpu(void) cpu_initialize(info->index); } -/* Returns APIC id for coreboot CPU number or < 0 on failure. */ -int mp_get_apic_id(int logical_cpu) -{ - if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) - return -1; - - return cpus[logical_cpu].default_apic_id; -} - void smm_initiate_relocation_parallel(void) { if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { @@ -769,7 +748,7 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) struct smm_runtime *runtime = smm_params->runtime; for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); + runtime->apic_id_to_cpu[i] = cpu_get_apic_id(i); } static int install_relocation_handler(int num_cpus, size_t save_state_size) @@ -891,13 +870,20 @@ static int run_ap_work(struct mp_callback *val, long expire_us) int i; int cpus_accepted; struct stopwatch sw; - int cur_cpu = cpu_index(); + int cur_cpu; if (!CONFIG(PARALLEL_MP_AP_WORK)) { printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n"); return -1; } + cur_cpu = cpu_index(); + + if (cur_cpu < 0) { + printk(BIOS_ERR, "Invalid CPU index.\n"); + return -1; + } + /* Signal to all the APs to run the func. */ for (i = 0; i < ARRAY_SIZE(ap_callbacks); i++) { if (cur_cpu == i) @@ -939,6 +925,12 @@ static void ap_wait_for_instruction(void) return; cur_cpu = cpu_index(); + + if (cur_cpu < 0) { + printk(BIOS_ERR, "Invalid CPU index.\n"); + return; + } + per_cpu_slot = &ap_callbacks[cur_cpu]; while (1) { diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d87c3d43d30..60eee319cee 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -331,7 +331,6 @@ static void commit_fixed_mtrrs(void) desc = &fixed_mtrr_desc[i]; num_ranges = (desc->end - desc->begin) / desc->step; - ASSERT(num_ranges > 0); for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { msr_index[msr_num] = desc->msr_index_base + (j / RANGES_PER_FIXED_MTRR); @@ -355,6 +354,9 @@ static void commit_fixed_mtrrs(void) } } + /* Ensure that both arrays were fully initialized */ + ASSERT(msr_num == NUM_FIXED_MTRRS) + for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 062ee402f12..9c921342f10 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -116,12 +116,12 @@ void *map_2M_page(unsigned long page) static struct pg_table pgtbl[CONFIG_MAX_CPUS] __attribute__((aligned(4096))); static unsigned long mapped_window[CONFIG_MAX_CPUS]; - unsigned long index; + int index; unsigned long window; void *result; int i; index = cpu_index(); - if (index >= CONFIG_MAX_CPUS) + if (index < 0) return MAPPING_ERROR; window = page >> 10; if (window != mapped_window[index]) { diff --git a/src/device/device.c b/src/device/device.c index 1b4255bffe7..17cd8f4ab82 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -340,6 +340,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, resource_t base; base = round(bridge->base, bridge->align); + if (!bus) + return; + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), base, bridge->size, bridge->align, @@ -484,6 +487,9 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, resource_t base; base = bridge->base; + if (!bus) + return; + printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " "limit:%llx\n", dev_path(bus->dev), resource2str(bridge), diff --git a/src/device/device_util.c b/src/device/device_util.c index 5c4f911b8b3..47df3052e24 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -628,7 +628,7 @@ void disable_children(struct bus *bus) /* * Returns true if the device is an enabled bridge that has at least - * one enabled device on its secondary bus. + * one enabled device on its secondary bus that is not of type NONE. */ bool dev_is_active_bridge(struct device *dev) { @@ -643,6 +643,9 @@ bool dev_is_active_bridge(struct device *dev) for (link = dev->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_NONE) + continue; + if (child->enabled) return 1; } diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 53106f23f9b..60588b880bb 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -26,6 +26,7 @@ #include #include #include +#include /*============================================================================== * = DDR2 SPD decoding helpers diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index f27fdcb1e01..3272dac6d72 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -27,6 +27,7 @@ #include #include #include +#include /*============================================================================== * = DDR3 SPD decoding helpers @@ -136,7 +137,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) u8 reg8; u32 mtb; /* medium time base */ u32 ftb; /* fine time base */ - unsigned int val, param; + unsigned int val; ret = SPD_STATUS_OK; @@ -173,8 +174,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) printram(" Invalid number of memory banks\n"); ret = SPD_STATUS_INVALID_FIELD; } - param = 1 << (val + 3); - printram(" Banks : %u\n", param); + printram(" Banks : %u\n", 1 << (val + 3)); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; if (capacity_shift > 0x06) { diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index fa23e55cd30..4ae82d96ff5 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -42,7 +42,6 @@ #define __X86EMU_X86EMU_H #include -#include #if CONFIG(X86EMU_DEBUG) #define DEBUG #endif diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index f89d5abc4aa..01f633cb5c1 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -39,6 +39,8 @@ #ifndef __X86EMU_DEBUG_H #define __X86EMU_DEBUG_H +#include + /*---------------------- Macros and type definitions ----------------------*/ /* printf is not available in coreboot... use printk */ diff --git a/src/device/pci_device.c b/src/device/pci_device.c index b5453c7e76b..31c35dc02ea 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -780,9 +780,6 @@ static int should_run_oprom(struct device *dev) */ should_run = display_init_required(); - if (!should_run && CONFIG(VBOOT)) - should_run = vboot_wants_oprom(); - if (!should_run) printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); return should_run; diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 92ccff8b73a..fa41500e409 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -15,6 +15,7 @@ */ #include +#include #include #include diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 6cfcde520b7..887da308d4e 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016-2019 Kyösti Mälkki + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,62 +16,126 @@ #include #include #include +#include #include #include #include +#include #include #include -#include - static const char undefined[] = "undefined"; -/* Match order of enum AGESA_STRUCT_NAME. */ -static const char *AgesaFunctionNameStr[] = { - "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", - "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", - "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", +struct agesa_mapping +{ + AGESA_STRUCT_NAME func; + const char *name; + uint32_t entry_id; + uint32_t exit_id; }; -/* heapManager.h */ -static const char *HeapStatusStr[] = { - "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +static const struct agesa_mapping entrypoint[] = { + { + .func = AMD_INIT_RESET, + .name = "AmdInitReset", + .entry_id = TS_AGESA_INIT_RESET_START, + .exit_id = TS_AGESA_INIT_RESET_DONE, + }, + { + .func = AMD_INIT_EARLY, + .name = "AmdInitEarly", + .entry_id = TS_AGESA_INIT_EARLY_START, + .exit_id = TS_AGESA_INIT_EARLY_DONE, + }, + { + .func = AMD_INIT_POST, + .name = "AmdInitPost", + .entry_id = TS_AGESA_INIT_POST_START, + .exit_id = TS_AGESA_INIT_POST_DONE, + }, + { + .func = AMD_INIT_RESUME, + .name = "AmdInitResume", + .entry_id = TS_AGESA_INIT_RESUME_START, + .exit_id = TS_AGESA_INIT_RESUME_DONE, + }, + { + .func = AMD_INIT_ENV, + .name = "AmdInitEnv", + .entry_id = TS_AGESA_INIT_ENV_START, + .exit_id = TS_AGESA_INIT_ENV_DONE, + }, + { + .func = AMD_INIT_MID, + .name = "AmdInitMid", + .entry_id = TS_AGESA_INIT_MID_START, + .exit_id = TS_AGESA_INIT_MID_DONE, + }, + { + .func = AMD_INIT_LATE, + .name = "AmdInitLate", + .entry_id = TS_AGESA_INIT_LATE_START, + .exit_id = TS_AGESA_INIT_LATE_DONE, + }, + { + .func = AMD_S3LATE_RESTORE, + .name = "AmdS3LateRestore", + .entry_id = TS_AGESA_S3_LATE_START, + .exit_id = TS_AGESA_S3_LATE_DONE, + }, +#if !defined(AMD_S3_SAVE_REMOVED) + { + .func = AMD_S3_SAVE, + .name = "AmdS3Save", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, + }, +#endif + { + .func = AMD_S3FINAL_RESTORE, + .name = "AmdS3FinalRestore", + .entry_id = TS_AGESA_S3_FINAL_START, + .exit_id = TS_AGESA_S3_FINAL_DONE, + }, + { + .func = AMD_INIT_RTB, + .name = "AmdInitRtb", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, + }, }; -/* This function has to match with enumeration of AGESA_STRUCT_NAME defined - * inside AMD.h header file. Unfortunately those are different across - * different vendorcode subtrees. - * - * TBD: Fix said header or move this function together with the strings above - * under vendorcode/ tree. - */ - -const char *agesa_struct_name(int state) +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) { -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) - if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) - return undefined; - - int index = state - AMD_INIT_RECOVERY; -#else - state >>= 12; - if ((state < AMD_INIT_RECOVERY >> 12) || (state > AMD_IDENTIFY_DIMMS >> 12)) - return undefined; + int i; + + task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->func = func; + task->function_name = undefined; + + for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { + if (task->func == entrypoint[i].func) { + task->function_name = entrypoint[i].name; + task->ts_entry_id = entrypoint[i].entry_id; + task->ts_exit_id = entrypoint[i].exit_id; + break; + } + } - int index = state - (AMD_INIT_RECOVERY >> 12); -#endif - return AgesaFunctionNameStr[index]; + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + task->apic_id, task->function_name, task->func); } -const char *heap_status_name(int status) +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader) { - if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) - return undefined; + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + task->apic_id, heap_status_name(StdHeader->HeapStatus), + StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); - int index = status - HEAP_DO_NOT_EXIST_YET; - return HeapStatusStr[index]; + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + task->apic_id, task->function_name, task->func); } /* diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index a38696fc0f3..513e8049b13 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -20,6 +20,7 @@ #include #include +#include #include /* BIOS_HEAP_START_ADDRESS is only for cold boots. */ diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 586189b406c..acd34b8edfc 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index d5b20b76f93..adf6e0d0e32 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -90,8 +90,6 @@ void *asmlinkage romstage_main(unsigned long bist) else agesa_execute_state(cb, AMD_INIT_RESUME); - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); timestamp_add_now(TS_AFTER_INITRAM); /* Work around AGESA setting all memory as WB on normal diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index c6e36b22595..c8529c5e048 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -16,11 +16,12 @@ #include #include - #include #include #include #include +#include +#include #include #include @@ -148,6 +149,11 @@ static AGESA_STATUS romstage_dispatch(struct sysinfo *cb, platform_BeforeInitPost(cb, param); board_BeforeInitPost(cb, param); status = module_dispatch(func, StdHeader); + + /* FIXME: Detect if TSC frequency really + * changed during raminit? */ + timestamp_rescale_table(1, 4); + platform_AfterInitPost(cb, param); break; } @@ -157,6 +163,11 @@ static AGESA_STATUS romstage_dispatch(struct sysinfo *cb, AMD_RESUME_PARAMS *param = (void *)StdHeader; platform_BeforeInitResume(cb, param); status = module_dispatch(func, StdHeader); + + /* FIXME: Detect if TSC frequency really + * changed during raminit? */ + timestamp_rescale_table(1, 4); + platform_AfterInitResume(cb, param); break; } @@ -231,38 +242,6 @@ static AGESA_STATUS ramstage_dispatch(struct sysinfo *cb, return status; } -/* DEBUG trace helper */ - -struct agesa_state -{ - u8 apic_id; - - AGESA_STRUCT_NAME func; - const char *function_name; -}; - -static void state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func, - const char *struct_name) -{ - task->apic_id = (u8) (cpuid_ebx(1) >> 24); - task->func = func; - task->function_name = struct_name; - - printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - -static void state_on_exit(struct agesa_state *task, - AMD_CONFIG_PARAMS *StdHeader) -{ - printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", - task->apic_id, heap_status_name(StdHeader->HeapStatus), - StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); - - printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) { AMD_INTERFACE_PARAMS aip; @@ -272,13 +251,12 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) } agesa_params; void *buf = NULL; size_t len = 0; - const char *state_name = agesa_struct_name(func); AGESA_STATUS status, final; struct agesa_state task; memset(&task, 0, sizeof(task)); - state_on_entry(&task, func, state_name); + agesa_state_on_entry(&task, func); aip.StdHeader = cb->StdHeader; @@ -296,19 +274,25 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) AMD_CONFIG_PARAMS *StdHeader = aip.NewStructPtr; ASSERT(StdHeader->Func == func); + if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id) + timestamp_add_now(task.ts_entry_id); + if (ENV_ROMSTAGE) final = romstage_dispatch(cb, func, StdHeader); if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); - agesawrapper_trace(final, StdHeader, state_name); + if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_exit_id) + timestamp_add_now(task.ts_exit_id); + + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); status = amd_release_struct(&aip); ASSERT(status == AGESA_SUCCESS); - state_on_exit(&task, &aip.StdHeader); + agesa_state_on_exit(&task, &aip.StdHeader); return (final < AGESA_FATAL) ? 0 : -1; } diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 631372d4289..21af5c7c80d 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -37,13 +37,12 @@ static void aspeed_ast2050_set_resources(struct device *dev) static void aspeed_ast2050_init(struct device *dev) { - u8 ret; struct drm_device drm_dev; drm_dev.pdev = dev; printk(BIOS_INFO, "ASpeed AST2050: initializing video device\n"); - ret = ast_driver_load(&drm_dev, 0); + ast_driver_load(&drm_dev, 0); /* Unlock extended configuration registers */ outb(0x80, 0x3d4); outb(0xa8, 0x3d5); diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 85b79983a57..e41b55bba5f 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -797,7 +797,7 @@ static bool elog_do_add_boot_count(void) #endif } -static void ramstage_elog_add_boot_count(void) +static void elog_add_boot_count(void) { if (elog_do_add_boot_count()) { elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); @@ -860,7 +860,7 @@ int elog_init(void) es->full_threshold, es->shrink_size); if (ENV_RAMSTAGE) - ramstage_elog_add_boot_count(); + elog_add_boot_count(); return 0; } diff --git a/src/drivers/emulation/qemu/qemu_debugcon.c b/src/drivers/emulation/qemu/qemu_debugcon.c index 3807524c5cb..b040bd83882 100644 --- a/src/drivers/emulation/qemu/qemu_debugcon.c +++ b/src/drivers/emulation/qemu/qemu_debugcon.c @@ -17,14 +17,13 @@ #include #include #include -#include -static int qemu_debugcon_detected CAR_GLOBAL; +static int qemu_debugcon_detected; void qemu_debugcon_init(void) { int detected = (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9); - car_set_var(qemu_debugcon_detected, detected); + qemu_debugcon_detected = detected; printk(BIOS_INFO, "QEMU debugcon %s [port 0x%x]\n", detected ? "detected" : "not found", CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); @@ -32,6 +31,6 @@ void qemu_debugcon_init(void) void qemu_debugcon_tx_byte(unsigned char data) { - if (car_get_var(qemu_debugcon_detected) != 0) + if (qemu_debugcon_detected != 0) outb(data, CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); } diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index 3183bf1a845..ecea513bfb3 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#include + enum { BH720_PROTECT = 0xd0, BH720_PROTECT_LOCK_OFF = 0, diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 6e18a8a1b09..2cf8f28e0b0 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 3b335252bbe..3b7718c6f0a 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 1408dacca61..838491dc84e 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -36,9 +36,14 @@ static void max98357a_fill_ssdt(struct device *dev) if (!dev->enabled || !config) return; + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + /* Device */ - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index d570892c1d0..035e5633c6e 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -18,6 +18,8 @@ #include #include #include "chip.h" +#include +#include #if CONFIG(HAVE_ACPI_TABLES) static void i2c_hid_fill_dsm(struct device *dev) @@ -60,6 +62,23 @@ static void i2c_hid_enable(struct device *dev) { struct drivers_i2c_hid_config *config = dev->chip_info; + if (!config) + return; + + /* Check if device is present by reading GPIO */ + if (config->generic.device_present_gpio) { + int present = gpio_get(config->generic.device_present_gpio); + present ^= config->generic.device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + dev->ops = &i2c_hid_ops; if (config && config->generic.desc) { diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 4ce528fb77d..361dd5ea851 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -13,6 +13,13 @@ ## GNU General Public License for more details. ## +config PLATFORM_USES_FSP1_0 + bool + default n + help + Selected for Intel processors/platform combinations that use the + Intel Firmware Support Package (FSP) 1.0 for initialization. + if PLATFORM_USES_FSP1_0 comment "Intel FSP" diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e0da19e8ac0..e09bbd9b655 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -17,6 +17,8 @@ #define FSP_UTIL_H #include +#include + #include "fsp_values.h" #if CONFIG(ENABLE_MRC_CACHE) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 2575577ba46..da9e1888e9c 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -18,6 +18,8 @@ config PLATFORM_USES_FSP1_1 bool select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select POSTCAR_STAGE + select POSTCAR_CONSOLE help Does the code require the Intel Firmware Support Package? @@ -25,8 +27,14 @@ if PLATFORM_USES_FSP1_1 comment "Intel FSP 1.1" +config FSP_USE_REPO + bool "Use FSP binary from 3rdparty/fsp repo" + select HAVE_FSP_BIN + depends on SOC_INTEL_BRASWELL && !USE_GOOGLE_FSP + default y + config HAVE_FSP_BIN - bool "Should the Intel FSP binary be added to the flash image" + bool "Add Intel FSP binary to flash image" help Select this option to add an Intel FSP binary to the resulting coreboot image. @@ -34,6 +42,25 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot +config FSP_FILE + string + prompt "Intel FSP binary path and filename" if !FSP_USE_REPO + depends on HAVE_FSP_BIN + default "3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd" if FSP_USE_REPO + default "" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_LOC + hex "Intel FSP Binary location in CBFS" + default 0xfff6e000 if SOC_INTEL_BRASWELL && USE_GOOGLE_FSP + default 0xfff20000 if SOC_INTEL_BRASWELL + default 0xffee0000 if SOC_INTEL_SKYLAKE + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0x0 @@ -47,19 +74,6 @@ config CPU_MICROCODE_CBFS_LOC The location (base address) in CBFS that contains the microcode update binary. -config FSP_FILE - string "Intel FSP binary path and filename" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex "Intel FSP Binary location in CBFS" - default 0xffee0000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - config DISPLAY_HOBS bool "Display hand-off-blocks (HOBs)" default n diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4ffed..93f3b59d4b3 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c @@ -45,6 +44,13 @@ CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc +postcar-y += stage_cache.c +ifneq ($(CONFIG_SKIP_FSP_CAR),y) +postcar-y += temp_ram_exit.c +postcar-y += exit_car.S +endif +postcar-y += fsp_util.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S deleted file mode 100644 index 3f2a7ae02f2..00000000000 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ /dev/null @@ -1,170 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/* - * This is the common entry point after DRAM has been initialized. - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - -#if CONFIG(SKIP_FSP_CAR) - - /* chipset_teardown_car() is expected to disable cache-as-ram. */ - call chipset_teardown_car - -#else -.extern fih_car - - post_code(POST_FSP_TEMP_RAM_EXIT) - - /* Calculate TempRamExit entry into FSP */ - movl fih_car, %ebp - mov 0x40(%ebp), %eax - add 0x1c(%ebp), %eax - - /* Build the call frame */ - pushl $0 - - /* Call TempRamExit */ - call *%eax - add $4, %esp - cmp $0, %eax - jz 1f - /* - * Failures for post code BC - failed in TempRamExit - * - * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. - */ - movb $0xBC, %ah - jmp .Lhlt -1: -#endif - /* Display the MTRRs */ - call display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - -#if CONFIG(SOC_SETS_MSRS) - push %esp - call soc_set_mtrrs - - /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ - movl %eax, %esp -#else - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - -#if CONFIG(SOC_SETS_MSRS) - call soc_enable_mtrrs -#else - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call after_cache_as_ram diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 48fcb8f39f2..493dbc8d04c 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,19 +24,18 @@ * performs the final stage of initialization. */ - -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 * * Shift values to release MM2. - * mm0 -> edi: BIST value + * mm0 -> ebx: BIST value * mm1 -> mm0: low 32-bits of TSC value * mm2 -> mm1: high 32-bits of TSC value */ - movd %mm0, %edi + movd %mm0, %ebx movd %mm1, %eax movd %eax, %mm0 movd %mm2, %eax @@ -80,8 +79,8 @@ find_fsp_ret: /* * BIST value is zero * eax: TempRamInitApi address + * ebx: BIST value * ebp: FSP_INFO_HEADER address - * edi: BIST value * esi: Not used * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value @@ -91,13 +90,12 @@ find_fsp_ret: jmp *%eax CAR_init_done: - addl $4, %esp /* * ebp: FSP_INFO_HEADER address + * ebx: BIST value * ecx: Temp RAM base * edx: Temp RAM top - * edi: BIST value * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ @@ -110,49 +108,42 @@ CAR_init_done: /* * ebp: FSP_INFO_HEADER address + * ebx: BIST value * ecx: Temp RAM base * edx: Temp RAM top - * edi: BIST value * esp: Top of stack in temp RAM * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - /* Create cache_as_ram_params on stack */ - pushl %edx /* bootloader CAR end */ - pushl %ecx /* bootloader CAR begin */ - pushl %ebp /* FSP_INFO_HEADER */ - pushl %edi /* bist */ - movd %mm1, %eax - pushl %eax /* tsc[63:32] */ - movd %mm0, %eax - pushl %eax /* tsc[31:0] */ - pushl %esp /* pointer to cache_as_ram_params */ - - /* Save FSP_INFO_HEADER location in ebx */ - mov %ebp, %ebx - /* coreboot assumes stack/heap region will be zero */ cld movl %ecx, %edi neg %ecx - /* Only clear up to current stack value. */ - add %esp, %ecx + /* Clear up to Temp Ram top. */ + add %edx, %ecx shrl $2, %ecx xorl %eax, %eax rep stosl + /* Need to align stack to 16 bytes at call instruction. Account for + the pushes below. */ + andl $0xfffffff0, %esp + subl $4, %esp + + /* Push BIST and initial timestamp on the stack */ + pushl %ebx /* bist */ + movd %mm1, %eax + pushl %eax /* tsc[63:32] */ + movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + before_romstage: post_code(0x2A) - /* Call cache_as_ram_main(struct cache_as_ram_params *) */ - call cache_as_ram_main - -/* One will never return from cache_as_ram_main() in verstage so there's - * no such thing as after RAM init. */ -#if !ENV_VERSTAGE -#include "after_raminit.S" -#endif + /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) + in cpu/intel/car/romstage.c */ + call bootblock_c_entry_bist movb $0x69, %ah jmp .Lhlt @@ -165,8 +156,8 @@ halt1: * 0x01 - FV signature, "_FVH" not present * 0x02 - FFS GUID not present * 0x03 - FSP INFO Header not found - * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to - * a different location, or does it need to be? + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased + * to a different location, or does it need to be? * 0x05 - FSP INFO Header signature "FSPH" not found * 0x06 - FSP Image ID is not the expected ID. */ @@ -181,7 +172,8 @@ halt2: * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode + * region. * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked */ movb $0xBB, %ah @@ -213,7 +205,7 @@ CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ - .long CONFIG_ROM_SIZE /* Total Firmware Length */ + .long CONFIG_ROM_SIZE /* Firmware Length */ CAR_init_stack: .long CAR_init_done diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 3a41e404687..dd17664036d 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -13,118 +13,117 @@ * GNU General Public License for more details. */ -#include +#include #include +#include #include #include #include +#include #include #include -FSP_INFO_HEADER *fih_car CAR_GLOBAL; +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* Save FSP_INFO_HEADER for TempRamExit() call in assembly. */ -static inline void set_fih_car(FSP_INFO_HEADER *fih) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { - /* This variable is written in the raw form because it's only - * ever accessed in code that that has the cache-as-ram enabled. The - * assembly routine which tears down cache-as-ram utilizes this - * variable for determining where to find FSP. */ - fih_car = fih; -} - -asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) -{ - int i; - const int num_guards = 4; - const u32 stack_guard = 0xdeadbeef; - u32 *stack_base; - void *ram_stack; - u32 size; - - /* Size of unallocated CAR. */ - size = _car_region_end - _car_relocatable_data_end; - size = ALIGN_DOWN(size, 16); - - stack_base = (u32 *) (_car_region_end - size); - - for (i = 0; i < num_guards; i++) - stack_base[i] = stack_guard; - - /* Initialize timestamp book keeping only once. */ - timestamp_init(car_params->tsc); - - /* Call into pre-console init code then initialize console. */ - car_soc_pre_console_init(); - car_mainboard_pre_console_init(); - console_init(); - - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); - - display_mtrrs(); - - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - car_params->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); - } - - car_soc_post_console_init(); - car_mainboard_post_console_init(); - - set_fih_car(car_params->fih); - - /* Return new stack value in RAM back to assembly stub. */ - ram_stack = cache_as_ram_stage_main(car_params->fih); - - /* Check the stack. */ - for (i = 0; i < num_guards; i++) { - if (stack_base[i] == stack_guard) - continue; - printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + struct postcar_frame pcf; + size_t alignment; + uint32_t aligned_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By + * setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, + MTRR_TYPE_WRBACK); } - return ram_stack; + run_postcar_phase(&pcf); } -/* Entry point taken when romstage is called after a separate verstage. */ -asmlinkage void *romstage_c_entry(void) +/* This is the romstage entry called from cpu/intel/car/romstage.c */ +void mainboard_romstage_entry(unsigned long bist) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ - FSP_INFO_HEADER *fih; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - console_init(); + if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { + /* Call into pre-console init code then initialize console. */ + car_soc_pre_console_init(); + car_mainboard_pre_console_init(); + console_init(); - if (prog_locate(&fsp)) { - fih = NULL; - printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); - } else - /* This leaks a mapping which this code assumes is benign as - * the flash is memory mapped CPU's address space. */ - fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); + display_mtrrs(); - set_fih_car(fih); + car_soc_post_console_init(); + car_mainboard_post_console_init(); + } - /* Return new stack value in RAM back to assembly stub. */ - return cache_as_ram_stage_main(fih); -} + if (prog_locate(&fsp)) + die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); -asmlinkage void after_cache_as_ram(void *chipset_context) -{ - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); - printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - display_mtrrs(); + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); + + if (!fih) + die("Invalid FSP header\n"); - after_cache_as_ram_stage(); + cache_as_ram_stage_main(fih); } void __weak car_mainboard_pre_console_init(void) diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S new file mode 100644 index 00000000000..4b2822a8878 --- /dev/null +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +.text +.global chipset_teardown_car +chipset_teardown_car: + + pop %ebx + /* Move the stack pointer to real ram */ + movl post_car_stack_top, %esp + /* Align the stack 16 bytes */ + andl $0xfffffff0, %esp + + call chipset_teardown_car_main + + jmp *%ebx diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index ee1a6a328e8..0a123cff789 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 5214d73b296..8d7a6836722 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -20,24 +20,10 @@ #include #include -/* cache-as-ram support for FSP 1.1. */ -struct cache_as_ram_params { - uint64_t tsc; - uint32_t bist; - FSP_INFO_HEADER *fih; - uintptr_t bootloader_car_start; - uintptr_t bootloader_car_end; -}; - -/* Entry points from the cache-as-ram assembly code. */ -asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params); -asmlinkage void after_cache_as_ram(void *chipset_context); -asmlinkage void *romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih); -void after_cache_as_ram_stage(void); +void cache_as_ram_stage_main(FSP_INFO_HEADER *fih); /* Mainboard and SoC initialization prior to console. */ void car_mainboard_pre_console_init(void); diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d608484999f..2caceebfa08 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -18,71 +18,41 @@ #ifndef _COMMON_ROMSTAGE_H_ #define _COMMON_ROMSTAGE_H_ +#include #include #include #include #include #include #include -#include #include /* chip_power_state */ struct romstage_params { uint32_t fsp_version; struct chipset_power_state *power_state; - struct pei_data *pei_data; void *chipset_context; -}; -/* - * FSP Boot Flow: - * 1. src/cpu/x86/16bit/reset.inc - * 2. src/cpu/x86/16bit/entry.inc - * 3. other modules - * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc - * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp - * 6. FSP binary/TempRamInit - * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return - * 8. src/soc/intel/common/romstage.c/romstage_main - * 9 src/soc/.../romstage/.../soc_pre_console_init - * 10 src/console/console.c/console_init - * 11 src/soc/.../romstage/.../soc_romstage_init - * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry - * 13. src/soc/intel/common/romstage.c/romstage_common - * 14 src/soc/.../romstage/.../soc_pre_raminit - * 15. FSP binary/MemoryInit - * 16. src/soc/intel/common/romstage.c/romstage_common - return - * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return - * 18. src/soc/intel/common/romstage.c/romstage_main - return - * 19. src/soc/intel/common/stack.c/setup_stack_and_mtrrs - * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup - * after call to romstage_main - * 21. FSP binary/TempRamExit - * 22. src/soc/intel/common/romstage.c/romstage_after_car - * 23. FSP binary/SiliconInit - * 24. src/soc/intel/common/romstage.c/romstage_after_car - return - * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback - * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify - * 27. FSP binary/FspNotify - * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback - * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify - * 30. FSP binary/FspNotify - */ + /* Fast boot and S3 resume MRC data */ + size_t saved_data_size; + const void *saved_data; + bool disable_saved_data; + + /* New save data from MRC */ + size_t data_to_save_size; + const void *data_to_save; +}; void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); -void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); void mainboard_add_dimm_info(struct romstage_params *params, struct memory_info *mem_info, int channel, int dimm, int index); void raminit(struct romstage_params *params); void report_memory_config(void); -void romstage_common(struct romstage_params *params); -asmlinkage void *romstage_main(FSP_INFO_HEADER *fih); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); -void *setup_stack_and_mtrrs(void); void soc_after_ram_init(struct romstage_params *params); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 0ad7a4117a7..45b8eda2435 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -17,6 +17,8 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H +#include +#include #include /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include @@ -107,4 +109,6 @@ void *get_first_guid_hob(const EFI_GUID *guid); __attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes); +asmlinkage void chipset_teardown_car_main(void); + #endif /* FSP1_1_UTIL_H */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 8405c943aa3..eff011aa622 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -28,6 +28,7 @@ void raminit(struct romstage_params *params) { + const bool s3wake = params->power_state->prev_sleep_state == ACPI_S3; const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; FSP_INFO_HEADER *fsp_header; @@ -46,7 +47,6 @@ void raminit(struct romstage_params *params) u32 *mrc_hob; u32 fsp_reserved_bytes; MEMORY_INIT_UPD *original_params; - struct pei_data *pei_ptr; EFI_STATUS status; VPD_DATA_REGION *vpd_ptr; UPD_DATA_REGION *upd_ptr; @@ -80,10 +80,9 @@ void raminit(struct romstage_params *params) /* Zero fill RT Buffer data and start populating fields. */ memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); - pei_ptr = params->pei_data; - if (pei_ptr->boot_mode == ACPI_S3) { + if (s3wake) { fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; - } else if (pei_ptr->saved_data != NULL) { + } else if (params->saved_data != NULL) { fsp_rt_common_buffer.BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; } else { @@ -93,7 +92,7 @@ void raminit(struct romstage_params *params) fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size(); /* Get any board specific changes */ - fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; + fsp_memory_init_params.NvsBufferPtr = (void *)params->saved_data; fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; fsp_memory_init_params.HobListPtr = &hob_list_ptr; @@ -131,7 +130,8 @@ void raminit(struct romstage_params *params) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); if (status != EFI_SUCCESS) - die("ERROR - FspMemoryInit failed to initialize memory!\n"); + die_with_post_code(POST_RAM_FAILURE, + "ERROR - FspMemoryInit failed to initialize memory!\n"); /* Locate the FSP reserved memory area */ fsp_reserved_bytes = 0; @@ -158,7 +158,7 @@ void raminit(struct romstage_params *params) /* Migrate CAR data */ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); - if (pei_ptr->boot_mode != ACPI_S3) { + if (!s3wake) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, @@ -196,9 +196,6 @@ void raminit(struct romstage_params *params) } #if CONFIG(DISPLAY_HOBS) - if (hob_list_ptr == NULL) - die("ERROR - HOB pointer is NULL!\n"); - /* * Verify that FSP is generating the required HOBs: * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 @@ -220,7 +217,7 @@ void raminit(struct romstage_params *params) } hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (hob_ptr.Raw == NULL) { - if (params->pei_data->saved_data == NULL) { + if (params->saved_data == NULL) { printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); fsp_verification_failure = 1; } @@ -245,7 +242,10 @@ void raminit(struct romstage_params *params) "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ - print_hob_type_structure(0, hob_list_ptr); + if (hob_list_ptr != NULL) + print_hob_type_structure(0, hob_list_ptr); + else + printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); #endif /* Get the address of the CBMEM region for the FSP reserved memory */ @@ -275,14 +275,16 @@ void raminit(struct romstage_params *params) printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); - die("Please verify the chipset reserved size\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Please verify the chipset reserved size\n"); } #endif } /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) - die("ERROR - coreboot's requirements not met by FSP binary!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "ERROR - coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); @@ -294,8 +296,8 @@ void raminit(struct romstage_params *params) "Memory Configuration Data Hob not present\n"); else if (!vboot_recovery_mode_enabled()) { /* Do not save MRC data in recovery path */ - pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); - pei_ptr->data_to_save_size = ALIGN( + params->data_to_save = GET_GUID_HOB_DATA(mrc_hob); + params->data_to_save_size = ALIGN( ((u32)GET_HOB_LENGTH(mrc_hob)), 16); } } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ebb6a6678bf..d86d3ab4842 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -38,70 +37,15 @@ #include #include -asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) -{ - void *top_of_stack; - struct pei_data pei_data; - struct romstage_params params = { - .pei_data = &pei_data, - .chipset_context = fih, - }; - - post_code(0x30); - - timestamp_add_now(TS_START_ROMSTAGE); - - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - - memset(&pei_data, 0, sizeof(pei_data)); - - /* Display parameters */ - if (!CONFIG(NO_MMCONF_SUPPORT)) - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); - printk(BIOS_INFO, "Using FSP 1.1\n"); - - /* Display FSP banner */ - print_fsp_info(fih); - - /* Stash FSP version. */ - params.fsp_version = fsp_version(fih); - - /* Get power state */ - params.power_state = fill_power_state(); - - /* Call into mainboard. */ - mainboard_romstage_entry(¶ms); - soc_after_ram_init(¶ms); - post_code(0x38); - - top_of_stack = setup_stack_and_mtrrs(); - - printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - return top_of_stack; -} - -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) -{ - return romstage_main(fih); -} - -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +static void raminit_common(struct romstage_params *params) { bool s3wake; struct region_device rdev; - struct pei_data *pei_data; post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); - pei_data = params->pei_data; - pei_data->boot_mode = params->power_state->prev_sleep_state; s3wake = params->power_state->prev_sleep_state == ACPI_S3; if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) @@ -112,9 +56,9 @@ void romstage_common(struct romstage_params *params) post_code(0x33); /* Check recovery and MRC cache */ - params->pei_data->saved_data_size = 0; - params->pei_data->saved_data = NULL; - if (!params->pei_data->disable_saved_data) { + params->saved_data_size = 0; + params->saved_data = NULL; + if (!params->disable_saved_data) { if (vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, @@ -124,12 +68,11 @@ void romstage_common(struct romstage_params *params) params->fsp_version, &rdev))) { /* MRC cache found */ - params->pei_data->saved_data_size = - region_device_sz(&rdev); - params->pei_data->saved_data = rdev_mmap_full(&rdev); + params->saved_data_size = region_device_sz(&rdev); + params->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - } else if (params->pei_data->boot_mode == ACPI_S3) { + } else if (s3wake) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -147,15 +90,15 @@ void romstage_common(struct romstage_params *params) /* Save MRC output */ if (CONFIG(CACHE_MRC_SETTINGS)) { - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", - pei_data->data_to_save, pei_data->data_to_save_size); - if ((params->pei_data->boot_mode != ACPI_S3) - && (params->pei_data->data_to_save_size != 0) - && (params->pei_data->data_to_save != NULL)) + printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n", + params->data_to_save, params->data_to_save_size); + if (!s3wake + && (params->data_to_save_size != 0) + && (params->data_to_save != NULL)) mrc_cache_stash_data(MRC_TRAINING_DATA, params->fsp_version, - params->pei_data->data_to_save, - params->pei_data->data_to_save_size); + params->data_to_save, + params->data_to_save_size); } /* Save DIMM information */ @@ -169,11 +112,45 @@ void romstage_common(struct romstage_params *params) full_reset(); } -void after_cache_as_ram_stage(void) +void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) { - /* Load the ramstage. */ - run_ramstage(); - die("ERROR - Failed to load ramstage!"); + struct romstage_params params = { + .chipset_context = fih, + }; + + post_code(0x30); + + timestamp_add_now(TS_START_ROMSTAGE); + + /* Load microcode before RAM init */ + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) + intel_update_microcode_from_cbfs(); + + /* Display parameters */ + if (!CONFIG(NO_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); + printk(BIOS_INFO, "Using FSP 1.1\n"); + + /* Display FSP banner */ + print_fsp_info(fih); + + /* Stash FSP version. */ + params.fsp_version = fsp_version(fih); + + /* Get power state */ + params.power_state = fill_power_state(); + + /* Board initialization before and after RAM is enabled */ + mainboard_pre_raminit(¶ms); + + post_code(0x31); + + /* Initialize memory */ + raminit_common(¶ms); + + soc_after_ram_init(¶ms); + post_code(0x38); } /* Initialize the power state */ @@ -183,13 +160,8 @@ __weak struct chipset_power_state *fill_power_state(void) } /* Board initialization before and after RAM is enabled */ -__weak void mainboard_romstage_entry( - struct romstage_params *params) +__weak void mainboard_pre_raminit(struct romstage_params *params) { - post_code(0x31); - - /* Initialize memory */ - romstage_common(params); } /* Save the DIMM information for SMBIOS table 17 */ @@ -343,25 +315,11 @@ __weak int mrc_cache_stash_data(int type, uint32_t version, return -1; } -/* Transition RAM from off or self-refresh to active */ -__weak void raminit(struct romstage_params *params) -{ - post_code(POST_MEM_PREINIT_PREP_START); - die("ERROR - No RAM initialization specified!\n"); -} - /* Display the memory configuration */ __weak void report_memory_config(void) { } -/* Choose top of stack and setup MTRRs */ -__weak void *setup_stack_and_mtrrs(void) -{ - die("ERROR - Must specify top of stack!\n"); - return NULL; -} - /* SOC initialization after RAM is enabled */ __weak void soc_after_ram_init(struct romstage_params *params) { diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c deleted file mode 100644 index 88ff36a8473..00000000000 --- a/src/drivers/intel/fsp1_1/stack.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. - */ -void *setup_stack_and_mtrrs(void) -{ - size_t alignment; - uint32_t aligned_ram; - uint32_t mtrr_mask_upper; - uint32_t max_mtrrs; - uint32_t num_mtrrs; - uint32_t *slot; - - /* Display the MTRRs */ - display_mtrrs(); - - /* Top of stack needs to be aligned to a 8-byte boundary. */ - slot = (void *)romstage_ram_stack_top(); - num_mtrrs = 0; - max_mtrrs = get_var_mtrr_count(); - - /* - * The upper bits of the MTRR mask need to set according to the number - * of physical address bits. - */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); - - /* - * The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) - | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ - - /* - * Cache the stack and the other CBMEM entries as well as part or all - * of the FSP reserved memory region. - */ - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - -#if CONFIG(HAVE_SMI_HANDLER) - void *smm_base; - size_t smm_size; - uint32_t tseg_base; - - /* - * Cache the TSEG region at the top of ram. This region is not - * restricted to SMM mode until SMM has been relocated. By setting - * the region to cacheable it provides faster access when relocating - * the SMM handler as well as using the TSEG region for other purposes. - */ - smm_region(&smm_base, &smm_size); - tseg_base = (uint32_t)smm_base; - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); - num_mtrrs++; -#endif - - /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) - | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; - - /* Validate the MTRR usage */ - if (num_mtrrs > max_mtrrs) { - printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d", - max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs); - die("ERROR - MTRR use count incorrect!\n"); - } - - /* - * Save the number of MTRRs to setup and clear. Return the stack - * location pointing to the number of MTRRs. - */ - slot = stack_push32(slot, num_mtrrs); - slot = stack_push32(slot, max_mtrrs); - return slot; -} diff --git a/src/drivers/intel/fsp1_1/temp_ram_exit.c b/src/drivers/intel/fsp1_1/temp_ram_exit.c new file mode 100644 index 00000000000..c1535e0bc0a --- /dev/null +++ b/src/drivers/intel/fsp1_1/temp_ram_exit.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include + +asmlinkage void chipset_teardown_car_main(void) +{ + FSP_INFO_HEADER *fih; + uint32_t status; + FSP_TEMP_RAM_EXIT temp_ram_exit; + struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + + if (prog_locate(&fsp)) { + die("Unable to locate fsp.bin\n"); + } else { + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + + /* FIXME: the implementation of find_fsp is utter garbage + as it casts error values to FSP_INFO_HEADER pointers. + Checking for return values can only be done sanely once + that is fixed. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); + } + + temp_ram_exit = (FSP_TEMP_RAM_EXIT)(fih->TempRamExitEntryOffset + + fih->ImageBase); + printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); + status = temp_ram_exit(NULL); + + if (status != FSP_SUCCESS) { + printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); + die("TempRamExit returned an error!\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7fe81e51a0e..3fb39d50762 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -27,7 +27,7 @@ config PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE help Include FSP 2.1 wrappers and functionality. - Features added into FSP 2.1 specification that impacts corerboot are: + Features added into FSP 2.1 specification that impacts coreboot are: 1. Remove FSP stack switch and use the same stack with boot firmware 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index f26a7761330..d627a3dbb1d 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -69,7 +69,7 @@ $(CONFIG_FSP_S_CBFS)-type := fsp ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) - python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index e0c63d25702..55dc6dfddca 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -13,6 +13,7 @@ #include #include #include +#include enum pixel_format { pixel_rgbx_8bpc = 0, diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 5efd59058c5..95b80200029 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -10,7 +10,6 @@ * (at your option) any later version. */ -#include #include #include #include @@ -100,7 +99,7 @@ struct hob_resource *fsp_hob_header_to_resource(const struct hob_header *hob) * Utilities for locating and identifying HOBs */ -static void *fsp_hob_list_ptr CAR_GLOBAL; +static void *fsp_hob_list_ptr; static void save_hob_list(int is_recovery) { @@ -122,14 +121,14 @@ const void *fsp_get_hob_list(void) uint32_t *list_loc; if (ENV_ROMSTAGE) - return (void *)car_get_var(fsp_hob_list_ptr); + return fsp_hob_list_ptr; list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL; } void *fsp_get_hob_list_ptr(void) { - return car_get_var_ptr(&fsp_hob_list_ptr); + return &fsp_hob_list_ptr; } static const @@ -237,9 +236,9 @@ static void display_fsp_version_info_hob(const void *hob, size_t size) /* Don't show ingredient name and version if its all 0xFF */ if (fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && + fvi[index].Version.MinorVersion == 0xFF && + fvi[index].Version.Revision == 0xFF && + fvi[index].Version.BuildNumber == 0xFF && fvi[index].VersionStringIndex == 0) { str_ptr = (char *)((uintptr_t)str_ptr + cnt + sizeof(uint8_t)); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index e0659243ba4..3e86b29c8dd 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -44,7 +44,6 @@ struct fsp_header { enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -#if ENV_RAMSTAGE /* * This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains * both SiliconInit and Notify APIs. When SiliconInit is loaded the @@ -52,6 +51,5 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); * header parsing again. */ extern struct fsp_header fsps_hdr; -#endif #endif /* _FSP2_0_INFO_HEADER_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 231162ed17b..ef7ecd163f9 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -19,6 +19,7 @@ #include #include #include +#include struct hob_header { uint16_t type; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 985ee3a07f5..f248a58c774 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -32,6 +32,7 @@ #include #include #include +#include /* TPM MRC hash functionality depends on vboot starting before memory init. */ _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || @@ -277,7 +278,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) - die("Invalid FSPM signature!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPM signature!\n"); /* Copy the default values from the UPD area */ memcpy(&fspm_upd, upd, sizeof(fspm_upd)); @@ -290,7 +292,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) - die("FSPM_ARCH_UPD not found!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); @@ -310,16 +313,22 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); - fsp_debug_after_memory_init(status); - /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); - die("FspMemoryInit returned an error!\n"); + die_with_post_code(POST_RAM_FAILURE, + "FspMemoryInit returned an error!\n"); } do_fsp_post_memory_init(s3wake, fsp_version); + + /* + * fsp_debug_after_memory_init() checks whether the end of the tolum + * region is the same as the top of cbmem, so must be called here + * after cbmem has been initialised in do_fsp_post_memory_init(). + */ + fsp_debug_after_memory_init(status); } /* Load the binary into the memory specified by the info header. */ diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index fe6c4b36b81..e26701b0991 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 402b05d55e0..e72e4ac163e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -18,9 +18,11 @@ #include #include #include +#include #include #include #include +#include struct fsp_header fsps_hdr; @@ -29,11 +31,13 @@ static void do_silicon_init(struct fsp_header *hdr) FSPS_UPD *upd, *supd; fsp_silicon_init_fn silicon_init; uint32_t status; + uint8_t postcode; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) - die("Invalid FSPS signature\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPS signature\n"); upd = xmalloc(sizeof(FSPS_UPD)); @@ -58,8 +62,18 @@ static void do_silicon_init(struct fsp_header *hdr) /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { + if (vbt_get()) { + /* Attempted to initialize graphics. Assume failure + * is related to a video failure. + */ + postcode = POST_VIDEO_FAILURE; + } else { + /* Other silicon initialization failed */ + postcode = POST_HW_INIT_FAILURE; + } printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); - die("FspSiliconINit returned an error!\n"); + die_with_post_code(postcode, + "FspSiliconInit returned an error!\n"); } } diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index ced3584fd05..075e923f843 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -15,6 +15,7 @@ #include #include #include +#include void fsp_temp_ram_exit(void) { diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 19b8127ac5c..f670e6facd2 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -16,6 +16,7 @@ #include #include #include +#include static bool looks_like_fsp_header(const uint8_t *raw_hdr) { diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 4f897fab13a..59a9e8aa5bc 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -67,7 +67,7 @@ config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ - || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ + || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE depends on MAINBOARD_USE_LIBGFXINIT select RAMSTAGE_LIBHWBASE @@ -86,22 +86,19 @@ config GFX_GMA_INTERNAL_IS_LVDS if GFX_GMA -config GFX_GMA_CPU +config GFX_GMA_DYN_CPU + def_bool y + help + Activates runtime CPU detection in libgfxinit. + +config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE - default "Broadwell" if SOC_INTEL_BROADWELL - default "Haswell" if NORTHBRIDGE_INTEL_HASWELL - default "Ivybridge" if NORTHBRIDGE_INTEL_IVYBRIDGE - default "Sandybridge" if NORTHBRIDGE_INTEL_SANDYBRIDGE - default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM + default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X -config GFX_GMA_CPU_VARIANT - string - default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL - default "Normal" - config GFX_GMA_INTERNAL_PORT string default "DP" if GFX_GMA_INTERNAL_IS_EDP diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 5caa1b38d8a..80949d1bf8a 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -16,6 +16,8 @@ #include #include +#include + #include "int15.h" static int active_lfp, pfit, display, panel_type; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index f6f04a1035b..097b768b12d 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -26,6 +26,7 @@ #include #include #include +#include #define REG_SPI_FLASH_CTRL 0x200 #define SPI_FLASH_CTRL_EN_VPD 0x2000 diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 3200163ab37..31887789003 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -33,6 +33,8 @@ #include #include #include +#include + #include "chip.h" #define NIC_TIMEOUT 1000 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 99079b985e2..e0869a93371 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -29,6 +28,7 @@ #include #include #include +#include /* There's no way around this include guard. option_table.h is autogenerated */ #if CONFIG(USE_OPTION_TABLE) @@ -39,6 +39,9 @@ #define LB_CKS_LOC 0 #endif +/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #include #if (defined(__PRE_RAM__) && \ diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index d01d778ca46..cc8fbf7c5d0 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -109,7 +109,7 @@ const struct spi_flash *boot_device_spi_flash(void) return car_get_var_ptr(&sfg); } -int boot_device_wp_region(struct region_device *rd, +int boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type) { uint32_t ctrlr_pr; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 82398ddf06b..ae1d2efb22e 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -338,7 +339,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi, printk(BIOS_INFO, "Manufacturer: %02x\n", *idp); /* search the table for matches in shift and id */ - for (i = 0; i < ARRAY_SIZE(flashes); ++i) + for (i = 0; i < (int)ARRAY_SIZE(flashes); ++i) if (flashes[i].shift == shift && flashes[i].idcode == *idp) { /* we have a match, call probe */ if (flashes[i].probe(spi, idp, flash) == 0) { diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 71bdac72a2e..e4ea7805dd3 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -187,7 +187,7 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, const void *buf) { - size_t actual, chunk_len, cmd_len; + size_t actual, chunk_len; unsigned long byte_addr; unsigned long page_size; int ret = 0; @@ -208,7 +208,6 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, if (ret) goto done; - cmd_len = 4; cmd[0] = CMD_SST_AAI_WP; cmd[1] = offset >> 16; cmd[2] = offset >> 8; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index be0850493fd..11a518746c8 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 62671e2b6f4..614a849f7a4 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,6 @@ void uart_tx_flush(int idx) uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; @@ -138,4 +137,3 @@ void uart_fill_lb(void *data) lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); } -#endif diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index c3dff6a72ce..a5aa74a3325 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,6 @@ void uart_tx_flush(int idx) uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; @@ -166,4 +165,3 @@ void uart_fill_lb(void *data) lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index 91c069d6c89..17019b599b1 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,2 @@ -romstage-$(CONFIG_VPD) += lib_vpd.c -ramstage-$(CONFIG_VPD) += vpd.c lib_vpd.c +romstage-$(CONFIG_VPD) += vpd_decode.c +ramstage-$(CONFIG_VPD) += vpd.c vpd_decode.c diff --git a/src/drivers/vpd/lib_vpd.c b/src/drivers/vpd/lib_vpd.c deleted file mode 100644 index 0744a712abb..00000000000 --- a/src/drivers/vpd/lib_vpd.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - */ -#include -#include "lib_vpd.h" - -/* Given an encoded string, this functions decodes the length field which varies - * from 1 byte to many bytes. - * - * The in points the actual byte going to be decoded. The *length returns - * the decoded length field. The number of consumed bytes will be stroed in - * decoded_len. - * - * Returns VPD_FAIL if more bit is 1, but actually reaches the end of string. - */ -int decodeLen(const int32_t max_len, - const uint8_t *in, - int32_t *length, - int32_t *decoded_len) -{ - uint8_t more; - int i = 0; - - assert(length); - assert(decoded_len); - - *length = 0; - do { - if (i >= max_len) - return VPD_FAIL; - - more = in[i] & 0x80; - *length <<= 7; - *length |= in[i] & 0x7f; - ++i; - } while (more); - - *decoded_len = i; - - return VPD_OK; -} - -/* Given the encoded string, this function invokes callback with extracted - * (key, value). The *consumed will be plused the number of bytes consumed in - * this function. - * - * The input_buf points to the first byte of the input buffer. - * - * The *consumed starts from 0, which is actually the next byte to be decoded. - * It can be non-zero to be used in multiple calls. - * - * If one entry is successfully decoded, sends it to callback and returns the - * result. - */ -int decodeVpdString(const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed, - VpdDecodeCallback callback, - void *callback_arg) -{ - int type; - int32_t key_len, value_len; - int32_t decoded_len; - const uint8_t *key, *value; - - /* type */ - if (*consumed >= max_len) - return VPD_FAIL; - - type = input_buf[*consumed]; - switch (type) { - case VPD_TYPE_INFO: - case VPD_TYPE_STRING: - (*consumed)++; - /* key */ - if (VPD_OK != decodeLen(max_len - *consumed, - &input_buf[*consumed], &key_len, - &decoded_len) || - *consumed + decoded_len >= max_len) { - return VPD_FAIL; - } - - *consumed += decoded_len; - key = &input_buf[*consumed]; - *consumed += key_len; - - /* value */ - if (VPD_OK != decodeLen(max_len - *consumed, - &input_buf[*consumed], - &value_len, &decoded_len) || - *consumed + decoded_len > max_len) { - return VPD_FAIL; - } - *consumed += decoded_len; - value = &input_buf[*consumed]; - *consumed += value_len; - - if (type == VPD_TYPE_STRING) - return callback(key, key_len, value, value_len, - callback_arg); - - return VPD_OK; - - default: - return VPD_FAIL; - break; - } - - return VPD_OK; -} diff --git a/src/drivers/vpd/lib_vpd.h b/src/drivers/vpd/lib_vpd.h deleted file mode 100644 index 156d27939ff..00000000000 --- a/src/drivers/vpd/lib_vpd.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - */ - -#ifndef __LIB_VPD__ -#define __LIB_VPD__ - -#include - -enum { - VPD_OK = 0, - VPD_FAIL, -}; - -enum { - VPD_TYPE_TERMINATOR = 0, - VPD_TYPE_STRING, - VPD_TYPE_INFO = 0xfe, - VPD_TYPE_IMPLICIT_TERMINATOR = 0xff, -}; - -enum { - VPD_AS_LONG_AS = -1, -}; - -enum { /* export_type */ - VPD_EXPORT_KEY_VALUE = 1, - VPD_EXPORT_VALUE, - VPD_EXPORT_AS_PARAMETER, -}; - -/* Callback for decodeVpdString to invoke. */ -typedef int VpdDecodeCallback(const uint8_t *key, int32_t key_len, - const uint8_t *value, int32_t value_len, - void *arg); - -/* Container data types */ -struct StringPair { - uint8_t *key; - uint8_t *value; - int pad_len; - int filter_out; /* TRUE means not exported. */ - struct StringPair *next; -}; - -struct PairContainer { - struct StringPair *first; -}; - - -/*********************************************************************** - * Encode and decode VPD entries - ***********************************************************************/ - -/* Encodes the len into multiple bytes with the following format. - * - * 7 6 ............ 0 - * +----+------------------+ - * |More| Length | ... - * +----+------------------+ - * - * The encode_buf points to the actual position we are going to store. - * encoded_len will return the exact bytes we encoded in this function. - * Returns fail if the buffer is not long enough. - */ -int encodeLen( - const int32_t len, - uint8_t *encode_buf, - const int32_t max_len, - int32_t *encoded_len); - -/* Given an encoded string, this functions decodes the length field which varies - * from 1 byte to many bytes. - * - * The in points the actual byte going to be decoded. The *length returns - * the decoded length field. The number of consumed bytes will be stroed in - * decoded_len. - * - * Returns VPD_FAIL if more bit is 1, but actually reaches the end of string. - */ -int decodeLen( - const int32_t max_len, - const uint8_t *in, - int32_t *length, - int32_t *decoded_len); - - -/* Encodes the terminator. - * When calling, the output_buf should point to the start of buffer while - * *generated_len should contain how many bytes exist in buffer now. - * After return, *generated_len would be plused the number of bytes generated - * in this function. - */ -int encodeVpdTerminator( - const int max_buffer_len, - uint8_t *output_buf, - int *generated_len); - -/* Encodes the given type/key/value pair into buffer. - * - * The pad_value_len is used to control the output value length. - * When pad_value_len > 0, the value is outputted into fixed length (pad \0 - * if the value is shorter). Truncated if too long. - * pad_value_len == VPD_NO_LIMIT, output the value as long as possible. - * This is useful when we want to fix the structure layout at beginning. - * - * The encoded string will be stored in output_buf. If it is longer than - * max_buffer_len, this function returns fail. If the buffer is long enough, - * the generated_len will be updated. - * - * When calling, the output_buf should point to the start of buffer while - * *generated_len should contain how many bytes exist in buffer now. - * After return, *generated_len would be plused the number of bytes generated - * in this function. - * - * The initial value of *generated_len can be non-zero, so that this value - * can be used between multiple calls to encodeVpd2Pair(). - */ -int encodeVpdString( - const uint8_t *key, - const uint8_t *value, - const int pad_value_len, - const int max_buffer_len, - uint8_t *output_buf, - int *generated_len); - - -/* Given the encoded string, this function invokes callback with extracted - * (key, value). The *consumed will be plused the number of bytes consumed in - * this function. - * - * The input_buf points to the first byte of the input buffer. - * - * The *consumed starts from 0, which is actually the next byte to be decoded. - * It can be non-zero to be used in multiple calls. - * - * If one entry is successfully decoded, sends it to callback and returns the - * result. - */ -int decodeVpdString( - const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed, - VpdDecodeCallback callback, - void *callback_arg); - -/*********************************************************************** - * Container helpers - ***********************************************************************/ -void initContainer(struct PairContainer *container); - -struct StringPair *findString(struct PairContainer *container, - const uint8_t *key, - struct StringPair ***prev_next); - -/* If key is already existed in container, its value will be replaced. - * If not existed, creates new entry in container. - */ -void setString(struct PairContainer *container, - const uint8_t *key, - const uint8_t *value, - const int pad_len); - -/* merge all entries in src into dst. If key is duplicate, overwrite it. - */ -void mergeContainer(struct PairContainer *dst, - const struct PairContainer *src); - -/* subtract src from dst. -*/ -int subtractContainer(struct PairContainer *dst, - const struct PairContainer *src); - -/* Given a container, encode its all entries into the buffer. - */ -int encodeContainer(const struct PairContainer *container, - const int max_buf_len, - uint8_t *buf, - int *generated); - -/* Given a VPD blob, decode its entries and push into container. - */ -int decodeToContainer(struct PairContainer *container, - const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed); - -/* Set filter for exporting functions. - * If filter is NULL, resets the filter so that everything can be exported. - */ -int setContainerFilter(struct PairContainer *container, - const uint8_t *filter); - -/* - * Remove a key. - * Returns VPD_OK if deleted successfully. Otherwise, VPD_FAIL. - */ -int deleteKey(struct PairContainer *container, - const uint8_t *key); - -/* - * Returns number of pairs in container. - */ -int lenOfContainer(const struct PairContainer *container); - -/* - * Export the container content with human-readable text. - * - * The buf points to the first byte of buffer and *generated contains the number - * of bytes already existed in buffer. - * - * Afterward, the *generated will be plused on exact bytes this function has - * generated. - */ -int exportContainer(const int export_type, - const struct PairContainer *container, - const int max_buf_len, - uint8_t *buf, - int *generated); - -void destroyContainer(struct PairContainer *container); - -#endif /* __LIB_VPD__ */ diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index e620b58b31d..c6dd339f619 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -12,7 +12,7 @@ #include #include "vpd.h" -#include "lib_vpd.h" +#include "vpd_decode.h" #include "vpd_tables.h" /* Currently we only support Google VPD 2.0, which has a fixed offset. */ @@ -160,27 +160,27 @@ static void cbmem_add_cros_vpd(int is_recovery) } } -static int vpd_gets_callback(const uint8_t *key, int32_t key_len, - const uint8_t *value, int32_t value_len, - void *arg) +static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, + const uint8_t *value, uint32_t value_len, + void *arg) { struct vpd_gets_arg *result = (struct vpd_gets_arg *)arg; if (key_len != result->key_len || memcmp(key, result->key, key_len) != 0) - /* Returns VPD_OK to continue parsing. */ - return VPD_OK; + /* Returns VPD_DECODE_OK to continue parsing. */ + return VPD_DECODE_OK; result->matched = 1; result->value = value; result->value_len = value_len; - /* Returns VPD_FAIL to stop parsing. */ - return VPD_FAIL; + /* Returns VPD_DECODE_FAIL to stop parsing. */ + return VPD_DECODE_FAIL; } const void *vpd_find(const char *key, int *size, enum vpd_region region) { struct vpd_gets_arg arg = {0}; - int consumed = 0; + uint32_t consumed = 0; const struct vpd_cbmem *vpd; vpd = cbmem_find(CBMEM_ID_VPD); @@ -190,18 +190,21 @@ const void *vpd_find(const char *key, int *size, enum vpd_region region) arg.key = (const uint8_t *)key; arg.key_len = strlen(key); - if (region == VPD_ANY || region == VPD_RO) - while (VPD_OK == decodeVpdString(vpd->ro_size, vpd->blob, - &consumed, vpd_gets_callback, &arg)) { - /* Iterate until found or no more entries. */ + if (region == VPD_ANY || region == VPD_RO) { + while (vpd_decode_string( + vpd->ro_size, vpd->blob, &consumed, + vpd_gets_callback, &arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ } - - if (!arg.matched && region != VPD_RO) - while (VPD_OK == decodeVpdString(vpd->rw_size, - vpd->blob + vpd->ro_size, &consumed, - vpd_gets_callback, &arg)) { - /* Iterate until found or no more entries. */ + } + if (!arg.matched && region != VPD_RO) { + while (vpd_decode_string( + vpd->rw_size, vpd->blob + vpd->ro_size, + &consumed, vpd_gets_callback, + &arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ } + } if (!arg.matched) return NULL; diff --git a/src/drivers/vpd/vpd_decode.c b/src/drivers/vpd/vpd_decode.c new file mode 100644 index 00000000000..0eab704ca80 --- /dev/null +++ b/src/drivers/vpd/vpd_decode.c @@ -0,0 +1,92 @@ +/* + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This is a copy from upstream: + * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/lib/vpd_decode.c + */ +#include "vpd_decode.h" + +int vpd_decode_len( + const u32 max_len, const u8 *in, u32 *length, u32 *decoded_len) +{ + u8 more; + int i = 0; + + if (!length || !decoded_len) + return VPD_DECODE_FAIL; + + *length = 0; + do { + if (i >= max_len) + return VPD_DECODE_FAIL; + + more = in[i] & 0x80; + *length <<= 7; + *length |= in[i] & 0x7f; + ++i; + } while (more); + + *decoded_len = i; + return VPD_DECODE_OK; +} + +int vpd_decode_string( + const u32 max_len, const u8 *input_buf, u32 *consumed, + vpd_decode_callback callback, void *callback_arg) +{ + int type; + int res; + u32 key_len; + u32 value_len; + u32 decoded_len; + const u8 *key; + const u8 *value; + + /* type */ + if (*consumed >= max_len) + return VPD_DECODE_FAIL; + + type = input_buf[*consumed]; + + switch (type) { + case VPD_TYPE_INFO: + case VPD_TYPE_STRING: + (*consumed)++; + + /* key */ + res = vpd_decode_len(max_len - *consumed, &input_buf[*consumed], + &key_len, &decoded_len); + /* key name cannot be empty, and must be followed by value. */ + if (res != VPD_DECODE_OK || key_len < 1 || + *consumed + decoded_len + key_len >= max_len) + return VPD_DECODE_FAIL; + + *consumed += decoded_len; + key = &input_buf[*consumed]; + *consumed += key_len; + + /* value */ + res = vpd_decode_len(max_len - *consumed, &input_buf[*consumed], + &value_len, &decoded_len); + /* value can be empty (value_len = 0). */ + if (res != VPD_DECODE_OK || + *consumed + decoded_len + value_len > max_len) + return VPD_DECODE_FAIL; + + *consumed += decoded_len; + value = &input_buf[*consumed]; + *consumed += value_len; + + if (type == VPD_TYPE_STRING) + return callback(key, key_len, value, value_len, + callback_arg); + break; + + default: + return VPD_DECODE_FAIL; + } + + return VPD_DECODE_OK; +} diff --git a/src/drivers/vpd/vpd_decode.h b/src/drivers/vpd/vpd_decode.h new file mode 100644 index 00000000000..99ca7efa81a --- /dev/null +++ b/src/drivers/vpd/vpd_decode.h @@ -0,0 +1,68 @@ +/* + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This is a copy from upstream: + * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/include/lib/vpd_decode.h + */ + +#ifndef __VPD_DECODE_H +#define __VPD_DECODE_H + +#include + +enum { + VPD_DECODE_OK = 0, + VPD_DECODE_FAIL = 1, +}; + +enum { + VPD_TYPE_TERMINATOR = 0, + VPD_TYPE_STRING, + VPD_TYPE_INFO = 0xfe, + VPD_TYPE_IMPLICIT_TERMINATOR = 0xff, +}; + +/* Callback for vpd_decode_string to invoke. */ +typedef int vpd_decode_callback( + const u8 *key, u32 key_len, const u8 *value, u32 value_len, + void *arg); + +/* + * vpd_decode_len + * + * Given an encoded string, this function extracts the length of content + * (either key or value). The *consumed will contain the number of bytes + * consumed. + * + * The input_buf points to the first byte of the input buffer. + * + * The *consumed starts from 0, which is actually the next byte to be decoded. + * It can be non-zero to be used in multiple calls. + * + * Returns VPD_DECODE_OK on success, otherwise VPD_DECODE_FAIL. + */ +int vpd_decode_len( + const u32 max_len, const u8 *in, u32 *length, u32 *decoded_len); + +/* + * vpd_decode_string + * + * Given the encoded string, this function invokes callback with extracted + * (key, value). The *consumed will be plused the number of bytes consumed in + * this function. + * + * The input_buf points to the first byte of the input buffer. + * + * The *consumed starts from 0, which is actually the next byte to be decoded. + * It can be non-zero to be used in multiple calls. + * + * If one entry is successfully decoded, sends it to callback and returns the + * result. + */ +int vpd_decode_string( + const u32 max_len, const u8 *input_buf, u32 *consumed, + vpd_decode_callback callback, void *callback_arg); + +#endif /* __VPD_DECODE_H */ diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index a20c0683d48..b9191abe3d9 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -17,7 +17,7 @@ * GNU General Public License for more details. */ -#include +/* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 162d00cfcf8..64412566a1b 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +/* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c index f71ad5680a6..248b8af5f87 100644 --- a/src/drivers/xgi/common/vb_util.c +++ b/src/drivers/xgi/common/vb_util.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include "xgi_coreboot.h" +/* coreboot related includes come indirectly from xgi_coreboot.h */ +#include "xgi_coreboot.h" #include "vgatypes.h" #include "vb_util.h" diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 41952d6925d..5e593eb1c21 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c index da575ccffd5..93e864dff72 100644 --- a/src/drivers/xpowers/axp209/axp209.c +++ b/src/drivers/xpowers/axp209/axp209.c @@ -8,12 +8,13 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -#include "axp209.h" -#include "chip.h" - #include #include #include +#include + +#include "axp209.h" +#include "chip.h" /* Hide these definitions from the rest of the source, so keep them here */ enum registers { diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index 3a7790c097a..f17869ecbcc 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) -bootblock-y += bootblock.c +bootblock-y += bootblock.c commands.c mailbox.c +verstage-y += commands.c mailbox.c romstage-y += commands.c mailbox.c romstage.c boardid.c ramstage-y += chip.c commands.c mailbox.c boardid.c smm-y += commands.c mailbox.c smihandler.c boardid.c diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index d0d572d569e..626f9ddc2c0 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -159,7 +159,7 @@ void wilco_ec_power_off(enum ec_power_off_reason reason) int wilco_ec_radio_control(enum ec_radio radio, uint8_t state) { - uint8_t radio_control[3] = { 0, radio, state }; + uint8_t radio_control[3] = { radio, RADIO_WRITE, state }; return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_RADIO_CONTROL, radio_control, ARRAY_SIZE(radio_control), @@ -181,3 +181,46 @@ int wilco_ec_signed_fw(void) CONFIG_EC_BASE_ACPI_DATA); return !!ec_read(EC_RAM_SIGNED_FW); } + +struct err_code_entry { + uint8_t post_code; + enum ec_err_code ec_err; +}; + +/* + * Any post codes not listed in the post_code_err_map[] use default. + */ +static const enum ec_err_code default_ec_err = DLED_ROM; +static const struct err_code_entry post_code_err_map[] = { + { .post_code = POST_RAM_FAILURE, .ec_err = DLED_MEMORY, }, + { .post_code = POST_VIDEO_FAILURE, .ec_err = DLED_PANEL, }, +}; + +/* Records the most recent post code during boot */ +static uint8_t wilco_ec_saved_post_code; + +void wilco_ec_save_post_code(uint8_t post_code) +{ + wilco_ec_saved_post_code = post_code; +} + +/* Send error code to the EC based on last saved post code */ +void die_notify(void) +{ + size_t i; + enum ec_err_code err_code = default_ec_err; + + for (i = 0; i < ARRAY_SIZE(post_code_err_map); i++) { + if (post_code_err_map[i].post_code == + wilco_ec_saved_post_code) { + err_code = post_code_err_map[i].ec_err; + break; + } + } + + printk(BIOS_EMERG, "Fatal error: post_code 0x%02x, EC err 0x%02x\n", + wilco_ec_saved_post_code, err_code); + + wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE, + &err_code, 1, NULL, 0); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 3077eee5787..9a185805af9 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -50,6 +50,8 @@ enum { KB_SLP_EN = 0x64, /* Inform the EC about BIOS boot progress */ KB_BIOS_PROGRESS = 0xc2, + /* Inform the EC that a fatal error occurred */ + KB_ERR_CODE = 0x7b, }; enum ec_ram_addr { @@ -78,7 +80,15 @@ enum ec_audio_mute { }; enum ec_radio { - RADIO_WIFI = 0x02, + RADIO_WIFI = 0, + RADIO_WWAN, + RADIO_BT, +}; + +enum ec_radio_action { + RADIO_READ = 1, + RADIO_WRITE, + RADIO_TOGGLE, }; enum ec_camera { @@ -86,6 +96,12 @@ enum ec_camera { CAMERA_OFF }; +enum ec_err_code { + DLED_MEMORY = 0x03, + DLED_PANEL = 0x10, + DLED_ROM = 0x19, +}; + /** * wilco_ec_radio_control() - Control wireless radios. * @ec_radio: Wireless radio type. @@ -310,4 +326,15 @@ enum ec_acpi_wake_events { */ int wilco_ec_signed_fw(void); +/** + * wilco_ec_save_post_code + * + * Save this post code as the most recent progress step. If the boot fails + * and calls die_notify() this post code will be used to send an error code + * to the EC indicating the failure. + * + * @post_code: Post code to save + */ +void wilco_ec_save_post_code(uint8_t post_code); + #endif /* EC_GOOGLE_WILCO_COMMANDS_H */ diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index b109831105c..d8749754280 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -32,6 +32,14 @@ config H8_HAS_BAT_TRESHOLDS_IMPL bool default n +config H8_FN_KEY_AS_VBOOT_RECOVERY_SW + bool "Enable Fn-Key as VBOOT recovery switch" + depends on VBOOT + default n + help + If VBOOT is enabled, press Fn-Key at power on to force a recovery mode + boot instead of regular FW_MAIN_x boot. + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index ebf6d7d7a4b..51c11be625d 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,5 +1,18 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) +ramstage-y += sense.c +verstage-y += sense.c +romstage-y += sense.c +bootblock-y += sense.c +postcar-y += sense.c +smm-y += sense.c + +ramstage-$(CONFIG_VBOOT) += vboot.c +verstage-$(CONFIG_VBOOT) += vboot.c +romstage-$(CONFIG_VBOOT) += vboot.c +bootblock-$(CONFIG_VBOOT) += vboot.c +postcar-$(CONFIG_VBOOT) += vboot.c + ifneq ($(filter y,$(CONFIG_H8_BEEP_ON_DEATH) $(CONFIG_H8_FLASH_LEDS_ON_DEATH)),) romstage-y += panic.c ramstage-y += panic.c diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 080f247838a..5f97ed9dc52 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -160,7 +160,7 @@ Method(BSTA, 4, NotSerialized) Return (Arg1) } -Method(BINF, 2, NotSerialized) +Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) ^BPAG(Or(1, Arg1)) /* Battery 0 static information */ diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index a8e17cb7856..c9142f5ff9e 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -28,7 +28,7 @@ Device(LID) { Name(_HID, "PNP0C0D") - Method(_LId, 0, NotSerialized) + Method(_LID, 0, NotSerialized) { return (LIDS) } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index de4f2c29b2d..f707014c315 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "h8.h" #include "chip.h" diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index a46ba1f5e04..14948c55cec 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -38,6 +38,9 @@ void h8_usb_always_on(void); void h8_mainboard_init_dock (void); +int h8_get_fn_key(void); +int h8_get_sense_ready(void); + void h8_bluetooth_enable(int on); bool h8_bluetooth_nv_enable(void); bool h8_has_bdc(struct device *dev); @@ -135,8 +138,10 @@ void h8_ssdt_generator(struct device *dev); #define H8_EVENT_FN_PRESS 0x39 #define H8_STATUS0 0x46 +#define H8_STATUS0_FN_KEY_DOWN 0x01 #define H8_STATUS1 0x47 #define H8_STATUS2 0x48 +#define H8_STATUS3 0x49 #define H8_EVENT_BAT0 0x4a #define H8_EVENT_BAT0_STATE 0x4b diff --git a/src/ec/lenovo/h8/sense.c b/src/ec/lenovo/h8/sense.c new file mode 100644 index 00000000000..b929d7ede38 --- /dev/null +++ b/src/ec/lenovo/h8/sense.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include "h8.h" + +/** + * Return the EC sense status register state. + * + * Observations showed the sense registers are all zero until the EC populates + * them after some time. Likely the EC sets all bits to it's valid state at + * once, but there's no prove as the firmware isn't available. + * + * Wait for any register having at least one bit set. + * Unlikely that all register will be zero after booting has finished. + * + * @return 1 if the EC provides valid data in sense status registers + */ +int h8_get_sense_ready(void) +{ + static const u8 regs[] = { H8_STATUS0, H8_STATUS1, H8_STATUS2, + H8_STATUS3}; + + for (size_t i = 0; i < ARRAY_SIZE(regs); i++) { + if (ec_read(regs[i])) + return 1; + } + + return 0; +} + +/** + * Return the state of Fn key. + * Only valid if h8_get_sense_ready (see above) returns true. + * + * @return 1 if the key is pressed. + */ +int h8_get_fn_key(void) +{ + return ec_read(H8_STATUS0) & H8_STATUS0_FN_KEY_DOWN; +} diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c new file mode 100644 index 00000000000..3b9f74a117b --- /dev/null +++ b/src/ec/lenovo/h8/vboot.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "h8.h" + +/** + * HACK: Use Fn-Key as recovery mode switch. + * Wait for sense register ready and read Fn-Key state. + */ +int get_recovery_mode_switch(void) +{ + struct stopwatch sw; + + if (!CONFIG(H8_FN_KEY_AS_VBOOT_RECOVERY_SW)) + return 0; + + /* Tests showed that it takes: + * - 700msec on Lenovo T500 from AC power on + * - less than 150msec on Lenovo T520 from AC power on + */ + stopwatch_init_msecs_expire(&sw, 1000); + while (!stopwatch_expired(&sw) && !h8_get_sense_ready()) + mdelay(1); + + if (!h8_get_sense_ready()) + return 0; + + return h8_get_fn_key(); +} + +/** + * Only used if CONFIG_CHROMEOS is set. + * Always zero as the #WP pin of the flash is tied high. + */ +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index cf3c8f7cf0b..e79cb613320 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "h8.h" #include "chip.h" diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 986abb5d813..ef505cd164d 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pmh7.h" #include "chip.h" diff --git a/src/include/assert.h b/src/include/assert.h index 60366352739..e0db0bc05c8 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -19,6 +19,12 @@ #include #include +/* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more + properly isolated. */ +#ifdef ASSERT +#undef ASSERT +#endif + /* GCC and CAR versions */ #define ASSERT(x) { \ if (!(x)) { \ @@ -50,7 +56,8 @@ * bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42' */ #define __dead_code(line) do { \ - extern void dead_code_assertion_failed_at_line_##line(void); \ + extern void dead_code_assertion_failed_at_line_##line(void) \ + __attribute__((noreturn)); \ dead_code_assertion_failed_at_line_##line(); \ } while (0) #define _dead_code(line) __dead_code(line) diff --git a/src/include/boot_device.h b/src/include/boot_device.h index c882968e589..f392c101482 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -65,7 +65,7 @@ int boot_device_rw_subregion(const struct region *sub, * by the region device. * Returns 0 on success, < 0 on error. */ -int boot_device_wp_region(struct region_device *rd, +int boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type); /* diff --git a/src/include/console/console.h b/src/include/console/console.h index ed10807c9a4..082ba29be84 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -43,6 +43,7 @@ void post_log_clear(void); /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __noreturn die(const char *msg); +void __noreturn die_with_post_code(uint8_t value, const char *msg); /* * This function is weak and can be overridden to provide additional diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index f482ae9e476..c1917adafff 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -318,6 +318,50 @@ */ #define POST_JUMPING_TO_PAYLOAD 0xf3 +/** + * \brief Invalid or corrupt ROM + * + * Set if firmware failed to find or validate a resource that is stored in ROM. + */ +#define POST_INVALID_ROM 0xe0 + +/** + * \brief Invalid or corrupt CBFS + * + * Set if firmware failed to find or validate a resource that is stored in CBFS. + */ +#define POST_INVALID_CBFS 0xe1 + +/** + * \brief Vendor binary error + * + * Set if firmware failed to find or validate a vendor binary, or the binary + * generated a fatal error. + */ +#define POST_INVALID_VENDOR_BINARY 0xe2 + +/** + * \brief RAM failure + * + * Set if RAM could not be initialized. This includes RAM is missing, + * unsupported RAM configuration, or RAM failure. + */ +#define POST_RAM_FAILURE 0xe3 + +/** + * \brief Hardware initialization failure + * + * Set when a required hardware component was not found or is unsupported. + */ +#define POST_HW_INIT_FAILURE 0xe4 + +/** + * \brief Video failure + * + * Video subsystem failed to initialize. + */ +#define POST_VIDEO_FAILURE 0xe5 + /** * \brief TPM failure * diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 60940f07d11..9a283735d37 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,6 +5,10 @@ #if !defined(__ROMCC__) void cpu_initialize(unsigned int cpu_index); +/* Returns default APIC id based on logical_cpu number or < 0 on failure. */ +int cpu_get_apic_id(int logical_cpu); +/* Function to keep track of cpu default apic_id */ +void cpu_add_map_entry(unsigned int index); struct bus; void initialize_cpus(struct bus *cpu_bus); asmlinkage void secondary_cpu_init(unsigned int cpu_index); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 9789910b46f..c04252ec353 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -145,9 +145,6 @@ int mp_run_on_all_cpus(void (*func)(void *), void *arg, long expire_us); */ int mp_park_aps(void); -/* Returns APIC id for coreboot CPU number or < 0 on failure. */ -int mp_get_apic_id(int logical_cpu); - /* * SMM helpers to use with initializing CPUs. */ diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 9ff332e964b..343e261d060 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -17,11 +17,9 @@ #define DEVICE_AZALIA_H #include -#include #include #include #include - #include void azalia_audio_init(struct device *dev); diff --git a/src/include/device/device.h b/src/include/device/device.h index 39a4d567a2a..32cf07282ba 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -141,6 +141,12 @@ struct device { #if !DEVTREE_EARLY struct chip_operations *chip_ops; const char *name; +#if CONFIG(GENERATE_SMBIOS_TABLES) + u8 smbios_slot_type; + u8 smbios_slot_data_width; + u8 smbios_slot_length; + const char *smbios_slot_designation; +#endif #endif DEVTREE_CONST void *chip_info; }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 85bd6c3864c..a35e134dc99 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -18,7 +18,9 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_ATA 0x0105 #define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SAS 0x0107 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 @@ -2689,6 +2691,12 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 +#define PCI_DEVICE_ID_INTEL_SPT_H_H170 0xa144 +#define PCI_DEVICE_ID_INTEL_SPT_H_Z170 0xa145 +#define PCI_DEVICE_ID_INTEL_SPT_H_Q170 0xa146 +#define PCI_DEVICE_ID_INTEL_SPT_H_Q150 0xa147 +#define PCI_DEVICE_ID_INTEL_SPT_H_B150 0xa148 +#define PCI_DEVICE_ID_INTEL_KBP_H_C236 0xa149 #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e #define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 @@ -3076,6 +3084,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 #define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 #define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 14be8322c69..d9d9613f968 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -33,7 +33,7 @@ struct fdt_header { uint32_t reserve_map_offset; uint32_t version; - uint32_t last_compatible_version; + uint32_t last_comp_version; uint32_t boot_cpuid_phys; @@ -42,15 +42,17 @@ struct fdt_header { }; #define FDT_HEADER_MAGIC 0xd00dfeed +#define FDT_SUPPORTED_VERSION 17 #define FDT_TOKEN_BEGIN_NODE 1 #define FDT_TOKEN_END_NODE 2 #define FDT_TOKEN_PROPERTY 3 #define FDT_TOKEN_END 9 +#define FDT_PHANDLE_ILLEGAL 0xdeadbeef struct fdt_property { const char *name; - const void *data; + void *data; uint32_t size; }; @@ -70,6 +72,8 @@ struct device_tree_property struct device_tree_node { const char *name; + uint32_t phandle; + // List of struct device_tree_property-s. struct list_node properties; // List of struct device_tree_nodes. @@ -90,6 +94,7 @@ struct device_tree { const void *header; uint32_t header_size; + uint32_t max_phandle; struct list_node reserve_map; @@ -135,10 +140,15 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, // represented as an array of strings. struct device_tree_node *dt_find_node(struct device_tree_node *parent, const char **path, u32 *addrcp, u32 *sizecp, int create); -// Look up or create a node relative to a parent node, through its path +struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, + uint32_t phandle); +// Look up or create a node in the tree, through its path // represented as a string of '/' separated node names. -struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, const char *path, - u32 *addrcp, u32 *sizecp, int create); +struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, + const char *path, u32 *addrcp, u32 *sizecp, int create); +// Look up a node through an alias. +struct device_tree_node *dt_find_node_by_alias(struct device_tree *tree, + const char *alias); // Look up a node relative to a parent node, through its compatible string. struct device_tree_node *dt_find_compat(struct device_tree_node *parent, const char *compatible); // Look up the next child of a parent node, through its compatible string. It @@ -149,15 +159,13 @@ struct device_tree_node *dt_find_next_compat_child(struct device_tree_node *pare // Look up a node relative to a parent node, through its property value. struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, const char *name, void *data, size_t size); -// Return the phandle -uint32_t dt_get_phandle(const struct device_tree_node *node); // Write src into *dest as a 'length'-byte big-endian integer. void dt_write_int(u8 *dest, u64 src, size_t length); // Delete a property void dt_delete_prop(struct device_tree_node *node, const char *name); // Add different kinds of properties to a node, or update existing ones. void dt_add_bin_prop(struct device_tree_node *node, const char *name, - const void *data, size_t size); + void *data, size_t size); void dt_add_string_prop(struct device_tree_node *node, const char *name, const char *str); void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val); diff --git a/src/include/endian.h b/src/include/endian.h index 08636f3da61..8dc18542ae0 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -85,6 +85,32 @@ #define setbits_8(addr, set) setbits_8(addr, 0, set) #ifndef __ROMCC__ +/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ +#define DEFINE_ENDIAN_DEC(endian, width) \ + static inline uint##width##_t endian##width##dec(const void *p) \ + { \ + return endian##width##_to_cpu(*(uint##width##_t *)p); \ + } +DEFINE_ENDIAN_DEC(be, 16) +DEFINE_ENDIAN_DEC(be, 32) +DEFINE_ENDIAN_DEC(be, 64) +DEFINE_ENDIAN_DEC(le, 16) +DEFINE_ENDIAN_DEC(le, 32) +DEFINE_ENDIAN_DEC(le, 64) + +/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */ +#define DEFINE_ENDIAN_ENC(endian, width) \ + static inline void endian##width##enc(void *p, uint##width##_t u) \ + { \ + *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + } +DEFINE_ENDIAN_ENC(be, 16) +DEFINE_ENDIAN_ENC(be, 32) +DEFINE_ENDIAN_ENC(be, 64) +DEFINE_ENDIAN_ENC(le, 16) +DEFINE_ENDIAN_ENC(le, 32) +DEFINE_ENDIAN_ENC(le, 64) + /* * Portable (API) endian support that can be used in code that is shared * with userspace (man 3 endian) tools. diff --git a/src/include/fmap.h b/src/include/fmap.h index 5834831489a..ab7e5ab8956 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -40,4 +40,12 @@ int fmap_locate_area(const char *name, struct region *r); * Return 0 on success, < 0 on error. */ int fmap_find_region_name(const struct region * const ar, char name[FMAP_STRLEN]); + +/* Read fmap area into provided buffer. + * Return size read on success, < 0 on error. */ +ssize_t fmap_read_area(const char *name, void *buffer, size_t size); + +/* Write provided buffer into fmap area. + * Return size written on success, < 0 on error. */ +ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size); #endif diff --git a/src/include/kconfig.h b/src/include/kconfig.h index 0478548d598..50ef3022935 100644 --- a/src/include/kconfig.h +++ b/src/include/kconfig.h @@ -17,7 +17,6 @@ #define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0, 0) #define ___config_enabled(__ignored, val, ...) val -#define IS_ENABLED(option) config_enabled(option) /* deprecated */ #define CONFIG(option) config_enabled(CONFIG_##option) #endif diff --git a/src/include/rules.h b/src/include/rules.h index ea8335fb8ca..ce968f0dd9d 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -257,6 +257,10 @@ #endif +/* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload. + * For now, that is the ramstage. */ +#define ENV_PAYLOAD_LOADER ENV_RAMSTAGE + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/include/smbios.h b/src/include/smbios.h index 5e069470e19..0bba0a7f9e4 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -26,6 +26,16 @@ int smbios_add_string(u8 *start, const char *str); int smbios_string_table_len(u8 *start); /* Used by mainboard to add an on-board device */ +enum misc_slot_type; +enum misc_slot_length; +enum misc_slot_usage; +enum slot_data_bus_bandwidth; +int smbios_write_type9(unsigned long *current, int *handle, + const char *name, const enum misc_slot_type type, + const enum slot_data_bus_bandwidth bandwidth, + const enum misc_slot_usage usage, + const enum misc_slot_length length, + u8 slot_char1, u8 slot_char2, u8 bus, u8 dev_func); enum smbios_bmc_interface_type; int smbios_write_type38(unsigned long *current, int *handle, const enum smbios_bmc_interface_type interface_type, @@ -34,7 +44,7 @@ int smbios_write_type38(unsigned long *current, int *handle, const u8 irq); int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, - u8 bus, u8 device, u8 function); + u8 bus, u8 device, u8 function, u8 device_type); const char *smbios_system_manufacturer(void); const char *smbios_system_product_name(void); @@ -481,6 +491,146 @@ struct smbios_type7 { u8 eos[2]; } __packed; +/* System Slots - Slot Type */ +enum misc_slot_type { + SlotTypeOther = 0x01, + SlotTypeUnknown = 0x02, + SlotTypeIsa = 0x03, + SlotTypeMca = 0x04, + SlotTypeEisa = 0x05, + SlotTypePci = 0x06, + SlotTypePcmcia = 0x07, + SlotTypeVlVesa = 0x08, + SlotTypeProprietary = 0x09, + SlotTypeProcessorCardSlot = 0x0A, + SlotTypeProprietaryMemoryCardSlot = 0x0B, + SlotTypeIORiserCardSlot = 0x0C, + SlotTypeNuBus = 0x0D, + SlotTypePci66MhzCapable = 0x0E, + SlotTypeAgp = 0x0F, + SlotTypeApg2X = 0x10, + SlotTypeAgp4X = 0x11, + SlotTypePciX = 0x12, + SlotTypeAgp8X = 0x13, + SlotTypeM2Socket1_DP = 0x14, + SlotTypeM2Socket1_SD = 0x15, + SlotTypeM2Socket2 = 0x16, + SlotTypeM2Socket3 = 0x17, + SlotTypeMxmTypeI = 0x18, + SlotTypeMxmTypeII = 0x19, + SlotTypeMxmTypeIIIStandard = 0x1A, + SlotTypeMxmTypeIIIHe = 0x1B, + SlotTypeMxmTypeIV = 0x1C, + SlotTypeMxm30TypeA = 0x1D, + SlotTypeMxm30TypeB = 0x1E, + SlotTypePciExpressGen2Sff_8639 = 0x1F, + SlotTypePciExpressGen3Sff_8639 = 0x20, + SlotTypePciExpressMini52pinWithBSKO = 0x21, + SlotTypePciExpressMini52pinWithoutBSKO = 0x22, + SlotTypePciExpressMini76pin = 0x23, + SlotTypePC98C20 = 0xA0, + SlotTypePC98C24 = 0xA1, + SlotTypePC98E = 0xA2, + SlotTypePC98LocalBus = 0xA3, + SlotTypePC98Card = 0xA4, + SlotTypePciExpress = 0xA5, + SlotTypePciExpressX1 = 0xA6, + SlotTypePciExpressX2 = 0xA7, + SlotTypePciExpressX4 = 0xA8, + SlotTypePciExpressX8 = 0xA9, + SlotTypePciExpressX16 = 0xAA, + SlotTypePciExpressGen2 = 0xAB, + SlotTypePciExpressGen2X1 = 0xAC, + SlotTypePciExpressGen2X2 = 0xAD, + SlotTypePciExpressGen2X4 = 0xAE, + SlotTypePciExpressGen2X8 = 0xAF, + SlotTypePciExpressGen2X16 = 0xB0, + SlotTypePciExpressGen3 = 0xB1, + SlotTypePciExpressGen3X1 = 0xB2, + SlotTypePciExpressGen3X2 = 0xB3, + SlotTypePciExpressGen3X4 = 0xB4, + SlotTypePciExpressGen3X8 = 0xB5, + SlotTypePciExpressGen3X16 = 0xB6 +}; + +/* System Slots - Slot Data Bus Width. */ +enum slot_data_bus_bandwidth { + SlotDataBusWidthOther = 0x01, + SlotDataBusWidthUnknown = 0x02, + SlotDataBusWidth8Bit = 0x03, + SlotDataBusWidth16Bit = 0x04, + SlotDataBusWidth32Bit = 0x05, + SlotDataBusWidth64Bit = 0x06, + SlotDataBusWidth128Bit = 0x07, + SlotDataBusWidth1X = 0x08, + SlotDataBusWidth2X = 0x09, + SlotDataBusWidth4X = 0x0A, + SlotDataBusWidth8X = 0x0B, + SlotDataBusWidth12X = 0x0C, + SlotDataBusWidth16X = 0x0D, + SlotDataBusWidth32X = 0x0E +}; + +/* System Slots - Current Usage. */ +enum misc_slot_usage { + SlotUsageOther = 0x01, + SlotUsageUnknown = 0x02, + SlotUsageAvailable = 0x03, + SlotUsageInUse = 0x04, + SlotUsageUnavailable = 0x05 +}; + +/* System Slots - Slot Length.*/ +enum misc_slot_length { + SlotLengthOther = 0x01, + SlotLengthUnknown = 0x02, + SlotLengthShort = 0x03, + SlotLengthLong = 0x04 +}; + +/* System Slots - Slot Characteristics 1. */ +#define SMBIOS_SLOT_UNKNOWN (1 << 0) +#define SMBIOS_SLOT_5V (1 << 1) +#define SMBIOS_SLOT_3P3V (1 << 2) +#define SMBIOS_SLOT_SHARED (1 << 3) +#define SMBIOS_SLOT_PCCARD_16 (1 << 4) +#define SMBIOS_SLOT_PCCARD_CARDBUS (1 << 5) +#define SMBIOS_SLOT_PCCARD_ZOOM (1 << 6) +#define SMBIOS_SLOT_PCCARD_MODEM_RING (1 << 7) +/* System Slots - Slot Characteristics 2. */ +#define SMBIOS_SLOT_PME (1 << 0) +#define SMBIOS_SLOT_HOTPLUG (1 << 1) +#define SMBIOS_SLOT_SMBUS (1 << 2) +#define SMBIOS_SLOT_BIFURCATION (1 << 3) + +struct slot_peer_groups { + u16 peer_seg_num; + u8 peer_bus_num; + u8 peer_dev_fn_num; + u8 peer_data_bus_width; +} __packed; + +struct smbios_type9 { + u8 type; + u8 length; + u16 handle; + u8 slot_designation; + u8 slot_type; + u8 slot_data_bus_width; + u8 current_usage; + u8 slot_length; + u16 slot_id; + u8 slot_characteristics_1; + u8 slot_characteristics_2; + u16 segment_group_number; + u8 bus_number; + u8 device_function_number; + u8 data_bus_width; + u8 peer_group_count; + struct slot_peer_groups peer[0]; + u8 eos[2]; +} __packed; + struct smbios_type11 { u8 type; u8 length; @@ -606,6 +756,8 @@ typedef enum { SMBIOS_DEVICE_TYPE_SAS, } smbios_onboard_device_type; +#define SMBIOS_DEVICE_TYPE_COUNT 10 + struct smbios_type41 { u8 type; u8 length; diff --git a/src/include/string.h b/src/include/string.h index 4a2f5e9ee66..d164f32b83c 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -25,33 +25,13 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); #endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); - -// simple string functions - -static inline size_t strnlen(const char *src, size_t max) -{ - size_t i = 0; - while ((*src++) && (i < max)) - i++; - return i; -} - -static inline size_t strlen(const char *src) -{ - size_t i = 0; - while (*src++) - i++; - return i; -} - -static inline char *strchr(const char *s, int c) -{ - for (; *s; s++) { - if (*s == c) - return (char *) s; - } - return 0; -} +size_t strnlen(const char *src, size_t max); +size_t strlen(const char *src); +char *strchr(const char *s, int c); +char *strncpy(char *to, const char *from, int count); +char *strcpy(char *dst, const char *src); +int strcmp(const char *s1, const char *s2); +int strncmp(const char *s1, const char *s2, int maxlen); /** * Find a character in a string. @@ -61,71 +41,14 @@ static inline char *strchr(const char *s, int c) * @return A pointer to the last occurrence of the character in the * string, or NULL if the character was not encountered within the string. */ -static inline char *strrchr(const char *s, int c) -{ - char *p = (char *)s + strlen(s); - - for (; p >= s; p--) { - if (*p == c) - return p; - } - - return NULL; -} - -static inline char *strncpy(char *to, const char *from, int count) -{ - register char *ret = to; - register char data; - - while (count > 0) { - count--; - data = *from++; - *to++ = data; - if (data == '\0') - break; - } +char *strrchr(const char *s, int c); - while (count > 0) { - count--; - *to++ = '\0'; - } - return ret; -} - -static inline char *strcpy(char *dst, const char *src) -{ - char *ptr = dst; - - while (*src) - *dst++ = *src++; - *dst = '\0'; - - return ptr; -} - -static inline int strcmp(const char *s1, const char *s2) -{ - int r; - - while ((r = (*s1 - *s2)) == 0 && *s1) { - s1++; - s2++; - } - return r; -} - -static inline int strncmp(const char *s1, const char *s2, int maxlen) -{ - int i; - - for (i = 0; i < maxlen; i++) { - if ((s1[i] != s2[i]) || (s1[i] == '\0')) - return s1[i] - s2[i]; - } - - return 0; -} +/* + * Parses an unsigned integer and moves the input pointer forward to the first + * character that's not a valid digit. s and *s must not be NULL. Result + * undefined if it overruns the return type size. + */ +unsigned int skip_atoi(char **s); static inline int isspace(int c) { @@ -178,4 +101,5 @@ static inline int tolower(int c) c -= 'A'-'a'; return c; } + #endif /* STRING_H */ diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index ecc365df7e5..8e753ea43be 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ void pnp_enter_conf_mode_6767(struct device *dev); void pnp_enter_conf_mode_7777(struct device *dev); void pnp_enter_conf_mode_8787(struct device *dev); void pnp_enter_conf_mode_a0a0(struct device *dev); +void pnp_enter_conf_mode_a5a5(struct device *dev); void pnp_exit_conf_mode_aa(struct device *dev); void pnp_enter_conf_mode_870155aa(struct device *dev); void pnp_exit_conf_mode_0202(struct device *dev); @@ -34,6 +36,7 @@ extern const struct pnp_mode_ops pnp_conf_mode_6767_aa; extern const struct pnp_mode_ops pnp_conf_mode_7777_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; extern const struct pnp_mode_ops pnp_conf_mode_a0a0_aa; +extern const struct pnp_mode_ops pnp_conf_mode_a5a5_aa; extern const struct pnp_mode_ops pnp_conf_mode_870155_aa; #endif /* DEVICE_PNP_CONF_MODE_H */ diff --git a/src/include/types.h b/src/include/types.h index b76c95b5bb2..d6fdc085884 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -15,6 +15,8 @@ #ifndef __TYPES_H #define __TYPES_H + +/* types.h is supposed to provide stdint and stddef defined in here: */ #include #include diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 2f10c1ccdf7..cb1e4a5cc8f 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -30,6 +30,31 @@ config FLATTENED_DEVICE_TREE Selected by features that require to parse and manipulate a flattened devicetree in ramstage. +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 4 + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config SPD_READ_BY_WORD + bool + if RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152a404..16d5c649b21 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -104,7 +104,7 @@ bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += gcc.c verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += gcc.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c -smm-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c +smm-y += gcc.c endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c @@ -118,7 +118,6 @@ ramstage-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c -ramstage-y += string.c ramstage-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c @@ -167,6 +166,7 @@ postcar-y += imd.c postcar-y += romstage_handoff.c bootblock-y += hexdump.c +postcar-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c verstage-y += hexdump.c @@ -244,6 +244,14 @@ postcar-y += reset.c ramstage-y += reset.c smm-y += reset.c +decompressor-y += string.c +bootblock-y += string.c +verstage-y += string.c +romstage-y += string.c +postcar-y += string.c +ramstage-y += string.c +smm-y += string.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c @@ -272,7 +280,7 @@ verstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c +romstage-y += rmodule.c RMODULE_LDFLAGS := -z defs -Bsymbolic diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index 429a6d8710e..e91a97f4616 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -20,7 +20,7 @@ void __weak boot_device_init(void) /* Provide weak do-nothing init. */ } -int __weak boot_device_wp_region(struct region_device *rd, +int __weak boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type) { /* return a failure, make aware WP is not implemented */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 43674effc7a..c28a67aceb5 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -42,12 +42,12 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, timestamps[i].entry_stamp); } - sanitize_cmos(); - cmos_post_init(); - bootblock_soc_early_init(); bootblock_mainboard_early_init(); + sanitize_cmos(); + cmos_post_init(); + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 01ad3e841bf..02727d74123 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -96,6 +96,28 @@ static void bootmem_init(void) bootmem_arch_add_ranges(); bootmem_platform_add_ranges(); + + if (CONFIG_CUSTOM_RAM_RES_SIZE != 0) { + const struct range_entry *r; + size_t start = CONFIG_CUSTOM_RAM_RES_ADDR; + size_t end = CONFIG_CUSTOM_RAM_RES_ADDR + CONFIG_CUSTOM_RAM_RES_SIZE; + memranges_each_entry(r, bm) { + /* All further bootmem entries are beyond this range. */ + if (end <= range_entry_base(r)) + break; + + if (start >= range_entry_base(r) && end <= range_entry_end(r)) { + if (range_entry_tag(r) == BM_MEM_RAM) { + bootmem_add_range(CONFIG_CUSTOM_RAM_RES_ADDR, + CONFIG_CUSTOM_RAM_RES_SIZE, BM_MEM_RESERVED); + return; + } + } + } + printk(BIOS_ERR, "ERROR: Tried to reserve memory %lx - %lx," + " but it is not RAM\n", start, end); + die("Check CUSTOM_RAM_RES_ADDR and CUSTOM_RAM_RES_ADDR\n"); + } } void bootmem_add_range(uint64_t start, uint64_t size, diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 052eb8f2823..737dcf93d04 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -17,7 +17,6 @@ #include #include -#if ENV_RAMSTAGE static int gfx_init_done = -1; int gfx_get_init_done(void) @@ -31,16 +30,17 @@ void gfx_set_init_done(int done) { gfx_init_done = done; } -#endif int display_init_required(void) { - /* For vboot always honor vboot_handoff_skip_display_init(). */ + /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { - /* Must always select OPROM_MATTERS when using this function. */ - if (!CONFIG(VBOOT_OPROM_MATTERS)) + /* Must always select MUST_REQUEST_DISPLAY when using this + function. */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) dead_code(); - return !vboot_handoff_skip_display_init(); + return vboot_get_working_data()->flags + & VBOOT_WD_FLAG_DISPLAY_INIT; } /* By default always initialize display. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 728674f0da7..91368fb67df 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index faa937b3813..df2d1ffa96a 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d3d55..df756983d0a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -219,7 +219,7 @@ static void lb_vboot_handoff(struct lb_header *header) return; vbho = (struct lb_range *)lb_new_record(header); - vbho->tag = LB_TAB_VBOOT_HANDOFF; + vbho->tag = LB_TAG_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); vbho->range_start = (intptr_t)addr; vbho->range_size = size; @@ -231,7 +231,7 @@ static void lb_vboot_workbuf(struct lb_header *header) struct vboot_working_data *wd = vboot_get_working_data(); vbwb = (struct lb_range *)lb_new_record(header); - vbwb->tag = LB_TAB_VBOOT_WORKBUF; + vbwb->tag = LB_TAG_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; vbwb->range_size = wd->buffer_size; @@ -321,6 +321,22 @@ static void lb_sku_id(struct lb_header *header) printk(BIOS_INFO, "SKU ID: %d\n", sid); } +static void lb_mmc_info(struct lb_header *header) +{ + struct lb_mmc_info *rec; + int32_t *ms_cbmem; + + ms_cbmem = cbmem_find(CBMEM_ID_MMC_STATUS); + if (!ms_cbmem) + return; + + rec = (struct lb_mmc_info *)lb_new_record(header); + + rec->tag = LB_TAG_MMC_INFO; + rec->size = sizeof(*rec); + rec->early_cmd1_status = *ms_cbmem; +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -559,6 +575,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_ram_code(head); lb_sku_id(head); + /* Pass mmc early init status */ + lb_mmc_info(head); + /* Add SPI flash description if available */ if (CONFIG(BOOT_DEVICE_SPI_FLASH)) lb_spi_flash(head); diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 79561a69b84..a5021ca8fd5 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -56,7 +57,7 @@ int fdt_next_property(const void *blob, uint32_t offset, int fdt_node_name(const void *blob, uint32_t offset, const char **name) { uint8_t *ptr = ((uint8_t *)blob) + offset; - if (be32toh(*(uint32_t *)ptr) != FDT_TOKEN_BEGIN_NODE) + if (be32dec(ptr) != FDT_TOKEN_BEGIN_NODE) return 0; ptr += 4; @@ -65,6 +66,12 @@ int fdt_node_name(const void *blob, uint32_t offset, const char **name) return ALIGN_UP(strlen((char *)ptr) + 1, sizeof(uint32_t)) + 4; } +static int dt_prop_is_phandle(struct device_tree_property *prop) +{ + return !(strcmp("phandle", prop->prop.name) && + strcmp("linux,phandle", prop->prop.name)); +} + /* @@ -73,21 +80,36 @@ int fdt_node_name(const void *blob, uint32_t offset, const char **name) static void print_indent(int depth) { - while (depth--) - printk(BIOS_DEBUG, " "); + printk(BIOS_DEBUG, "%*s", depth * 8, ""); } static void print_property(const struct fdt_property *prop, int depth) { + int is_string = prop->size > 0 && + ((char *)prop->data)[prop->size - 1] == '\0'; + + if (is_string) + for (const char *c = prop->data; *c != '\0'; c++) + if (!isprint(*c)) + is_string = 0; + print_indent(depth); - printk(BIOS_DEBUG, "prop \"%s\" (%d bytes).\n", prop->name, prop->size); - print_indent(depth + 1); - for (int i = 0; i < MIN(25, prop->size); i++) { - printk(BIOS_DEBUG, "%02x ", ((uint8_t *)prop->data)[i]); + if (is_string) { + printk(BIOS_DEBUG, "%s = \"%s\";\n", + prop->name, (const char *)prop->data); + } else { + printk(BIOS_DEBUG, "%s = < ", prop->name); + for (int i = 0; i < MIN(128, prop->size); i += 4) { + uint32_t val = 0; + for (int j = 0; j < MIN(4, prop->size - i); j++) + val |= ((uint8_t *)prop->data)[i + j] << + (24 - j * 8); + printk(BIOS_DEBUG, "%#.2x ", val); + } + if (prop->size > 128) + printk(BIOS_DEBUG, "..."); + printk(BIOS_DEBUG, ">;\n"); } - if (prop->size > 25) - printk(BIOS_DEBUG, "..."); - printk(BIOS_DEBUG, "\n"); } static int print_flat_node(const void *blob, uint32_t start_offset, int depth) @@ -102,7 +124,7 @@ static int print_flat_node(const void *blob, uint32_t start_offset, int depth) offset += size; print_indent(depth); - printk(BIOS_DEBUG, "name = %s\n", name); + printk(BIOS_DEBUG, "%s {\n", name); struct fdt_property prop; while ((size = fdt_next_property(blob, offset, &prop))) { @@ -111,9 +133,14 @@ static int print_flat_node(const void *blob, uint32_t start_offset, int depth) offset += size; } + printk(BIOS_DEBUG, "\n"); // empty line between props and nodes + while ((size = print_flat_node(blob, offset, depth + 1))) offset += size; + print_indent(depth); + printk(BIOS_DEBUG, "}\n"); + return offset - start_offset + sizeof(uint32_t); } @@ -153,26 +180,9 @@ int fdt_skip_node(const void *blob, uint32_t start_offset) /* * Functions to turn a flattened tree into an unflattened one. */ -static struct device_tree_node *alloc_node(void) -{ - struct device_tree_node *buf = malloc(sizeof(struct device_tree_node)); - if (!buf) - return NULL; - memset(buf, 0, sizeof(*buf)); - return buf; -} - -static struct device_tree_property *alloc_prop(void) -{ - struct device_tree_property *buf = - malloc(sizeof(struct device_tree_property)); - if (!buf) - return NULL; - memset(buf, 0, sizeof(*buf)); - return buf; -} static int fdt_unflatten_node(const void *blob, uint32_t start_offset, + struct device_tree *tree, struct device_tree_node **new_node) { struct list_node *last; @@ -185,20 +195,22 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset, return 0; offset += size; - struct device_tree_node *node = alloc_node(); + struct device_tree_node *node = xzalloc(sizeof(*node)); *new_node = node; - if (!node) - return 0; node->name = name; struct fdt_property fprop; last = &node->properties; while ((size = fdt_next_property(blob, offset, &fprop))) { - struct device_tree_property *prop = alloc_prop(); - if (!prop) - return 0; + struct device_tree_property *prop = xzalloc(sizeof(*prop)); prop->prop = fprop; + if (dt_prop_is_phandle(prop)) { + node->phandle = be32dec(prop->prop.data); + if (node->phandle > tree->max_phandle) + tree->max_phandle = node->phandle; + } + list_insert_after(&prop->list_node, last); last = &prop->list_node; @@ -207,7 +219,7 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset, struct device_tree_node *child; last = &node->children; - while ((size = fdt_unflatten_node(blob, offset, &child))) { + while ((size = fdt_unflatten_node(blob, offset, tree, &child))) { list_insert_after(&child->list_node, last); last = &child->list_node; @@ -227,10 +239,7 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, if (!size) return 0; - struct device_tree_reserve_map_entry *entry = malloc(sizeof(*entry)); - if (!entry) - return 0; - memset(entry, 0, sizeof(*entry)); + struct device_tree_reserve_map_entry *entry = xzalloc(sizeof(*entry)); *new = entry; entry->start = start; entry->size = size; @@ -240,13 +249,28 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, struct device_tree *fdt_unflatten(const void *blob) { - struct device_tree *tree = malloc(sizeof(*tree)); + struct device_tree *tree = xzalloc(sizeof(*tree)); const struct fdt_header *header = (const struct fdt_header *)blob; - if (!tree) - return NULL; - memset(tree, 0, sizeof(*tree)); tree->header = header; + uint32_t magic = be32toh(header->magic); + uint32_t version = be32toh(header->version); + uint32_t last_comp_version = be32toh(header->last_comp_version); + + if (magic != FDT_HEADER_MAGIC) { + printk(BIOS_DEBUG, "Invalid device tree magic %#.8x!\n", magic); + return NULL; + } + if (last_comp_version > FDT_SUPPORTED_VERSION) { + printk(BIOS_DEBUG, "Unsupported device tree version %u(>=%u)\n", + version, last_comp_version); + return NULL; + } + if (version > FDT_SUPPORTED_VERSION) + printk(BIOS_DEBUG, + "NOTE: FDT version %u too new, should add support!\n", + version); + uint32_t struct_offset = be32toh(header->structure_offset); uint32_t strings_offset = be32toh(header->strings_offset); uint32_t reserve_offset = be32toh(header->reserve_map_offset); @@ -269,7 +293,7 @@ struct device_tree *fdt_unflatten(const void *blob) offset += size; } - fdt_unflatten_node(blob, struct_offset, &tree->root); + fdt_unflatten_node(blob, struct_offset, tree, &tree->root); return tree; } @@ -358,14 +382,14 @@ static void dt_flatten_prop(struct device_tree_property *prop, uint8_t *dstruct = (uint8_t *)*struct_start; uint8_t *dstrings = (uint8_t *)*strings_start; - *((uint32_t *)dstruct) = htobe32(FDT_TOKEN_PROPERTY); + be32enc(dstruct, FDT_TOKEN_PROPERTY); dstruct += sizeof(uint32_t); - *((uint32_t *)dstruct) = htobe32(prop->prop.size); + be32enc(dstruct, prop->prop.size); dstruct += sizeof(uint32_t); uint32_t name_offset = (uintptr_t)dstrings - (uintptr_t)strings_base; - *((uint32_t *)dstruct) = htobe32(name_offset); + be32enc(dstruct, name_offset); dstruct += sizeof(uint32_t); strcpy((char *)dstrings, prop->prop.name); @@ -385,7 +409,7 @@ static void dt_flatten_node(const struct device_tree_node *node, uint8_t *dstruct = (uint8_t *)*struct_start; uint8_t *dstrings = (uint8_t *)*strings_start; - *((uint32_t *)dstruct) = htobe32(FDT_TOKEN_BEGIN_NODE); + be32enc(dstruct, FDT_TOKEN_BEGIN_NODE); dstruct += sizeof(uint32_t); strcpy((char *)dstruct, node->name); @@ -401,7 +425,7 @@ static void dt_flatten_node(const struct device_tree_node *node, dt_flatten_node(child, (void **)&dstruct, strings_base, (void **)&dstrings); - *((uint32_t *)dstruct) = htobe32(FDT_TOKEN_END_NODE); + be32enc(dstruct, FDT_TOKEN_END_NODE); dstruct += sizeof(uint32_t); *struct_start = dstruct; @@ -454,15 +478,22 @@ void dt_flatten(const struct device_tree *tree, void *start_dest) static void print_node(const struct device_tree_node *node, int depth) { print_indent(depth); - printk(BIOS_DEBUG, "name = %s\n", node->name); + if (depth == 0) // root node has no name, print a starting slash + printk(BIOS_DEBUG, "/"); + printk(BIOS_DEBUG, "%s {\n", node->name); struct device_tree_property *prop; list_for_each(prop, node->properties, list_node) print_property(&prop->prop, depth + 1); + printk(BIOS_DEBUG, "\n"); // empty line between props and nodes + struct device_tree_node *child; list_for_each(child, node->children, list_node) print_node(child, depth + 1); + + print_indent(depth); + printk(BIOS_DEBUG, "};\n"); } void dt_print_node(const struct device_tree_node *node) @@ -489,9 +520,9 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, struct device_tree_property *prop; list_for_each(prop, node->properties, list_node) { if (addrcp && !strcmp("#address-cells", prop->prop.name)) - *addrcp = be32toh(*(u32 *)prop->prop.data); + *addrcp = be32dec(prop->prop.data); if (sizecp && !strcmp("#size-cells", prop->prop.name)) - *sizecp = be32toh(*(u32 *)prop->prop.data); + *sizecp = be32dec(prop->prop.data); } } @@ -534,7 +565,7 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, if (!create) return NULL; - found = alloc_node(); + found = malloc(sizeof(*found)); if (!found) return NULL; found->name = strdup(*path); @@ -548,11 +579,11 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, } /* - * Find a node from a string device tree path, relative to a parent node. + * Find a node in the tree from a string device tree path. * - * @param parent The node from which to start the relative path lookup. + * @param tree The device tree to search. * @param path A string representing a path in the device tree, with - * nodes separated by '/'. Example: "soc/firmware/coreboot" + * nodes separated by '/'. Example: "/firmware/coreboot" * @param addrcp Pointer that will be updated with any #address-cells * value found in the path. May be NULL to ignore. * @param sizecp Pointer that will be updated with any #size-cells @@ -560,27 +591,65 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, * @param create 1: Create node(s) if not found. 0: Return NULL instead. * @return The found/created node, or NULL. * - * It is the caller responsibility to provide the correct path string, namely - * not starting or ending with a '/', and not having "//" anywhere in it. - */ -struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, + * It is the caller responsibility to provide a path string that doesn't end + * with a '/' and doesn't contain any "//". If the path does not start with a + * '/', the first segment is interpreted as an alias. */ +struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, const char *path, u32 *addrcp, u32 *sizecp, int create) { - char *dup_path = strdup(path); + char *sub_path; + char *duped_str; + struct device_tree_node *parent; + char *next_slash; /* Hopefully enough depth for any node. */ const char *path_array[15]; int i; - char *next_slash; struct device_tree_node *node = NULL; - if (!dup_path) - return NULL; + if (path[0] == '/') { // regular path + if (path[1] == '\0') { // special case: "/" is root node + dt_read_cell_props(tree->root, addrcp, sizecp); + return tree->root; + } - next_slash = dup_path; - path_array[0] = dup_path; - for (i = 1; i < (ARRAY_SIZE(path_array) - 1); i++) { + sub_path = duped_str = strdup(&path[1]); + if (!sub_path) + return NULL; + + parent = tree->root; + } else { // alias + char *alias; + + alias = duped_str = strdup(path); + if (!alias) + return NULL; + + sub_path = strchr(alias, '/'); + if (sub_path) + *sub_path = '\0'; + + parent = dt_find_node_by_alias(tree, alias); + if (!parent) { + printk(BIOS_DEBUG, + "Could not find node '%s', alias '%s' does not exist\n", + path, alias); + free(duped_str); + return NULL; + } + if (!sub_path) { + // it's just the alias, no sub-path + free(duped_str); + return parent; + } + + sub_path++; + } + + next_slash = sub_path; + path_array[0] = sub_path; + for (i = 1; i < (ARRAY_SIZE(path_array) - 1); i++) { next_slash = strchr(next_slash, '/'); if (!next_slash) break; @@ -595,10 +664,54 @@ struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, addrcp, sizecp, create); } - free(dup_path); + free(duped_str); return node; } +/* + * Find a node from an alias + * + * @param tree The device tree. + * @param alias The alias name. + * @return The found node, or NULL. + */ +struct device_tree_node *dt_find_node_by_alias(struct device_tree *tree, + const char *alias) +{ + struct device_tree_node *node; + const char *alias_path; + + node = dt_find_node_by_path(tree, "/aliases", NULL, NULL, 0); + if (!node) + return NULL; + + alias_path = dt_find_string_prop(node, alias); + if (!alias_path) + return NULL; + + return dt_find_node_by_path(tree, alias_path, NULL, NULL, 0); +} + +struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, + uint32_t phandle) +{ + if (!root) + return NULL; + + if (root->phandle == phandle) + return root; + + struct device_tree_node *node; + struct device_tree_node *result; + list_for_each(node, root->children, list_node) { + result = dt_find_node_by_phandle(node, phandle); + if (result) + return result; + } + + return NULL; +} + /* * Check if given node is compatible. * @@ -728,28 +841,6 @@ struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, return NULL; } -/** - * Find the phandle of a node. - * - * @param node Pointer to node containing the phandle - * @return Zero on error, the phandle on success - */ -uint32_t dt_get_phandle(const struct device_tree_node *node) -{ - const uint32_t *phandle; - size_t len; - - dt_find_bin_prop(node, "phandle", (const void **)&phandle, &len); - if (phandle != NULL && len == sizeof(*phandle)) - return be32_to_cpu(*phandle); - - dt_find_bin_prop(node, "linux,phandle", (const void **)&phandle, &len); - if (phandle != NULL && len == sizeof(*phandle)) - return be32_to_cpu(*phandle); - - return 0; -} - /* * Write an arbitrary sized big-endian integer into a pointer. * @@ -792,7 +883,7 @@ void dt_delete_prop(struct device_tree_node *node, const char *name) * @param size The size of data in bytes. */ void dt_add_bin_prop(struct device_tree_node *node, const char *name, - const void *data, size_t size) + void *data, size_t size) { struct device_tree_property *prop; @@ -804,9 +895,7 @@ void dt_add_bin_prop(struct device_tree_node *node, const char *name, } } - prop = alloc_prop(); - if (!prop) - return; + prop = xzalloc(sizeof(*prop)); list_insert_after(&prop->list_node, &node->properties); prop->prop.name = name; prop->prop.data = data; @@ -866,7 +955,7 @@ void dt_find_bin_prop(const struct device_tree_node *node, const char *name, void dt_add_string_prop(struct device_tree_node *node, const char *name, const char *str) { - dt_add_bin_prop(node, name, str, strlen(str) + 1); + dt_add_bin_prop(node, name, (char *)str, strlen(str) + 1); } /* @@ -878,9 +967,7 @@ void dt_add_string_prop(struct device_tree_node *node, const char *name, */ void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val) { - u32 *val_ptr = malloc(sizeof(val)); - if (!val_ptr) - return; + u32 *val_ptr = xmalloc(sizeof(val)); *val_ptr = htobe32(val); dt_add_bin_prop(node, name, val_ptr, sizeof(*val_ptr)); } @@ -894,9 +981,7 @@ void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val) */ void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val) { - u64 *val_ptr = malloc(sizeof(val)); - if (!val_ptr) - return; + u64 *val_ptr = xmalloc(sizeof(val)); *val_ptr = htobe64(val); dt_add_bin_prop(node, name, val_ptr, sizeof(*val_ptr)); } @@ -916,9 +1001,7 @@ void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes, { int i; size_t length = (addr_cells + size_cells) * sizeof(u32) * count; - u8 *data = malloc(length); - if (!data) - return; + u8 *data = xmalloc(length); u8 *cur = data; for (i = 0; i < count; i++) { @@ -971,7 +1054,7 @@ int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path, *prop_name++ = '\0'; /* Separate path from the property name. */ - dt_node = dt_find_node_by_path(tree->root, path_copy, NULL, + dt_node = dt_find_node_by_path(tree, path_copy, NULL, NULL, create); if (!dt_node) { @@ -1001,7 +1084,7 @@ struct device_tree_node *dt_init_reserved_memory_node(struct device_tree *tree) struct device_tree_node *reserved; u32 addr = 0, size = 0; - reserved = dt_find_node_by_path(tree->root, "reserved-memory", &addr, + reserved = dt_find_node_by_path(tree, "/reserved-memory", &addr, &size, 1); if (!reserved) return NULL; diff --git a/src/lib/fit.c b/src/lib/fit.c index 4e2b75c1a47..c98ba2f8020 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -26,7 +27,7 @@ #include #include #include -#include +#include static struct list_node image_nodes; static struct list_node config_nodes; @@ -62,6 +63,14 @@ static void fit_add_default_compat_strings(void) fit_add_compat_string(compat_string); } + if (sku_id() != UNDEFINED_STRAPPING_ID) { + snprintf(compat_string, sizeof(compat_string), "%s,%s-sku%u", + CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, + sku_id()); + + fit_add_compat_string(compat_string); + } + if (board_id() != UNDEFINED_STRAPPING_ID) { snprintf(compat_string, sizeof(compat_string), "%s,%s-rev%u", CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, @@ -414,19 +423,17 @@ static void fit_update_compat(const void *fdt_blob, struct fit_config_node *fit_load(void *fit) { - struct fdt_header *header = (struct fdt_header *)fit; struct fit_image_node *image; struct fit_config_node *config; struct compat_string_entry *compat_node; printk(BIOS_DEBUG, "FIT: Loading FIT from %p\n", fit); - if (be32toh(header->magic) != FDT_HEADER_MAGIC) { - printk(BIOS_ERR, "FIT: Bad header magic value 0x%08x.\n", - be32toh(header->magic)); + struct device_tree *tree = fdt_unflatten(fit); + if (!tree) { + printk(BIOS_ERR, "ERROR: Failed to unflatten FIT image!\n"); return NULL; } - struct device_tree *tree = fdt_unflatten(fit); const char *default_config_name = NULL; struct fit_config_node *default_config = NULL; diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 9602134d942..2b4e3bae2c6 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -173,3 +173,25 @@ int fmap_find_region_name(const struct region * const ar, return -1; } + +ssize_t fmap_read_area(const char *name, void *buffer, size_t size) +{ + struct region_device rdev; + if (fmap_locate_area_as_rdev(name, &rdev)) + return -1; + return rdev_readat(&rdev, buffer, 0, + MIN(size, region_device_sz(&rdev))); +} + +ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size) +{ + struct region_device rdev; + + if (fmap_locate_area_as_rdev_rw(name, &rdev)) + return -1; + if (size > region_device_sz(&rdev)) + return -1; + if (rdev_eraseat(&rdev, 0, region_device_sz(&rdev)) < 0) + return -1; + return rdev_writeat(&rdev, buffer, 0, size); +} diff --git a/src/lib/generic_dump_spd.c b/src/lib/generic_dump_spd.c index 63e47a2d281..fdde0263b66 100644 --- a/src/lib/generic_dump_spd.c +++ b/src/lib/generic_dump_spd.c @@ -3,6 +3,8 @@ * It should go away either there or here, depending what fits better. */ +#include + static void dump_spd_registers(const struct mem_controller *ctrl) { int i; diff --git a/src/lib/gpio.c b/src/lib/gpio.c index ab473cb229c..8ea3b5eb8e7 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 2861d6321e9..ca36ddee0e2 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -14,11 +14,7 @@ #include #include - -static int isprint(int c) -{ - return (c >= 32 && c <= 126); -} +#include void hexdump(const void *memory, size_t length) { diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 0a5d0386380..c45e1317081 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -20,7 +20,7 @@ */ #include "lzmadecode.h" -#include +#include #define kNumTopBits 24 #define kTopValue ((UInt32)1 << kNumTopBits) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3b77712550a..a21663fc0fb 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -69,7 +69,8 @@ void run_romstage(void) fail: if (CONFIG(BOOTBLOCK_CONSOLE)) - die("Couldn't load romstage.\n"); + die_with_post_code(POST_INVALID_ROM, + "Couldn't load romstage.\n"); halt(); } @@ -162,7 +163,7 @@ void run_ramstage(void) prog_run(&ramstage); fail: - die("Ramstage was not loaded!\n"); + die_with_post_code(POST_INVALID_ROM, "Ramstage was not loaded!\n"); } #ifdef __RAMSTAGE__ // gc-sections should take care of this @@ -195,13 +196,14 @@ void payload_load(void) break; } /* else fall-through */ default: - die("Unsupported payload type.\n"); + die_with_post_code(POST_INVALID_ROM, + "Unsupported payload type.\n"); break; } out: if (prog_entry(payload) == NULL) - die("Payload not loaded.\n"); + die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n"); } void payload_run(void) diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 9aa47413c5c..0d6ae54f91d 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -46,6 +46,17 @@ static void cbfs_decode_payload_segment(struct cbfs_payload_segment *segment, segment->mem_len = read_be32(&src->mem_len); } +static int payload_target_custom_reserved_ram(uint64_t start, uint64_t size) +{ + if (start >= CONFIG_CUSTOM_RAM_RES_ADDR && + (start + size) <= (CONFIG_CUSTOM_RAM_RES_ADDR + CONFIG_CUSTOM_RAM_RES_SIZE)) { + printk(BIOS_DEBUG, "Payload being loaded in reserved memory.\n"); + return 1; + } + + return 0; +} + static int segment_targets_type(void *dest, unsigned long memsz, enum bootmem_type dest_type) { @@ -56,6 +67,9 @@ static int segment_targets_type(void *dest, unsigned long memsz, if (payload_arch_usable_ram_quirk(d, memsz)) return 1; + if (payload_target_custom_reserved_ram(d, memsz)) + return 1; + printk(BIOS_ERR, "SELF segment doesn't target RAM: 0x%p, %lu bytes\n", dest, memsz); bootmem_dump_ranges(); return 0; @@ -146,10 +160,10 @@ static int check_payload_segments(struct cbfs_payload_segment *cbfssegs, { uint8_t *dest; size_t memsz; - struct cbfs_payload_segment *first_segment, *seg, segment; + struct cbfs_payload_segment *seg, segment; enum bootmem_type dest_type = *(enum bootmem_type *)args; - for (first_segment = seg = cbfssegs;; ++seg) { + for (seg = cbfssegs;; ++seg) { printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; diff --git a/src/lib/string.c b/src/lib/string.c index df2fd808491..a19f0178520 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -1,21 +1,133 @@ +#include +#include #include #include #include char *strdup(const char *s) { + if (!ENV_RAMSTAGE) + dead_code(); /* This can't be used without malloc(). */ + size_t sz = strlen(s) + 1; char *d = malloc(sz); - memcpy(d, s, sz); + if (d) + memcpy(d, s, sz); return d; } char *strconcat(const char *s1, const char *s2) { + if (!ENV_RAMSTAGE) + dead_code(); /* This can't be used without malloc(). */ + size_t sz_1 = strlen(s1); size_t sz_2 = strlen(s2); char *d = malloc(sz_1 + sz_2 + 1); - memcpy(d, s1, sz_1); - memcpy(d + sz_1, s2, sz_2 + 1); + if (d) { + memcpy(d, s1, sz_1); + memcpy(d + sz_1, s2, sz_2 + 1); + } return d; } + +size_t strnlen(const char *src, size_t max) +{ + size_t i = 0; + while ((*src++) && (i < max)) + i++; + return i; +} + +size_t strlen(const char *src) +{ + size_t i = 0; + while (*src++) + i++; + return i; +} + +char *strchr(const char *s, int c) +{ + do { + if (*s == c) + return (char *)s; + } while (*s++); + + return NULL; +} + +char *strrchr(const char *s, int c) +{ + char *p = NULL; + + do { + if (*s == c) + p = (char *)s; + } while (*s++); + + return p; +} + +char *strncpy(char *to, const char *from, int count) +{ + char *ret = to; + char data; + + while (count > 0) { + count--; + data = *from++; + *to++ = data; + if (data == '\0') + break; + } + + while (count > 0) { + count--; + *to++ = '\0'; + } + return ret; +} + +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + while (*src) + *dst++ = *src++; + *dst = '\0'; + + return ptr; +} + +int strcmp(const char *s1, const char *s2) +{ + int r; + + while ((r = (*s1 - *s2)) == 0 && *s1) { + s1++; + s2++; + } + return r; +} + +int strncmp(const char *s1, const char *s2, int maxlen) +{ + int i; + + for (i = 0; i < maxlen; i++) { + if ((s1[i] != s2[i]) || (s1[i] == '\0')) + return s1[i] - s2[i]; + } + + return 0; +} + +unsigned int skip_atoi(char **s) +{ + unsigned int i = 0; + + while (isdigit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index b6330fa2585..38d02128451 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -47,12 +47,15 @@ DECLARE_OPTIONAL_REGION(timestamp); #define USE_TIMESTAMP_REGION 0 #endif -/* The cache location will sit in BSS when in ramstage. */ -#define TIMESTAMP_CACHE_IN_BSS ENV_RAMSTAGE +/* The cache location will sit in BSS when in ramstage/postcar. */ +#define TIMESTAMP_CACHE_IN_BSS (ENV_RAMSTAGE || ENV_POSTCAR) #define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR) -/* Storage of cache entries during ramstage prior to cbmem coming online. */ +/* + * Storage of cache entries during ramstage/postcar prior to cbmem coming + * online. + */ static struct timestamp_cache timestamp_cache; enum { @@ -220,7 +223,7 @@ void timestamp_init(uint64_t base) /* Timestamps could have already been recovered. * In those circumstances honor the cache which sits in BSS * as it has already been initialized. */ - if (ENV_RAMSTAGE && + if (TIMESTAMP_CACHE_IN_BSS && ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED) return; @@ -350,6 +353,7 @@ uint32_t get_us_since_boot(void) } ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) /* Provide default timestamp implementation using monotonic timer. */ diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e4020b0ed02..d318d0c43f5 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index af5d34e6130..056daa248bd 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 30e6fdcb3c0..3cf38c035a9 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 8891abb57db..8e49e8e966d 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index e3107b18a5f..8975dc8e5d7 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 30e6fdcb3c0..3cf38c035a9 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index 2f227587122..e7a320eda52 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 65ed138c8d0..1d89e4d6d16 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -16,10 +16,10 @@ #include #include #include +#include #include #include #include - #include #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index 2f227587122..e7a320eda52 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 3a729ce17a7..905ddd58007 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -33,12 +33,4 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x4000 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0 - endif # BOARD_AOPEN_DXPLPLUSU diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index c524446274a..1c84c8432b4 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -18,14 +18,13 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include -#include +#include #include #include #include #include #include #include -#include #include #include #include @@ -245,8 +244,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 9d4047dc9ba..df8ecfd79d5 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT config MAINBOARD_DIR @@ -31,17 +31,9 @@ config VGA_BIOS_ID string default "8086,0116" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x7270 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config DRAM_RESET_GATE_GPIO int - default 60 + default 28 config MAX_CPUS int diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index 5fc3c5e4baf..878eaad0980 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select USE_NATIVE_RAMINIT @@ -37,14 +37,6 @@ config MAINBOARD_PART_NUMBER string default "B75 Pro3-M" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x1e49 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1849 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index 51991248afd..cbd26a52ac0 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl index 0ba8899a607..7994ae31a52 100644 --- a/src/mainboard/asrock/e350m1/acpi/gpe.asl +++ b/src/mainboard/asrock/e350m1/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 833ea00ad72..156fe3fd649 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -62,8 +62,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 63bcbc8d395..ba2f00d1ec8 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 971eebd7c08..45a20142f4e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 4c910c5f766..b458115134c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -56,8 +56,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1c.1 on end # PCIe 2 (ethernet) device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 55f163769f5..928a01042e8 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -40,14 +40,6 @@ config CBFS_SIZE hex default 0x200000 -# -# The override of GFX_GMA_CPU_VARIANT should be removed once the patches -# for dynamic CPU detection are merged in libgfxinit. -# -config GFX_GMA_CPU_VARIANT - string - default "Normal" - config MAINBOARD_DIR string default asrock/h81m-hds @@ -56,14 +48,6 @@ config MAINBOARD_PART_NUMBER string default "H81M-HDS" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x8c5c - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1849 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index 7c1bf9ecd4b..de18bc5aa80 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,3 +16,4 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/h81m-hds/bootblock.c b/src/mainboard/asrock/h81m-hds/bootblock.c new file mode 100644 index 00000000000..7a841b84aa7 --- /dev/null +++ b/src/mainboard/asrock/h81m-hds/bootblock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + /* + * Don't know what's needed here, just set the same as the vendor + * firmware. + */ + pnp_set_logical_device(IR_DEV); + pnp_write_config(IR_DEV, 0xf1, 0x5c); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a9177223063..3af82f2907b 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -23,8 +23,6 @@ #include #include #include -#include -#include static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -41,35 +39,6 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ - const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); - const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); - const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); - const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); - - /* Select HWM/LED functions instead of floppy functions. */ - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); - - /* Power RAM in S3 and let the PCH handle power failure actions. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x70); - - /* - * Don't know what's needed here, just set the same as the vendor - * firmware. - */ - pnp_set_logical_device(IR_DEV); - pnp_write_config(IR_DEV, 0xf1, 0x5c); - - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index a1018b3e5f6..ce547419d26 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 2727904641e..d5acdb55e30 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -15,15 +15,14 @@ */ #include +#include #include #include - #include #include #include #include #include - #include #include #include diff --git a/src/mainboard/asus/h61m-cs/Kconfig b/src/mainboard/asus/h61m-cs/Kconfig index d21c76191b1..69efa9da81b 100644 --- a/src/mainboard/asus/h61m-cs/Kconfig +++ b/src/mainboard/asus/h61m-cs/Kconfig @@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select USE_NATIVE_RAMINIT @@ -25,14 +25,6 @@ config MAINBOARD_PART_NUMBER string default "H61M-CS" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 5d43a542729..6c40627823b 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -44,6 +43,7 @@ #include #include #include +#include #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index f7d30bda98b..d017b0616a8 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -45,6 +44,7 @@ #include #include #include +#include #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index 1170ed7a497..cb263f90f24 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index 92d7840031b..a0bc31864eb 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -46,14 +46,6 @@ config VGA_BIOS_ID string default "8086,0112" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 642f1ee0097..2f7d2781d73 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -64,8 +64,6 @@ chip northbridge/intel/i945 device pci 1c.1 on end # PCIe device pci 1c.2 off end # PCIe port 3 device pci 1c.3 off end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on # USB UHCI ioapic_irq 2 INTA 0x10 end diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 6727f4ab885..b076b9d7fb7 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -18,7 +18,7 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include +#include #include #include #include @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -214,8 +213,7 @@ void mainboard_romstage_entry(unsigned long bist) if (!s3resume && setup_sio_gpio(c_bsel)) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - outb(0xe, 0xcf9); - halt(); + full_reset(); } /* Enable SPD ROMs and DDR-II DRAM */ diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 8ce59799981..7d028434d67 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -191,8 +190,7 @@ void mainboard_romstage_entry(unsigned long bist) if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - outb(0xe, 0xcf9); - halt(); + full_reset(); } sdram_initialize(boot_path, spd_addrmap); diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index cc2f8a9979d..010641ac66d 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -43,14 +43,6 @@ config MAINBOARD_PART_NUMBER string default "P8H61-M LX" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 082d3e4028a..e8a6f6404a2 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select USE_NATIVE_RAMINIT @@ -31,6 +31,9 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select DRIVERS_ASMEDIA_ASPM_BLACKLIST select MAINBOARD_HAS_LPC_TPM + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string @@ -48,14 +51,6 @@ config VGA_BIOS_ID string default "8086,0152" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x844d - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1043 - config MAX_CPUS int default 8 diff --git a/src/mainboard/asus/p8h61-m_pro/data.vbt b/src/mainboard/asus/p8h61-m_pro/data.vbt new file mode 100644 index 00000000000..114a840660f Binary files /dev/null and b/src/mainboard/asus/p8h61-m_pro/data.vbt differ diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index f8534527281..d3f1795f915 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -49,7 +49,13 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on end # Realtek RTL8111E Ethernet Controller + device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + chip drivers/net + register "customized_leds" = "0x00f6" + register "wake" = "9" + device pci 00.0 on end + end + end device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) device pci 1c.5 on end # ASMedia ASM1062 SATA Controller diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 9f7fbf89f66..4f5ab882329 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 1d86d53be9f..6458b974ff4 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 43db0d755b3..17c25aece6e 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index 0bfde495fff..3326b74bf68 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -28,14 +28,6 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x7270 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config DRAM_RESET_GATE_GPIO # FIXME: check this int default 60 diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index dbd28c8affe..6d0b3af8c04 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -18,6 +18,7 @@ #include #include #include +#include #define SIO_PORT 0x164e diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index e1eb8206e7b..05e3847d396 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 21fa9b535fb..bfb5e029d6d 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -31,7 +31,7 @@ #include #include #include - +#include #define GPB_TWI0_FUNC 2 #define GPB_TWI0_PINS ((1 << 0) | (1 << 1)) diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl index 30e6fdcb3c0..3cf38c035a9 100644 --- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig new file mode 100644 index 00000000000..3f451945b45 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_FACEBOOK_FBG1701 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE + select HAVE_FSP_BIN + select CACHE_MRC_SETTINGS + select DISABLE_HPET + select GENERIC_SPD_BIN + +choice + prompt "Onboard memory manufacturer" + default ONBOARD_MICRON_MEM + +config ONBOARD_SAMSUNG_MEM + bool "Samsung" + help + Samsung K4B8G1646D memory + +config ONBOARD_MICRON_MEM + bool "Micron" + help + Micron MT41K512M16HA memory +endchoice + +config MAINBOARD_DIR + string + default facebook/fbg1701 + +config MAINBOARD_PART_NUMBER + string + default "FBG-1701" + +config CBFS_SIZE + hex + default 0x00800000 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x10C00 + help + This should be updated when the microcode patch changes. + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFFE9400 + +config MRC_SETTINGS_CACHE_SIZE + hex + default 0x08000 + +config FSP_LOC + hex + default 0xfff9c000 + +config FSP1_1_DISPLAY_LOGO + bool + default n + +config BOOTBLOCK_LOC + hex + default 0xFFFF0000 + +config BOOTBLOCK_SIZE + hex + default 0x10000 + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SPI_FLASH_WINBOND + bool + default y + +config TPM_INIT + bool "TPM Setup in RAMSTAGE" + default n + +config C_ENV_BOOTBLOCK_SIZE + hex "C Bootblock Size" + default 0x4000 + +endif # BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/facebook/fbg1701/Kconfig.name b/src/mainboard/facebook/fbg1701/Kconfig.name new file mode 100644 index 00000000000..1ead7d587fd --- /dev/null +++ b/src/mainboard/facebook/fbg1701/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FACEBOOK_FBG1701 + bool "fbg1701" diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc new file mode 100644 index 00000000000..07309c564c7 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += irqroute.c +ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c + +cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp +logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) +logo.bmp-type := raw +logo.bmp-compression := LZMA + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO +SPD_SOURCES += MICRON_MT41K512M16HA-125A diff --git a/src/mainboard/facebook/fbg1701/acpi/ec.asl b/src/mainboard/facebook/fbg1701/acpi/ec.asl new file mode 100644 index 00000000000..3c9d818baed --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl new file mode 100644 index 00000000000..9575748446e --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "onboard.h" + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +/* + * Onboard CPLD + */ +Scope (\_SB.PCI0.LPCB) +{ + Device (CPLD) /* Onboard CPLD */ + { + Name(_HID, EISAID("PNP0C01")) + Name(_CRS, ResourceTemplate() + { + /* Reserve 0x280 to 0x2BF for the CPLD */ + FixedIO (0x0280, 0x40) + IRQNoFlags () {7} + }) + } +} diff --git a/src/arch/x86/stages.c b/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl similarity index 62% rename from src/arch/x86/stages.c rename to src/mainboard/facebook/fbg1701/acpi/sleepstates.asl index b4d0723e168..428fda2a015 100644 --- a/src/arch/x86/stages.c +++ b/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl @@ -1,11 +1,13 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -13,9 +15,6 @@ * GNU General Public License for more details. */ -static void skip_romstage(void) -{ - asm volatile ( - "jmp __main\n" - ); -} +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl new file mode 100644 index 00000000000..468c95c531e --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "onboard.h" + +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c new file mode 100644 index 00000000000..15c955afc2e --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; + + /* PMIC is configured in I2C1, hide it for the OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/facebook/fbg1701/board_info.txt b/src/mainboard/facebook/fbg1701/board_info.txt new file mode 100644 index 00000000000..41d91fd2bea --- /dev/null +++ b/src/mainboard/facebook/fbg1701/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Facebook +Board name: FBG-1701 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout similarity index 63% rename from src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout rename to src/mainboard/facebook/fbg1701/cmos.layout index 095e3833e15..c293c5f9895 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -2,7 +2,8 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,10 +18,32 @@ # ----------------------------------------------------------------- entries +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C #96 4 r 0 status_c_rsvd @@ -42,9 +65,10 @@ entries # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) +# reboot_counter reserved for core, not used by platform. 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? +#390 2 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console @@ -52,23 +76,21 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused +# coreboot config options: cpu +#400 1 e 2 unused +#401 7 r 0 unused + # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +#411 5 r 0 unused -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused - -# coreboot config options: cpu -#425 7 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused +# coreboot config options: bootloader +#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum +#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- @@ -77,6 +99,8 @@ enumerations #ID value text 1 0 Disable 1 1 Enable +2 0 Enable +2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency @@ -91,17 +115,7 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M - # ----------------------------------------------------------------- checksums -checksum 392 439 984 +checksum 392 415 984 diff --git a/src/soc/intel/common/block/include/intelblocks/vmx.h b/src/mainboard/facebook/fbg1701/com_init.c similarity index 55% rename from src/soc/intel/common/block/include/intelblocks/vmx.h rename to src/mainboard/facebook/fbg1701/com_init.c index b93ceeb8c14..f19aba311c7 100644 --- a/src/soc/intel/common/block/include/intelblocks/vmx.h +++ b/src/mainboard/facebook/fbg1701/com_init.c @@ -1,6 +1,10 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,22 +15,15 @@ * GNU General Public License for more details. */ -#ifndef SOC_INTEL_COMMON_BLOCK_VMX_H -#define SOC_INTEL_COMMON_BLOCK_VMX_H - -#include - -struct vmx_param { - uint8_t enable; -}; - -/* - * Configure VMX. - */ -void vmx_configure(void *unused); +#include +#include +#include "onboard.h" -/* SOC specific API to get VMX params. - * returns 0, if able to get VMX params; otherwise returns -1 */ -int soc_fill_vmx_param(struct vmx_param *vmx_param); +#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ -#endif /* SOC_INTEL_COMMON_BLOCK_VMX_H */ +void bootblock_mainboard_early_init(void) +{ + /* Enable the serial port inside the EC */ + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 1); +} diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb new file mode 100644 index 00000000000..3c82a034b4d --- /dev/null +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -0,0 +1,131 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "0" + register "PcdEnableDma0" = "0" + register "PcdEnableDma1" = "0" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "1" + register "PcdEmmcMode" = "PCH_PCI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in PCI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # CPLD requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC router + device pci 02.0 on end # 8086 22B1 - GFX + device pci 0b.0 off end # 8086 22DC - PUNIT/DPTF + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - SATA Port + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 18.0 off end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 off end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 off end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 off end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl new file mode 100644 index 00000000000..4eea7b93f49 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015-2018 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include + + /* global NVS and variables */ + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + } + } + + /* Chipset specific sleep states */ + #include "acpi/sleepstates.asl" + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/facebook/fbg1701/fadt.c b/src/mainboard/facebook/fbg1701/fadt.c new file mode 100644 index 00000000000..73adfad94c9 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/fadt.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch &= ~ACPI_FADT_8042; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/facebook/fbg1701/gpio.c b/src/mainboard/facebook/fbg1701/gpio.c new file mode 100644 index 00000000000..5a73ca91485 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/gpio.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPIO_NC, /* 77 GPIO_ALERT */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + Native_M1, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ + Native_M1, /* 82 SPKR */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN, /* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + NATIVE_PU20K(1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B NC */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + Native_M2, /* 30 MF_HDA_CLK */ + Native_M2, /* 31 MF_HDA_RSTB */ + Native_M2, /* 32 MF_HDA_SDI0 */ + Native_M2, /* 33 MF_HDA_SDO */ + GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ + Native_M2, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 MF_HDA_SDI1 */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + GPIO_INPUT_NO_PULL, /* 47 I2C6_SDA SD_WP_1P8*/ + GPIO_NC, /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + GPIO_NC, /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + GPIO_NC, /* 63 I2C1_SCL */ + GPIO_NC, /* 64 I2C3_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_NC, /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERT_N */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3, MMC1_RST */ + Native_M1, /* 81 MF_SMB_CLK */ + Native_M1, /* 82 MF_SMB_DATA */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + Native_M1, /* 91 PCIE_CLKREQ1B */ + GPIO_NC, /* 92 GP_SSP_2_CLK */ + Native_M1, /* 93 PCIE_CLKREQ2B */ + GPIO_NC, /* 94 GP_SSP_2_RXD */ + Native_M1, /* 93 PCIE_CLKREQ3B */ + GPIO_NC, /* 96 GP_SSP_2_FS */ + GPIO_NC, /* 97 GP_SSP_2_TXD */ + GPIO_END +}; + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 00 GPIO_DFX0 SMC_EXTSMI_N */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 03 GPIO_DFX1 PM_THRM_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 04 GPIO_DFX5 LID_N */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 08 GPIO_DFX6 WAKE1_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPIO_NC, /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + Native_M2, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + Native_M2, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + Native_M2, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + GPIO_NC, /* 62 HV_DDI2_DDC_SDA */ + GPIO_NC, /* 63 PANEL1_BKLTCTL */ + Native_M1, /* 64 HV_DDI1_HPD */ + Native_M1, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */ + GPIO_NC, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + GPIO_NC, /* 69 PANEL1_VDDEN */ + GPIO_NC, /* 70 PANEL1_BKLTEN */ + NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c new file mode 100644 index 00000000000..344443f09ae --- /dev/null +++ b/src/mainboard/facebook/fbg1701/hda_verb.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10EC0298, /* Codec Vendor - Device ID: Realtek ALC298 */ + 0x152D1165, /* Subsystem ID Quanta */ + 0x0000000C, /* Number of jacks */ + + /* HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x152D1165), + + /* Pin Widget Verb Table */ + + /* Widget node 1 (NID 0x01) */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + + /* Pin Complex (NID 0x12) DMIC */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90A60130), + + /* Pin Complex (NID 0x13) DMIC */ + AZALIA_PIN_CFG(0x0, 0x13, 0x411111F0), + + /* Pin Complex (NID 0x14) SPEAKER-OUT (Port-D) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90180110), + + /* Pin Complex (NID 0x17) I2S-OUT */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01011120), + + /* Pin Complex (NID 0x18) MIC1 (Port-B) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x41111F0), + + /* Pin Complex (NID 0x19) I2S-IN */ + AZALIA_PIN_CFG(0x0, 0x19, 0x90870140), + + /* Pin Complex (NID 0x1A) LINE1 (Port-C) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), + + /* Pin Complex (NID 0x1D) PC-BEEP */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40400001), + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + + /* Pin Complex (NID 0x1F) SPDIF-IN */ + AZALIA_PIN_CFG(0x0, 0x1F, 0x411111F0), + + /* Pin Complex (NID 0x21) HP-OUT (Port-A) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x411111F0), + + /* POST I2S bypass output SRC */ + 0x0205002D, + 0x0204C020, + 0x0205002D, + 0x0204C020, + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/soc/intel/icelake/cbmem.c b/src/mainboard/facebook/fbg1701/irqroute.c similarity index 79% rename from src/soc/intel/icelake/cbmem.c rename to src/mainboard/facebook/fbg1701/irqroute.c index 4f447773ac9..a4ff6bf2b2e 100644 --- a/src/soc/intel/icelake/cbmem.c +++ b/src/mainboard/facebook/fbg1701/irqroute.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,6 @@ * GNU General Public License for more details. */ -#include +#include "irqroute.h" -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/facebook/fbg1701/irqroute.h b/src/mainboard/facebook/fbg1701/irqroute.h new file mode 100644 index 00000000000..6b7cb4169e8 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/irqroute.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * IR02h GFX INT(A) - PIRQ A + * IR0Bh PUNIT INT(A) - PIRQ F + * IR10h EMMC INT(ABCD) - PIRQ DEFG + * IR11h SDIO INT(A) - PIRQ B + * IR12h SD INT(A) - PIRQ C + * IR13h SATA INT(A) - PIRQ D + * IR14h XHCI INT(A) - PIRQ E + * IR15h LP Audio INT(A) - PIRQ F + * IR17h MMC INT(A) - PIRQ F + * IR18h SIO INT(ABCD) - PIRQ BADC + * IR1Ah TXE INT(A) - PIRQ F + * IR1Bh HD Audio INT(A) - PIRQ G + * IR1Ch PCIe INT(ABCD) - PIRQ EFGH + * IR1Dh EHCI INT(A) - PIRQ D + * IR1Eh SIO INT(ABCD) - PIRQ BDEF + * IR1Fh LPC INT(ABCD) - PIRQ HGBC +*/ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PUNIT_DEV, F, F, F, F), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c new file mode 100644 index 00000000000..678d2e29233 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/logo.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "mainboard.h" + +static char logo_data[1 * MiB]; +static size_t logo_data_sz = 0; + +void *load_logo(size_t *logo_size) +{ + const char *filename = "logo.bmp"; + + if (logo_data_sz != 0) { + if (logo_size) + *logo_size = logo_data_sz; + return (void *)logo_data; + } + + logo_data_sz = cbfs_boot_load_file(filename, logo_data, + sizeof(logo_data), CBFS_TYPE_RAW); + if (logo_data_sz == 0) + return NULL; + + if (logo_size) + *logo_size = logo_data_sz; + + printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", + logo_data_sz); + + return (void *)logo_data; +} diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c new file mode 100644 index 00000000000..ff2564d67a7 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "onboard.h" +#include "mainboard.h" + +/* + * Declare the resources we are using + */ +static void mainboard_reserve_resources(struct device *dev) +{ + unsigned int idx = 0; + struct resource *res; + + /* + * CPLD: Reserve the IRQ here all others are within the default LPC + * range 0 to 1000h + */ + res = new_resource(dev, idx++); + res->base = 0x7; + res->size = 0x1; + res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(struct device *dev) +{ + mainboard_reserve_resources(dev); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/mainboard/facebook/fbg1701/mainboard.h similarity index 79% rename from src/soc/intel/cannonlake/cbmem.c rename to src/mainboard/facebook/fbg1701/mainboard.h index 300556a45f5..e161da03965 100644 --- a/src/soc/intel/cannonlake/cbmem.c +++ b/src/mainboard/facebook/fbg1701/mainboard.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,9 @@ * GNU General Public License for more details. */ -#include +#ifndef MAINBOARD_H +#define MAINBOARD_H -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} +void *load_logo(size_t *logo_size); + +#endif diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/mainboard/facebook/fbg1701/onboard.h similarity index 50% rename from src/soc/intel/skylake/romstage/car_stage.S rename to src/mainboard/facebook/fbg1701/onboard.h index ee04f0272d3..d1fd0509a6b 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -1,7 +1,9 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,28 +15,22 @@ * GNU General Public License for more details. */ -/* I/O delay between post codes on failure */ -#define LHLT_DELAY 0x50000 +#ifndef ONBOARD_H +#define ONBOARD_H -.text -.global car_stage_entry -car_stage_entry: - call romstage_c_entry - #include "src/drivers/intel/fsp1_1/after_raminit.S" +/* SD CARD gpio */ +#define SDCARD_CD 81 /* Not used */ +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F - movb $0x69, %ah - jmp .Lhlt +/* CPLD definitions */ +#define CPLD_PCB_VERSION_PORT 0x283 +#define CPLD_PCB_VERSION_MASK 0xF0 +#define CPLD_PCB_VERSION_BIT 4 + +#define CPLD_RESET_PORT 0x287 +#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 +#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 -.Lhlt: - xchg %al, %ah -#if CONFIG(POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) #endif - movl $LHLT_DELAY, %ecx -.Lhlt_Delay: - outb %al, $0xED - loop .Lhlt_Delay - jmp .Lhlt diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h b/src/mainboard/facebook/fbg1701/ramstage.c similarity index 59% rename from src/mainboard/gigabyte/ga-b75m-d3v/thermal.h rename to src/mainboard/facebook/fbg1701/ramstage.c index 9db69104a03..91dfe3b2cf8 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,13 +13,20 @@ * GNU General Public License for more details. */ -#ifndef GAB75MD3H_THERMAL_H -#define GAB75MD3H_THERMAL_H +#include +#include "mainboard.h" - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + if (CONFIG(FSP1_1_DISPLAY_LOGO)) { + size_t logo_len; + void *logo = NULL; - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 + logo = load_logo(&logo_len); -#endif + if (logo) { + params->PcdLogoPtr = (u32)logo; + params->PcdLogoSize = logo_len; + } + } +} diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c new file mode 100644 index 00000000000..e2e37d6387b --- /dev/null +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + struct region_device spd_rdev; + u8 spd_index = 0; + + if (CONFIG(ONBOARD_MICRON_MEM)) + spd_index = 1; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (uintptr_t)rdev_mmap_full(&spd_rdev); + memory_params->PcdMemChannel0Config = 1; /* Memory down */ + memory_params->PcdMemChannel1Config = 2; /* Disabled */ +} + +void mainboard_after_memory_init(void) +{ + printk(BIOS_DEBUG, "%s/%s called\n", __FILE__, __func__); + + /* Disable the Braswell UART hardware for COM1. */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 0); +} diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex new file mode 100644 index 00000000000..f18cbc2a87f --- /dev/null +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -0,0 +1,257 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A +# +# SINGLE DIE +# + +# 512MBx16 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 5-6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 5,6,7,8,9,10,11 +FE + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 1 = Auto Self Refresh (ASR) is supported +# byte [7] : 1 = Partial Array Self Refres (PASR) is supported +85 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 1 = Non-Standard Device +80 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 2C + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4D 54 34 31 4B 35 31 32 4D 31 36 48 41 2D 31 32 +35 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 2C + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex new file mode 100644 index 00000000000..64faf1e163d --- /dev/null +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -0,0 +1,254 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018-2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0 +# +# DUAL DIE +# +# 512Mb x16 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 5-6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 100b = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 001b = 2 ranks +# bits[7:6]: reserved +0A + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 5,6,7,8,9,10,11 +FE + +# 15 CAS Latencies supported, Most Significate Byte +# Not supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 48 tRRD = 6.0ns DDR3-1600, 1KB +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0x680 : tRFC = 208ns 4 Gb +80 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0x680 : tRFC = 208ns 4 Gb +06 + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns DDR3-1600K, 2 KB page size +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns DDR3-1600K, 2 KB page size +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [2]: 1 = Auto Self Refresh (ASR) is supported +04 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 01b = multi load stack +# byte [6:4] : 100b = 8 die +# byte [7] : 0 = Standard Device +41 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 CE + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +12 1B + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4B 34 42 38 47 31 36 34 36 44 2D 4D 59 4B 30 20 +20 20 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 CE + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c new file mode 100644 index 00000000000..bc908f04b34 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * SPI lockdown configuration + */ +#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ +#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ + +#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ +#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ + +#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ +#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ + +#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ +#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ +#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ + +#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ +#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ +#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ + +#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ + /* with flashrom */ + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) + +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) + +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = CMD_W25_WREN, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +} diff --git a/src/mainboard/facebook/watson/mainboard.c b/src/mainboard/facebook/watson/mainboard.c index 3a1692fa1d6..403090a06fc 100644 --- a/src/mainboard/facebook/watson/mainboard.c +++ b/src/mainboard/facebook/watson/mainboard.c @@ -29,7 +29,7 @@ static void mainboard_enable(struct device *dev) static void mainboard_init(void *chip_info) { -#if !IS_ENABLED(CONFIG_ENABLE_TURBO) +#if !CONFIG(ENABLE_TURBO) disable_turbo(); #endif } diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc index f3d7e76263f..057b5bfcd33 100644 --- a/src/mainboard/foxconn/d41s/Makefile.inc +++ b/src/mainboard/foxconn/d41s/Makefile.inc @@ -1,2 +1,4 @@ +romstage-y += early_init.c +bootblock-y += early_init.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/early_init.c similarity index 90% rename from src/mainboard/foxconn/d41s/romstage.c rename to src/mainboard/foxconn/d41s/early_init.c index ecff4b9a2df..6568d96139c 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,13 +24,12 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) -void mb_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index bf940b46aad..ca952ba7c6e 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 01c6edd0976..ec4541f92eb 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 81669ed8231..aaa3422c02a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -24,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -256,8 +256,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 659f47c5b01..ceb2dbc85f5 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -1,9 +1,9 @@ -if BOARD_GIGABYTE_GA_B75M_D3H +if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select INTEL_INT15 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT @@ -29,20 +30,23 @@ config MAINBOARD_DIR string default gigabyte/ga-b75m-d3h +config VARIANT_DIR + string + default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H + default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + config MAINBOARD_PART_NUMBER string - default "GA-B75M-D3H" + default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H + default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V config MAX_CPUS int default 8 -config VGA_BIOS_ID - string - default "8086,0162" - -config VGA_BIOS_FILE +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE string - default "pci8086,0162.rom" + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" -endif # BOARD_GIGABYTE_GA_B75M_D3H +endif # BOARD_GIGABYTE_GA_B75M* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name index 571f6d1647f..f8fbe54215f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_GIGABYTE_GA_B75M_D3H bool "GA-B75M-D3H" + +config BOARD_GIGABYTE_GA_B75M_D3V + bool "GA-B75M-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 63976c4b793..07fc277c287 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -13,5 +13,10 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl index 34de86f9761..a1c79896d7e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -18,6 +18,6 @@ Scope (\_SB) { Device (PWRB) { - Name (_HID, EisaId("PNP0C0C")) + Name (_HID, EisaId ("PNP0C0C")) } } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl index 06031646b9a..10856d33948 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -17,14 +17,13 @@ * entering a sleep state. The sleep state number is passed in Arg0 */ -Method(_PTS,1) +Method (_PTS, 1) { - } /* The _WAK method is called on system wakeup */ Method(_WAK,1) { - Return(Package(){0,0}) + Return (Package () {0, 0}) } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl index 78bf687938f..e69de29bb2d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt index 7ee7f956d8e..c4fb591c0be 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -1,5 +1,5 @@ Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4150#ov ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt b/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt new file mode 100644 index 00000000000..ccbf6eed7f9 Binary files /dev/null and b/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt differ diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7a3568aba3a..ceb92793653 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -21,16 +21,15 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - # GPI routing register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" @@ -109,7 +108,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end end device pci 1f.2 on # SATA Controller 1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 67054cc28d6..c00ee30e6b4 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -24,7 +24,9 @@ DefinitionBlock( #include // Some generic macros + #include "acpi/mainboard.asl" #include "acpi/platform.asl" + #include "acpi/thermal.asl" #include /* global NVS and variables. */ #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c index 23cd570fb21..34610f09ee7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -13,9 +13,7 @@ #include -const u32 cim_verb_data[] = { - /* FIXME: Add configuration for sound */ -}; +#include const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 4e8d9f579f9..cc267579143 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -19,54 +19,16 @@ #include #include -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->init = mainboard_init; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable }; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index aa5f4840a3a..67bcbcb8c94 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -25,12 +25,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | @@ -40,7 +34,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} +void mainboard_config_superio(void) +{ /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -87,18 +84,21 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 5, 6 }, }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mainboard_early_init(int s3resume) { - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); } -void mainboard_early_init(int s3resume) +/* FIXME: The GA-B75M-D3V only has two DIMM slots! */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); } -void mainboard_config_superio(void) +void mainboard_rcba_config(void) { + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/gpio.c rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h new file mode 100644 index 00000000000..53e7c65ddbf --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GA_B75M_D3H_HDA_VERB_H +#define GA_B75M_D3H_HDA_VERB_H + +const u32 cim_verb_data[] = { + /* FIXME: Add configuration for sound */ +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/board_info.txt new file mode 100644 index 00000000000..5535d9af60c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4151#ov +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/gpio.c rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h similarity index 93% rename from src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h index 3ae6b5d01e9..c84c80df7b8 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h @@ -11,7 +11,8 @@ * GNU General Public License for more details. */ -#include +#ifndef GA_B75M_D3V_HDA_VERB_H +#define GA_B75M_D3V_HDA_VERB_H const u32 cim_verb_data[] = { /* coreboot specific header */ @@ -36,6 +37,4 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) }; -const u32 pc_beep_verbs[] = {}; - -AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig deleted file mode 100644 index e01d4847ef2..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -if BOARD_GIGABYTE_GA_B75M_D3V - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_ITE_IT8728F - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_LIBGFXINIT - -config DRAM_RESET_GATE_GPIO - int - default 25 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3v - -config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3V" - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_ID - string - default "8086,0102" - -config VGA_BIOS_FILE - string - default "pci8086,0102.rom" - -endif # BOARD_GIGABYTE_GA_B75M_D3V diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name deleted file mode 100644 index 92f5744f2d7..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_GA_B75M_D3V - bool "GA-B75M-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl deleted file mode 100644 index 4c50b6c689b..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl +++ /dev/null @@ -1,4 +0,0 @@ -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl deleted file mode 100644 index ca561a50394..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -External (\PPKG, MethodObj) - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x03) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 10 seconds - Name (_TSP, 100) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) - { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt deleted file mode 100644 index ede1945aec8..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Release date: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default deleted file mode 100644 index 6f3cec735e8..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default +++ /dev/null @@ -1,6 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Enable -nmi=Enable -sata_mode=AHCI -gfx_uma_size=32M diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb deleted file mode 100644 index a00e2ee0c5d..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ /dev/null @@ -1,120 +0,0 @@ -chip northbridge/intel/sandybridge - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge - subsystemid 0x1458 0x5000 - end - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller - subsystemid 0x1458 0xd000 - end - - chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - - # GPI routing - register "alt_gp_smi_en" = "0x0000" - register "gen1_dec" = "0x003c0a01" - - # Set max SATA speed to 6.0 Gb/s - register "sata_port_map" = "0x3f" - register "sata_interface_speed_support" = "0x3" - - register "pcie_port_coalesce" = "0" - register "p_cnt_throttling_supported" = "0" - register "docking_supported" = "0" - register "c2_latency" = "0x0065" - - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x1458 0x5007 - end - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x1458 0x5006 - end - device pci 1b.0 on # High Definition Audio - subsystemid 0x1458 0xa002 - end - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 - device pci 00.0 on # PCI 10ec:8168 - subsystemid 0x1458 0xe000 - end - end - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x1458 0x5006 - end - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - subsystemid 0x1458 0x5001 - chip superio/ite/it8728f - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # EC - io 0x60 = 0xa30 - irq 0x70 = 9 - io 0x62 = 0xa20 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.a off end # IR - end - end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x1458 0xb005 - end - device pci 1f.3 on # SMBus - subsystemid 0x1458 0x5001 - end - device pci 1f.4 off end - device pci 1f.5 off end # SATA Controller 2 - end - end -end diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c deleted file mode 100644 index 4e8d9f579f9..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c deleted file mode 100644 index 035e20e2a9b..00000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define SUPERIO_BASE 0x2e -#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) -#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) -#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) - -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - -void pch_enable_lpc(void) -{ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | - CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); - - /* Initialize SuperIO */ - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot - - /* FIXME: These values could be configured in ramstage */ - ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16 - ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34 - ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port - ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00 - ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear! - ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear! - ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in - ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable - ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ? - ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ? - ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12) - - /* EC SIO settings */ - ite_reg_write(IT8728F_EC, 0xf1, 0xc0); - ite_reg_write(IT8728F_EC, 0xf6, 0xf0); - ite_reg_write(IT8728F_EC, 0xf9, 0x48); - ite_reg_write(IT8728F_EC, 0x60, 0x0a); - ite_reg_write(IT8728F_EC, 0x61, 0x30); - ite_reg_write(IT8728F_EC, 0x62, 0x0a); - ite_reg_write(IT8728F_EC, 0x63, 0x20); - ite_reg_write(IT8728F_EC, 0x30, 0x01); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, -}; - -/* FIXME: This board only has two DIMM slots! */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); -} - -void mainboard_early_init(int s3resume) -{ -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 05edb278d97..8b47c4f21f9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -63,8 +63,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1458 0x5004 end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 5fba47a90fe..5e46365bba5 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -40,14 +40,6 @@ config MAINBOARD_PART_NUMBER string default "GA-H61M-S2PV" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x5001 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1458 - config MAX_CPUS int default 8 diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl index 0b9250d5747..e520724101e 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl @@ -16,12 +16,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -43,7 +37,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -64,14 +57,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 3f350e8dd2a..69b086fefea 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -72,4 +72,8 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 170e1686da6..d2b6d0eb9a6 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -17,6 +17,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c @@ -32,3 +33,5 @@ subdirs-y += variants/$(VARIANT_DIR) subdirs-y += variants/$(VARIANT_DIR)/spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index a07ce3e7bea..cd6a8305646 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -16,8 +16,14 @@ #include -#if !CONFIG(BOARD_GOOGLE_BUDDY) +/* + * WLAN on Buddy connected to RP4, becomes RP2 after coalesce + */ +#if CONFIG(BOARD_GOOGLE_BUDDY) +Scope (\_SB.PCI0.RP02) +#else Scope (\_SB.PCI0.RP01) +#endif { Device (WLAN) { @@ -35,7 +41,6 @@ Scope (\_SB.PCI0.RP01) } } } -#endif #include diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 942e9dd8db7..0147a317fee 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {CROS_WP_GPIO, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index aea8e211fab..568c4c819c3 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -17,11 +17,9 @@ #include #include #include -#include #include #include #include -#include #include #include "variant.h" @@ -29,24 +27,16 @@ __weak void variant_romstage_entry(struct romstage_params *rp) { } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - struct pei_data pei_data; - - post_code(0x32); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); +} +void mainboard_post_raminit(struct romstage_params *rp) +{ /* Do variant-specific init */ variant_romstage_entry(rp); } diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_paine/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h rename to src/mainboard/google/auron/variants/auron_paine/gpio.c index eca65d14fc6..e8b6c065b18 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef AURON_YUNA_GPIO_H -#define AURON_YUNA_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 12c876e61b9..2991d15eff4 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index 62d4f522f71..84e26db1b7c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -26,7 +26,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_yuna/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h rename to src/mainboard/google/auron/variants/auron_yuna/gpio.c index 44b930a4419..e8b6c065b18 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef AURON_PAINE_GPIO_H -#define AURON_PAINE_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 12c876e61b9..2991d15eff4 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index 62d4f522f71..84e26db1b7c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -26,7 +26,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb index e6627949b57..f75da84eee8 100644 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -90,8 +90,8 @@ chip soc/intel/broadwell device pci 1b.0 off end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on end # USB2 EHCI diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h b/src/mainboard/google/auron/variants/buddy/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/buddy/include/variant/gpio.h rename to src/mainboard/google/auron/variants/buddy/gpio.c index efa720f60df..fbb682abf97 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -14,12 +14,9 @@ * GNU General Public License for more details. */ -#ifndef BUDDY_GPIO_H -#define BUDDY_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -117,5 +114,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 788fbdc61ec..e9fd212e8dc 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -117,27 +117,3 @@ Scope (\_SB.PCI0.RP01) } } } - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - - /* GPIO10 is WLAN_WAKE_L_Q */ - Name (GPIO, BOARD_WLAN_WAKE_GPIO) - - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } - } -} diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 9f8188fe43e..dcda04dbb6e 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -35,7 +35,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h b/src/mainboard/google/auron/variants/gandof/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/gandof/include/variant/gpio.h rename to src/mainboard/google/auron/variants/gandof/gpio.c index 68fe4a01906..3de9a0b9d7a 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef GANDOF_GPIO_H -#define GANDOF_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 12c876e61b9..2991d15eff4 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index cd7a66332d0..29b298839fd 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -29,7 +29,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h b/src/mainboard/google/auron/variants/lulu/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/lulu/include/variant/gpio.h rename to src/mainboard/google/auron/variants/lulu/gpio.c index 726dcc755e8..a46c4d4e2ac 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -14,12 +14,9 @@ * GNU General Public License for more details. */ -#ifndef LULU_GPIO_H -#define LULU_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -117,5 +114,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index ac99f5c7bc3..bd76947d688 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 97302b84865..a76cc858c3e 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -29,7 +29,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -38,7 +39,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h b/src/mainboard/google/auron/variants/samus/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/samus/include/variant/gpio.h rename to src/mainboard/google/auron/variants/samus/gpio.c index 8362a4dbfbe..72ddcb2259e 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef SAMUS_GPIO_H -#define SAMUS_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index dd632f30d73..ffb90f997d6 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 872d49ddeec..df5da9df20d 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -59,4 +59,8 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 5e45472cedc..bb90e9780b7 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -15,6 +15,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c ramstage-y += lan.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 92bb7b445a4..e695ab5f08e 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -36,7 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e0fd105eb13..7bda2f66943 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -25,8 +24,8 @@ #include #include #include -#include "onboard.h" +#include "onboard.h" void mainboard_suspend_resume(void) { diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index 1a03f2340bb..e786ef56fd0 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -24,6 +23,7 @@ #include #include #include + #include "onboard.h" void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 570a1b3573f..76bcc3d3b09 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -40,16 +40,12 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - config MAINBOARD_VENDOR string default "Hewlett-Packard" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BUTTERFLY diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 2301d3eec44..7f72ad24bfa 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -40,9 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {WP_GPIO, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: virtual GPIO active high */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* lid switch value from EC */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 9cc13c94732..c298689639e 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -264,7 +264,8 @@ static int butterfly_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index 71e85562d6c..b0d2d99996c 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,15 @@ FLASH@0x0 8M { RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - # TODO(hungte): Remove RO_PRESERVE. - RO_PRESERVE(PRESERVE) { - RO_DDR_TRAINING 8K - RO_FSG - } + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index cb4f5d061a2..7a19d32e9c6 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -16,9 +16,22 @@ #include #include #include +#include + +static struct usb_board_data usb1_board_data = { + .pll_bias_control_2 = 0x28, + .imp_ctrl1 = 0x08, + .port_tune1 = 0x20, +}; static void setup_usb(void) { + /* + * Primary USB is used only for DP functionality on cheza platform. + * Hence Setting up only Secondary USB DWC3 controller. + */ + setup_usb_host1(&usb1_board_data); + gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */ } diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index ad8506193d9..de737b11599 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -14,7 +14,22 @@ */ #include +#include +#include + +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb1(); +} void platform_romstage_main(void) { + prepare_usb(); + + /* QCLib: DDR init & train */ + qclib_load_and_run(); } diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 1d9b7b791b3..bf0cd095f7a 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN select HAVE_ACPI_RESUME select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN select SYSTEM_TYPE_LAPTOP + select USE_GOOGLE_FSP if BOARD_GOOGLE_BASEBOARD_CYAN @@ -107,4 +108,12 @@ config GBB_HWID default "ULTIMA TEST A-A 6017" if BOARD_GOOGLE_ULTIMA default "WIZPIG TEST A-A 0597" if BOARD_GOOGLE_WIZPIG +config CBFS_SIZE + hex + default 0x200000 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 81bec16ea50..b412551a4ac 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -35,7 +35,7 @@ Scope (\_SB.PCI0.I2C2) } }) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 4a1d48de7b9..d697aace3ea 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -26,7 +26,7 @@ Scope (\_SB.PCI0.I2C5) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 44101e347c8..5d5bc556e54 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -35,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 397f6d2637d..3afdaaab55f 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -42,6 +42,7 @@ DefinitionBlock( #else #include #endif + #include } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index aa20593d5f0..dea73e9eeed 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -16,32 +16,13 @@ #include #include -#include -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} +#include "spd/spd_util.h" void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - /* Update SPD data */ - if (CONFIG(BOARD_GOOGLE_CYAN)) { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - } else - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; + spd_memory_init_params(memory_params); /* Variant-specific memory params */ variant_memory_init_params(memory_params); diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index af694a43395..7c66e947fc1 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -40,11 +40,24 @@ __weak uint8_t get_ramid(void) return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +static void *get_spd_pointer(int *dual) { + char *spd_file; + size_t spd_file_len; + int total_spds; int ram_id = 0; int spd_index = 0; + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_PAGE_LEN) + die("Missing SPD data."); + total_spds = spd_file_len / SPD_PAGE_LEN; + ram_id = get_ramid(); printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); @@ -54,33 +67,20 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) return NULL; } /* Return the serial product data for the RAM */ - return &spd_file_content[SPD_PAGE_LEN * spd_index]; + return &spd_file[SPD_PAGE_LEN * spd_index]; } /* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *ps) +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params) { - char *spd_file; - size_t spd_file_len; void *spd_content; int dual_channel = 0; - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < SPD_PAGE_LEN) - die("Missing SPD data."); - /* * Both channels are always present in SPD data. Always use matched * DIMMs so use the same SPD data for each DIMM. */ - spd_content = get_spd_pointer(spd_file, - spd_file_len / SPD_PAGE_LEN, - &dual_channel); + spd_content = get_spd_pointer(&dual_channel); if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) { printk(BIOS_DEBUG, "SPD Data:\n"); hexdump(spd_content, SPD_PAGE_LEN); @@ -94,21 +94,27 @@ void mainboard_fill_spd_data(struct pei_data *ps) * 2=DimmDisabled */ if (spd_content != NULL) { - ps->spd_data_ch0 = spd_content; - ps->spd_ch0_config = 1; + memory_params->PcdMemChannel0Config = 1; printk(BIOS_DEBUG, "Channel 0 DIMM soldered down\n"); if (dual_channel) { printk(BIOS_DEBUG, "Channel 1 DIMM soldered down\n"); - ps->spd_data_ch1 = spd_content; - ps->spd_ch1_config = 1; + memory_params->PcdMemChannel1Config = 1; } else { printk(BIOS_DEBUG, "Channel 1 DIMM not installed\n"); - ps->spd_ch1_config = 2; + memory_params->PcdMemChannel1Config = 2; } } + + /* Update SPD data */ + if (CONFIG(BOARD_GOOGLE_CYAN)) { + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (uintptr_t)spd_content; + } else { + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + } } -static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) +static void set_dimm_info(const uint8_t *spd, struct dimm_info *dimm) { const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; @@ -171,9 +177,15 @@ static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) void mainboard_save_dimm_info(struct romstage_params *params) { + const void *spd_content; + int dual_channel; struct dimm_info *dimm; struct memory_info *mem_info; + spd_content = get_spd_pointer(&dual_channel); + if (spd_content == NULL) + return; + /* * Allocate CBMEM area for DIMM information used to populate SMBIOS * table 17 @@ -186,13 +198,13 @@ void mainboard_save_dimm_info(struct romstage_params *params) /* Describe the first channel memory */ dimm = &mem_info->dimm[0]; - set_dimm_info(params->pei_data->spd_data_ch0, dimm); + set_dimm_info(spd_content, dimm); mem_info->dimm_cnt = 1; /* Describe the second channel memory */ - if (params->pei_data->spd_ch1_config == 1) { + if (dual_channel) { dimm = &mem_info->dimm[1]; - set_dimm_info(params->pei_data->spd_data_ch1, dimm); + set_dimm_info(spd_content, dimm); dimm->channel_num = 1; mem_info->dimm_cnt = 2; } diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h index 11d6eaa16d9..0c5b3265ef2 100644 --- a/src/mainboard/google/cyan/spd/spd_util.h +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -16,7 +16,10 @@ #ifndef SPD_UTIL_H #define SPD_UTIL_H +#include + uint8_t get_ramid(void); int get_variant_spd_index(int ram_id, int *dual); +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); #endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb index 2e708af0d6a..a1ab5108109 100644 --- a/src/mainboard/google/cyan/variants/celes/devicetree.cb +++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb @@ -73,12 +73,6 @@ chip soc/intel/braswell register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect - # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) - register "D0Usb2Port0PerPortRXISet" = "2" - register "D0Usb2Port1PerPortRXISet" = "2" - register "D0Usb2Port2PerPortRXISet" = "2" - register "D0Usb2Port3PerPortRXISet" = "2" - register "D0Usb2Port4PerPortRXISet" = "2" # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index 88b17f5da7e..6c522a1d0ce 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -19,29 +19,36 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) params->Usb2Port0PerPortPeTxiSet = 7; params->Usb2Port0PerPortTxiSet = 0; params->Usb2Port0IUsbTxEmphasisEn = 3; params->Usb2Port0PerPortTxPeHalf = 1; + params->D0Usb2Port0PerPortRXISet = 2; params->Usb2Port1PerPortPeTxiSet = 7; params->Usb2Port1PerPortTxiSet = 0; params->Usb2Port1IUsbTxEmphasisEn = 3; params->Usb2Port1PerPortTxPeHalf = 1; + params->D0Usb2Port1PerPortRXISet = 2; params->Usb2Port2PerPortPeTxiSet = 7; params->Usb2Port2PerPortTxiSet = 6; params->Usb2Port2IUsbTxEmphasisEn = 3; params->Usb2Port2PerPortTxPeHalf = 1; + params->D0Usb2Port2PerPortRXISet = 2; params->Usb2Port3PerPortPeTxiSet = 7; params->Usb2Port3PerPortTxiSet = 6; params->Usb2Port3IUsbTxEmphasisEn = 3; params->Usb2Port3PerPortTxPeHalf = 1; + params->D0Usb2Port3PerPortRXISet = 2; params->Usb2Port4PerPortPeTxiSet = 7; params->Usb2Port4PerPortTxiSet = 6; params->Usb2Port4IUsbTxEmphasisEn = 3; params->Usb2Port4PerPortTxPeHalf = 1; + params->D0Usb2Port4PerPortRXISet = 2; } } diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index 5e94e715fa6..7799e8d2b33 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c +ramstage-y += ramstage.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb index 1ce056f32e4..807dbcb2fed 100644 --- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb +++ b/src/mainboard/google/cyan/variants/kefka/devicetree.cb @@ -80,13 +80,6 @@ chip soc/intel/braswell register "I2C5Frequency" = "1" register "I2C6Frequency" = "1" - # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) - register "D0Usb2Port0PerPortRXISet" = "2" - register "D0Usb2Port1PerPortRXISet" = "2" - register "D0Usb2Port2PerPortRXISet" = "2" - register "D0Usb2Port3PerPortRXISet" = "2" - register "D0Usb2Port4PerPortRXISet" = "2" - # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c new file mode 100644 index 00000000000..d790708cce5 --- /dev/null +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { + + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) + params->D0Usb2Port0PerPortRXISet = 2; + params->D0Usb2Port1PerPortRXISet = 2; + params->D0Usb2Port2PerPortRXISet = 2; + params->D0Usb2Port3PerPortRXISet = 2; + params->D0Usb2Port4PerPortRXISet = 2; + } +} diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb index 65e662c5dd6..e1bbb0ac5b8 100644 --- a/src/mainboard/google/cyan/variants/relm/devicetree.cb +++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb @@ -80,13 +80,6 @@ chip soc/intel/braswell register "I2C5Frequency" = "1" register "I2C6Frequency" = "1" - # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) - register "D0Usb2Port0PerPortRXISet" = "2" - register "D0Usb2Port1PerPortRXISet" = "2" - register "D0Usb2Port2PerPortRXISet" = "2" - register "D0Usb2Port3PerPortRXISet" = "2" - register "D0Usb2Port4PerPortRXISet" = "2" - # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c index 27f9dfa2413..3fbd2aebd96 100644 --- a/src/mainboard/google/cyan/variants/relm/ramstage.c +++ b/src/mainboard/google/cyan/variants/relm/ramstage.c @@ -36,5 +36,13 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) params->Usb2Port3PerPortTxiSet = 0; params->Usb2Port3IUsbTxEmphasisEn = 2; params->Usb2Port3PerPortTxPeHalf = 1; + + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) + params->D0Usb2Port0PerPortRXISet = 2; + params->D0Usb2Port1PerPortRXISet = 2; + params->D0Usb2Port2PerPortRXISet = 2; + params->D0Usb2Port3PerPortRXISet = 2; + params->D0Usb2Port4PerPortRXISet = 2; } } diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index c06f8394eb0..974cd49f25a 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -30,9 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {EXYNOS5_GPD1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: active low */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: active high (LID_GPIO) */ {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"}, diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index e812189923c..46939b70e9d 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -350,7 +350,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 657320cba33..7132b04698e 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -28,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index e866c620d9a..f2c6851a3fe 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include #include -#include #include void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1dd15d..f8209242806 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -167,6 +167,16 @@ chip soc/intel/icelake }, }" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 06a4de9d35d..8c276e9ae16 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index 2f365a7b5cd..077bed4bf14 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 3bd5b641c01..31887c59fb3 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, /* Lid switch always open */ {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 026dd3e5dd1..7ce13005096 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -29,9 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ {-1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: active high */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* TODO: Power: active low / high depending on board id */ {GPIO(X5), ACTIVE_LOW, -1, "power"}, diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index e3efd34529a..13e2a4743fd 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -34,10 +34,6 @@ struct max77620_init_reg { u8 delay; }; -static struct max77620_init_reg init_list[] = { - /* TODO */ -}; - static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) { if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) { @@ -51,20 +47,8 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) } } -static void pmic_slam_defaults(unsigned bus) -{ - int i; - for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct max77620_init_reg *reg = &init_list[i]; - pmic_write_reg(bus, reg->reg, reg->val, reg->delay); - } -} - void pmic_init(unsigned bus) { - /* Restore PMIC POR defaults, in case kernel changed 'em */ - pmic_slam_defaults(bus); - /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1); diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 69c3a7a3c74..d0bdbb09400 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -68,8 +68,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {PP_SW, ACTIVE_LOW, read_gpio(PP_SW), "presence"}, - {get_rec_sw_gpio_pin(), ACTIVE_LOW, - read_gpio(get_rec_sw_gpio_pin()), "recovery"}, {get_wp_status_gpio_pin(), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index c8ab88a7fa9..8025374efa1 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -74,7 +74,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index f826b55ea8e..b6029dd0f9b 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 81f0866dd68..f2daa38d003 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -15,62 +15,40 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include -#include #include -#include "spd/spd.h" #include #include -void mainboard_romstage_entry(struct romstage_params *params) +#include "spd/spd_util.h" +#include "spd/spd.h" + +void mainboard_pre_raminit(struct romstage_params *params) { #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(25); #endif +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ /* Get SPD index */ - gpio_t spd_gpios[] = { + const gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, GPIO_MEM_CONFIG_1, GPIO_MEM_CONFIG_2, GPIO_MEM_CONFIG_3, }; - params->pei_data->mem_cfg_id = - gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); - /* Initialize memory */ - romstage_common(params); -} + const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; - if (CONFIG(BOARD_GOOGLE_CAROLINE)) - memory_params->DdrFreqLimit = 1600; + + spd_memory_init_params(memory_params, spd_idx); + variant_memory_init_params(memory_params, spd_idx); } diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 391b7021723..b3cf3f94160 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -19,10 +19,11 @@ #include #include #include -#include #include #include #include + +#include "spd_util.h" #include "spd.h" static void mainboard_print_spd_info(uint8_t spd[]) @@ -83,13 +84,11 @@ __weak int is_dual_channel(const int spd_index) } /* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) +void spd_memory_init_params(MEMORY_INIT_UPD *const memory_params, int spd_index) { - char *spd_file; + uint8_t *spd_file; size_t spd_file_len; - int spd_index; - spd_index = pei_data->mem_cfg_id; printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ @@ -108,15 +107,15 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_index = 1; } - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - if (is_dual_channel(spd_index)) - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); - + const size_t spd_offset = spd_index * SPD_LEN; /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) + if (spd_file[spd_offset] == 0) die("Invalid SPD data."); - mainboard_print_spd_info(pei_data->spd_data[0][0]); + /* Assume same memory in both channels */ + memory_params->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset; + if (is_dual_channel(spd_index)) + memory_params->MemorySpdPtr10 = memory_params->MemorySpdPtr00; + + mainboard_print_spd_info(spd_file + spd_offset); } diff --git a/src/mainboard/google/glados/spd/spd_util.h b/src/mainboard/google/glados/spd/spd_util.h new file mode 100644 index 00000000000..90dbd5ff987 --- /dev/null +++ b/src/mainboard/google/glados/spd/spd_util.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_UTIL_H +#define SPD_UTIL_H + +#include + +void spd_memory_init_params(MEMORY_INIT_UPD *, int spd_index); + +#endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 13cfe4fecde..4c778970fe1 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -17,10 +17,10 @@ #include #include #include -#include -#include +#include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -39,12 +39,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h index bbab7fc1f58..72eef684b8f 100644 --- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h +++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h @@ -15,7 +15,10 @@ #ifndef GLADOS_VARIANT_H #define GLADOS_VARIANT_H +#include + int is_dual_channel(const int spd_index); void mainboard_gpio_smi_sleep(void); +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params, int spd_index); #endif /* GLADOS_VARIANT_H */ diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index a00eacf0ed2..d61a538d56b 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); + memory_params->DdrFreqLimit = 1600; } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index 2ce0a9001c4..fc27fb4b615 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index da83ed0f7d9..2d1b363caba 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index 2ce0a9001c4..fc27fb4b615 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 4fe88ef7c8e..cff00962917 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -17,8 +17,7 @@ #include #include #include -#include -#include +#include #define K4E6E304EB_MEM_ID 0x5 @@ -29,7 +28,8 @@ #define MEM_SINGLE_CHANB 0xb #define MEM_SINGLE_CHANC 0xc -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -54,17 +54,18 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Default Rcomp Target assignment */ const u16 *targeted_rcomp = RcompTarget; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - /* Override Rcomp Target assignment for specific SKU(s) */ - if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID) + if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(pei_data->RcompTarget, targeted_rcomp, - sizeof(pei_data->RcompTarget)); + memcpy(params->DqByteMapCh0, dq_map, + sizeof(params->DqByteMapCh0) * 2); + memcpy(params->DqsMapCpu2DramCh0, dqs_map, + sizeof(params->DqsMapCpu2DramCh0) * 2); + memcpy(params->RcompResistor, RcompResistor, + sizeof(params->RcompResistor)); + memcpy(params->RcompTarget, targeted_rcomp, + sizeof(params->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 00f49fecf75..4c7fa23f085 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -17,12 +17,12 @@ #include #include #include -#include -#include +#include #define K4E6E304EE_MEM_ID 0x3 -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -47,15 +47,16 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Default Rcomp Target assignment */ const u16 *targeted_rcomp = RcompTarget; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - /* Override Rcomp Target assignment for specific SKU(s) */ - if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) + if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(pei_data->RcompTarget, targeted_rcomp, - sizeof(pei_data->RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, targeted_rcomp, + sizeof(memory_params->RcompTarget)); } diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 7c18e12fd12..79d9b0f6404 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 53d00fb1887..c92a4923103 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -34,7 +34,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_WP.raw, wp_polarity, get_write_protect_state() ^ !wp_polarity, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, #if CONFIG(GRU_BASEBOARD_SCARLET) {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, #endif diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 63339f2dd8f..80451299f67 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 @@ -63,7 +64,9 @@ config GBB_HWID depends on CHROMEOS default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL - default "KOHAKU TEST 1953" if BOARD_GOOGLE_HATCH_WHL + default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS + default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED + default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU config MAINBOARD_DIR string @@ -77,6 +80,8 @@ config MAINBOARD_PART_NUMBER string default "Hatch" if BOARD_GOOGLE_HATCH default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL + default "Helios" if BOARD_GOOGLE_HELIOS + default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU config MAINBOARD_VENDOR @@ -99,6 +104,8 @@ config VARIANT_DIR string default "hatch" if BOARD_GOOGLE_HATCH default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL + default "helios" if BOARD_GOOGLE_HELIOS + default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU config VBOOT diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index eb8e61274a8..9a257259ad4 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -17,3 +17,15 @@ config BOARD_GOOGLE_KOHAKU select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMETLAKE + +config BOARD_GOOGLE_KINDRED + bool "-> Kindred" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE + +config BOARD_GOOGLE_HELIOS + bool "-> Helios" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index fa54148ee88..4119670ef40 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index bdf951b0161..2c630a8ce89 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -16,23 +16,63 @@ #include #include #include +#include #include #include #include #include +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +#define GPIO_MEM_CH_SEL GPP_F2 + +static int memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; - - const struct spd_info spd = { - .spd_by_index = true, - .spd_spec.spd_index = variant_memory_sku(), - }; + int mem_sku; + int is_single_ch_mem; variant_memory_params(&memcfg); - cannonlake_memcfg_init(&memupd->FspmConfig, - &memcfg, &spd); + mem_sku = memory_sku(); + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. + * Dual-DIMM memory is not used in hatch family, so we only + * fill in spd_info for CH0D0 and CH1D0 here. + */ + memcfg.spd[0].read_type = READ_SPD_CBFS; + memcfg.spd[0].spd_spec.spd_index = mem_sku; + if (!is_single_ch_mem) { + memcfg.spd[2].read_type = READ_SPD_CBFS; + memcfg.spd[2].spd_spec.spd_index = mem_sku; + } + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } void mainboard_get_dram_part_num(const char **part_num, size_t *len) diff --git a/src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex b/src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex new file mode 100644 index 00000000000..5fd8533ab73 --- /dev/null +++ b/src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex @@ -0,0 +1,32 @@ +21 01 0F 0E 15 19 90 08 00 00 00 0B 0B 03 00 00 +00 00 08 FF D4 01 00 00 78 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 08 7F C2 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e39f1405889..1123d537341 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -72,16 +72,15 @@ chip soc/intel/cannonlake # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" @@ -92,6 +91,16 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + device cpu_cluster 0 on device lapic 0 on end end @@ -204,7 +213,7 @@ chip soc/intel/cannonlake device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 on end #I2C #4 + device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 7e82b9b6ec6..0b6607595d1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -30,8 +30,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : EMR_GARAGE_DET */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_A8, NONE, DEEP), + /* A8 : PEN_GARAGE_DET_L */ + PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), @@ -339,17 +339,15 @@ static const struct pad_config gpio_table[] = { /* G4 : SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* G5 : SD_CD# */ - PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP => NC */ PAD_NC(GPP_G7, DN_20K), /* * H0 : HP_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. */ - PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, LEVEL), /* H1 : CNV_RF_RESET_L */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ @@ -428,7 +426,7 @@ static const struct pad_config s5_sleep_gpio_table[] = { PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ }; -const struct pad_config * __weak variant_sleep_gpio_table( +const struct pad_config *__weak variant_sleep_gpio_table( u8 slp_typ, size_t *num) { if (slp_typ == ACPI_S5) { @@ -441,6 +439,8 @@ const struct pad_config * __weak variant_sleep_gpio_table( /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index 1384ccfeb70..ff7db493341 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -21,7 +21,7 @@ #define DPTF_CPU_ACTIVE_AC3 80 #define DPTF_CPU_ACTIVE_AC4 75 -#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 @@ -31,7 +31,7 @@ #define DPTF_TSR0_ACTIVE_AC3 42 #define DPTF_TSR0_ACTIVE_AC4 39 -#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index 5d6311ba243..e83732cb62e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -22,13 +22,6 @@ #define GPIO_PCH_WP GPP_C20 -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 - - /* EC wake pin is LAN_WAKE# */ #define GPE_EC_WAKE GPE0_LAN_WAK diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index d41ad536f21..17bd5df63d1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -31,9 +31,6 @@ const struct pad_config *base_early_gpio_table(size_t *num); const struct pad_config *override_gpio_table(size_t *num); const struct pad_config *override_early_gpio_table(size_t *num); -/* Return memory SKU for the board. */ -int variant_memory_sku(void); - /* Return board specific memory configuration */ void variant_memory_params(struct cnl_mb_cfg *bcfg); diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index b6a66150fa3..bcfc49f20e6 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -15,26 +15,15 @@ #include #include -#include #include #include static const struct cnl_mb_cfg baseboard_memcfg = { - /* - * The dqs_map arrays map the ddr4 pins to the SoC pins - * for both channels. - * - * the index = pin number on ddr4 part - * the value = pin number on SoC - */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* Baseboard Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Set CaVref config to 2 */ .vref_ca_config = 2, @@ -46,32 +35,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = { void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) { memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); - /* - * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single - * channel skus and 0 for dual channel skus. - */ - if (gpio_get(GPP_F2) == 1) { - /* - * Single channel config: for Hatch, Channel 0 is - * always populated. - */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 1; - } else { - /* Dual channel config: both channels populated. */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 0; - } -} - -int __weak variant_memory_sku(void) -{ - const gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index cf6ee5ac97d..555cbb463c1 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -18,3 +18,5 @@ SPD_SOURCES += 8G_2400 # 0b010 SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 + +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c new file mode 100644 index 00000000000..7e737243873 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* C13 : EC_PCH_INT_L + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 22a0947b77e..562bb8b229e 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -44,6 +44,9 @@ chip soc/intel/cannonlake }, }" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic @@ -75,15 +78,17 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" @@ -129,7 +134,7 @@ chip soc/intel/cannonlake register "hid" = ""10EC5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H0_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc b/src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc index 4fa98eacf26..ecf5c2fbdbd 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc @@ -18,3 +18,5 @@ SPD_SOURCES += empty_ddr4 # 0b010 SPD_SOURCES += empty_ddr4 # 0b011 SPD_SOURCES += empty_ddr4 # 0b100 SPD_SOURCES += 8G_2666 # 0b101 + +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch_whl/gpio.c b/src/mainboard/google/hatch/variants/hatch_whl/gpio.c new file mode 100644 index 00000000000..7e737243873 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch_whl/gpio.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* C13 : EC_PCH_INT_L + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 5bcb67e9c7c..eec78807527 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -29,6 +29,9 @@ chip soc/intel/cannonlake }, }" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic @@ -60,15 +63,17 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" @@ -114,7 +119,7 @@ chip soc/intel/cannonlake register "hid" = ""10EC5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H0_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc new file mode 100644 index 00000000000..cf6ee5ac97d --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl new file mode 100644 index 00000000000..f1f09438fae --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/purism/librem_skl/pei_data.h b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h similarity index 61% rename from src/mainboard/purism/librem_skl/pei_data.h rename to src/mainboard/google/hatch/variants/helios/include/variant/ec.h index 320d9803d10..768987d2258 100644 --- a/src/mainboard/purism/librem_skl/pei_data.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Purism SPC. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef _MAINBOARD_PEI_DATA_H_ -#define _MAINBOARD_PEI_DATA_H_ +#ifndef VARIANT_EC_H +#define VARIANT_EC_H -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#include #endif diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h new file mode 100644 index 00000000000..d99e2bbd65e --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb new file mode 100644 index 00000000000..84f0e29afaf --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -0,0 +1,46 @@ +chip soc/intel/cannonlake + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Digitizer | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on end +end diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc new file mode 100644 index 00000000000..8173ca4389a --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl new file mode 100644 index 00000000000..f1f09438fae --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h new file mode 100644 index 00000000000..768987d2258 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h new file mode 100644 index 00000000000..d99e2bbd65e --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb new file mode 100644 index 00000000000..562bb8b229e --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -0,0 +1,158 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 2f590bf0261..9cdff32074e 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -12,12 +12,9 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += 8G_2400 # 0b010 -SPD_SOURCES += 8G_2666 # 0b011 -SPD_SOURCES += 16G_2400 # 0b100 -SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES = LP_8G_2133 # 0b000 + +romstage-y += memory.c bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c new file mode 100644 index 00000000000..490124776e1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4}, + .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4}, + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Kohaku uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Kohaku Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6e6414e8a82..69875bdde29 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,18 +1,114 @@ chip soc/intel/cannonlake - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Digitizer | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + device usb 2.5 off end + end + chip drivers/usb/acpi + device usb 3.4 off end + end + end + end + end + device pci 14.5 off end # SDCard + + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + # TODO: enable this when b/123967687 is fixed. + # register "generic.wake" = "GPE0_DW2_27" + # also set next line to ACPI_IRQ_WAKE_EDGE_LOW + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + register "generic.reset_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x09 on end + end + end # I2C #2 + device pci 19.0 on + chip drivers/i2c/da7219 + # TODO: these settings were copied from another board + # with the same chip. verify the settings + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 0x1a on end + end + end + + # No PCIe WiFi + device pci 1d.5 off end + end # domain end diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 15ed05b04be..5ffc1bc435a 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -53,4 +53,8 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 01914bae7d5..116792fab7b 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c @@ -23,7 +24,11 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c -romstage-y += led.c +bootblock-y += led.c + +bootblock-y += bootblock.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/mainboard/google/jecht/bootblock.c similarity index 59% rename from src/soc/intel/skylake/include/soc/pei_wrapper.h rename to src/mainboard/google/jecht/bootblock.c index d53fe8b7690..43725cd7472 100644 --- a/src/soc/intel/skylake/include/soc/pei_wrapper.h +++ b/src/mainboard/google/jecht/bootblock.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2007-2010 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +14,18 @@ * GNU General Public License for more details. */ -#ifndef _SOC_PEI_WRAPPER_H_ -#define _SOC_PEI_WRAPPER_H_ +#include +#include +#include +#include "onboard.h" -#include +void bootblock_mainboard_early_init(void) +{ + /* Early SuperIO setup */ + it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_kill_watchdog(IT8772F_GPIO_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); -typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); - -void soc_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); - -#endif + /* Turn On Power LED */ + set_power_led(LED_ON); +} diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b3215a0ec66..2b72cae0363 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -37,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 3705feb28a2..4fc2ba0c93b 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -18,47 +18,24 @@ #include #include #include -#include #include #include #include #include #include #include -#include #include "onboard.h" -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - struct pei_data pei_data; - - post_code(0x32); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); - - if (CONFIG(CHROMEOS)) - init_bootmode_straps(); + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); } -void mainboard_pre_console_init(void) +void mainboard_post_raminit(struct romstage_params *rp) { - /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); - ite_kill_watchdog(IT8772F_GPIO_DEV); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn On Power LED */ - set_power_led(LED_ON); - + if (CONFIG(CHROMEOS)) + init_bootmode_straps(); } diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h b/src/mainboard/google/jecht/variants/guado/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/guado/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/guado/gpio.c index 4c167e3a589..60e769dbd01 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef GUADO_GPIO_H -#define GUADO_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h b/src/mainboard/google/jecht/variants/jecht/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/jecht/gpio.c index 94e6516ce70..6a2a64cd7b6 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef JECHT_GPIO_H -#define JECHT_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h b/src/mainboard/google/jecht/variants/rikku/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/rikku/gpio.c index f58ad24f674..bc065a03a15 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef RIKKU_GPIO_H -#define RIKKU_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h b/src/mainboard/google/jecht/variants/tidus/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/tidus/gpio.c index 846fe816d4f..78aa1776791 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef TIDUS_GPIO_H -#define TIDUS_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 3bce66bbd6f..195eb94378f 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 1bf6c070455..cfd56376337 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -145,13 +146,13 @@ static void mainboard_init(void *chip_info) pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ - clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), + clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), GPP_CLK2_REQ_MAP_MASK, GPP_CLK2_REQ_MAP_CLK_REQ2 << GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ - clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), + clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), GPP_CLK0_REQ_MAP_MASK, GPP_CLK0_REQ_MAP_CLK_REQ0 << GPP_CLK0_REQ_MAP_SHIFT); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 6bb41ae6b34..87890daf36a 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -35,7 +35,7 @@ Device (I2S) Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Return (RBUF) diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex index d4afea7263d..67640fe849b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex @@ -6,7 +6,7 @@ 16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index b9f1ba2226e..71f051f3120 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -82,8 +83,13 @@ static uint32_t get_adc_index(unsigned int channel) if (value < (voltages[id] + voltages[id + 1]) / 2) break; + /* The last level is NC and may be larger than standard tolerance. */ const int tolerance = 10000; /* 10,000 uV */ - assert(ABS(value - voltages[id]) < tolerance); + if (id < ADC_LEVELS - 1 && ABS(value - voltages[id]) > tolerance) { + printk(BIOS_ERR, "ADC channel %u value out of range: %d\n", + channel, value); + assert(0); + } return id; } diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 44e75e29f0b..2cef10e82bb 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -27,6 +27,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(EC_IRQ); gpio_input_pullup(CR50_IRQ); gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_EN_SPK_AMP, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -34,10 +35,10 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_WP.id, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 92d238ece23..977acc37392 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -23,6 +23,7 @@ #define EC_IN_RW GPIO(PERIPHERAL_EN14) #define CR50_IRQ GPIO(PERIPHERAL_EN3) #define GPIO_RESET GPIO(PERIPHERAL_EN8) +#define GPIO_EN_SPK_AMP GPIO(PERIPHERAL_EN12) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5fb8d7..40b8a49c61a 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include #include #include +#include #include static void configure_emmc(void) @@ -37,10 +38,22 @@ static void configure_usb(void) setup_usb_host(); } +static void configure_audio(void) +{ + /* Audio PWR*/ + mtcmos_audio_power_on(); + + /* SoC I2S */ + gpio_set_mode(GPIO(CAM_RST0), PAD_CAM_RST0_FUNC_I2S2_LRCK); + gpio_set_mode(GPIO(CAM_PDN1), PAD_CAM_PDN1_FUNC_I2S2_BCK); + gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); + gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); +} static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + configure_audio(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 81ae9c538dc..baaca43b908 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "early_init.h" @@ -28,6 +29,7 @@ void platform_romstage_main(void) mainboard_early_init(); mt6358_init(); + mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index fea82f67564..6d62f64e3e7 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_LINK config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC @@ -14,8 +14,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_NATIVE_VGA_INIT - select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_LIBGFXINIT select HAVE_IFD_BIN select HAVE_ME_BIN @@ -45,4 +43,9 @@ config GBB_HWID string depends on CHROMEOS default "X86 LINK TEST 6638" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_LINK diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 281ce32442f..89bb3650233 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -17,9 +17,6 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 5156404ab74..ecd7592823e 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -28,10 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO57 = PCH_SPI_WP_D */ {57, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - /* Recovery: the "switch" comes from the EC */ - /* -1 indicates that this is a pseudo GPIO */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: the "switch" comes from the EC */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c deleted file mode 100644 index e09785d8257..00000000000 --- a/src/mainboard/google/link/i915.c +++ /dev/null @@ -1,375 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "onboard.h" -#include "ec.h" -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include "i915io.h" - -enum { - vmsg = 1, vio = 2, vspin = 4, -}; - -static int verbose = 0; - -static unsigned int *mmio; -static unsigned int graphics; -static unsigned short addrport; -static unsigned short dataport; -static unsigned int physbase; -static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u32 link_edid_data[] = { - 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000, - 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259, - 0x00545017, 0x01010000, 0x01010101, 0x01010101, - 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031, - 0xb510003a, 0x19000010, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00, - 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000, - 0x31504c00, 0x45513932, 0x50532d31, 0x24003141, -}; - -#define READ32(addr) io_i915_READ32(addr) -#define WRITE32(val, addr) io_i915_WRITE32(val, addr) - -static char *regname(unsigned long addr) -{ - static char name[16]; - snprintf(name, sizeof(name), "0x%lx", addr); - return name; -} - -unsigned long io_i915_READ32(unsigned long addr) -{ - unsigned long val; - outl(addr, addrport); - val = inl(dataport); - if (verbose & vio) - printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); - return val; -} - -void io_i915_WRITE32(unsigned long val, unsigned long addr) -{ - if (verbose & vio) - printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); - outl(addr, addrport); - outl(val, dataport); -} - - -/* - 2560 - 4 words per - 4 *p - 10240 - 4k bytes per page - 4096/p - 2.50 - 1700 lines - 1700 * p - 4250.00 - PTEs -*/ -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - for(i = start; i < end; i++){ - u32 word = base + i*inc; - WRITE32(word|1,(i*4)|1); - } -} - -static unsigned long tickspermicrosecond = 1795; -static unsigned long long globalstart; - -static unsigned long -microseconds(unsigned long long start, unsigned long long end) -{ - unsigned long ret; - ret = ((end - start)/tickspermicrosecond); - return ret; -} - -static unsigned long globalmicroseconds(void) -{ - return microseconds(globalstart, rdtscll()); -} - -extern struct iodef iodefs[]; -extern int niodefs; - -static int i915_init_done = 0; - -/* fill the palette. This runs when the P opcode is hit. */ -/* and, yes, it's needed for even 32 bits per pixel */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for(i = 0; i < 256; i++, color += 0x010101){ - io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2)); - } -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = NULL; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for(i = index, id = &iodefs[i]; id->op; i++, id++){ - switch (id->op) { - case M: - if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr){ - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++){ - u = READ32(id->addr); - } - if (verbose & vspin) printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL){ - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: break; - case 7: break; - default: udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", 100000); - } - } - break; - case V: - if (id->count < 8){ - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 pphysbase, u16 piobase, u8 *pmmio, u32 pgfx) -{ - static struct edid edid; - const struct edid_mode *mode; - int edid_ok; - - int index; - u32 auxin[16], auxout[16]; - mmio = (void *)pmmio; - addrport = piobase; - dataport = addrport + 4; - physbase = pphysbase; - graphics = pgfx; - printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p" - "addrport %04x physbase %08x\n", - (void *)graphics, mmio, addrport, physbase); - globalstart = rdtscll(); - - - edid_ok = decode_edid((unsigned char *)&link_edid_data, - sizeof(link_edid_data), &edid); - mode = &edid.mode; - printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - edid.framebuffer_bits_per_pixel = 32; - - htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (mode->ha + mode->hso - 1) | - ((mode->ha + mode->hso + mode->hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); - - vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); - - vsync = (mode->va + mode->vso - 1) | - ((mode->va + mode->vso + mode->vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); - - printk(BIOS_SPEW, "Table has %d elements\n", niodefs); - - index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); - auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); - index = run(index); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); - index = run(index); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; - auxout[1] = 0x01000000; - /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; - auxout[1] = 0x0a840000; - /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/ - auxout[2] = 0x00000000; - auxout[3] = 0x01000000; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x21000000; - /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; - auxout[1] = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x22000000; - /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; - auxout[1] = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x00000000; - /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - - if (index != niodefs) - printk(BIOS_ERR, "Left over IO work in i915_lightup" - " -- this is likely a table error. " - "Only %d of %d were done.\n", index, niodefs); - printk(BIOS_SPEW, "DONE startup\n"); - verbose = 0; - /* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * There are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. We will be exploiting this - * trick in a later rev of this code. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n", - (void *)graphics, FRAME_BUFFER_BYTES); - memset((void *)graphics, 0, FRAME_BUFFER_BYTES); - printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); - set_vbe_mode_info_valid(&edid, (uintptr_t)graphics); - i915_init_done = 1; - return i915_init_done; -} diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c deleted file mode 100644 index 5ebb42d4e70..00000000000 --- a/src/mainboard/google/link/i915io.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "i915io.h" - -struct iodef iodefs[] = { - {V, 0}, - {W, 1, "", PCH_GMBUS0, 0x00000000, 0}, - {R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0}, - {W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0}, - {M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0}, - {R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10}, - {W, 1, "", FORCEWAKE_MT, 0x00010001, 0}, - {R, 1, "", FORCEWAKE_MT, 0x00010001, 0}, - {R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0}, - {R, 1, "", 0x13805c, 0x40000000, 0}, - {R, 1, "", 0xa180, 0x84100020, 0}, - {W, 1, "", FORCEWAKE_MT, 0x00010000, 0}, - {R, 1, "", 0x120000, 0x00000000, 0}, - {M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 300}, - {W, 1, "", CPU_VGACNTRL, 0x80000000, 0}, - {R, 1, "", CPU_VGACNTRL, 0x80000000, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0}, - {R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0}, - {R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0}, - {M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {I,}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0}, - {R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0}, - {M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0}, - {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0}, - {W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0}, - {R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200}, - {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0}, - {W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0}, - {R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200}, - {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", 0x9404, 0x00002000, 0}, - {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, - {W, 1, "", IVB_CHICKEN3, 0x00000024, 0}, - {W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0}, - {W, 1, "", 0xb01c, 0x3c4fff8c, 0}, - {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, - {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, - {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, - {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, - {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, - {R, 1, "", _DSPAADDR, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {R, 1, "", _DSPBCNTR, 0x00000000, 0}, - {W, 1, "", _DSPBCNTR, 0x00004000, 0}, - {R, 1, "", _DSPBADDR, 0x00000000, 0}, - {W, 1, "", _DSPBADDR, 0x00000000, 0}, - {R, 1, "", _DSPBSURF, 0x00000000, 0}, - {W, 1, "", _DSPBSURF, 0x00000000, 0}, - {R, 1, "", _DVSACNTR, 0x00000000, 0}, - {W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0}, - {R, 1, "", _DVSALINOFF, 0x00000000, 0}, - {W, 1, "", _DVSALINOFF, 0x00000000, 0}, - {R, 1, "", _DVSASURF, 0x00000000, 0}, - {W, 1, "", _DVSASURF, 0x00000000, 0}, - {W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0}, - {R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0}, - {W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0}, - {W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0}, - {W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0}, - {M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {I,}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_DP_D, 0x00000004, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, - {M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0}, - {W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0}, - {W, 1, "", _PCH_FPA1, 0x00020e08, 0}, - {W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0}, - {W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0}, - {W, 1, "", _HBLANK_A, 0x0a9f09ff, 0}, - {W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0}, - {W, 1, "", _VTOTAL_A, 0x06d406a3, 0}, - {W, 1, "", _VBLANK_A, 0x06d406a3, 0}, - {W, 1, "", _VSYNC_A, 0x06b006a6, 0}, - {W, 1, "", _PIPEASRC, 0x09ff06a3, 0}, - {W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0}, - {W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0}, - {W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0}, - {W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0}, - {M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, - {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00000040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, - {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, - {P, 1, "Set Palette"}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, - {R, 1, "", _DSPAADDR, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4392, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0}, - {R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0}, - {R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0}, - {R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0}, - {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0}, - {M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, - {R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, - {R, 1, "", _PIPEADSL, 0x00000633, 500}, - {R, 1, "", _PIPEADSL, 0x00000652, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 5085, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, - {I,}, -}; - -int niodefs = ARRAY_SIZE(iodefs); diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h deleted file mode 100644 index c7663d4db08..00000000000 --- a/src/mainboard/google/link/i915io.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* things that are, strangely, not defined anywhere? */ -#define PCH_PP_UNLOCK 0xabcd0000 -#define WMx_LP_SR_EN (1 << 31) - -/* Google Link-specific defines */ -/* how many 4096-byte pages do we need for the framebuffer? - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * HencetThere are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - */ -#define FRAME_BUFFER_PAGES ((2560*1700)/1024) -#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096) - -/* One-letter commands for code not meant to be ready for humans. - * The code was generated by a set of programs/scripts. - * M print out a kernel message - * R read a register. We do these mainly to ensure that if hardware wanted - * the register read, it was read; also, in debug, we can see what was expected - * and what was found. This has proven *very* useful to get this debugged. - * The udelay, if non-zero, will make sure there is a - * udelay() call with the value. - * The count is from the kernel and tells us how many times this read was done. - * Also useful for debugging and the state - * machine uses the info to drive a poll. - * W Write a register - * V set verbosity. It's a bit mask. - * 0 -> nothing - * 1 -> print kernel messages - * 2 -> print IO ops - * 4 -> print the number of times we spin on a register in a poll - * 8 -> restore whatever the previous verbosity level was - * (only one deep stack) - * - * Again, this is not really meant for human consumption. There is not a poll - * operator as such because, sometimes, there is a read/write/read where the - * second read is a poll, and this chipset is so touchy I'm reluctant to move - * things around and/or delete too many reads. - */ -#define M 1 -#define R 2 -#define W 4 -#define V 8 -#define I 16 -#define P 32 - -struct iodef { - unsigned char op; - unsigned int count; - const char *msg; - unsigned long addr; - unsigned long data; - unsigned long udelay; -}; - -/* i915.c */ -unsigned long io_i915_READ32(unsigned long addr); -void io_i915_WRITE32(unsigned long val, unsigned long addr); - -/* intel_dp.c */ -u32 pack_aux(u32 *src, int src_bytes); -void unpack_aux(u32 src, u32 *dst, int dst_bytes); -int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size); diff --git a/src/mainboard/google/link/intel_dp.c b/src/mainboard/google/link/intel_dp.c deleted file mode 100644 index f74743aab12..00000000000 --- a/src/mainboard/google/link/intel_dp.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Keith Packard - * - */ - -#include -#include -#include -#include "i915io.h" - -u32 -pack_aux(u32 *src32, int src_bytes) -{ - u8 *src = (u8 *)src32; - int i; - u32 v = 0; - - if (src_bytes > 4) - src_bytes = 4; - for (i = 0; i < src_bytes; i++) - v |= ((u32) src[i]) << ((3-i) * 8); - return v; -} - -void -unpack_aux(u32 src, u32 *dst32, int dst_bytes) -{ - u8 *dst = (u8 *)dst32; - - int i; - if (dst_bytes > 4) - dst_bytes = 4; - for (i = 0; i < dst_bytes; i++) - dst[i] = src >> ((3-i) * 8); -} - -int -intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size) -{ - int i; - int recv_bytes; - u32 status; - u32 aux_clock_divider; - int try, precharge = 5; - - /* The clock divider is based off the hrawclk, - * and would like to run at 2MHz. So, take the - * hrawclk value and divide by 2 and use that - * - * Note that PCH attached eDP panels should use a 125MHz input - * clock divider. - */ - /* 200 on link */ - aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ - - /* Try to wait for any previous AUX channel activity */ - for (try = 0; try < 3; try++) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(1000); - } - - if (try == 3) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n", - io_i915_READ32(ch_ctl)); - return -1; - } - - /* Must try at least 3 times according to DP spec */ - for (try = 0; try < 5; try++) { - /* Load the send data into the aux channel data registers */ - for (i = 0; i < send_bytes; i += 4) - io_i915_WRITE32(send[i], ch_data + i); - - /* Send the command and wait for it to complete */ - io_i915_WRITE32( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_TIME_OUT_400us | - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | - (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - for (;;) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(100); - } - - /* Clear done status and any errors */ - io_i915_WRITE32( - status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - - if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) - continue; - if (status & DP_AUX_CH_CTL_DONE) - break; - } - - if ((status & DP_AUX_CH_CTL_DONE) == 0) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status); - return -1; - } - - /* Check for timeout or receive error. - * Timeouts occur when the sink is not connected - */ - if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status); - return -1; - } - - /* Timeouts occur when the device isn't connected, so they're - * "normal" -- don't fill the kernel log with these */ - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status); - return -1; - } - - /* Unload any bytes sent back from the other side */ - recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); - if (recv_bytes > recv_size) - recv_bytes = recv_size; - - for (i = 0; i < recv_bytes; i += 4) - unpack_aux(io_i915_READ32(ch_data + i), - recv + i, recv_bytes - i); - - return recv_bytes; -} diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 410866d0feb..37d1a672cda 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -170,7 +170,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -179,7 +180,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -188,7 +190,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66a503d0b18..8da13080b3a 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include "ec/google/chromeec/ec.h" #include diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index d1ab9c4f112..a2ba7cc24a5 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS select COMMON_CBFS_SPI_WRAPPER select SOC_QUALCOMM_QCS405 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS config VBOOT diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index 2cb963123bb..ca191d147e0 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += bootblock.c verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += reset.c +verstage-y += verstage.c romstage-y += memlayout.ld romstage-y += chromeos.c diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 6718d521561..4ef8fec6c34 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -14,7 +14,6 @@ */ #include -#include void bootblock_mainboard_init(void) { diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 1d62adba5c7..d50758c9e3d 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c new file mode 100644 index 00000000000..a34e4fa361f --- /dev/null +++ b/src/mainboard/google/mistral/verstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +void verstage_mainboard_init(void) +{ + struct spi_slave spi; + + printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n"); + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + } +} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index ba851c76c3e..e3e09e6dbd3 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index b1cf19e2584..807cec3f3f4 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -259,7 +259,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index f2979989fad..1fbaac72348 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index c0769f1b00f..c8bb8136d46 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -257,7 +257,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index dbbd91f1ddc..bbb274fb90b 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index a296092a192..97d05762783 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -257,7 +257,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 4e07236b4c6..b613cc3a85f 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -36,7 +36,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {WRITE_PROTECT.id, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {LID.id, ACTIVE_HIGH, -1, "lid"}, {POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"}, {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 9c0a2f771ef..48753ed4b16 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -59,6 +59,7 @@ config VARIANT_DIR default "casta" if BOARD_GOOGLE_CASTA default "bloog" if BOARD_GOOGLE_BLOOG default "octopus" if BOARD_GOOGLE_OCTOPUS + default "garg" if BOARD_GOOGLE_GARG config DEVICETREE string @@ -79,6 +80,7 @@ config MAINBOARD_PART_NUMBER default "Casta" if BOARD_GOOGLE_CASTA default "Bloog" if BOARD_GOOGLE_BLOOG default "Octopus" if BOARD_GOOGLE_OCTOPUS + default "Garg" if BOARD_GOOGLE_GARG config MAINBOARD_FAMILY string @@ -96,6 +98,7 @@ config GBB_HWID default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS + default "GARG TEST 1337" if BOARD_GOOGLE_GARG config MAX_CPUS int diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index e5684e0268a..b192134fb46 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -52,3 +52,9 @@ config BOARD_GOOGLE_BLOOG select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_GARG + bool "-> Garg" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 5eb39901242..ca9f6fbeb26 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 9d8b94d0b99..ff0354dc10c 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -44,7 +44,7 @@ void mainboard_save_dimm_info(void) if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { /* Fall back on part numbers encoded in lp4cfg array. */ - if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { + if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { save_dimm_info_by_sku_config(); return; } diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index e134aa222d6..fc609cd125a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -165,7 +165,7 @@ chip soc/intel/apollolake end # - XHCI device pci 15.1 on end # - XDCI device pci 16.0 on end # - I2C 0 - device pci 16.1 on end # - I2C 1 + device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 device pci 16.3 off end # - I2C 3 device pci 17.0 on end # - I2C 4 diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index aec2ba2a4f5..fc7c87dcb20 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -210,7 +210,7 @@ const struct lpddr4_cfg *__weak variant_lpddr4_config(void) if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { /* Fall back non cbi memory config. */ - if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) + if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) return &non_cbi_lp4cfg; } diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 20b5dd3b71e..cf70bb31085 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -49,12 +49,32 @@ chip soc/intel/apollolake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, + }" device domain 0 on @@ -101,6 +121,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.has_power_resource" = "1" + register "generic.enable_delay_ms" = "10" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h index 16f931b6cdf..196d52e3e97 100644 --- a/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/bobba/include/variant/ec.h @@ -18,4 +18,7 @@ #include +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index dc9c9118af6..091b3027f44 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -1,4 +1,45 @@ chip soc/intel/apollolake + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x00000505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x00000c0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x0001000f" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x00000a0a" + # Override USB2 PER PORT register (PORT 4) register "usb2eye[4]" = "{ .Usb20OverrideEn = 1, diff --git a/src/mainboard/google/octopus/variants/garg/Makefile.inc b/src/mainboard/google/octopus/variants/garg/Makefile.inc new file mode 100644 index 00000000000..9fb63f5f433 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c new file mode 100644 index 00000000000..a4362409b52 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl new file mode 100644 index 00000000000..4f6497ab2d4 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h similarity index 63% rename from src/soc/intel/braswell/include/soc/pei_wrapper.h rename to src/mainboard/google/octopus/variants/garg/include/variant/ec.h index 3222328bef7..feb6c716555 100644 --- a/src/soc/intel/braswell/include/soc/pei_wrapper.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,14 +13,12 @@ * GNU General Public License for more details. */ -#ifndef _SOC_PEI_WRAPPER_H_ -#define _SOC_PEI_WRAPPER_H_ +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H -#include +#include -typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); - -void broadwell_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT #endif diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h new file mode 100644 index 00000000000..750b0d4cccf --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb new file mode 100644 index 00000000000..0230a29a894 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -0,0 +1,180 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0b" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c272828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10021" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 88, + .fall_time_ns = 16, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_145)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.wake" = "GPE0_DW2_04" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + device generic 0 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end + + # Disable compliance mode + register "DisableComplianceMode" = "1" +end diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 076476bbdd6..281bde06a48 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -19,7 +19,6 @@ #include #include #include -#include #define SKU_UNKNOWN 0xFFFFFFFF diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index f2c9b20a1cf..daf605d436e 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_PARROT config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 select BOARD_ROMSIZE_KB_8192 @@ -41,12 +41,8 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" endif # BOARD_GOOGLE_PARROT diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index f17b6a64e1c..095d5049edf 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -39,9 +39,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO70 active high */ {70, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid switch GPIO active high (open). */ {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 52e4af3ea77..8c3ad6352e3 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -57,7 +57,8 @@ static int parrot_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ } else { len += smbios_write_type41( current, handle, @@ -66,7 +67,8 @@ static int parrot_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ } return len; diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 00dd1f39872..8bd35bee954 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -30,9 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {EXYNOS5_GPX3, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: active low */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: active high (LID_GPIO) */ {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X34), "lid"}, diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 0441e529897..ecd2260511d 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -485,7 +485,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 419b10eb3d2..6bc8269aa7c 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 @@ -151,6 +152,7 @@ config VARIANT_SPECIFIC_OPTIONS_ATLAS select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 83b8aa05633..3879732135c 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -28,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex new file mode 100644 index 00000000000..ada67c96202 --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 00 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 47 41 4C 41 52 2D 4E +56 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex new file mode 100644 index 00000000000..a1dc212a9f4 --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 08 00 40 55 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex new file mode 100644 index 00000000000..e59d8286d51 --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 40 55 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 +4B 34 45 42 45 33 30 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc index 06776ffd4a2..397ef687e91 100644 --- a/src/mainboard/google/poppy/variants/atlas/Makefile.inc +++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc @@ -12,6 +12,8 @@ SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1001 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b1100 +SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b1101 +SPD_SOURCES += samsung_dimm_K4EBE304ED-EGCG # 0b1110 bootblock-y += gpio.c diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 53af87d49e3..1ea28a0e5f4 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -88,8 +88,8 @@ chip soc/intel/skylake #| ImonOffset | 0 | 0 | 0 | 0 | #| IccMax | set by SoC code per CPU SKU | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 14.75 | 4.42 | 4.7 | 4.7 | - #| DcLoadline | 14.2 | 4.2 | 4.41 | 4.41 | + #| AcLoadline | 16.20 | 5.24 | 4.62 | 4.62 | + #| DcLoadline | 14.2 | 4.94 | 4.25 | 4.25 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, @@ -101,7 +101,7 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 1475, + .ac_loadline = 1620, .dc_loadline = 1420, }" @@ -115,8 +115,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 442, - .dc_loadline = 420, + .ac_loadline = 524, + .dc_loadline = 494, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -129,8 +129,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 470, - .dc_loadline = 441, + .ac_loadline = 462, + .dc_loadline = 425, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -143,8 +143,8 @@ chip soc/intel/skylake .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 470, - .dc_loadline = 441, + .ac_loadline = 462, + .dc_loadline = 425, }" # PCIe Root port 1 with SRCCLKREQ1# (WLAN) @@ -265,7 +265,30 @@ chip soc/intel/skylake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + end + end + end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 29c1d3f38b5..570fbbbdfa9 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -49,9 +49,6 @@ Name (CHPS, Package () { }) Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 200, 0, 0, 0, 0 }, diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c index 0b34e72830c..022b7333982 100644 --- a/src/mainboard/google/poppy/variants/atlas/memory.c +++ b/src/mainboard/google/poppy/variants/atlas/memory.c @@ -13,8 +13,11 @@ * GNU General Public License for more details. */ +#include #include +#define SAMSUNG_C_DIE_2G 10 +#define SAMSUNG_C_DIE_4G 11 /* DQ byte map */ static const u8 dq_map[][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -34,9 +37,12 @@ static const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */ static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; +static const u16 rcomp_target_samsung_c_die[] = { 100, 40, 35, 18, 40 }; void variant_memory_params(struct memory_params *p) { + int spd_index; + p->type = MEMORY_LPDDR3; p->dq_map = dq_map; p->dq_map_size = sizeof(dq_map); @@ -44,6 +50,11 @@ void variant_memory_params(struct memory_params *p) p->dqs_map_size = sizeof(dqs_map); p->rcomp_resistor = rcomp_resistor; p->rcomp_resistor_size = sizeof(rcomp_resistor); - p->rcomp_target = rcomp_target; + spd_index = variant_memory_sku(); + assert(spd_index >= 0); + if (spd_index == SAMSUNG_C_DIE_2G || spd_index == SAMSUNG_C_DIE_4G) + p->rcomp_target = rcomp_target_samsung_c_die; + else + p->rcomp_target = rcomp_target; p->rcomp_target_size = sizeof(rcomp_target); } diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index dc803578353..0033c60ee71 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -43,3 +43,6 @@ oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw $(call add_vbt_to_cbfs, vbt-bard.bin, bard-data.vbt) +$(call add_vbt_to_cbfs, vbt-akali.bin, akali-data.vbt) +$(call add_vbt_to_cbfs, vbt-pantheon.bin, pantheon-data.vbt) +$(call add_vbt_to_cbfs, vbt-vayne.bin, vayne-data.vbt) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 00000000000..84063621d0a Binary files /dev/null and b/src/mainboard/google/poppy/variants/nami/data.vbt differ diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 836c97ea40f..23870175b7f 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -237,6 +238,7 @@ void variant_devtree_update(void) struct device *root = SA_DEV_ROOT; config_t *cfg = root->chip_info; uint8_t pl2_id = PL2_ID_DEFAULT; + struct device *spi_fpmcu = PCH_DEV_GSPI1; switch (sku_id) { case SKU_0_SONA: @@ -250,6 +252,7 @@ void variant_devtree_update(void) case SKU_6_SYNDRA: case SKU_7_SYNDRA: pl2_id = PL2_ID_SONA_SYNDRA; + /* fallthrough */ case SKU_0_VAYNE: case SKU_1_VAYNE: case SKU_2_VAYNE: @@ -259,6 +262,7 @@ void variant_devtree_update(void) case SKU_3_PANTHEON: case SKU_4_PANTHEON: cfg->usb2_ports[5].enable = 0; + spi_fpmcu->enabled = 0; break; case SKU_0_BARD: case SKU_1_BARD: diff --git a/src/mainboard/google/poppy/variants/nami/pantheon-data.vbt b/src/mainboard/google/poppy/variants/nami/pantheon-data.vbt new file mode 100644 index 00000000000..7e4fb0afe5a Binary files /dev/null and b/src/mainboard/google/poppy/variants/nami/pantheon-data.vbt differ diff --git a/src/mainboard/google/poppy/variants/nami/smihandler.c b/src/mainboard/google/poppy/variants/nami/smihandler.c index 6816508f24e..61162b40b1a 100644 --- a/src/mainboard/google/poppy/variants/nami/smihandler.c +++ b/src/mainboard/google/poppy/variants/nami/smihandler.c @@ -15,8 +15,8 @@ #include #include -#include #include + #include "gpio.h" #define TOUCH_DISABLE GPP_C3 diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 00000000000..7e4fb0afe5a Binary files /dev/null and b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt differ diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 44dd07bcded..0d835cbe88c 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -3,6 +3,7 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-093 # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 +SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NVD # 0b0101 bootblock-y += gpio.c diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 6d0c0dfce06..56d44bcea0a 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -90,8 +90,8 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME string default "" -config VGA_BIOS_FILE +config MAINBOARD_SMBIOS_MANUFACTURER string - default "pci8086,0f31.rom" + default "GOOGLE" endif # BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index d47a323a4fc..7880154586a 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 15faac9bf81..d3f6164cd38 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -142,7 +142,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ #endif #ifdef BOARD_TOUCHSCREEN_NAME len += smbios_write_type41( @@ -152,7 +153,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ #endif return len; } diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index 1e50e53c770..c010af1e73c 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -32,16 +32,25 @@ chip soc/intel/baytrail register "sdcard_cap_high" = "0x0" # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" register "scc_acpi_mode" = "1" # Enable PIPEA as DP_C register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "5" # 400ms - register "gpu_pipea_power_on_delay" = "2000" # 200ms - register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_light_off_delay" = "2000" # 200ms + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + device cpu_cluster 0 on device lapic 0 on end end @@ -59,11 +68,11 @@ chip soc/intel/baytrail device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 + device pci 18.5 on end # I2C5 device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 off end # TXE - device pci 1b.0 off end # HDA + device pci 1b.0 on end # HDA device pci 1c.0 on end # PCIE_PORT1 device pci 1c.1 on end # PCIE_PORT2 device pci 1c.2 off end # PCIE_PORT3 diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 7b7f2b8ce0a..4dbbe6d5811 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9d658fa3a26..e6d1f1f60f3 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -16,7 +16,6 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE @@ -37,7 +36,7 @@ config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY - select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC config DIMM_MAX int @@ -59,6 +58,10 @@ config TPM_TIS_ACPI_INTERRUPT int default 82 # GPE0_DW2_18 (GPP_D18) +config POWER_OFF_ON_CR50_UPDATE + bool + default n + config GBB_HWID string depends on CHROMEOS @@ -100,11 +103,6 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config TOUCHSCREEN_HID - string "Specify the touchscreen HID enabled for the OS" - default "WCOM48E2" if BOARD_GOOGLE_ARCADA - default "ELAN900C" if BOARD_GOOGLE_SARIEN - config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 6fd23cefcda..7c37bc9901d 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -29,5 +29,10 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 15670d0d8ed..fafc4692702 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -36,8 +36,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), - "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0ccad2e0..58e0704deb3 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -40,6 +40,8 @@ DefinitionBlock( #include #include } + /* Per board variant mainboard hooks. */ + #include } #if CONFIG(CHROMEOS) diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/google/sarien/ec.c similarity index 62% rename from src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl rename to src/mainboard/google/sarien/ec.c index d8d33208f89..fd8e84fbc81 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl +++ b/src/mainboard/google/sarien/ec.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,17 +13,11 @@ * GNU General Public License for more details. */ -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ +#include +#include +#include -Method(_WAK,1) +void mainboard_post(uint8_t value) { - Return(Package(){0,0}) + wilco_ec_save_post_code(value); } diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index d8d1c9dbe37..1d220461cf5 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -21,6 +22,26 @@ #include #if CONFIG(GENERATE_SMBIOS_TABLES) +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index e83cd4aed45..20eee7f34b8 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -18,6 +18,18 @@ #include static const struct cnl_mb_cfg memcfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -25,16 +37,16 @@ static const struct cnl_mb_cfg memcfg = { * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Disable Early Command Training */ .ect = 0, @@ -45,12 +57,7 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xa0, - .spd_smbus_address[2] = 0xa4 - }; - wilco_ec_romstage_init(); - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9ecbf001520..767df1f7959 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -26,8 +26,10 @@ chip soc/intel/cannonlake register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" register "speed_shift_enable" = "1" + register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "dmipwroptimize" = "1" @@ -36,10 +38,10 @@ chip soc/intel/cannonlake register "tdp_pl2_override" = "51" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "0" - register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "0" + register "SlowSlewRateForFivr" = "2" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C @@ -160,7 +162,7 @@ chip soc/intel/cannonlake #| I2C4 | H1 TPM | #+-------------------+---------------------------+ - register "tcc_offset" = "10" + register "tcc_offset" = "1" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -195,9 +197,20 @@ chip soc/intel/cannonlake # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end @@ -301,8 +314,10 @@ chip soc/intel/cannonlake register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" @@ -345,11 +360,15 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index b66e1dda435..ff0240c991a 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -31,7 +31,7 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ -/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), @@ -123,7 +123,7 @@ static const struct pad_config gpio_table[] = { /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), /* ISH_CPU_UART0_RX */ -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ @@ -211,8 +211,6 @@ static const struct pad_config gpio_table[] = { /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -240,6 +238,9 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ @@ -251,6 +252,7 @@ static const struct pad_config early_gpio_table[] = { /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 6fa06c7d730..4d380713e22 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -13,14 +13,14 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 96 -#define DPTF_CPU_CRITICAL 103 +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 56 -#define DPTF_TSR0_CRITICAL 108 +#define DPTF_TSR0_PASSIVE 60 +#define DPTF_TSR0_CRITICAL 105 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 @@ -31,24 +31,24 @@ /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 50 -#define DPTF_TSR2_CRITICAL 95 +#define DPTF_TSR2_PASSIVE 37 +#define DPTF_TSR2_CRITICAL 80 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 500, 30, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 50, 2, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, }) Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 00000000000..4b05ba8e908 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 +#define SSD_EN GPP_H13 +#define SSD_RST GPP_H12 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN adn RST pin to avoid leakage */ + If (Arg0 == 5) { + \_SB.PCI0.CTXS (SSD_RST) + Sleep(1) + \_SB.PCI0.CTXS (SSD_EN) + } +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc index fa5b2ea36a5..2bf028eb1f2 100644 --- a/src/mainboard/google/sarien/variants/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc @@ -14,6 +14,6 @@ ## bootblock-y += gpio.c -ramstage-y += gpio.c ramstage.c +ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 625655b38c2..c96423c93dd 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -43,6 +43,7 @@ chip soc/intel/cannonlake register "SlowSlewRateForFivr" = "2" register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" + register "psys_pmax" = "136" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" @@ -52,6 +53,9 @@ chip soc/intel/cannonlake # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + register "LanWakeFromDeepSx" = "0" + register "WolEnableOverride" = "0" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -197,9 +201,20 @@ chip soc/intel/cannonlake # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end @@ -305,30 +320,21 @@ chip soc/intel/cannonlake end device pci 14.5 off end # SDCard device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ACPI0C50"" - register "generic.desc" = ""Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x0" - device i2c 10 on end - end chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" device i2c 10 on end end chip drivers/i2c/generic @@ -336,9 +342,13 @@ chip soc/intel/cannonlake register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "enable_delay_ms" = "5" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" device i2c 34 on end end end # I2C #0 @@ -378,11 +388,15 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 19fd45cdeaa..78db12e8a1e 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -31,9 +31,9 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* BM_BUSY# */ PAD_NC(GPP_A12, NONE), -/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ + /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ + /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -197,8 +197,6 @@ static const struct pad_config gpio_table[] = { /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* /D3 cold RST */ -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -225,8 +223,13 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -237,6 +240,7 @@ static const struct pad_config early_gpio_table[] = { /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 00000000000..4b05ba8e908 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 +#define SSD_EN GPP_H13 +#define SSD_RST GPP_H12 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN adn RST pin to avoid leakage */ + If (Arg0 == 5) { + \_SB.PCI0.CTXS (SSD_RST) + Sleep(1) + \_SB.PCI0.CTXS (SSD_EN) + } +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/sarien/variants/sarien/ramstage.c b/src/mainboard/google/sarien/variants/sarien/ramstage.c deleted file mode 100644 index d20260cc91f..00000000000 --- a/src/mainboard/google/sarien/variants/sarien/ramstage.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * This board may have different touchscreen devices that are at the - * same I2C slave address but need different drivers or ACPI configuration. - * - * The default touchscreen to be enabled is specified in Kconfig by the - * ACPI HID of the device. If a board is connected to a different - * touchscreen device it can be enabled in Kconfig or by setting the - * VPD key 'touchscreen_hid'. - */ - -#define TOUCHSCREEN_I2C_ADDR 0x10 -#define TOUCHSCREEN_VPD_KEY "touchscreen_hid" - -static void disable_unused_touchscreen(void *unused) -{ - struct device *i2c0 = PCH_DEV_I2C0; - struct bus *i2c_slaves = i2c0->link_list; - struct device *slave = i2c_slaves->children; - char touchscreen_hid[9] = CONFIG_TOUCHSCREEN_HID; - struct drivers_i2c_hid_config *info; - - /* Look for VPD key that indicates which touchscreen is present */ - if (CONFIG(VPD) && - !vpd_gets(TOUCHSCREEN_VPD_KEY, touchscreen_hid, - ARRAY_SIZE(touchscreen_hid), VPD_ANY)) - printk(BIOS_INFO, "%s: VPD key '%s' not found, default to %s\n", - __func__, TOUCHSCREEN_VPD_KEY, touchscreen_hid); - - /* Go through all I2C slave devices on this bus */ - while (slave) { - /* Find all the I2C slaves with the matching address */ - if (slave->path.type == DEVICE_PATH_I2C && - slave->path.i2c.device == TOUCHSCREEN_I2C_ADDR) { - info = slave->chip_info; - /* Disable all devices except the matching HID */ - if (strncmp(info->generic.hid, touchscreen_hid, - ARRAY_SIZE(touchscreen_hid))) { - printk(BIOS_INFO, "%s: Disable %s\n", __func__, - info->generic.hid); - slave->enabled = 0; - } else { - printk(BIOS_INFO, "%s: Enable %s\n", __func__, - info->generic.hid); - } - } - slave = slave->sibling; - } -} -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - disable_unused_touchscreen, NULL); diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index ecc8aff5ba6..242876da86b 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -71,5 +71,8 @@ config VGA_BIOS_FILE config INTEL_GMA_VBT_FILE default "src/mainboard/$(MAINBOARDDIR)/data.vbt" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 15779ee9657..f52bace2717 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {58, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 4bbc1d6907a..b98fc8a3809 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -54,7 +54,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_LIGHTSENSOR_I2C_BUS, /* segment */ BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -63,7 +64,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -72,7 +74,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 567a3ae253d..3d36cd9dc0c 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {WRITE_PROTECT_L, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {POWER_BUTTON, ACTIVE_LOW, -1, "power"}, {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index d9dacb7d08b..9add211ccd5 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -36,10 +36,6 @@ struct max77620_init_reg { u8 delay; }; -static struct max77620_init_reg init_list[] = { - /* TODO */ -}; - static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val, int delay) { @@ -66,20 +62,8 @@ static inline void pmic_write_reg_77621(unsigned bus, uint8_t reg, uint8_t val, pmic_write_reg(bus, MAX77621_CPU_I2C_ADDR, reg, val, delay); } -static void pmic_slam_defaults(unsigned bus) -{ - int i; - for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct max77620_init_reg *reg = &init_list[i]; - pmic_write_reg_77620(bus, reg->reg, reg->val, reg->delay); - } -} - void pmic_init(unsigned bus) { - /* Restore PMIC POR defaults, in case kernel changed 'em */ - pmic_slam_defaults(bus); - /* MAX77620: Set SD0 to 1.0V - VDD_CORE */ pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1); pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1); diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index ccc0b53e026..9587c3c384e 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -39,7 +39,7 @@ static int read_gpio(gpio_t gpio_num) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {REC_SW, ACTIVE_LOW, read_gpio(REC_SW), "recovery"}, + {DEV_SW, ACTIVE_LOW, read_gpio(REC_SW), "presence"}, {WP_SW, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index fdff5ab0f45..783e6ad7a13 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -119,7 +119,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index c9b67ccee16..dfe687b0ff6 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_STOUT config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 @@ -43,12 +43,8 @@ config VGA_BIOS_ID string default "8086,0156" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" endif # BOARD_GOOGLE_STOUT diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 015e0aad322..60c7a09249b 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -35,9 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO7 */ {7, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: Virtual switch */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid Switch: Virtual switch */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 5f51a6b8bc1..05de8cb63d8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -22,14 +22,14 @@ #include #include #include -#include "onboard.h" -#include "ec.h" #include -#include #include #include #include +#include "ec.h" +#include "onboard.h" + void mainboard_suspend_resume(void) { /* Stout EC needs to be put back in ACPI mode */ diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 5b0b29d0f76..16e75809d39 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c index 3eaad3451e5..7bf8b908a39 100644 --- a/src/mainboard/google/urara/mainboard.c +++ b/src/mainboard/google/urara/mainboard.c @@ -43,7 +43,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 357a7fc468f..d27b4dd3d5e 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -43,7 +43,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_WP.raw, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {GPIO_LID.raw, ACTIVE_HIGH, -1, "lid"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, {GPIO_ECINRW.raw, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index d8ac310643c..5243dc9290b 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -123,7 +123,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 46a6738b937..c549e70b51e 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -34,7 +34,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_WP.raw, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index bb239732b5b..9024b6c66a9 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -101,7 +101,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index e86d86305f4..65866f3ceca 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -41,7 +41,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Note for early development, we want to support both servo * and pushkey recovery buttons in firmware boot stages. */ {GPIO_RECOVERY_PUSHKEY.raw, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 074e6a4e995..6259955669c 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -107,7 +107,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index f9da619ad28..5e33aac2c2b 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -49,14 +49,6 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x17df - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index af3e31b8bc4..ab298369e17 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -49,14 +49,6 @@ config VGA_BIOS_ID string default "8086,0116" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x162a - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index ca737ea65b0..ca97cd69f68 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -52,14 +52,6 @@ config VGA_BIOS_ID string default "8086,0116" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x161c - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index d8bf5ec2b5c..5b30208b64a 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -50,14 +50,6 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x179b - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index c60283d009d..41e2ed3c6b5 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -41,14 +41,6 @@ config MAINBOARD_PART_NUMBER string default "EliteBook 8770w" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x176c - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index c4b9d6db6b4..cbfb0ed387e 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -35,14 +35,6 @@ config VGA_BIOS_ID string default "8086,0102" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x1495 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index f65aeed93d6..d9bb68e7e11 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -35,14 +35,6 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x18df - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config MAX_CPUS int default 8 diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index a08a9e5b893..ce7364ce5e8 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -37,14 +37,6 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x18f8 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x103c - config DRAM_RESET_GATE_GPIO # FIXME: check this int default 60 diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index a35619516d8..c98556c30f6 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -16,8 +16,7 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include -#include +#include #include #include #include @@ -218,8 +217,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 5ef8363e35f..06e86c1d6cb 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -15,5 +15,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index f1fd3ed84c8..6561927d3b8 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -33,7 +32,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {0, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index 0fd0639b562..da6f8e81990 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 296a3a51eac..44254bcbcb5 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 5ceff51f446..dd209dce557 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -12,10 +12,11 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include -#include #include #include + #include "spd.h" void mainboard_fill_dq_map_ch0(void *dq_map_ptr) diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 84f5f27f6af..a581217e17e 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index a13000cc13d..b093a20d2c8 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -20,6 +20,23 @@ #include static const struct cnl_mb_cfg baseboard_memcfg_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA0} + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA2} + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA4} + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA6} + }, /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -27,16 +44,16 @@ static const struct cnl_mb_cfg baseboard_memcfg_cfg = { * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, - .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Baseboard is an interleaved design */ .dq_pins_interleaved = 1, diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 1ab2d78b5a4..09ef148e362 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -20,13 +20,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xA0, - .spd_smbus_address[1] = 0xA2, - .spd_smbus_address[2] = 0xA4, - .spd_smbus_address[3] = 0xA6, - }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memcfg_config(), &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); } diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc index f3d7e76263f..f87689b8a1d 100644 --- a/src/mainboard/intel/d510mo/Makefile.inc +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -1,2 +1,4 @@ +bootblock-y += early_init.c +romstage-y += early_init.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/early_init.c similarity index 91% rename from src/mainboard/intel/d510mo/romstage.c rename to src/mainboard/intel/d510mo/early_init.c index c91d40e8900..2719e87fe63 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,13 +24,12 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -void mb_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517fb90e..716654c6eb6 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/i945 device pci 1c.1 off end # PCIe port 2 device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index dd7f1ca497b..b1c7bab07d8 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -41,14 +41,6 @@ config VGA_BIOS_ID string default "8086,0106" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x2044 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config MAX_CPUS int default 2 diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 510073540f2..705ace9bc60 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -17,12 +17,12 @@ */ #include -#include -#include +#include #include #include #include #include +#include #include "superio.h" #include "thermal.h" @@ -52,8 +52,7 @@ void mainboard_rcba_config(void) RCBA32(BUC) &= ~PCH_DISABLE_GBE; /* Datasheet says clearing the bit requires a reset after */ printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); - outb(0xe, 0xcf9); - halt(); + full_reset(); } #endif diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 24ec912a4c3..235ad228f80 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -23,6 +23,7 @@ #else #include #endif +#include #if !CONFIG(USE_NATIVE_RAMINIT) void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad9541c9..be28763a004 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -77,8 +77,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x8086 0x5756 end diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index eeb441ce68c..61dd1b0f3d9 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -2,7 +2,7 @@ if BOARD_INTEL_EMERALDLAKE2 config BOARD_SPECIFIC_OPTIONS def_bool y - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_SIO1007 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 78610d398d4..699141fc0ff 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -33,7 +32,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {48, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, !get_recovery_mode_switch(), "recovery"}, + {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 4b1f09f2e8b..8b6706c15ce 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 07d92e96fe6..4edd4a0ab48 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 7cc4e535b81..728a532054f 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -3,6 +3,7 @@ if BOARD_INTEL_ICELAKE_RVPU || BOARD_INTEL_ICELAKE_RVPY config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select EC_ACPI select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 5965d95c320..ce8e5486d8a 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index dd33021ae5f..b9ce3941f49 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -14,12 +14,12 @@ */ #include -#include #include #include -#include "spd/spd.h" #include +#include "spd/spd.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { } diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index 6b733642cdc..8d7eaf69cee 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -12,12 +12,13 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include #include -#include #include #include #include + #include "../board_id.h" #include "spd.h" diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 51680742adc..ff93d27f229 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -31,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 12d9d10b361..f22dcaa3b7b 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -12,12 +12,11 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include -#include #include #include -#include -#include + #include "../board_id.h" #include "spd.h" diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index dc4b83c0bb5..3330a0aab81 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -18,8 +18,6 @@ subdirs-y += spd bootblock-y += bootblock_mainboard.c -romstage-y += pei_data.c - bootblock-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -28,7 +26,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index f7a9d52ba64..64224889a5b 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c deleted file mode 100644 index bfc40c27485..00000000000 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "boardid.h" -#include "spd/spd.h" - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); -} diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 1c6f5a2cd34..f900ca319bc 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,45 +15,19 @@ * GNU General Public License for more details. */ -#include #include -#include -#include #include #include "gpio.h" #include "spd/spd.h" -void mainboard_romstage_entry(struct romstage_params *params) -{ - params->pei_data->mem_cfg_id = get_spd_index(); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); - /* Initialize memory */ - romstage_common(params); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + spd_memory_init_params(memory_params); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); + mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c index 8656d4bc170..bebb544a4d5 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ b/src/mainboard/intel/kunimitsu/spd/spd.c @@ -16,8 +16,9 @@ #include #include -#include +#include #include +#include #include #include "spd.h" @@ -73,20 +74,19 @@ static void mainboard_print_spd_info(uint8_t spd[]) } } -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) +/* Fill SPD pointers for on-board memory */ +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params) { uintptr_t spd_data; spd_data = mainboard_get_spd_data(); - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) + if (*(uint8_t *)spd_data == 0) die("Invalid SPD data."); - mainboard_print_spd_info(pei_data->spd_data[0][0]); + memory_params->MemorySpdPtr00 = spd_data; + if (mainboard_has_dual_channel_mem()) + memory_params->MemorySpdPtr10 = spd_data; + + mainboard_print_spd_info((uint8_t *)spd_data); } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index f53c9ec9fac..22d371f4bc1 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -16,6 +16,7 @@ #ifndef MAINBOARD_SPD_H +#include #include #include "../gpio.h" @@ -53,6 +54,7 @@ static inline int get_spd_index(void) { }; return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index fc0581cb24d..b173628e291 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include "boardid.h" #include "spd.h" diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc index 63889af078c..683462b9de0 100644 --- a/src/mainboard/intel/saddlebrook/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/Makefile.inc @@ -17,6 +17,5 @@ subdirs-y += spd bootblock-y += bootblock.c -romstage-y += pei_data.c ramstage-y += ramstage.c diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index d19629cf9ed..45f39d46e27 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -19,29 +19,11 @@ #include #include #include -#include -#include #include #include #include "spd/spd.h" #include -#include -#include -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) - -void car_mainboard_pre_console_init(void) -{ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_romstage_entry(struct romstage_params *params) -{ - post_code(0x31); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - romstage_common(params); -} void mainboard_memory_init_params( struct romstage_params *params, @@ -67,18 +49,10 @@ void mainboard_memory_init_params( * should be set in the FSP flash image and should not need to be * changed. */ - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); + mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); /* update spd length*/ memory_params->MemorySpdDataLen = blk.len; diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 2c26d787d7f..5055d9a3af7 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -15,8 +15,6 @@ #include #include -#include -#include #include "spd.h" void mainboard_fill_dq_map_data(void *dq_map_ptr) diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 4aa7640974a..da04d78a054 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -58,4 +58,9 @@ config GBB_HWID string depends on CHROMEOS default "STRAGO TEST A-A 9657" + +config CBFS_SIZE + hex + default 0x200000 + endif # BOARD_INTEL_STRAGO diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index 68ac133eec4..1d5437bbf26 100644 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -74,7 +74,7 @@ Scope (\_SB.PCI0.I2C1) Name (_UID, 5) Name (ISTP, 0) /* TouchScreen */ - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name (BUF0, ResourceTemplate () { @@ -120,7 +120,7 @@ Scope (\_SB.PCI0.I2C5) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 03eff1be4e4..df36b38a318 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -29,7 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index c8be3cea17b..5052ba265c4 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ - #include DefinitionBlock( "dsdt.aml", @@ -39,6 +38,7 @@ DefinitionBlock( { #include #include + #include } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0f3067ea819..1dc7ba32fc1 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -14,10 +14,7 @@ * GNU General Public License for more details. */ -#include -#include #include -#include #include "onboard.h" #include diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index 16137462c92..c4afb98cc5b 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c + +verstage-y += chromeos.c romstage-y += chromeos.c ramstage-y += chromeos.c diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 0f5cfbba35e..802221446de 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -29,7 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, // force open {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.c similarity index 97% rename from src/mainboard/intel/wtm2/gpio.h rename to src/mainboard/intel/wtm2/gpio.c index 9e6f2e64455..c81ad100817 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef INTEL_WTM2_GPIO_H -#define INTEL_WTM2_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 3c9bb363638..f4e336694db 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -21,21 +21,13 @@ #include #include #include -#include "gpio.h" -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - struct pei_data pei_data; - - post_code(0x32); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); +} - romstage_common(rp); +void mainboard_post_raminit(struct romstage_params *rp) +{ } diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index 30e6fdcb3c0..3cf38c035a9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 2edb7daf0ed..1b5d45efb33 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 05f9d1fd2a5..85a82c5acbd 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,8 +16,7 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include -#include -#include +#include #include #include #include @@ -266,8 +265,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index b85d9381caa..c215bdf65bb 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -2,7 +2,7 @@ if BOARD_KONTRON_KTQM77 config BOARD_SPECIFIC_OPTIONS def_bool y - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_WINBOND_W83627DHG select EC_KONTRON_IT8516E @@ -31,14 +31,6 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x0000 # TODO - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0000 # TODO - config MAINBOARD_VENDOR string default "Kontron" diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a57b4625290..ea1ead13e0b 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -13,4 +13,8 @@ config MAINBOARD_VENDOR string default "LENOVO" +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + endif # VENDOR_LENOVO diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index a807316bbf6..4495d79bb26 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -34,14 +34,6 @@ config VGA_BIOS_ID string default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21dd - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index b86186404c7..31f41e75611 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -35,7 +35,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h index a2007ffedaf..72953fd2c2e 100644 --- a/src/mainboard/lenovo/l520/thermal.h +++ b/src/mainboard/lenovo/l520/thermal.h @@ -2,7 +2,10 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef L520_THERMAL_H -#define L520_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* L520_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 714f13f3420..c7faebb4291 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_S230U config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 @@ -52,12 +52,4 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x2205 - endif # BOARD_LENOVO_S230U diff --git a/src/mainboard/lenovo/s230u/acpi/gpe.asl b/src/mainboard/lenovo/s230u/acpi/gpe.asl index a69f5629b12..e6f4153aca8 100644 --- a/src/mainboard/lenovo/s230u/acpi/gpe.asl +++ b/src/mainboard/lenovo/s230u/acpi/gpe.asl @@ -16,15 +16,6 @@ Scope (_GPE) { - Field(GPIO, ByteAcc, NoLock, Preserve) - { - Offset(0x2c), // GPIO Invert - , 2, - GV02, 1, - , 1, - GV04, 1, - } - Name (PDET, Zero) Method (PNOT, 2, Serialized) { ShiftLeft (Arg0, Arg1, Local0) @@ -39,10 +30,20 @@ Scope (_GPE) } } + Method (TINV, 2, Serialized) { + ShiftLeft (One, Arg1, Local0) + If (LEqual (Arg0, Zero)) { + Not (Local0, Local0) + And (GIV0, Local0, GIV0) + } Else { + Or (GIV0, Local0, GIV0) + } + } + /* Palm detect sensor 1 */ Method (_L12, 0, NotSerialized) { // Invert trigger - Store(GP02, GV02) + TINV (GP02, 2) PNOT (GP02, 0) } @@ -50,7 +51,7 @@ Scope (_GPE) /* Palm detect sensor 2 */ Method (_L14, 0, NotSerialized) { // Invert trigger - Store(GP04, GV04) + TINV (GP04, 4) PNOT (GP04, 1) } diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index 21fce85f5a1..8d6d93f1c36 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -14,6 +14,13 @@ */ #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -28,6 +35,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* The LID is open by default */ gnvs->lids = 1; - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/s230u/thermal.h b/src/mainboard/lenovo/s230u/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/s230u/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9f9405162cf..2bd67c28bc0 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -1,5 +1,5 @@ if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 \ - || BOARD_LENOVO_W500 + || BOARD_LENOVO_W500 || BOARD_LENOVO_R500 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,7 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL select H8_DOCK_EARLY_INIT - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 + select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 select DRIVERS_GENERIC_IOAPIC select HAVE_MP_TABLE select HAVE_ACPI_TABLES @@ -24,19 +25,31 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_NSC_PC87384 select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string default lenovo/t400 +config VARIANT_DIR + string + default "t400" if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 \ + || BOARD_LENOVO_R400 || BOARD_LENOVO_W500 + default "r500" if BOARD_LENOVO_R500 + config MAINBOARD_PART_NUMBER string default "ThinkPad T400" if BOARD_LENOVO_T400 default "ThinkPad T500" if BOARD_LENOVO_T500 default "ThinkPad R400" if BOARD_LENOVO_R400 + default "ThinkPad R500" if BOARD_LENOVO_R500 default "ThinkPad W500" if BOARD_LENOVO_W500 +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config USBDEBUG_HCD_INDEX int default 2 @@ -53,4 +66,7 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" + endif # BOARD_LENOVO_T400 diff --git a/src/mainboard/lenovo/t400/Kconfig.name b/src/mainboard/lenovo/t400/Kconfig.name index d459ce9236f..a259ddece46 100644 --- a/src/mainboard/lenovo/t400/Kconfig.name +++ b/src/mainboard/lenovo/t400/Kconfig.name @@ -7,5 +7,8 @@ config BOARD_LENOVO_T500 config BOARD_LENOVO_R400 bool "ThinkPad R400" +config BOARD_LENOVO_R500 + bool "ThinkPad R500" + config BOARD_LENOVO_W500 bool "ThinkPad W500" diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index 7721e0345fd..d0ee1537f43 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -13,9 +13,10 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c romstage-y += dock.c +subdirs-y += variants/$(VARIANT_DIR)/ + ramstage-y += dock.c ramstage-y += cstates.c ramstage-y += blc.c diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 818ea93724b..038774fdfd3 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -63,9 +63,7 @@ Method (ATPX, 2, Serialized) { }) CreateWordField (ATPR, 0x00, SIZE) CreateWordField (ATPR, 0x02, VERS) - CreateDWordField (ATPR, 0x02, MASK) CreateDWordField (ATPR, 0x04, FUNC) - CreateDWordField (ATPR, 0x06, FLAG) /* Version request */ if (LEqual(Arg0, 0x0)) diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 301ca50735d..8fb9056c518 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -21,6 +21,13 @@ #include #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -32,9 +39,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 8e90431d5fe..b4c2ea89b1e 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -109,6 +109,7 @@ chip northbridge/intel/gm45 end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -210,46 +211,12 @@ chip northbridge/intel/gm45 io 0x60 = 0x1620 end end - - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "22" - register "panel_integrated_lvl" = "0" - - register "has_backlight_gpio" = "1" - register "backlight_gpio" = "19" - register "backlight_integrated_lvl" = "0" - - register "has_dgpu_power_gpio" = "1" - register "dgpu_power_gpio" = "49" - register "dgpu_power_off_lvl" = "0" - - register "has_thinker1" = "0" - end end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 ioapic_irq 2 INTB 0x11 end - device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x20f9 - ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA/IDE 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 75f4bce0c54..6aafec69c48 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -18,6 +18,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 #include DefinitionBlock( diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 6b03ad0ad82..43d6088788a 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -75,7 +75,21 @@ void mb_pre_raminit_setup(sysinfo_t *sysinfo) else dock_info(); - hybrid_graphics_init(sysinfo); + if (CONFIG(BOARD_LENOVO_R500)) { + int use_integrated = get_gpio(21); + printk(BIOS_DEBUG, "R500 variant found with an %s GPU\n", + use_integrated ? "integrated" : "discrete"); + if (use_integrated) { + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + } else { + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + } + } else { + hybrid_graphics_init(sysinfo); + } + } void mb_post_raminit_setup(void) diff --git a/src/mainboard/lenovo/t400/thermal.h b/src/mainboard/lenovo/t400/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/t400/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc new file mode 100644 index 00000000000..3dae61e8a80 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t400/variants/r500/data.vbt b/src/mainboard/lenovo/t400/variants/r500/data.vbt new file mode 100644 index 00000000000..799b9b687ef Binary files /dev/null and b/src/mainboard/lenovo/t400/variants/r500/data.vbt differ diff --git a/src/mainboard/lenovo/t400/variants/r500/gpio.c b/src/mainboard/lenovo/t400/variants/r500/gpio.c new file mode 100644 index 00000000000..a1cc4586dae --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/r500/gpio.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/t400/variants/r500/overridetree.cb b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb new file mode 100644 index 00000000000..65b9387f594 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb @@ -0,0 +1,45 @@ +chip northbridge/intel/gm45 + device domain 0 on + device pci 03.0 off end + chip southbridge/intel/i82801ix + register "sata_clock_request" = "1" + # Enable PCIe ports 1,2,4,5,6 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x3b" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 41, 0 }, { 41, 0 }, { 0, 0 }, { 41, 0 }, { 41, 0 }, { 41, 0 } }" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 1, 0, 0 }" + device pci 19.0 off end # LAN + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x17aa 0x20f3 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x17aa 0x20f3 # Ethernet NIC + end + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x20f5 + chip ec/lenovo/h8 + register "config1" = "0x05" + register "config3" = "0x40" + register "event6_enable" = "0x87" + register "event7_enable" = "0x09" + register "event8_enable" = "0x5b" + register "eventa_enable" = "0x83" + register "eventb_enable" = "0x00" + end + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + ioapic_irq 2 INTC 0x12 + # eeprom, 4 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + end + end + end + end +end diff --git a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc new file mode 100644 index 00000000000..3dae61e8a80 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t400/variants/t400/data.vbt b/src/mainboard/lenovo/t400/variants/t400/data.vbt new file mode 100644 index 00000000000..e9bfaaf6512 Binary files /dev/null and b/src/mainboard/lenovo/t400/variants/t400/data.vbt differ diff --git a/src/mainboard/lenovo/t400/gpio.c b/src/mainboard/lenovo/t400/variants/t400/gpio.c similarity index 100% rename from src/mainboard/lenovo/t400/gpio.c rename to src/mainboard/lenovo/t400/variants/t400/gpio.c diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb new file mode 100644 index 00000000000..64cb6db03fe --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb @@ -0,0 +1,43 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x20f5 + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "22" + register "panel_integrated_lvl" = "0" + + register "has_backlight_gpio" = "1" + register "backlight_gpio" = "19" + register "backlight_integrated_lvl" = "0" + + register "has_dgpu_power_gpio" = "1" + register "dgpu_power_gpio" = "49" + register "dgpu_power_off_lvl" = "0" + + register "has_thinker1" = "0" + end + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + ioapic_irq 2 INTC 0x12 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + end + end +end diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index f40e9c0c923..02bcc4f4a49 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -28,6 +28,25 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default lenovo/t420 @@ -56,14 +75,6 @@ config VGA_BIOS_ID string default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21ce - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index f55c2037d56..a9f5f5ff471 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -81,6 +81,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 47c14ef909c..c4092fe901a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -94,6 +94,7 @@ chip northbridge/intel/sandybridge device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x21ce + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 on subsystemid 0x17aa 0x21ce diff --git a/src/mainboard/lenovo/t420/thermal.h b/src/mainboard/lenovo/t420/thermal.h index 6ca5b2a672c..72953fd2c2e 100644 --- a/src/mainboard/lenovo/t420/thermal.h +++ b/src/mainboard/lenovo/t420/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef T420_THERMAL_H -#define T420_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -23,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd new file mode 100644 index 00000000000..8a4cd3b4776 --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 71b94afa520..60735b049db 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -27,6 +27,25 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default lenovo/t420s @@ -55,14 +74,6 @@ config VGA_BIOS_ID string default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21d2 - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 2be55f67c7a..172191a59ae 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -81,6 +81,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 0f09db8fa93..d1e3f754994 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -93,6 +93,7 @@ chip northbridge/intel/sandybridge device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x21d2 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index be4228dc90a..2713725b360 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t420s/thermal.h b/src/mainboard/lenovo/t420s/thermal.h index c7803e5c7a4..72953fd2c2e 100644 --- a/src/mainboard/lenovo/t420s/thermal.h +++ b/src/mainboard/lenovo/t420s/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T420S_THERMAL_H -#define T420S_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd new file mode 100644 index 00000000000..8a4cd3b4776 --- /dev/null +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 687edea021a..7137b5eb730 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP @@ -38,14 +38,6 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21f3 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 9e731f9fbdb..2731b69ec0c 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -88,6 +88,7 @@ chip northbridge/intel/sandybridge end device pci 1c.2 on # PCIe Port #3 subsystemid 0x17aa 0x21f3 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end device pci 1c.3 off # PCIe Port #4 end diff --git a/src/mainboard/lenovo/t430/thermal.h b/src/mainboard/lenovo/t430/thermal.h index e3e49f594e6..edfe3bc7ce1 100644 --- a/src/mainboard/lenovo/t430/thermal.h +++ b/src/mainboard/lenovo/t430/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef _LENOVO_T430_THERMAL_H -#define _LENOVO_T430_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Config TDP Sensor ID */ #define CTDP_SENSOR_ID 0 /* PECI */ @@ -37,4 +41,4 @@ /* Tj_max value for calculating PECI CPU temperature */ #define MAX_TEMPERATURE 105 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 47ff441d833..b0a22aafbf8 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T430S || BOARD_LENOVO_T431S config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 @@ -60,15 +60,6 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fb if BOARD_LENOVO_T430S - default 0x2208 if BOARD_LENOVO_T431S - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 2ecf05ee43d..21d54acf113 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -99,6 +99,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 on subsystemid 0x17aa 0x21fb + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 ExpressCard device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 876d81c0d74..2810e5ae91c 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); - - if (value < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); - - if (value > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/thermal.h b/src/mainboard/lenovo/t430s/thermal.h index 1d55584ce95..72953fd2c2e 100644 --- a/src/mainboard/lenovo/t430s/thermal.h +++ b/src/mainboard/lenovo/t430s/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef T430S_THERMAL_H -#define T430S_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -23,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif /* T430S_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index e461681f190..5bc7b809614 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0:, OC 0 */ diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c4140836dad..e847f8e39de 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -27,6 +27,21 @@ config BOARD_LENOVO_BASEBOARD_T520 if BOARD_LENOVO_BASEBOARD_T520 +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config VARIANT_DIR string default "t520" if BOARD_LENOVO_T520 @@ -40,6 +55,10 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_PART_NUMBER string default "ThinkPad T520" if BOARD_LENOVO_T520 @@ -65,14 +84,6 @@ config VGA_BIOS_FILE string default "pci8086,0126.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21cf - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index a3b0894bcc4..279674d0021 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -32,7 +32,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 1a7943e5a43..ec6ce858ebf 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -81,6 +81,9 @@ entries #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 88ce5046fc3..46ad664c3cb 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h index 60721bf244a..72953fd2c2e 100644 --- a/src/mainboard/lenovo/t520/thermal.h +++ b/src/mainboard/lenovo/t520/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T520_THERMAL_H -#define T520_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* T520_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce1d29..eff2d693045 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -80,12 +80,16 @@ chip northbridge/intel/sandybridge device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on # dummy @@ -165,6 +169,8 @@ chip northbridge/intel/sandybridge device i2c 5f on end end end # SMBus + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller end end end diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 1770ad9722c..ceca46ea841 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -80,7 +80,9 @@ chip northbridge/intel/sandybridge device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd new file mode 100644 index 00000000000..8a4cd3b4776 --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 14f9fb2478c..5b5b7ffa49b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -1,7 +1,7 @@ config BOARD_LENOVO_BASEBOARD_T530 def_bool n select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 @@ -62,14 +62,6 @@ config VGA_BIOS_FILE default "pci8086,0106.rom" if BOARD_LENOVO_T530 default "pci8086,0166.rom" if BOARD_LENOVO_W530 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index a3b0894bcc4..279674d0021 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -32,7 +32,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index bf0f81fc572..46ad664c3cb 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h index 0b24ea81860..72953fd2c2e 100644 --- a/src/mainboard/lenovo/t530/thermal.h +++ b/src/mainboard/lenovo/t530/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T530_THERMAL_H -#define T530_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* T530_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 1a1e7075f26..335543a8f79 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -83,7 +83,9 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (expresscard) + device pci 1c.2 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 253096c3165..0a80fa1d8c4 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -98,6 +98,7 @@ chip northbridge/intel/sandybridge end device pci 1c.2 on # PCIe Port #3 subsystemid 0x17aa 0x21f6 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end device pci 1c.3 off # PCIe Port #4 end diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 183b7fe2990..bd10a0e3fb6 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -16,6 +16,13 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,7 +30,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2d998fbaa2b..b78d862d417 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index be71cf4bb23..0c7c0cfb2d5 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -195,8 +195,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/t60/thermal.h b/src/mainboard/lenovo/t60/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/t60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index f3f56cec1fb..cc3ef49f25a 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -55,8 +55,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 2f936a915dd..e7da8d0d770 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -37,12 +37,4 @@ config USBDEBUG_HCD_INDEX int default 2 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fe - endif # BOARD_LENOVO_X131E diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h index ff928699aea..72953fd2c2e 100644 --- a/src/mainboard/lenovo/x131e/thermal.h +++ b/src/mainboard/lenovo/x131e/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,15 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X131E_THERMAL_H -#define X131E_THERMAL_H - -/* Active Thermal and fans are controlled by the EC. */ +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 +#define CRITICAL_TEMPERATURE 100 /* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +#define PASSIVE_TEMPERATURE 90 -#endif /* X131E_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 202fabd5fd5..a15cadf202c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_X1_CARBON_GEN1 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 @@ -54,12 +54,4 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - endif # BOARD_LENOVO_X1_CARBON_GEN1 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h index 199c27e637f..72953fd2c2e 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h +++ b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 301ca50735d..8fb9056c518 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -21,6 +21,13 @@ #include #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -32,9 +39,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index d800e4fdfe7..2ed4308cfab 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -113,6 +113,7 @@ chip northbridge/intel/gm45 end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/lenovo/x200/thermal.h b/src/mainboard/lenovo/x200/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/x200/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index e412503c882..82991b267ba 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -17,10 +17,15 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t * gnvs) { - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index fa33aeb4313..6ece08bee64 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -92,7 +92,9 @@ chip northbridge/intel/nehalem device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (wwan) - device pci 1c.3 on end # PCIe Port #4 (Expresscard) + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 (Expresscard) device pci 1c.4 on end # PCIe Port #5 (wlan) device pci 1d.0 on # USB2 EHCI diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7e895b46f0f..ae154e25b10 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -175,10 +175,6 @@ void mainboard_romstage_entry(unsigned long bist) int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - timestamp_init(timestamp_get()); - - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index e733b3b5fe8..fc6a0e96701 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/x201/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 70245d20bce..c80c2520b26 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -26,6 +26,21 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x220 @@ -35,6 +50,9 @@ config VARIANT_DIR default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I default "x1" if BOARD_LENOVO_X1 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT config MAINBOARD_PART_NUMBER string @@ -69,13 +87,4 @@ config VGA_BIOS_ID default "8086,0116" if BOARD_LENOVO_X220I default "8086,0126" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21db if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I - default 0x21e8 if BOARD_LENOVO_X1 - endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index d4a4ed33718..dc98010ea22 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -80,6 +80,9 @@ entries #435 549 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 0ec66f59b8a..360de049435 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -98,6 +98,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x21db + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on subsystemid 0x17aa 0x21db diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index bf0f81fc572..46ad664c3cb 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h index 82df3030939..72953fd2c2e 100644 --- a/src/mainboard/lenovo/x220/thermal.h +++ b/src/mainboard/lenovo/x220/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X220_THERMAL_H -#define X220_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd new file mode 100644 index 00000000000..8a4cd3b4776 --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 3ec537a2428..a043efcd70e 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_X230 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 @@ -55,12 +55,4 @@ config VGA_BIOS_ID string default "8086,0166" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - endif # BOARD_LENOVO_X230 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 68e2f8ea2c1..4687e9ccc3e 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -110,6 +110,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #2 device pci 1c.2 on subsystemid 0x17aa 0x21fa + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h index 199c27e637f..72953fd2c2e 100644 --- a/src/mainboard/lenovo/x230/thermal.h +++ b/src/mainboard/lenovo/x230/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 183b7fe2990..bd10a0e3fb6 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -16,6 +16,13 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,7 +30,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 274a15113a8..964e9c0b529 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "dock.h" #include #include diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 95192f733bf..b66ef668717 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -18,7 +18,7 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include +#include #include #include #include @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -198,8 +197,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/x60/thermal.h b/src/mainboard/lenovo/x60/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/x60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/z61t/acpi_tables.c index 3e9a81042e9..bd10a0e3fb6 100644 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ b/src/mainboard/lenovo/z61t/acpi_tables.c @@ -16,6 +16,13 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,4 +30,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c index 886b4fb4035..5f599465a14 100644 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ b/src/mainboard/lenovo/z61t/mainboard.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 86d94a6c853..502eac39d56 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -18,7 +18,7 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include +#include #include #include #include @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -196,8 +195,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/z61t/thermal.h b/src/mainboard/lenovo/z61t/thermal.h new file mode 100644 index 00000000000..72953fd2c2e --- /dev/null +++ b/src/mainboard/lenovo/z61t/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index eca687c6e74..9ce9ec768ed 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 48410085353..7e6d0c485e5 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig new file mode 100644 index 00000000000..4923bbfdea5 --- /dev/null +++ b/src/mainboard/msi/ms7707/Kconfig @@ -0,0 +1,49 @@ +if BOARD_MSI_MS7707 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_FINTEK_F71808A + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select MAINBOARD_USES_IFD_GBE_REGION + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default msi/ms7707 + +config MAINBOARD_PART_NUMBER + string + default "MS-7707" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 + +config CBFS_SIZE + hex + default 0x200000 + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vgabios.bin" + +config VGA_BIOS_ID + string + default "8086,0102" + +endif diff --git a/src/mainboard/msi/ms7707/Kconfig.name b/src/mainboard/msi/ms7707/Kconfig.name new file mode 100644 index 00000000000..f6217ef2a66 --- /dev/null +++ b/src/mainboard/msi/ms7707/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_MS7707 + bool "MS-7707" diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc new file mode 100644 index 00000000000..3dae61e8a80 --- /dev/null +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl b/src/mainboard/msi/ms7707/acpi/ec.asl similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl rename to src/mainboard/msi/ms7707/acpi/ec.asl diff --git a/src/mainboard/msi/ms7707/acpi/platform.asl b/src/mainboard/msi/ms7707/acpi/platform.asl new file mode 100644 index 00000000000..7c3b3c61ff9 --- /dev/null +++ b/src/mainboard/msi/ms7707/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/msi/ms7707/acpi/superio.asl b/src/mainboard/msi/ms7707/acpi/superio.asl new file mode 100644 index 00000000000..e69de29bb2d diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c similarity index 58% rename from src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c rename to src/mainboard/msi/ms7707/acpi_tables.c index 5c09059173b..370b70935fa 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -1,11 +1,13 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -13,20 +15,10 @@ * GNU General Public License for more details. */ -#include #include -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} void acpi_create_gnvs(global_nvs_t *gnvs) { - memset((void *)gnvs, 0, sizeof(*gnvs)); - /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; gnvs->s3u1 = 0; @@ -35,5 +27,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - acpi_update_thermal_table(gnvs); + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/msi/ms7707/board_info.txt b/src/mainboard/msi/ms7707/board_info.txt new file mode 100644 index 00000000000..eebec48438b --- /dev/null +++ b/src/mainboard/msi/ms7707/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb new file mode 100644 index 00000000000..4db2536148e --- /dev/null +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -0,0 +1,117 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1462 0x7707 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0a01" + register "p_cnt_throttling_supported" = "1" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "gpe0_en" = "0x28000040" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/fintek/f71808a + register "multi_function_register_0" = "0x00" # 0x28 + register "multi_function_register_1" = "0xc0" # 0x29 + register "multi_function_register_2" = "0x20" # 0x2a + register "multi_function_register_3" = "0x4f" # 0x2b + register "multi_function_register_4" = "0x90" # 0x2c + register "hwm_peci_tsi_ctrl" = "0x02" # 0x0a - PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x64" # 0x0c - TCC temperature = 100 °C + register "hwm_fan1_seg1_speed" = "0xff" # 0xaa - Fan 1 segment 1 + register "hwm_fan1_seg2_speed" = "0xe2" # 0xab - Fan 1 segment 2 + register "hwm_fan1_seg3_speed" = "0xaf" # 0xac - Fan 1 segment 3 + register "hwm_fan1_seg4_speed" = "0x89" # 0xad - Fan 1 segment 4 + register "hwm_fan1_seg5_speed" = "0x72" # 0xae - Fan 1 segment 5 + register "hwm_fan1_temp_src" = "0x10" # 0xaf - Fan 1 source = PECI + register "hwm_fan2_seg1_speed" = "0xff" # 0xba - Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xd9" # 0xbb - Fan 2 segment 2 = 86% + register "hwm_fan2_seg3_speed" = "0xb2" # 0xbc - Fan 2 segment 3 = 74% + register "hwm_fan2_seg4_speed" = "0x99" # 0xbd - Fan 2 segment 4 = 62% + register "hwm_fan2_seg5_speed" = "0x80" # 0xbe - Fan 2 segment 5 = 50% + register "hwm_fan2_temp_src" = "0x1e" # 0xbf - Fan 2 source = temperature 2 + + register "hwm_domain1_en" = "0x01" + register "hwm_fan1_boundary_hysteresis" = "0x43" + register "hwm_vt1_boundary_1_temperature" = "0x52" # 82°C + register "hwm_vt1_boundary_2_temperature" = "0x46" # 70°C + register "hwm_vt1_boundary_3_temperature" = "0x41" # 65°C + register "hwm_vt1_boundary_4_temperature" = "0x37" # 55°C + + device pnp 4e.1 off end # Serial Port + device pnp 4e.4 on # Hardware monitor + io 0x60 = 0x295 + irq 0x70 = 0 + # global + irq 0x27 = 0x10 # PWOK follows Intel sequence + irq 0x2d = 0x2e # Anykey+MouseButton wakeup + end + device pnp 4e.5 on # Keyboard + io 0x60 = 0x060 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.6 on # GPIO + irq 0x70 = 0 + irq 0xd0 = 0x20 # GPIO2 Output Enable + irq 0xd1 = 0x20 # GPIO2 Output Data + irq 0xd3 = 0x20 # GPIO2 Drive Enable + end + device pnp 4e.7 off # WDT + io 0x60 = 0xa00 + end + device pnp 4e.8 off end # CIR + device pnp 4e.a on # PME, ACPI, Power Saving Registers + irq 0xe2 = 0x0c # EuP control + irq 0xed = 0xc0 # EuP Watchdog Control + irq 0xf4 = 0x10 # Keep Last State Select + irq 0xf9 = 0x09 # LED VSB Mode Select + end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl new file mode 100644 index 00000000000..88085399b9c --- /dev/null +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/msi/ms7707/gpio.c b/src/mainboard/msi/ms7707/gpio.c new file mode 100644 index 00000000000..8fd8e445814 --- /dev/null +++ b/src/mainboard/msi/ms7707/gpio.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c new file mode 100644 index 00000000000..6a6cf41553f --- /dev/null +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x14627707, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x14627707), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01813c40), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01454130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c new file mode 100644 index 00000000000..30bb545328a --- /dev/null +++ b/src/mainboard/msi/ms7707/romstage.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void pch_enable_lpc(void) +{ + /* IO Decode Ranges Register */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + /* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); + + u16 reg16; + reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4); + reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD) + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 0, 0}, + {1, 0, 0}, + {1, 0, 1}, + {1, 0, 1}, + {1, 0, 2}, + {1, 0, 2}, + {1, 0, 3}, + {1, 0, 3}, + {1, 0, 4}, + {1, 0, 4}, + {1, 0, 6}, + {1, 0, 5}, + {1, 0, 5}, + {1, 0, 6}, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index aff6619b873..037c3226201 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,11 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + +config INTEGRATED_UART + def_bool n config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c22ebe..2d91b73b023 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ chip soc/intel/fsp_broadwell_de device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703266a..72b1c3c0868 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ DefinitionBlock( { #include "acpi/platform.asl" + Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -290,5 +293,97 @@ DefinitionBlock( } } + Scope (_SB.PCI0.LPC0) + { + Device (SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index 93c2a58f743..bbfeeafb3b8 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,17 +15,51 @@ */ #include +#include #if CONFIG(VGA_ROM_RUN) #include #endif +#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 2bb50f097b4..f3ec7e32b88 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -20,6 +20,9 @@ #include #include #include +#include +#include +#include /** * /brief mainboard call for setup that needs to be done before fsp init @@ -49,7 +52,9 @@ void early_mainboard_romstage_entry(void) */ void late_mainboard_romstage_entry(void) { - + // IPMI through BIC + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); } /** @@ -57,5 +62,4 @@ void late_mainboard_romstage_entry(void) */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - } diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl index 716c3a62de7..d341ab44886 100644 --- a/src/mainboard/packardbell/ms2290/acpi/battery.asl +++ b/src/mainboard/packardbell/ms2290/acpi/battery.asl @@ -52,7 +52,7 @@ Method(BSTA, 4, NotSerialized) Return (Arg1) } -Method(BINF, 2, NotSerialized) +Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) Store(0, PAGE) diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 5fb2498a3e2..4f3e5b6c163 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -101,7 +101,7 @@ Device(EC) BAOE, 128, /* Battery OEM info */ } - Method (_CRS, 0) + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() { diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 8442dfaee90..0ab55448582 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -31,7 +31,6 @@ #include #include -#include "arch/early_variables.h" #include #include @@ -168,14 +167,10 @@ void mainboard_romstage_entry(unsigned long bist) int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - timestamp_init(timestamp_get()); - /* SERR pin is confused on reset. Clear NMI. */ outb(4, 0x61); outb(0, 0x61); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index ff13543cde0..83562be9211 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -18,9 +18,9 @@ #include #include #include -#include #include #include +#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 906ecb648fc..df5f03731b9 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -13,11 +13,13 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include + #include "gpio_ftns.h" static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl index 30e6fdcb3c0..3cf38c035a9 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 535024a86f5..edacb22beee 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 293e186cec6..16ce37a95f8 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -13,5 +13,6 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/purism/librem_bdw/gpio.h b/src/mainboard/purism/librem_bdw/gpio.c similarity index 96% rename from src/mainboard/purism/librem_bdw/gpio.h rename to src/mainboard/purism/librem_bdw/gpio.c index 98b09bc45ad..510299659e5 100644 --- a/src/mainboard/purism/librem_bdw/gpio.h +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ PCH_GPIO_INPUT, /* 1 */ PCH_GPIO_INPUT, /* 2 */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 94 */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 2e0ae85b95b..0e1ad885b05 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -14,24 +14,16 @@ */ #include -#include #include #include #include -#include "gpio.h" -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - struct pei_data pei_data; - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); +} - /* Initialize memory */ - romstage_common(rp); +void mainboard_post_raminit(struct romstage_params *rp) +{ } diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 965318f5650..2372b9d2800 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -19,11 +19,8 @@ config IRQ_SLOT_COUNT config VARIANT_DIR string - default "librem13v2" if BOARD_PURISM_LIBREM13_V2 - default "librem13v2" if BOARD_PURISM_LIBREM13_V3 - default "librem15v3" if BOARD_PURISM_LIBREM15_V3 - default "librem13v2" if BOARD_PURISM_LIBREM13_V4 - default "librem15v3" if BOARD_PURISM_LIBREM15_V4 + default "librem13v2" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 + default "librem15v3" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 config MAINBOARD_VENDOR string @@ -31,28 +28,16 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY string - default "Librem 13" if BOARD_PURISM_LIBREM13_V2 - default "Librem 13" if BOARD_PURISM_LIBREM13_V3 - default "Librem 15" if BOARD_PURISM_LIBREM15_V3 - default "Librem 13" if BOARD_PURISM_LIBREM13_V4 - default "Librem 15" if BOARD_PURISM_LIBREM15_V4 + default "Librem 13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 + default "Librem 15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 config MAINBOARD_PART_NUMBER string default "Librem 13 v2" if BOARD_PURISM_LIBREM13_V2 - default "Librem 13 v2" if BOARD_PURISM_LIBREM13_V3 default "Librem 15 v3" if BOARD_PURISM_LIBREM15_V3 default "Librem 13 v4" if BOARD_PURISM_LIBREM13_V4 default "Librem 15 v4" if BOARD_PURISM_LIBREM15_V4 -config MAINBOARD_VERSION - string - default "2.0" if BOARD_PURISM_LIBREM13_V2 - default "3.0" if BOARD_PURISM_LIBREM13_V3 - default "3.0" if BOARD_PURISM_LIBREM15_V3 - default "4.0" if BOARD_PURISM_LIBREM13_V4 - default "4.0" if BOARD_PURISM_LIBREM15_V4 - config MAINBOARD_DIR string default "purism/librem_skl" @@ -67,11 +52,8 @@ config MAX_CPUS config VGA_BIOS_ID string - default "8086,1916" if BOARD_PURISM_LIBREM13_V2 - default "8086,1916" if BOARD_PURISM_LIBREM13_V3 - default "8086,1916" if BOARD_PURISM_LIBREM15_V3 - default "8086,5916" if BOARD_PURISM_LIBREM13_V4 - default "8086,5916" if BOARD_PURISM_LIBREM15_V4 + default "8086,1916" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 + default "8086,5916" if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 config DIMM_MAX int @@ -81,14 +63,6 @@ config DIMM_SPD_SIZE int default 512 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x18000 - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFE115A0 - config CBFS_SIZE hex default 0xe00000 diff --git a/src/mainboard/purism/librem_skl/Kconfig.name b/src/mainboard/purism/librem_skl/Kconfig.name index 5b82de74353..b0dac3e3389 100644 --- a/src/mainboard/purism/librem_skl/Kconfig.name +++ b/src/mainboard/purism/librem_skl/Kconfig.name @@ -1,9 +1,5 @@ config BOARD_PURISM_LIBREM13_V2 - bool "Librem 13 v2" - select BOARD_PURISM_BASEBOARD_LIBREM_SKL - -config BOARD_PURISM_LIBREM13_V3 - bool "Librem 13 v3" + bool "Librem 13 v2/v3" select BOARD_PURISM_BASEBOARD_LIBREM_SKL config BOARD_PURISM_LIBREM15_V3 diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index 5a7131f1ba6..35f0f6cbdee 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -13,8 +13,5 @@ ## GNU General Public License for more details. ## -romstage-y += pei_data.c - -ramstage-y += pei_data.c ramstage-y += ramstage.c ramstage-y += hda_verb.c diff --git a/src/mainboard/purism/librem_skl/pei_data.c b/src/mainboard/purism/librem_skl/pei_data.c deleted file mode 100644 index 0be917d3c72..00000000000 --- a/src/mainboard/purism/librem_skl/pei_data.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Purism SPC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pei_data.h" - -void mainboard_fill_dq_map_data(void *dq_map_ptr) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 121, 81, 100 }; - memcpy(rcomp_ptr, RcompResistor, - sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); -} diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 63d148a98ec..faf4090ae1a 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -19,7 +19,41 @@ #include #include #include -#include "pei_data.h" +#include + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} void mainboard_memory_init_params(FSPM_UPD *mupd) { diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index cf87d7fa953..2db0f759643 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index efb376cf386..2bdad276c1d 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -26,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -228,8 +228,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 01fc253eacd..54f04c406ec 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -3,7 +3,7 @@ if BOARD_RODA_RV11 || BOARD_RODA_RW11 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 2d4fb61be89..6760f036113 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -47,7 +47,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), - "recovery"}, + "presence"}, {100, ACTIVE_HIGH, lid & 1, "lid"}, diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1080689d4a1..a77149d9275 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -148,7 +148,6 @@ static const uint8_t *locate_spd(void) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); - // leave onboard dimm address at f0, and copy spd data there. return spd_data[spd_index]; } @@ -198,8 +197,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; - // leave onboard dimm address at f0, and copy spd data there. - memcpy(pei_data->spd_data[0], locate_spd(), 256); + memcpy(pei_data->spd_data[2], locate_spd(), 256); } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index b1ad1371135..9ec4218b01d 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -43,7 +43,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), - "recovery"}, + "presence"}, /* Hard code the lid switch GPIO to open. */ {100, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index 85b2f36cda2..6d27b3f1bd2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -3,7 +3,7 @@ if BOARD_SAPPHIRE_PUREPLATINUMH61 config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_FINTEK_F71808A @@ -32,14 +32,6 @@ config VGA_BIOS_ID string default "8086,0162" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x1007 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x174b - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index b39b6817f6e..c931e1008a1 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -28,6 +28,7 @@ #include #include #include +#include #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index 6d22fd98268..df6fc21bdec 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c index 060a35c0a8e..c0770f31247 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /** diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 0c2418ad278..7890ee02113 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -23,6 +23,12 @@ #include #include #include +#include +#include + +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814 void variant_mainboard_final(void) { @@ -36,6 +42,21 @@ void variant_mainboard_final(void) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* Reduce SD-Card speed to DDR50 because of PCB constraints. */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (dev) { + uint32_t reg; + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); + reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); + /* Disable HS400 and SDR104, keep SDR50 and DDR50 modes. */ + reg &= ~0x20005800; + write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + } } static void wait_for_legacy_dev(void *unused) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 3e2e7f09102..6a883c6a264 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -28,6 +28,7 @@ #include #include #include +#include #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c index 73d901935ae..47763ae5d88 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /* diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 9462497aa6e..e1b56bda131 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index 060a35c0a8e..c0770f31247 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /** diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 9acc60a3452..414baeb089b 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "soc/i2c.h" #include "ptn3460.h" diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index ea58e02b2e2..8ac6ff1208f 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -86,6 +87,11 @@ static void fixup_fdt(void *unused) /* load flat dt from cbfs */ fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL); + if (fdt_rom == NULL) { + printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); + return; + } + /* Expand DT into a tree */ tree = fdt_unflatten(fdt_rom); @@ -95,6 +101,12 @@ static void fixup_fdt(void *unused) /* convert the tree to a flat dt */ void *dt = malloc(dt_flat_size(tree)); + + if (dt == NULL) { + printk(BIOS_ERR, "Unable to allocate memory for flat device tree\n"); + return; + } + dt_flatten(tree, dt); /* update HLS */ diff --git a/src/mainboard/sifive/hifive-unleashed/mainboard.c b/src/mainboard/sifive/hifive-unleashed/mainboard.c index 2d62cd077aa..96a2678ee0b 100644 --- a/src/mainboard/sifive/hifive-unleashed/mainboard.c +++ b/src/mainboard/sifive/hifive-unleashed/mainboard.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 6bf0b2a1990..430bed379ab 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -44,14 +44,6 @@ config MAINBOARD_PART_NUMBER string default "X10SLM+-F" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x0803 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x15d9 - config MAX_CPUS int default 8 diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index ea9cc8ab889..301070b0842 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -15,3 +15,4 @@ ## romstage-y += gpio.c +bootblock-y += bootblock.c diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm-f/bootblock.c new file mode 100644 index 00000000000..aeffa69e88c --- /dev/null +++ b/src/mainboard/supermicro/x10slm-f/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 84ad0477257..e43302af24a 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -17,14 +17,11 @@ #include #include -#include #include #include #include #include #include -#include -#include static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -41,27 +38,6 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ - const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); - const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); - const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); - - /* Select HWM/LED functions instead of floppy functions. */ - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); - - /* Power RAM in S3 and let the PCH handle power failure actions. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x70); - - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { diff --git a/src/mainboard/up/Kconfig b/src/mainboard/up/Kconfig new file mode 100644 index 00000000000..04e290c0ae7 --- /dev/null +++ b/src/mainboard/up/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_UP + +choice + prompt "Mainboard model" + +source "src/mainboard/up/*/Kconfig.name" + +endchoice + +source "src/mainboard/up/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "UP" + +endif diff --git a/src/mainboard/up/Kconfig.name b/src/mainboard/up/Kconfig.name new file mode 100644 index 00000000000..ef694d30f97 --- /dev/null +++ b/src/mainboard/up/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UP + bool "UP" diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig new file mode 100644 index 00000000000..fd03b7a2ae5 --- /dev/null +++ b/src/mainboard/up/squared/Kconfig @@ -0,0 +1,88 @@ +if BOARD_UP_SQUARED + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select USE_BLOBS + select ADD_FSP_BINARIES + select FSP_USE_REPO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + select MAINBOARD_HAS_LIBGFXINIT + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config GBB_HWID + string + depends on VBOOT + default "UPSQUARED" + +config MAINBOARD_DIR + string + default "up/squared" + +config MAINBOARD_VENDOR + string + default "Up" + +config MAINBOARD_PART_NUMBER + string + default "Squared" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/upsquared.fmd" if !VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if !VBOOT_SLOTS_RW_A + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config VGA_BIOS_ID + string + default "8086,5a85" + +config PXE_ROM_ID + string + default "10ec,8168" + +config MAX_CPUS + int + default 2 + +config UART_FOR_CONSOLE + int + default 0 + +config IFWI_FMAP_NAME + string + default "IFWI" + +config POST_IO + bool + default n + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +endif diff --git a/src/mainboard/up/squared/Kconfig.name b/src/mainboard/up/squared/Kconfig.name new file mode 100644 index 00000000000..4d6a59bb7c6 --- /dev/null +++ b/src/mainboard/up/squared/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UP_SQUARED + bool "Squared" diff --git a/src/mainboard/up/squared/Makefile.inc b/src/mainboard/up/squared/Makefile.inc new file mode 100644 index 00000000000..af2508e8cf6 --- /dev/null +++ b/src/mainboard/up/squared/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/up/squared/acpi_tables.c b/src/mainboard/up/squared/acpi_tables.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/src/mainboard/up/squared/board_info.txt b/src/mainboard/up/squared/board_info.txt new file mode 100644 index 00000000000..851af32a781 --- /dev/null +++ b/src/mainboard/up/squared/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Up +Board name: Squared +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2017 diff --git a/src/mainboard/up/squared/bootblock.c b/src/mainboard/up/squared/bootblock.c new file mode 100644 index 00000000000..e35e8b8e7f2 --- /dev/null +++ b/src/mainboard/up/squared/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void bootblock_mainboard_init(void) +{ + lpc_configure_pads(); +} diff --git a/src/mainboard/up/squared/data.vbt b/src/mainboard/up/squared/data.vbt new file mode 100644 index 00000000000..a8b55501081 Binary files /dev/null and b/src/mainboard/up/squared/data.vbt differ diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb new file mode 100644 index 00000000000..a71405f0feb --- /dev/null +++ b/src/mainboard/up/squared/devicetree.cb @@ -0,0 +1,50 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 off end # - Iunit + device pci 0d.0 off end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 off end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - TXE + device pci 11.0 off end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 1 - PcieRootPort[2] + device pci 13.1 on end # - PCIe-A 2 - PcieRootPort[3] + device pci 13.2 on end # - PCIe-A 3 - PcieRootPort[4] + device pci 13.3 on end # - PCIe-A 4 - PcieRootPort[5] + device pci 14.0 on end # - PCIe-B 1 - PcieRootPort[0] + device pci 14.1 on end # - PCIe-B 2 - PcieRootPort[1] + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - HSUART 0 + device pci 18.1 on end # - HSUART 1 + device pci 18.2 off end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/up/squared/dsdt.asl similarity index 61% rename from src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl rename to src/mainboard/up/squared/dsdt.asl index 67054cc28d6..48b24b9190a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright 2016 Google Inc. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -18,24 +20,24 @@ DefinitionBlock( 0x02, // DSDT revision: ACPI v2.0 and up OEM_ID, ACPI_TABLE_CREATOR, - 0x20141018 // OEM revision + 0x20110725 // OEM revision ) { - #include + /* global NVS and variables */ + #include - // Some generic macros - #include "acpi/platform.asl" + /* CPU */ #include - /* global NVS and variables. */ - #include - #include Scope (\_SB) { Device (PCI0) { - #include - #include - #include + #include + #include + #include } } + + /* Chipset specific sleep states */ + #include } diff --git a/src/mainboard/up/squared/gma-mainboard.ads b/src/mainboard/up/squared/gma-mainboard.ads new file mode 100644 index 00000000000..6865970e167 --- /dev/null +++ b/src/mainboard/up/squared/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h new file mode 100644 index 00000000000..b4ac4e9b6d2 --- /dev/null +++ b/src/mainboard/up/squared/gpio.h @@ -0,0 +1,773 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include + +#ifndef GPIO_H +#define GPIO_H + +static const struct pad_config gpio_table[] = { + // ******************************** + // ******* GPIO Group North ******* + // ******************************** + // *GPIO + _PAD_CFG_STRUCT(GPIO_0, 0x04000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_1, 0x04000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_2, 0x04000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_3, 0x04000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_4, 0x04000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_5, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_6, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_7, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_8, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_9, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_10, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_11, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_12, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_13, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_14, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_15, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_16, 0x40880102, 0x00024000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_17, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_18, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_19, 0x44000201, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_20, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_21, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_22, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_23, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_24, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_25, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_26, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_28, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_30, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_31, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_32, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_33, 0x44000102, 0x00000000), + + // PWM0 + _PAD_CFG_STRUCT(GPIO_34, 0x44000400, 0x00001000), + + // PWM1 + _PAD_CFG_STRUCT(GPIO_35, 0x44000400, 0x00001000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_36, 0x44000201, 0x00000000), + + // PWM3 + _PAD_CFG_STRUCT(GPIO_37, 0x04000400, 0x00001000), + + // LPSS_UART0_RXD + _PAD_CFG_STRUCT(GPIO_38, 0x44000402, 0x00023100), + + // LPSS_UART0_TXD + _PAD_CFG_STRUCT(GPIO_39, 0x44000400, 0x00003100), + + // LPSS_UART0_RTS_N + _PAD_CFG_STRUCT(GPIO_40, 0x44000400, 0x00003100), + + // LPSS_UART0_CTS_N + _PAD_CFG_STRUCT(GPIO_41, 0x44000402, 0x00023100), + + // LPSS_UART1_RXD + _PAD_CFG_STRUCT(GPIO_42, 0x44000402, 0x00023100), + + // LPSS_UART1_TXD + _PAD_CFG_STRUCT(GPIO_43, 0x44000400, 0x0001f100), + + // LPSS_UART1_RTS_N + _PAD_CFG_STRUCT(GPIO_44, 0x44000400, 0x00003100), + + // LPSS_UART1_CTS_N + _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x0001c100), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_46, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_47, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_48, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_49, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_62, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_63, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_64, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_65, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_66, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_67, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_68, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_69, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_70, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_71, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_72, 0x44000200, 0x00001000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_73, 0x44000200, 0x00001000), + + // *JTAG_TCK + _PAD_CFG_STRUCT(TCK, 0x44000400, 0x00c3d000), + + // *JTAG_TRST_N + _PAD_CFG_STRUCT(TRST_B, 0x44000400, 0x00c3d000), + + // *JTAG_TMS + _PAD_CFG_STRUCT(TMS, 0x44000400, 0x00c3f000), + + // *JTAG_TDI + _PAD_CFG_STRUCT(TDI, 0x44000400, 0x00c3f000), + + // *JTAG_PMODE + _PAD_CFG_STRUCT(CX_PMODE, 0x44000400, 0x00c3c000), + + // *JTAG_PREQ_N + _PAD_CFG_STRUCT(CX_PREQ_B, 0x44000402, 0x00c3f000), + + // *JTAGX + _PAD_CFG_STRUCT(JTAGX, 0x44000402, 0x00c3f000), + + // *JTAG_PRDY_N + _PAD_CFG_STRUCT(CX_PRDY_B, 0x44000402, 0x0043f000), + + // *JTAG_TDO + _PAD_CFG_STRUCT(TDO, 0x44000400, 0x0043f000), + + // GPIO + _PAD_CFG_STRUCT(CNV_BRI_DT, 0x44000201, 0x0003d000), + + // GPIO + _PAD_CFG_STRUCT(CNV_BRI_RSP, 0x44000201, 0x00002400), + + // GPIO + _PAD_CFG_STRUCT(CNV_RGI_DT, 0x44000201, 0x00000000), + + // RESERVED +// _PAD_CFG_STRUCT(CNV_RGI_RSP, 0xffffffff, 0xffffffff), + + // GPIO + _PAD_CFG_STRUCT(SVID0_ALERT_B, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(SVID0_DATA, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(SVID0_CLK, 0x44000100, 0x00000000), + + + // ************************************ + // ******* GPIO Group NorthWest ******* + // ************************************ + // *DDI0_DDC_SDA + _PAD_CFG_STRUCT(GPIO_187, 0x44000400, 0x0001f000), + + // *DDI0_DDC_SCL + _PAD_CFG_STRUCT(GPIO_188, 0x44000400, 0x0001f000), + + // *DDI1_DDC_SDA + _PAD_CFG_STRUCT(GPIO_189, 0x44000400, 0x00002c00), + + // *DDI1_DDC_SCL + _PAD_CFG_STRUCT(GPIO_190, 0x44000400, 0x00002c00), + + // GPIO + _PAD_CFG_STRUCT(GPIO_191, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_192, 0x44000100, 0x00000000), + + // *PNL0_VDDEN + _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x00005000), + + // *PNL0_BKLTEN + _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x00005000), + + // *PNL0_BKLTCTL + _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x00005000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_196, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_197, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_198, 0x44000100, 0x00000000), + + // DDI1_HPD + _PAD_CFG_STRUCT(GPIO_199, 0x44000800, 0x00003000), + + // DDI0_HPD + _PAD_CFG_STRUCT(GPIO_200, 0x44000802, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_201, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_202, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_203, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_204, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_FS0, 0x44000102, 0x00000000), + + // DDI2_HPD + _PAD_CFG_STRUCT(PMC_SPI_FS1, 0x44000802, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_FS2, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_RXD, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_TXD, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_CLK, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x44000203, 0x00002400), + + // GPIO + _PAD_CFG_STRUCT(PMIC_RESET_B, 0x44000102, 0x0003c000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00000000), + + // *THERMTRIP_N + _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(PMIC_STDBY, 0x44000201, 0x00001000), + + // *PROCHOT_N + _PAD_CFG_STRUCT(PROCHOT_B, 0x44000402, 0x00023000), + + // RESERVED +// _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0xffffffff, 0xffffffff), + + // RESERVED +// _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0xffffffff, 0xffffffff), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_74, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_75, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_76, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_77, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_78, 0x44000100, 0x00000000), + + // AVS_DMIC_CLK_A1 + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d000), + + // AVS_DMIC_CLK_B1 + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d000), + + // AVS_DMIC_DATA_1 + _PAD_CFG_STRUCT(GPIO_81, 0x44000400, 0x00025200), + + // AVS_DMIC_CLK_AB2 + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d000), + + // AVS_DMIC_DATA_2 + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x00025200), + + // AVS_I2S2_MCLK + _PAD_CFG_STRUCT(GPIO_84, 0x44000400, 0x00001000), + + // AVS_I2S2_BCLK + _PAD_CFG_STRUCT(GPIO_85, 0x44000400, 0x0001d200), + + // AVS_I2S2_WS_SYNC + _PAD_CFG_STRUCT(GPIO_86, 0x44000402, 0x0001d200), + + // AVS_I2S2_SDI + _PAD_CFG_STRUCT(GPIO_87, 0x44000402, 0x0001f200), + + // AVS_I2S2_SDO + _PAD_CFG_STRUCT(GPIO_88, 0x44000400, 0x0001c200), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_89, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_90, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_91, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_92, 0x44000100, 0x00000000), + + // *FST_SPI_CS0_N + _PAD_CFG_STRUCT(GPIO_97, 0x44000402, 0x0003fc00), + + // GPIO + _PAD_CFG_STRUCT(GPIO_98, 0x44000100, 0x00000000), + + // *FST_SPI_MOSI_IO0 + _PAD_CFG_STRUCT(GPIO_99, 0x44000400, 0x0003fc00), + + // *FST_SPI_MISO_IO1 + _PAD_CFG_STRUCT(GPIO_100, 0x44000402, 0x0003fc00), + + // GPIO + _PAD_CFG_STRUCT(GPIO_101, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_102, 0x44000100, 0x00000000), + + // *FST_SPI_CLK + _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003fc00), + + // *n/a + _PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x44000400, 0x0003c000), + + // SIO_SPI_0_CLK + _PAD_CFG_STRUCT(GPIO_104, 0x44000400, 0x0001d200), + + // SIO_SPI_0_FS0 + _PAD_CFG_STRUCT(GPIO_105, 0x44000400, 0x0001f200), + + // SIO_SPI_0_FS1 + _PAD_CFG_STRUCT(GPIO_106, 0x44000400, 0x0001f200), + + // SIO_SPI_0_RXD + _PAD_CFG_STRUCT(GPIO_109, 0x44000402, 0x0001f200), + + // SIO_SPI_0_TXD + _PAD_CFG_STRUCT(GPIO_110, 0x44000400, 0x0001f200), + + // SIO_SPI_1_CLK + _PAD_CFG_STRUCT(GPIO_111, 0x44000400, 0x00001000), + + // SIO_SPI_1_FS0 + _PAD_CFG_STRUCT(GPIO_112, 0x44000400, 0x00001000), + + // SIO_SPI_1_FS1 + _PAD_CFG_STRUCT(GPIO_113, 0x44000400, 0x00001000), + + // SIO_SPI_1_RXD + _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0001d000), + + // SIO_SPI_1_TXD + _PAD_CFG_STRUCT(GPIO_117, 0x44000400, 0x00001000), + + // SIO_SPI_2_CLK + _PAD_CFG_STRUCT(GPIO_118, 0x44000400, 0x00001000), + + // SIO_SPI_2_FS0 + _PAD_CFG_STRUCT(GPIO_119, 0x44000400, 0x00001000), + + // SIO_SPI_2_FS1 + _PAD_CFG_STRUCT(GPIO_120, 0x44000400, 0x00001000), + + // SIO_SPI_2_FS2 + _PAD_CFG_STRUCT(GPIO_121, 0x44000400, 0x00001000), + + // SIO_SPI_2_RXD + _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00001000), + + // SIO_SPI_2_TXD + _PAD_CFG_STRUCT(GPIO_123, 0x44000400, 0x00001000), + + + // ******************************* + // ******* GPIO Group West ******* + // ******************************* + // LPSS_I2C0_SDA + _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x00012700), + + // LPSS_I2C0_SCL + _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x00012700), + + // LPSS_I2C1_SDA + _PAD_CFG_STRUCT(GPIO_126, 0x44000402, 0x00012700), + + // LPSS_I2C1_SCL + _PAD_CFG_STRUCT(GPIO_127, 0x44000402, 0x00012700), + + // LPSS_I2C2_SDA + _PAD_CFG_STRUCT(GPIO_128, 0x44000402, 0x00012700), + + // LPSS_I2C2_SCL + _PAD_CFG_STRUCT(GPIO_129, 0x44000402, 0x00012700), + + // LPSS_I2C3_SDA + _PAD_CFG_STRUCT(GPIO_130, 0x44000402, 0x00012700), + + // LPSS_I2C3_SCL + _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x00012700), + + // LPSS_I2C4_SDA + _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x00012700), + + // LPSS_I2C4_SCL + _PAD_CFG_STRUCT(GPIO_133, 0x44000402, 0x00012700), + + // LPSS_I2C5_SDA + _PAD_CFG_STRUCT(GPIO_134, 0x44000402, 0x0001f200), + + // LPSS_I2C5_SCL + _PAD_CFG_STRUCT(GPIO_135, 0x44000402, 0x0001f200), + + // LPSS_I2C6_SDA + _PAD_CFG_STRUCT(GPIO_136, 0x44000402, 0x0001f200), + + // LPSS_I2C6_SCL + _PAD_CFG_STRUCT(GPIO_137, 0x44000402, 0x0001f200), + + // LPSS_I2C7_SDA + _PAD_CFG_STRUCT(GPIO_138, 0x44000402, 0x00006700), + + // LPSS_I2C7_SCL + _PAD_CFG_STRUCT(GPIO_139, 0x44000402, 0x00006700), + + // AVS_I2S6_BCLK + _PAD_CFG_STRUCT(GPIO_146, 0x44000800, 0x0003d000), + + // AVS_I2S6_WS_SYNC + _PAD_CFG_STRUCT(GPIO_147, 0x44000800, 0x0003d000), + + // AVS_I2S6_SDI + _PAD_CFG_STRUCT(GPIO_148, 0x44000802, 0x0003d000), + + // AVS_I2S6_SDO + _PAD_CFG_STRUCT(GPIO_149, 0x44000800, 0x0003d000), + + // AVS_I2S5_BCLK + _PAD_CFG_STRUCT(GPIO_150, 0x44000800, 0x0001d200), + + // AVS_I2S5_WS_SYNC + _PAD_CFG_STRUCT(GPIO_151, 0x44000800, 0x0001d200), + + // AVS_I2S5_SDI + _PAD_CFG_STRUCT(GPIO_152, 0x44000802, 0x0001d200), + + // AVS_I2S5_SDO + _PAD_CFG_STRUCT(GPIO_153, 0x44000800, 0x0001c200), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_154, 0x44000102, 0x00000000), + + // SPKR + _PAD_CFG_STRUCT(GPIO_155, 0x44000800, 0x0003d000), + + // *PCIE_CLKREQ0_N + _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x00001000), + + // *PCIE_CLKREQ1_N + _PAD_CFG_STRUCT(GPIO_210, 0x44000400, 0x00001000), + + // *PCIE_CLKREQ2_N + _PAD_CFG_STRUCT(GPIO_211, 0x44000400, 0x00001000), + + // *PCIE_CLKREQ3_N + _PAD_CFG_STRUCT(GPIO_212, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_0 + _PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_1 + _PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_2 + _PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_3 + _PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x44000400, 0x00001000), + + // GPIO + _PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMU_BATLOW_B, 0x44000102, 0x00000000), + + // *PMU_PLTRST_N + _PAD_CFG_STRUCT(PMU_PLTRST_B, 0x44000400, 0x0003c000), + + // *PMU_PWRBTN_N + _PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x44000402, 0x0003f000), + + // *PMU_RSTBTN_N + _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x44000402, 0x0003c000), + + // *PMU_SLP_S0_N + _PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x44000400, 0x0003c000), + + // *PMU_SLP_S3_N + _PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x44000400, 0x0003c000), + + // *PMU_SLP_S4_N + _PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x44000400, 0x0003c000), + + // *PMU_SUSCLK + _PAD_CFG_STRUCT(PMU_SUSCLK, 0x44000400, 0x0003c000), + + // *GPIO + _PAD_CFG_STRUCT(PMU_WAKE_B, 0x44000201, 0x0003f000), + + // *SUS_STAT_B + _PAD_CFG_STRUCT(SUS_STAT_B, 0x44000400, 0x0003c000), + + // GPIO + _PAD_CFG_STRUCT(SUSPWRDNACK, 0x44000102, 0x00000000), + + + // ************************************ + // ******* GPIO Group SouthWest ******* + // ************************************ + // PCIE_WAKE0_N + _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00000000), + + // PCIE_WAKE1_N + _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00000000), + + // PCIE_WAKE2_N + _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00000000), + + // PCIE_WAKE3_N + _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00000000), + + // *EMMC_CLK + _PAD_CFG_STRUCT(GPIO_156, 0x44000402, 0x00005000), + + // *EMMC_D0 + _PAD_CFG_STRUCT(GPIO_157, 0x44000402, 0x00023000), + + // *EMMC_D1 + _PAD_CFG_STRUCT(GPIO_158, 0x44000402, 0x00023000), + + // *EMMC_D2 + _PAD_CFG_STRUCT(GPIO_159, 0x44000402, 0x00023000), + + // *EMMC_D3 + _PAD_CFG_STRUCT(GPIO_160, 0x44000402, 0x00023000), + + // *EMMC_D4 + _PAD_CFG_STRUCT(GPIO_161, 0x44000402, 0x00023000), + + // *EMMC_D5 + _PAD_CFG_STRUCT(GPIO_162, 0x44000402, 0x00023000), + + // *EMMC_D6 + _PAD_CFG_STRUCT(GPIO_163, 0x44000402, 0x00023000), + + // *EMMC_D7 + _PAD_CFG_STRUCT(GPIO_164, 0x44000402, 0x00023000), + + // *EMMC_CMD + _PAD_CFG_STRUCT(GPIO_165, 0x44000402, 0x00023000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_166, 0x44000300, 0x00001000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_167, 0x44000102, 0x00023000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_168, 0x44000100, 0x00023000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_169, 0x44000200, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_170, 0x44000201, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_171, 0x44000201, 0x00003000), + + // SDCARD_CLK + _PAD_CFG_STRUCT(GPIO_172, 0x44000400, 0x00021100), + + // n/a + _PAD_CFG_STRUCT(GPIO_179, 0x44000400, 0x00001000), + + // SDCARD_D0 + _PAD_CFG_STRUCT(GPIO_173, 0x44000402, 0x00023100), + + // SDCARD_D1 + _PAD_CFG_STRUCT(GPIO_174, 0x44000402, 0x00023000), + + // SDCARD_D2 + _PAD_CFG_STRUCT(GPIO_175, 0x44000402, 0x00023000), + + // SDCARD_D3 + _PAD_CFG_STRUCT(GPIO_176, 0x44000402, 0x00023000), + + // SDCARD_CD_B + _PAD_CFG_STRUCT(GPIO_177, 0x44000402, 0x00003000), + + // SDCARD_CMD + _PAD_CFG_STRUCT(GPIO_178, 0x44000402, 0x00023100), + + // SDCARD_LVL_WP + _PAD_CFG_STRUCT(GPIO_186, 0x44000402, 0x00003000), + + // *EMMC_RCLK + _PAD_CFG_STRUCT(GPIO_182, 0x44000400, 0x0001d000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_183, 0x44000200, 0x00001000), + + // SMB_ALERT_N + _PAD_CFG_STRUCT(SMB_ALERTB, 0x44000402, 0x0003f000), + + // SMB_CLK + _PAD_CFG_STRUCT(SMB_CLK, 0x44000402, 0x0003f000), + + // SMB_DATA + _PAD_CFG_STRUCT(SMB_DATA, 0x44000402, 0x0003f000), + + // LPC_ILB_SERIRQ + _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x44000402, 0x0003f000), + + // LPC_CLKOUT0 + _PAD_CFG_STRUCT(LPC_CLKOUT0, 0x44000400, 0x00020100), + + // LPC_CLKOUT1 + _PAD_CFG_STRUCT(LPC_CLKOUT1, 0x44000400, 0x00020100), + + // LPC_AD0 + _PAD_CFG_STRUCT(LPC_AD0, 0x44000402, 0x00023100), + + // LPC_AD1 + _PAD_CFG_STRUCT(LPC_AD1, 0x44000402, 0x00023100), + + // LPC_AD2 + _PAD_CFG_STRUCT(LPC_AD2, 0x44000402, 0x00023100), + + // LPC_AD3 + _PAD_CFG_STRUCT(LPC_AD3, 0x44000402, 0x00023100), + + // LPC_CLKRUNB + _PAD_CFG_STRUCT(LPC_CLKRUNB, 0x44000400, 0x00023100), + + // LPC_FRAMEB + _PAD_CFG_STRUCT(LPC_FRAMEB, 0x44000400, 0x00023100), +}; + +#endif diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c new file mode 100644 index 00000000000..e9fcfb2da34 --- /dev/null +++ b/src/mainboard/up/squared/ramstage.c @@ -0,0 +1,432 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + + silconfig->C1e = 0x1; // 0x0 + silconfig->PkgCStateLimit = 0xFE; // 0x2 + silconfig->CStateAutoDemotion = 0x3; // 0x0 + silconfig->CStateUnDemotion = 0x3; // 0x0 + silconfig->PkgCStateDemotion = 0x1; // 0x0 + silconfig->PkgCStateUnDemotion = 0x1; // 0x0 + silconfig->IpuEn = 0x0; // 0x1 + silconfig->Pme = 0x1; // 0x0 + silconfig->HdAudioIoBufferOwnership = 0x3; // 0x0 + silconfig->DspEndpointDmic = 0x0; // 0x1 + silconfig->DspEndpointBluetooth = 0x0; // 0x1 + silconfig->DspEndpointI2sSkp = 0x1; // 0x0 + silconfig->DspEndpointI2sHp = 0x1; // 0x0 + silconfig->HDAudioPwrGate = 0x1; // 0x0 + silconfig->HDAudioClkGate = 0x1; // 0x0 + silconfig->DspFeatureMask = 0x2A; // 0x0 + silconfig->HpetBdfValid = 0x1; // 0x0 + silconfig->HpetDeviceNumber = 0xF; // 0x1f + silconfig->IoApicBdfValid = 0x1; // 0x0 + silconfig->IoApicDeviceNumber = 0x1F; // 0xf + silconfig->IshEnable = 0x0; // 0x1 + silconfig->SpiEiss = 0x0; // 0x1 + silconfig->LPSS_S0ixEnable = 0x1; // 0x0 + silconfig->SdcardEnabled = 0x0; // 0x1 + silconfig->eMMCHostMaxSpeed = 0x2; // 0x0 + silconfig->Usb30Mode = 0x1; // 0x0 + silconfig->VtdEnable = 0x1; // 0x0 + silconfig->MonitorMwaitEnable = 0x0; // 0x1 + silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0 + silconfig->InitS3Cpu = 0x1; // 0x0 + + silconfig->PortUsb20PerPortTxPeHalf[0] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[0] = 0x7; + silconfig->PortUsb20PerPortTxiSet[0] = 0x0; + silconfig->PortUsb20HsSkewSel[0] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[0] = 0x3; + silconfig->PortUsb20PerPortRXISet[0] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[0] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[1] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[1] = 0x6; + silconfig->PortUsb20PerPortTxiSet[1] = 0x0; + silconfig->PortUsb20HsSkewSel[1] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[1] = 0x3; + silconfig->PortUsb20PerPortRXISet[1] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[1] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[2] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[2] = 0x6; + silconfig->PortUsb20PerPortTxiSet[2] = 0x0; + silconfig->PortUsb20HsSkewSel[2] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[2] = 0x3; + silconfig->PortUsb20PerPortRXISet[2] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[2] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[3] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[3] = 0x6; + silconfig->PortUsb20PerPortTxiSet[3] = 0x0; + silconfig->PortUsb20HsSkewSel[3] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[3] = 0x3; + silconfig->PortUsb20PerPortRXISet[3] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[3] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[4] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[4] = 0x7; + silconfig->PortUsb20PerPortTxiSet[4] = 0x0; + silconfig->PortUsb20HsSkewSel[4] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[4] = 0x3; + silconfig->PortUsb20PerPortRXISet[4] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[4] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[5] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[5] = 0x7; + silconfig->PortUsb20PerPortTxiSet[5] = 0x0; + silconfig->PortUsb20HsSkewSel[5] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[5] = 0x3; + silconfig->PortUsb20PerPortRXISet[5] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[5] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[6] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[6] = 0x7; + silconfig->PortUsb20PerPortTxiSet[6] = 0x0; + silconfig->PortUsb20HsSkewSel[6] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[6] = 0x3; + silconfig->PortUsb20PerPortRXISet[6] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[6] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[7] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[7] = 0x1; + silconfig->PortUsb20PerPortTxiSet[7] = 0x3; + silconfig->PortUsb20HsSkewSel[7] = 0x1; + silconfig->PortUsb20IUsbTxEmphasisEn[7] = 0x1; + silconfig->PortUsb20PerPortRXISet[7] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[7] = 0x3; + + + silconfig->WriteProtectionEnable[0] = 0x1; + silconfig->ReadProtectionEnable[0] = 0x1; + silconfig->ProtectedRangeLimit[0] = 0xFFF; + silconfig->ProtectedRangeBase[0] = 0x0; + + silconfig->IPC[0] = 0xFFFFEEF8; + silconfig->IPC[1] = 0xFFFFFFFF; + silconfig->IPC[2] = 0xFFFFFFFF; + silconfig->IPC[3] = 0xFFFFFFFF; + + silconfig->SataPortsDisableDynamicPg[0] = 0x0; + silconfig->SataPortsEnable[0] = 0x1; + silconfig->SataPortsDevSlp[0] = 0x0; + silconfig->SataPortsHotPlug[0] = 0x0; + silconfig->SataPortsInterlockSw[0] = 0x1; + silconfig->SataPortsExternal[0] = 0x0; + silconfig->SataPortsSpinUp[0] = 0x0; + silconfig->SataPortsSolidStateDrive[0] = 0x0; + silconfig->SataPortsEnableDitoConfig[0] = 0x0; + silconfig->SataPortsDmVal[0] = 0xF; + silconfig->SataPortsDitoVal[0] = 0x271; + + silconfig->SataPortsDisableDynamicPg[1] = 0x0; + silconfig->SataPortsEnable[1] = 0x1; + silconfig->SataPortsDevSlp[1] = 0x0; + silconfig->SataPortsHotPlug[1] = 0x0; + silconfig->SataPortsInterlockSw[1] = 0x1; + silconfig->SataPortsExternal[1] = 0x0; + silconfig->SataPortsSpinUp[1] = 0x0; + silconfig->SataPortsSolidStateDrive[1] = 0x0; + silconfig->SataPortsEnableDitoConfig[1] = 0x0; + silconfig->SataPortsDmVal[1] = 0xF; + silconfig->SataPortsDitoVal[1] = 0x271; + + + silconfig->PcieRootPortEn[0] = 0x1; + silconfig->PcieRpHide[0] = 0x0; + silconfig->PcieRpSlotImplemented[0] = 0x1; + silconfig->PcieRpHotPlug[0] = 0x0; + silconfig->PcieRpPmSci[0] = 0x1; + silconfig->PcieRpExtSync[0] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[0] = 0x0; + silconfig->PcieRpAcsEnabled[0] = 0x1; + silconfig->PcieRpClkReqSupported[0] = 0x1; + silconfig->PcieRpClkReqNumber[0] = 0x2; + silconfig->PcieRpClkReqDetect[0] = 0x0; + silconfig->AdvancedErrorReporting[0] = 0x0; + silconfig->PmeInterrupt[0] = 0x0; + silconfig->UnsupportedRequestReport[0] = 0x0; + silconfig->FatalErrorReport[0] = 0x0; + silconfig->NoFatalErrorReport[0] = 0x0; + silconfig->CorrectableErrorReport[0] = 0x0; + silconfig->SystemErrorOnFatalError[0] = 0x0; + silconfig->SystemErrorOnNonFatalError[0] = 0x0; + silconfig->SystemErrorOnCorrectableError[0] = 0x0; + silconfig->PcieRpSpeed[0] = 0x0; + silconfig->PhysicalSlotNumber[0] = 0x0; + silconfig->PcieRpCompletionTimeout[0] = 0x0; + silconfig->PtmEnable[0] = 0x0; + silconfig->PcieRpAspm[0] = 0x4; + silconfig->PcieRpL1Substates[0] = 0x3; + silconfig->PcieRpLtrEnable[0] = 0x1; + silconfig->PcieRpLtrConfigLock[0] = 0x0; + silconfig->PcieRpSelectableDeemphasis[0] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[0] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[0] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[0] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[0] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[0] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[0] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[0] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[0] = 0x2; + + silconfig->PcieRootPortEn[1] = 0x1; + silconfig->PcieRpHide[1] = 0x0; + silconfig->PcieRpSlotImplemented[1] = 0x1; + silconfig->PcieRpHotPlug[1] = 0x0; + silconfig->PcieRpPmSci[1] = 0x1; + silconfig->PcieRpExtSync[1] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[1] = 0x0; + silconfig->PcieRpAcsEnabled[1] = 0x1; + silconfig->PcieRpClkReqSupported[1] = 0x1; + silconfig->PcieRpClkReqNumber[1] = 0x3; + silconfig->PcieRpClkReqDetect[1] = 0x0; + silconfig->AdvancedErrorReporting[1] = 0x0; + silconfig->PmeInterrupt[1] = 0x0; + silconfig->UnsupportedRequestReport[1] = 0x0; + silconfig->FatalErrorReport[1] = 0x0; + silconfig->NoFatalErrorReport[1] = 0x0; + silconfig->CorrectableErrorReport[1] = 0x0; + silconfig->SystemErrorOnFatalError[1] = 0x0; + silconfig->SystemErrorOnNonFatalError[1] = 0x0; + silconfig->SystemErrorOnCorrectableError[1] = 0x0; + silconfig->PcieRpSpeed[1] = 0x0; + silconfig->PhysicalSlotNumber[1] = 0x1; + silconfig->PcieRpCompletionTimeout[1] = 0x0; + silconfig->PtmEnable[1] = 0x0; + silconfig->PcieRpAspm[1] = 0x4; + silconfig->PcieRpL1Substates[1] = 0x3; + silconfig->PcieRpLtrEnable[1] = 0x1; + silconfig->PcieRpLtrConfigLock[1] = 0x0; + silconfig->PcieRpSelectableDeemphasis[1] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[1] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[1] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[1] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[1] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[1] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[1] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[1] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[1] = 0x2; + + silconfig->PcieRootPortEn[2] = 0x1; + silconfig->PcieRpHide[2] = 0x0; + silconfig->PcieRpSlotImplemented[2] = 0x1; + silconfig->PcieRpHotPlug[2] = 0x0; + silconfig->PcieRpPmSci[2] = 0x1; + silconfig->PcieRpExtSync[2] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[2] = 0x0; + silconfig->PcieRpAcsEnabled[2] = 0x1; + silconfig->PcieRpClkReqSupported[2] = 0x1; + silconfig->PcieRpClkReqNumber[2] = 0x0; + silconfig->PcieRpClkReqDetect[2] = 0x0; + silconfig->AdvancedErrorReporting[2] = 0x0; + silconfig->PmeInterrupt[2] = 0x0; + silconfig->UnsupportedRequestReport[2] = 0x0; + silconfig->FatalErrorReport[2] = 0x0; + silconfig->NoFatalErrorReport[2] = 0x0; + silconfig->CorrectableErrorReport[2] = 0x0; + silconfig->SystemErrorOnFatalError[2] = 0x0; + silconfig->SystemErrorOnNonFatalError[2] = 0x0; + silconfig->SystemErrorOnCorrectableError[2] = 0x0; + silconfig->PcieRpSpeed[2] = 0x0; + silconfig->PhysicalSlotNumber[2] = 0x2; + silconfig->PcieRpCompletionTimeout[2] = 0x0; + silconfig->PtmEnable[2] = 0x0; + silconfig->PcieRpAspm[2] = 0x4; + silconfig->PcieRpL1Substates[2] = 0x3; + silconfig->PcieRpLtrEnable[2] = 0x1; + silconfig->PcieRpLtrConfigLock[2] = 0x0; + silconfig->PcieRpSelectableDeemphasis[2] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[2] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[2] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[2] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[2] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[2] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[2] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[2] = 0x0; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[2] = 0x2; + + silconfig->PcieRootPortEn[3] = 0x1; + silconfig->PcieRpHide[3] = 0x0; + silconfig->PcieRpSlotImplemented[3] = 0x1; + silconfig->PcieRpHotPlug[3] = 0x0; + silconfig->PcieRpPmSci[3] = 0x1; + silconfig->PcieRpExtSync[3] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[3] = 0x0; + silconfig->PcieRpAcsEnabled[3] = 0x1; + silconfig->PcieRpClkReqSupported[3] = 0x1; + silconfig->PcieRpClkReqNumber[3] = 0x1; + silconfig->PcieRpClkReqDetect[3] = 0x0; + silconfig->AdvancedErrorReporting[3] = 0x0; + silconfig->PmeInterrupt[3] = 0x0; + silconfig->UnsupportedRequestReport[3] = 0x0; + silconfig->FatalErrorReport[3] = 0x0; + silconfig->NoFatalErrorReport[3] = 0x0; + silconfig->CorrectableErrorReport[3] = 0x0; + silconfig->SystemErrorOnFatalError[3] = 0x0; + silconfig->SystemErrorOnNonFatalError[3] = 0x0; + silconfig->SystemErrorOnCorrectableError[3] = 0x0; + silconfig->PcieRpSpeed[3] = 0x0; + silconfig->PhysicalSlotNumber[3] = 0x3; + silconfig->PcieRpCompletionTimeout[3] = 0x0; + silconfig->PtmEnable[3] = 0x0; + silconfig->PcieRpAspm[3] = 0x4; + silconfig->PcieRpL1Substates[3] = 0x3; + silconfig->PcieRpLtrEnable[3] = 0x1; + silconfig->PcieRpLtrConfigLock[3] = 0x0; + silconfig->PcieRpSelectableDeemphasis[3] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[3] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[3] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[3] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[3] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[3] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[3] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[3] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[3] = 0x2; + + silconfig->PcieRootPortEn[4] = 0x1; + silconfig->PcieRpHide[4] = 0x0; + silconfig->PcieRpSlotImplemented[4] = 0x1; + silconfig->PcieRpHotPlug[4] = 0x0; + silconfig->PcieRpPmSci[4] = 0x1; + silconfig->PcieRpExtSync[4] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[4] = 0x0; + silconfig->PcieRpAcsEnabled[4] = 0x1; + silconfig->PcieRpClkReqSupported[4] = 0x1; + silconfig->PcieRpClkReqNumber[4] = 0x2; + silconfig->PcieRpClkReqDetect[4] = 0x0; + silconfig->AdvancedErrorReporting[4] = 0x0; + silconfig->PmeInterrupt[4] = 0x0; + silconfig->UnsupportedRequestReport[4] = 0x0; + silconfig->FatalErrorReport[4] = 0x0; + silconfig->NoFatalErrorReport[4] = 0x0; + silconfig->CorrectableErrorReport[4] = 0x0; + silconfig->SystemErrorOnFatalError[4] = 0x0; + silconfig->SystemErrorOnNonFatalError[4] = 0x0; + silconfig->SystemErrorOnCorrectableError[4] = 0x0; + silconfig->PcieRpSpeed[4] = 0x0; + silconfig->PhysicalSlotNumber[4] = 0x4; + silconfig->PcieRpCompletionTimeout[4] = 0x0; + silconfig->PtmEnable[4] = 0x0; + silconfig->PcieRpAspm[4] = 0x4; + silconfig->PcieRpL1Substates[4] = 0x3; + silconfig->PcieRpLtrEnable[4] = 0x1; + silconfig->PcieRpLtrConfigLock[4] = 0x0; + silconfig->PcieRpSelectableDeemphasis[4] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[4] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[4] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[4] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[4] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[4] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[4] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[4] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[4] = 0x2; + + silconfig->PcieRootPortEn[5] = 0x1; + silconfig->PcieRpHide[5] = 0x0; + silconfig->PcieRpSlotImplemented[5] = 0x1; + silconfig->PcieRpHotPlug[5] = 0x0; + silconfig->PcieRpPmSci[5] = 0x1; + silconfig->PcieRpExtSync[5] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; + silconfig->PcieRpAcsEnabled[5] = 0x1; + silconfig->PcieRpClkReqSupported[5] = 0x1; + silconfig->PcieRpClkReqNumber[5] = 0x3; + silconfig->PcieRpClkReqDetect[5] = 0x0; + silconfig->AdvancedErrorReporting[5] = 0x0; + silconfig->PmeInterrupt[5] = 0x0; + silconfig->UnsupportedRequestReport[5] = 0x0; + silconfig->FatalErrorReport[5] = 0x0; + silconfig->NoFatalErrorReport[5] = 0x0; + silconfig->CorrectableErrorReport[5] = 0x0; + silconfig->SystemErrorOnFatalError[5] = 0x0; + silconfig->SystemErrorOnNonFatalError[5] = 0x0; + silconfig->SystemErrorOnCorrectableError[5] = 0x0; + silconfig->PcieRpSpeed[5] = 0x0; + silconfig->PhysicalSlotNumber[5] = 0x5; + silconfig->PcieRpCompletionTimeout[5] = 0x0; + silconfig->PtmEnable[5] = 0x0; + silconfig->PcieRpAspm[5] = 0x4; + silconfig->PcieRpL1Substates[5] = 0x3; + silconfig->PcieRpLtrEnable[5] = 0x1; + silconfig->PcieRpLtrConfigLock[5] = 0x0; + silconfig->PcieRpSelectableDeemphasis[5] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[5] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[5] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[5] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[5] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[5] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[5] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[5] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[5] = 0x2; + + + silconfig->SsicRate[0] = 0x1; + silconfig->SsicPortEnable[0] = 0x0; + silconfig->SsicRate[1] = 0x1; + silconfig->SsicPortEnable[1] = 0x0; + + silconfig->PortUsb30Enable[0] = 0x1; + silconfig->PortUs30bOverCurrentPin[0] = 0x0; + silconfig->PortUsb30Enable[1] = 0x1; + silconfig->PortUs30bOverCurrentPin[1] = 0x1; + silconfig->PortUsb30Enable[2] = 0x1; + silconfig->PortUs30bOverCurrentPin[2] = 0x1; + silconfig->PortUsb30Enable[3] = 0x1; + silconfig->PortUs30bOverCurrentPin[3] = 0x1; + silconfig->PortUsb30Enable[4] = 0x1; + silconfig->PortUs30bOverCurrentPin[4] = 0x1; + silconfig->PortUsb30Enable[5] = 0x1; + silconfig->PortUs30bOverCurrentPin[5] = 0x1; + + silconfig->PortUsb20Enable[0] = 0x1; + silconfig->PortUs20bOverCurrentPin[0] = 0x0; + silconfig->PortUsb20Enable[1] = 0x1; + silconfig->PortUs20bOverCurrentPin[1] = 0x1; + silconfig->PortUsb20Enable[2] = 0x1; + silconfig->PortUs20bOverCurrentPin[2] = 0x1; + silconfig->PortUsb20Enable[3] = 0x1; + silconfig->PortUs20bOverCurrentPin[3] = 0x1; + silconfig->PortUsb20Enable[4] = 0x1; + silconfig->PortUs20bOverCurrentPin[4] = 0x1; + silconfig->PortUsb20Enable[5] = 0x1; + silconfig->PortUs20bOverCurrentPin[5] = 0x1; + silconfig->PortUsb20Enable[6] = 0x1; + silconfig->PortUs20bOverCurrentPin[6] = 0x2; + silconfig->PortUsb20Enable[7] = 0x1; + silconfig->PortUs20bOverCurrentPin[7] = 0x2; +} diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c new file mode 100644 index 00000000000..2cfaa0064aa --- /dev/null +++ b/src/mainboard/up/squared/romstage.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "gpio.h" + +static const uint8_t ch0_bit_swizzling[] = { + 0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09, + 0x06, 0x00, 0x03, 0x04, 0x07, 0x01, 0x05, 0x02, + 0x1C, 0x1A, 0x19, 0x1B, 0x1D, 0x1F, 0x1E, 0x18, + 0x10, 0x17, 0x15, 0x16, 0x14, 0x12, 0x13, 0x11 +}; + +static const uint8_t ch1_bit_swizzling[] = { + 0x00, 0x07, 0x04, 0x05, 0x06, 0x02, 0x03, 0x01, + 0x08, 0x0F, 0x0D, 0x0B, 0x0A, 0x09, 0x0E, 0x0C, + 0x17, 0x11, 0x13, 0x12, 0x14, 0x15, 0x16, 0x10, + 0x1C, 0x1A, 0x1D, 0x1F, 0x18, 0x19, 0x1E, 0x1B +}; + +static const uint8_t ch2_bit_swizzling[] = { + 0x0D, 0x08, 0x0B, 0x0E, 0x0C, 0x0F, 0x09, 0x0A, + 0x04, 0x07, 0x01, 0x06, 0x02, 0x03, 0x00, 0x05, + 0x18, 0x19, 0x1C, 0x1A, 0x1D, 0x1E, 0x1F, 0x1B, + 0x11, 0x13, 0x15, 0x10, 0x16, 0x12, 0x17, 0x14 +}; + +static const uint8_t ch3_bit_swizzling[] = { + 0x00, 0x05, 0x04, 0x07, 0x03, 0x02, 0x06, 0x01, + 0x0A, 0x0B, 0x08, 0x09, 0x0C, 0x0E, 0x0D, 0x0F, + 0x12, 0x16, 0x14, 0x13, 0x17, 0x11, 0x15, 0x10, + 0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A +}; + + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + memupd->FspmConfig.Package = 0x1; // 0x0 + memupd->FspmConfig.Profile = 0xB; // 0x19 + memupd->FspmConfig.MemoryDown = 0x1; // 0x0 + memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1 + memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0 + memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4 + memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0 + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 + memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1 + memupd->FspmConfig.NpkEn = 0x0; // 0x3 + memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0 + + memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch0_Option = 0x3; // 0x0 + memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch1_Option = 0x3; // 0x0 + memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch2_Option = 0x3; // 0x0 + memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch3_Option = 0x3; // 0x0 + memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling, + sizeof(ch0_bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling, + sizeof(ch1_bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling, + sizeof(ch2_bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling, + sizeof(ch3_bit_swizzling)); +} diff --git a/src/mainboard/up/squared/upsquared.fmd b/src/mainboard/up/squared/upsquared.fmd new file mode 100644 index 00000000000..4ea1375e108 --- /dev/null +++ b/src/mainboard/up/squared/upsquared.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + IFWI@0x0 0x2ff000 + OBB@0x2ff000 0xbff000 { + FMAP@0x0 0x800 + UNIFIED_MRC_CACHE@0x800 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + CONSOLE@0x21800 0x20000 + COREBOOT(CBFS)@0x41800 0xb7d800 + BIOS_UNUSABLE@0xbbf000 0x40000 + } + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd new file mode 100644 index 00000000000..72f92fe964d --- /dev/null +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -0,0 +1,35 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + WP_RO@0x0 0xe91000 { + IFWI@0x0 0x2ff000 + FMAP@0x2ff000 0x800 + RO_VPD(PRESERVE)@0x2ff800 0x4000 + RO_SECTION@0x303800 0xb8d800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0xb4d000 + } + } + MISC_RW@0xe91000 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + BIOS_UNUSABLE@0xebe000 0x40000 + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd new file mode 100644 index 00000000000..330ce037576 --- /dev/null +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + WP_RO@0x0 0x502000 { + IFWI@0x0 0x2ff000 + FMAP@0x2ff000 0x800 + RO_VPD(PRESERVE)@0x2ff800 0x4000 + RO_SECTION@0x303800 0x1fe800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x1be000 + } + } + MISC_RW@0x502000 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + RW_SECTION_A@0x52f000 0x98f000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x97efc0 + RW_FWID_A@0x98efc0 0x40 + } + BIOS_UNUSABLE@0xebe000 0x40000 + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd new file mode 100644 index 00000000000..4ddcbc0c2ec --- /dev/null +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -0,0 +1,45 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + WP_RO@0x0 0x503000 { + IFWI@0x0 0x2ff000 + FMAP@0x2ff000 0x800 + RO_VPD(PRESERVE)@0x2ff800 0x4000 + RO_SECTION@0x303800 0x1ff800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x1bf000 + } + } + MISC_RW@0x503000 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + RW_SECTION_A@0x530000 0x4c7000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x4b6fc0 + RW_FWID_A@0x4c6fc0 0x40 + } + RW_SECTION_B@0x9f7000 0x4c7000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x4b6fc0 + RW_FWID_B@0x4c6fc0 0x40 + } + BIOS_UNUSABLE@0xebe000 0x40000 + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index d29656cd22e..df55efa7494 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -15,17 +15,16 @@ #include #include - #include #include #include +#include #include #include #include #include #include #include - #include void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 93625fce124..7d9fe9c5efe 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -23,8 +23,6 @@ #define HAS_LEGACY_WRAPPER CONFIG(BINARYPI_LEGACY_WRAPPER) /* eventlog */ -const char *agesa_struct_name(int state); -const char *heap_status_name(int status); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); @@ -55,6 +53,19 @@ void board_BeforeAgesa(struct sysinfo *cb); void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); + +struct agesa_state { + u8 apic_id; + + AGESA_STRUCT_NAME func; + const char *function_name; + uint32_t ts_entry_id; + uint32_t ts_exit_id; +}; + +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader); int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func); /* AGESA dispatchers */ diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index 871a4366c27..384772374be 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index bbaec538871..b0a1ab679a5 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1d071c18772..a681961be2f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -34,6 +34,7 @@ #include #include #include +#include #if CONFIG(LOGICAL_CPUS) #include diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 8c33ad81569..cda0a28cef8 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -36,6 +36,7 @@ #include #include #include +#include /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index f4a782d63bc..c007089e03e 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -19,8 +19,8 @@ #include #include -#include #include + #include "comlib.h" #include "h3finit.h" #include "h3ffeat.h" diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index d9563152267..60a2c66de3f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -34,8 +34,10 @@ */ #include +#include #include #include + #include "mct_d.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, @@ -521,7 +523,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, { u8 Node; u32 NextBase, BottomIO; - u8 _MemHoleRemap, DramHoleBase, DramHoleOffset; + u8 _MemHoleRemap, DramHoleBase; u32 HoleSize, DramSelBaseAddr; u32 val; @@ -581,7 +583,6 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO)) base = DramSelBaseAddr; val = ((base + HoleSize) >> (24-8)) & 0xFF; - DramHoleOffset = val; val <<= 8; /* shl 16, rol 24 */ val |= DramHoleBase << 24; val |= 1 << DramHoleValid; @@ -970,7 +971,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, u8 Twr, Trtp; u8 Trp, Trrd, Trcd, Tras, Trc, Trfc[4], Rows; u32 DramTimingLo, DramTimingHi; - u16 Tk10, Tk40; + u16 Tk40; u8 Twtr; u8 LDIMM; u8 DDR2_1066; @@ -1093,7 +1094,6 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, if (byte == 5) DDR2_1066 = 1; Tk40 = Get_40Tk_D(byte); - Tk10 = Tk40 >> 2; /* Notes: 1. All secondary time values given in SPDs are in binary with units of ns. @@ -1738,7 +1738,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, * and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3). */ - u8 ChipSel, Rows, Cols, Ranks, Banks, DevWidth; + u8 ChipSel, Rows, Cols, Ranks, Banks; u32 BankAddrReg, csMask; u32 val; @@ -1771,7 +1771,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, Banks = mctRead_SPD(smbaddr, SPD_LBANKS); byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH); - DevWidth = byte & 0x7f; /* bits 0-6 = bank 0 width */ byte = mctRead_SPD(smbaddr, SPD_DMBANKS); Ranks = (byte & 7) + 1; @@ -1931,7 +1930,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, u8 b = 0; u32 nxtcsBase, curcsBase; u8 p, q; - u32 Sizeq, BiggestBank; + u32 BiggestBank; u8 _DSpareEn; u16 word; @@ -1987,7 +1986,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, val >>= 19; val++; val <<= 19; - Sizeq = val; //never used if (val > BiggestBank) { /*Bingo! possibly Map this chip-select next! */ BiggestBank = val; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 5d31d444280..14da928719b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -23,11 +23,11 @@ #define DQS_TRAIN_DEBUG 0 #include -#include "mct_d_gcc.h" -#include #include #include +#include "mct_d_gcc.h" + extern const u8 Table_DQSRcvEn_Offset[]; extern const u32 TestPattern0_D[]; extern const u32 TestPattern1_D[]; diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 75fc8a427e1..36ee3ab3324 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,9 +13,11 @@ * GNU General Public License for more details. */ +#include #include #include #include + #include "mct_d.h" static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, @@ -1190,8 +1192,6 @@ void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr) { - u32 value; - /* BIOS issues the remaining (Ntrain - 2) reads after checking that * F2x11C[PrefDramTrainMode] is cleared. These reads must be to * consecutive cache lines (i.e., 64 bytes apart) and must not cross @@ -1203,5 +1203,5 @@ void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, SetUpperFSbase(addr); /* 1st move causes read fill (to exclusive or shared)*/ - value = read32_fs(addr << 8); + read32_fs(addr << 8); } diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 7be63533a95..8eb7bf54b75 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -80,7 +80,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u16 OB_ECCRedir; u32 LDramECC; u32 OF_ScrubCTL; - u16 OB_ChipKill; u8 MemClrECC; u32 dev; @@ -96,7 +95,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ + mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ nvbits = mctGet_NVbits(NV_DCBKScrub); diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 0acb6f4ff49..83937330f84 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -280,7 +280,6 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) u32 Speed; u32 ch, ch_start, ch_end; u32 index_reg; - u32 index; u32 dev; u32 val; @@ -297,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) ch_end = dct+1; } dev = pDCTstat->dev_dct; - index = 0x0D00E001; + for (ch = ch_start; ch < ch_end; ch++) { index_reg = 0x98 + 0x100 * ch; val = Get_NB32_index(dev, index_reg, 0x0D00E001); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 4689c7b982f..649c1c85c24 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,8 +14,10 @@ * GNU General Public License for more details. */ +#include #include #include + #include "mct_d.h" /****************************************************************************** diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 192288a2c4a..a78d42df85e 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include + #include "mct_d.h" /* diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 9178c782d49..5be456695eb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -43,7 +43,9 @@ #include #include #include +#include #include + #include "s3utils.h" #include "mct_d_gcc.h" #include "mct_d.h" @@ -3808,7 +3810,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, { u8 Node; u32 NextBase, BottomIO; - u8 _MemHoleRemap, DramHoleBase, DramHoleOffset; + u8 _MemHoleRemap, DramHoleBase; u32 HoleSize, DramSelBaseAddr; u32 val; @@ -3867,7 +3869,6 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO)) base = DramSelBaseAddr; val = ((base + HoleSize) >> (24-8)) & 0xFF; - DramHoleOffset = val; val <<= 8; /* shl 16, rol 24 */ val |= DramHoleBase << 24; val |= 1 << DramHoleValid; @@ -5164,9 +5165,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, /* Special Jedec SPD diagnostic bit - "enable all clocks" */ if (!(pDCTstat->Status & (1<>= 19; val++; val <<= 19; - Sizeq = val; /* never used */ if (val > BiggestBank) { /*Bingo! possibly Map this chip-select next! */ BiggestBank = val; @@ -6983,7 +6981,6 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat, u32 index_reg = 0x98; u8 cs; u8 odt; - u8 max_dimms; dev = pDCTstat->dev_dct; @@ -6993,7 +6990,6 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat, /* FIXME: skip for Ax */ /* Tri-state unused ODTs when motherboard termination is available */ - max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS); odt = 0x0f; /* ODT tri-state setting */ if (pDCTstat->Status & (1 < #include #include +#include + #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 7aaf016d294..b8042fe46da 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "mcti.h" diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2b94daa1276..309a762840b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #if CONFIG(BINARYPI_LEGACY_WRAPPER) @@ -464,11 +463,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device, acpi_header_t *ssdt; acpi_header_t *alib; acpi_header_t *ivrs; - acpi_hest_t *hest; /* HEST */ current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; @@ -681,7 +678,6 @@ static void domain_set_resources(struct device *dev) struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -712,7 +708,6 @@ static void domain_set_resources(struct device *dev) // Use hole_basek as mmio_basek, and we don't need to reset hole anymore if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df7259fca..41641ee65f4 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -678,7 +678,6 @@ static void domain_set_resources(struct device *dev) struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -708,7 +707,6 @@ static void domain_set_resources(struct device *dev) /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 926208c4d5d..2ca9d4efbd5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -684,11 +684,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device, acpi_header_t *ssdt; acpi_header_t *alib; acpi_ivrs_t *ivrs; - acpi_hest_t *hest; /* HEST */ current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; @@ -910,7 +908,6 @@ static void domain_set_resources(struct device *dev) struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -941,7 +938,6 @@ static void domain_set_resources(struct device *dev) // Use hole_basek as mmio_basek, and we don't need to reset hole anymore if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index cda5e019803..1563216ba14 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 9f919cfbcd0..b5aa8044bef 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -15,9 +15,9 @@ */ #include -#include +#include #include -#include + #include "gm45.h" void gm45_early_reset(void/*const timings_t *const timings*/) @@ -63,8 +63,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Normally, we would set this after successful raminit. */ MCHBAR32(DCC_MCHBAR) |= (1 << 19); - /* Perform system reset through CF9 interface. */ - outb(0x02, 0xcf9); /* Set system reset bit. */ - outb(0x06, 0xcf9); /* Set CPU reset bit, too. */ - halt(); + system_reset(); } diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3549b492343..a2de7f0fb06 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "drivers/intel/gma/i915_reg.h" #include "chip.h" diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 15d3c3a344d..38f2d5f68f1 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 082f2d63d98..e1067c59494 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -22,16 +22,30 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL -config VBOOT - select VBOOT_OPROM_MATTERS - select VBOOT_STARTS_IN_ROMSTAGE +config HASWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Haswell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Haswell however uses a mrc.bin to initialize memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/haswell/bootblock.c" +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK config VGA_BIOS_ID string @@ -63,6 +77,13 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a System Agent binary" help @@ -88,4 +109,11 @@ config PRE_GRAPHICS_DELAY VBIOS. On those systems we need to wait for a bit before executing the VBIOS. +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + endif diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 055c2a8a0d6..7abbccacd2b 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -26,7 +28,6 @@ romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c -romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index e503e01fa15..2c1bd58dde2 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -12,11 +12,10 @@ */ #include +#include +#include "haswell.h" -/* Just re-define this instead of including haswell.h. It blows up romcc. */ -#define PCIEXBAR 0x60 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; @@ -33,7 +32,7 @@ static void bootblock_northbridge_init(void) * 4GiB. */ reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); } diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 1b2430f8498..ca446e25a7c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "chip.h" #include "haswell.h" @@ -235,14 +236,6 @@ static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); - - /* In the native graphics case, we've got about 20 ms. - * after we power up the AUX channel until we can talk to it. - * So get that going right now. We can't turn on the panel, yet, just VDD. - */ - if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { - gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); - } } static void gma_pm_init_pre_vbios(struct device *dev) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index faaa9d04126..9beb23cc8ed 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -15,11 +15,10 @@ #include #include -#include #include #include #include -#include +#include #include #include #include @@ -136,8 +135,7 @@ void sdram_initialize(struct pei_data *pei_data) post_code(POST_RESUME_FAILURE); printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Pass console handler in pei_data */ @@ -168,7 +166,8 @@ void sdram_initialize(struct pei_data *pei_data) default: printk(BIOS_ERR, "MRC returned %x.\n", rv); } - die("Nonzero MRC return value.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Nonzero MRC return value.\n"); } } else { die("UEFI PEI System Agent not found.\n"); @@ -187,7 +186,7 @@ void sdram_initialize(struct pei_data *pei_data) void setup_sdram_meminfo(struct pei_data *pei_data) { - u32 addr_decoder_common, addr_decode_ch[2]; + u32 addr_decode_ch[2]; struct memory_info* mem_info; struct dimm_info *dimm; int ddr_frequency; @@ -200,7 +199,8 @@ void setup_sdram_meminfo(struct pei_data *pei_data) die("Failed to add memory info to CBMEM.\n"); memset(mem_info, 0, sizeof(struct memory_info)); - addr_decoder_common = MCHBAR32(0x5000); + /* FIXME: Do we need to read MCHBAR32(0x5000) ? */ + MCHBAR32(0x5000); addr_decode_ch[0] = MCHBAR32(0x5004); addr_decode_ch[1] = MCHBAR32(0x5008); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 0c92c4bd7de..f9167dfc97b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -13,18 +13,19 @@ * GNU General Public License for more details. */ -#include #include +#include #include #include #include #include #include -#include #include -#include "i945.h" #include #include +#include + +#include "i945.h" int i945_silicon_revision(void) { @@ -158,10 +159,10 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static southbridge registers..."); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN); setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); @@ -518,8 +519,7 @@ static void i945_setup_dmi_rcrb(void) reg32 &= ~(7 << 0); reg32 |= (3 << 0); DMIBAR32(0x224) = reg32; - outb(0x06, 0xcf9); - halt(); /* wait for reset */ + system_reset(); } } } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9c4f410d027..54ff47cc646 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "i945.h" #include "chip.h" @@ -858,6 +859,7 @@ static const unsigned short i945_gma_func0_ids[] = { }; static const unsigned short i945_gma_func1_ids[] = { + 0x2776, /* Desktop 82945G/GZ/GC */ 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */ 0 }; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index be3d17a2fd9..797ea1229d2 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -18,14 +18,13 @@ #include #include #include -#include +#include #include #include #include #include #include #include -#include #include "raminit.h" #include "i945.h" #include "chip.h" @@ -247,13 +246,13 @@ static void sdram_detect_errors(struct sys_info *sysinfo) u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -261,27 +260,25 @@ static void sdram_detect_errors(struct sys_info *sysinfo) if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); - outb(0x00, 0xcf9); - outb(0x0e, 0xcf9); - halt(); /* Wait for reset! */ + full_reset(); } } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG(CHECK_SLFRCS_ON_RESUME) @@ -303,9 +300,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); - outb(0x00, 0xcf9); - outb(0x0e, 0xcf9); - halt(); /* Wait for reset! */ + full_reset(); } } @@ -1811,9 +1806,9 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2549,29 +2544,19 @@ static void sdram_jedec_enable(struct sys_info *sysinfo) u32 bankaddr = 0, tmpaddr, mrsaddr = 0; for (i = 0, nonzero = -1; i < 8; i++) { - if (sysinfo->banksize[i] == 0) + if (sysinfo->banksize[i] == 0) continue; printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i); - switch (i) { - case 0: - /* Start at address 0 */ - bankaddr = 0; - break; - case 4: - if (sysinfo->interleaved) { + + if (nonzero != -1) { + if (sysinfo->interleaved && nonzero < 4 && i >= 4) { bankaddr = 0x40; - break; - } - default: - if (nonzero != -1) { + } else { printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero); bankaddr += sysinfo->banksize[nonzero] << (sysinfo->interleaved ? 26 : 25); - break; } - /* No populated bank hit before. Start at address 0 */ - bankaddr = 0; } /* We have a bank with a non-zero size.. Remember it @@ -2827,9 +2812,9 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 9eb6e75eacf..1e504593ca6 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE + select HAVE_DEBUG_RAM_SETUP if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 8c0117f531d..087d37e5aa5 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "chip.h" #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index a9032bafea2..485cb27f459 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -171,13 +171,6 @@ static void mc_read_resources(struct device *dev) add_fixed_resources(dev, 10); } -u32 northbridge_get_tseg_base(void) -{ - struct device *dev = pcidev_on_root(0, 0); - - return pci_read_config32(dev, TSEG) & ~1; -} - u32 northbridge_get_tseg_size(void) { return CONFIG_SMM_TSEG_SIZE; @@ -311,7 +304,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index 163f21ce3cd..e32190f519d 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "nehalem.h" static uintptr_t smm_region_start(void) @@ -32,6 +33,11 @@ static uintptr_t smm_region_start(void) return tom; } +u32 northbridge_get_tseg_base(void) +{ + return (u32)smm_region_start(); +} + void *cbmem_top(void) { return (void *) smm_region_start(); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 78bc6de70a5..15d6abb67be 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -29,18 +30,18 @@ #include #include #include -#include "raminit.h" -#include "chip.h" #include #include #include #include #include - -#include "nehalem.h" - #include #include +#include + +#include "chip.h" +#include "nehalem.h" +#include "raminit.h" #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) @@ -1568,14 +1569,14 @@ static void write_training_data(struct raminfo *info) static void dump_timings(struct raminfo *info) { int channel, slot, rank, lane, i; - printk(BIOS_DEBUG, "Timings:\n"); + printk(RAM_DEBUG, "Timings:\n"); FOR_POPULATED_RANKS { - printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, + printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank); for (lane = 0; lane < 9; lane++) { - printk(BIOS_DEBUG, "lane %d: ", lane); + printk(RAM_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { - printk(BIOS_DEBUG, "%x (%x) ", + printk(RAM_DEBUG, "%x (%x) ", read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), @@ -1584,12 +1585,12 @@ static void dump_timings(struct raminfo *info) lane_timings[i][channel][slot][rank] [lane]); } - printk(BIOS_DEBUG, "\n"); + printk(RAM_DEBUG, "\n"); } } - printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178); - printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); } @@ -1623,8 +1624,8 @@ static void save_timings(struct raminfo *info) train.reg_6dc = MCHBAR32(0x6dc); train.reg_6e8 = MCHBAR32(0x6e8); - printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); - printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8); /* Save the MRC S3 restore data to cbmem */ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, @@ -3403,7 +3404,7 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); - printk (BIOS_SPEW, "[%x] <= %x\n", reg, + printk(RAM_SPEW, "[%x] <= %x\n", reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder << 8) @@ -3486,7 +3487,8 @@ static void set_2dxx_series(struct raminfo *info, int s3resume) frequency_11(info) / 2, 4000, 4000, 0, 0); if (s3resume) { - printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + printk(RAM_SPEW, "[6dc] <= %x\n", + info->cached_training->reg_6dc); MCHBAR32(0x6dc) = info->cached_training->reg_6dc; } else set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -3497,7 +3499,8 @@ static void set_2dxx_series(struct raminfo *info, int s3resume) set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); if (s3resume) { - printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + printk(RAM_SPEW, "[6e8] <= %x\n", + info->cached_training->reg_6e8); MCHBAR32(0x6e8) = info->cached_training->reg_6e8; } else set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -3679,8 +3682,7 @@ void chipset_init(const int s3resume) if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); MCHBAR8(0x2ca8) = 0; - outb(0x6, 0xcf9); - halt(); + system_reset(); } #if 0 if (!s3resume) { @@ -3905,8 +3907,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } } @@ -4026,19 +4027,19 @@ void raminit(const int s3resume, const u8 *spd_addrmap) int j; if (s3resume && info.cached_training) { restore_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.cached_training->reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.cached_training->reg274265[i][j]); } else { set_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.training.reg274265[i][j]); } @@ -4344,8 +4345,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) "Couldn't find training data. Rebooting\n"); reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - outb(0xe, 0xcf9); - halt(); + full_reset(); } int tm; info.training = *info.cached_training; @@ -4786,7 +4786,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); /* Failed S3 resume, reset to come up cleanly */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } } diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 1878cc4f38d..2b4f502c617 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -33,6 +33,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select C_ENVIRONMENT_BOOTBLOCK config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 90a9f483739..2d166138b66 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,9 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) +bootblock-y += ../../../cpu/x86/early_reset.S +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd76fb933c3..bd510b00eef 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */ #include -#define PCIEXBAR 0x60 +#include +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index a0d53052550..be6a5e27d66 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -24,6 +23,7 @@ #include #include #include +#include #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) @@ -119,9 +119,7 @@ static void early_graphics_setup(void) static void early_misc_setup(void) { - u32 reg32; - - reg32 = MCHBAR32(0x30); + MCHBAR32(0x30); MCHBAR32(0x30) = 0x21800; DMIBAR32(0x2c) = 0x86000040; pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); @@ -129,9 +127,9 @@ static void early_misc_setup(void) early_graphics_setup(); - reg32 = MCHBAR32(0x40); + MCHBAR32(0x40); MCHBAR32(0x40) = 0x0; - reg32 = MCHBAR32(0x40); + MCHBAR32(0x40); MCHBAR32(0x40) = 0x8; pci_write_config8(LPC, 0x8, 0x1d); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 019f7648f0b..dd6cb325969 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -23,10 +23,7 @@ #include #include #include - #include -#include "chip.h" -#include "pineview.h" #include #include #include @@ -34,6 +31,10 @@ #include #include #include +#include + +#include "chip.h" +#include "pineview.h" #define GTTSIZE (512*1024) diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 65d21cfb8d1..f53ff17aa3d 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -236,7 +236,6 @@ u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ -void mb_enable_lpc(void); void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */ diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index bf00099bab1..282765efcc6 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -1173,7 +1173,7 @@ static void sdram_dlltiming(struct sysinfo *s) static void sdram_rcomp(struct sysinfo *s) { - u8 i, j, reg8, f, rcompp, rcompn, srup, srun; + u8 i, j, reg8, rcompp, rcompn, srup, srun; u16 reg16; u32 reg32, rcomp1, rcomp2; @@ -1263,10 +1263,8 @@ static void sdram_rcomp(struct sysinfo *s) srun = 0; if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { - f = 0; rcomp1 = 0x00050431; } else { - f = 1; rcomp1 = 0x00050542; } if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) { @@ -1746,10 +1744,8 @@ static void sdram_checkreset(void) } pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3); - if (reset) { - printk(BIOS_DEBUG, "Power cycle reset...\n"); - outb(0xe, 0xcf9); - } + if (reset) + full_reset(); } static void sdram_dradrb(struct sysinfo *s) @@ -2125,31 +2121,25 @@ static void sdram_enhancedmode(struct sysinfo *s) reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1); - u32 nranks, curranksize, maxranksize, maxdra, dra; - u8 rankmismatch, dramismatch; + u32 nranks, curranksize, maxranksize, dra; + u8 rankmismatch; static const u8 drbtab[10] = { 0x4, 0x2, 0x8, 0x4, 0x8, 0x4, 0x10, 0x8, 0x20, 0x10 }; nranks = 0; curranksize = 0; maxranksize = 0; - maxdra = 0; rankmismatch = 0; - dramismatch = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { nranks++; dra = (u8) ((MCHBAR32(0x208) >> (8*r)) & 0x7f); curranksize = drbtab[dra]; if (maxranksize == 0) { maxranksize = curranksize; - maxdra = dra; } if (curranksize != maxranksize) { rankmismatch = 1; } - if (dra != maxdra) { - dramismatch = 1; - } } reg8 = 0; @@ -2220,7 +2210,7 @@ static void sdram_periodic_rcomp(void) static void sdram_new_trd(struct sysinfo *s) { u8 pidelay, i, j, k, cc, trd_perphase[5]; - u8 bypass, freqgb, trd, reg8, txfifo, cas; + u8 bypass, freqgb, trd, reg8, txfifo; u32 reg32, datadelay, tio, rcvendelay, maxrcvendelay; u16 tmclk, thclk, buffertocore, postcalib; static const u8 txfifo_lut[8] = { 0, 7, 6, 5, 2, 1, 4, 3 }; @@ -2236,7 +2226,6 @@ static void sdram_new_trd(struct sysinfo *s) freqgb = 110; buffertocore = 5000; - cas = s->selected_timings.CAS; postcalib = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 1250 : 500; tmclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500; tmclk = tmclk * 100 / freqgb; diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 771434472e2..8d7de451494 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -17,12 +17,11 @@ * so this one is named with prefix mainboard. */ -#include #include #include #include #include -#include +#include #include #include #include @@ -58,20 +57,12 @@ void mainboard_romstage_entry(unsigned long bist) if (bist == 0) enable_lapic(); - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); - mb_enable_lpc(); // nm10_enable_lpc - - /* Initialize console device(s) */ - console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -113,8 +104,7 @@ void mainboard_romstage_entry(unsigned long bist) if (!cbmem_was_initted && s3resume) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } romstage_handoff_init(s3resume); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index b3827c0d4c4..4f9da000a4e 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -23,16 +23,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select POSTCAR_STAGE select POSTCAR_CONSOLE -config NORTHBRIDGE_INTEL_IVYBRIDGE - bool - select CACHE_MRC_SETTINGS - select CPU_INTEL_MODEL_306AX - select HAVE_DEBUG_RAM_SETUP - select INTEL_GMA_ACPI - select POSTCAR_STAGE - select POSTCAR_CONSOLE - -if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE +if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ecab18a818b..ba55466026b 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) ramstage-y += ram_calc.c ramstage-y += northbridge.c @@ -29,6 +29,7 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c romstage-y += raminit_sandy.c diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824287e..7dddb8abd0a 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -52,6 +52,72 @@ struct northbridge_intel_sandybridge_config { * Maximum PCI mmio size in MiB. */ u16 pci_mmio_size; + + /* Data for RAM init */ + + /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ + u8 spd_addresses[4]; + + /* PEI data for RAM init and early silicon init */ + u8 ts_addresses[4]; + + bool ec_present; + bool ddr3lv_support; + + /* N mode functionality. Leave this setting at 0. + * 0 Auto + * 1 1N + * 2 2N + */ + enum { + DDR_NMODE_AUTO = 0, + DDR_NMODE_1N, + DDR_NMODE_2N, + } nmode; + + /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + enum { + DDR_REFRESH_RATE_TEMP_THRES = 0, + DDR_REFRESH_REATE_NORMAL, + DDR_REFRESH_RATE_DOUBLE, + } ddr_refresh_rate_config; + + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Ports 0-7 can be mapped to OC0-OC3 + * Ports 8-13 can be mapped to OC4-OC7 + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) + */ + u16 usb_port_config[16][3]; + + struct { + /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + u8 mode : 2; + /* 4 bit mask, 1: switchable, 0: not switchable */ + u8 hs_port_switch_mask : 4; + /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + u8 preboot_support : 1; + /* 0: Disable, 1: Enable */ + u8 xhci_streams : 1; + } usb3; }; #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c new file mode 100644 index 00000000000..6d41a2da96e --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void early_init_dmi(void) +{ + int i; + + DMIBAR32(0x0914) |= 0x80000000; + DMIBAR32(0x0934) |= 0x80000000; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; + DMIBAR32(0x0a04 + (i << 4)) |= 0x800; + } + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; + DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; + } + + DMIBAR32(0x090c) &= 0xfe1fffff; + DMIBAR32(0x092c) &= 0xfe1fffff; + + DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x7a1842ec; + DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c) = 0x00000128; + DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x7a1842ec; + DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c) = 0x00000128; + DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04) = 0x2e680008; + DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x3a1842ec; + DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x3a1842ec; + DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910) = 0x00004300; + DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930) = 0x00004300; + DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00) = 0x03042018; + DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10) = 0x03042018; + DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20) = 0x03042018; + DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30) = 0x03042018; + DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04) = 0x0c0718f0; + DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14) = 0x0c0718f0; + DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24) = 0x0c0718f0; + DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34) = 0x0c0718f0; + DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900) = 0x50000000; + DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920) = 0x50000000; + DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904) = 0x3a1846ec; + DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924) = 0x3a1846ec; + DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c) = 0x00063400; + DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46339008; + DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46339008; + DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700) = 0x45339008; + DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720) = 0x45339008; + DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700) = 0x453b9008; + DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720) = 0x453b9008; + DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700) = 0x45bb9008; + DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720) = 0x45bb9008; + DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700) = 0x45fb9008; + DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720) = 0x45fb9008; + DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914) = 0x9021a280; + DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934) = 0x9021a280; + DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914) = 0x9821a280; + DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934) = 0x9821a280; + DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03242018; + DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03242018; + DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03242018; + DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03242018; + DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258) = 0x60000600; + DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904) = 0x2a1846ec; + DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914) = 0x98200280; + DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924) = 0x2a1846ec; + DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934) = 0x98200280; + DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c) = 0x00c2403c; + + early_pch_init_native_dmi_pre(); + + /* Write once settings. */ + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | + (2 << 0) | // 5GT/s + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + + printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); + /* + * Virtual Channel resources must match settings in RCBA! + * + * Channel Vp and Vm are documented in + * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel + * Pentium Processor Family, and Desktop Intel Celeron Processor Family + * Vol. 2" + */ + + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ + DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ + DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ + DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + + /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ + DMIBAR8(DMIPVCCAP1) |= 1; + + early_pch_init_native_dmi_post(); + + /* + * BIOS Requirement: Check if DMI VC Negotiation was successful. + * Wait for virtual channels negotiation pending. + */ + while (DMIBAR16(DMIVC0RSTS) & VC0NP) + ; + while (DMIBAR16(DMIVC1RSTS) & VC1NP) + ; + while (DMIBAR16(DMIVCPRSTS) & VCPNP) + ; + while (DMIBAR16(DMIVCMRSTS) & VCMNP) + ; +} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b923065091d..fd3d34f2dee 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -14,15 +14,15 @@ * GNU General Public License for more details. */ -#include #include #include #include #include #include -#include #include #include +#include + #include "sandybridge.h" static void sandybridge_setup_bars(void) @@ -45,22 +45,7 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif + printk(BIOS_DEBUG, " done\n"); } static void sandybridge_setup_graphics(void) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d28d676020..19df8d4cc8e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -25,7 +25,9 @@ #include #include #include +#include #include +#include #include "chip.h" #include "sandybridge.h" @@ -624,7 +626,7 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) /* PCI Init, will run VBIOS */ pci_dev_init(dev); diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 0a60707136e..8e98becbe33 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -105,9 +105,10 @@ struct pei_data uint16_t usb_port_config[16][3]; /* See the usb3 struct above for details */ pch_usb3_controller_settings usb3; - /* SPD data array for onboard RAM. Specify address 0xf0, - * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in - * spd_address for a given "DIMM". + /* SPD data array for onboard RAM. + * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled" + * flag and the spd_addresses are used to determine which DIMMs should + * use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c0666343123..c13ae37fbc4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -18,18 +18,19 @@ #include #include #include +#include #include #include -#include #include #include #include -#include #include #include #include #include +#include #include +#include #include "raminit_native.h" #include "raminit_common.h" @@ -311,12 +312,11 @@ static void init_dram_ddr3(int min_tck, int s3resume) && reg_5d10 && !s3resume) { MCHBAR32(0x5d10) = 0; /* Need reset. */ - outb(0x6, 0xcf9); - - halt(); + system_reset(); } early_pch_init_native(); + early_init_dmi(); early_thermal_init(); /* try to find timings in MRC cache */ @@ -325,8 +325,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } ctrl_cached = NULL; } else { @@ -355,8 +354,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) if (err) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* no need to erase bad mrc cache here, it gets overwritten on * successful boot. */ @@ -429,8 +427,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } if (!s3resume) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index cbbd2317edb..4974173ef12 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,7 +23,7 @@ #include #include #include -#include + #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" @@ -1452,9 +1452,8 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) int lane; FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); } wait_428c(channel); @@ -1524,6 +1523,24 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); } +static void timC_threshold_process(int *data, const int count) +{ + int min = data[0]; + int max = min; + int i; + for (i = 1; i < count; i++) { + if (min > data[i]) + min = data[i]; + if (max < data[i]) + max = data[i]; + } + int threshold = min/2 + max/2; + for (i = 0; i < count; i++) + data[i] = data[i] > threshold; + printram("threshold=%d min=%d max=%d\n", + threshold, min, max); +} + static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; @@ -1554,14 +1571,25 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) } } FOR_ALL_LANES { - struct run rn = - get_longest_zero_run(statistics[lane], MAX_TIMC + 1); - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; - if (rn.all) { + struct run rn = get_longest_zero_run( + statistics[lane], ARRAY_SIZE(statistics[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - return MAKE_ERR; + /* With command training not happend yet, the lane can + * be erroneous. Take the avarage as reference and try + * again to find a run. + */ + timC_threshold_process(statistics[lane], + ARRAY_SIZE(statistics[lane])); + rn = get_longest_zero_run(statistics[lane], + ARRAY_SIZE(statistics[lane])); + if (rn.all || rn.length < 8) { + printk(BIOS_EMERG, "timC recovery failed\n"); + return MAKE_ERR; + } } + ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } @@ -1997,9 +2025,8 @@ int write_training(ramctr_timing * ctrl) MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - volatile u32 tmp; MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - tmp = MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ @@ -2344,9 +2371,8 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2425,8 +2451,7 @@ int discover_edges(ramctr_timing *ctrl) fill_pattern0(ctrl, channel, 0, 0); MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x400 * channel + lane * 4 + 0x4140); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2626,10 +2651,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2674,8 +2698,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, wait_428c(channel); FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x4340 + + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 852da7aa264..e88d3565937 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -16,9 +16,10 @@ #include #include #include +#include #include -#include #include +#include #include #include #include @@ -27,12 +28,13 @@ #include #include #include -#include #include #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" +#include "chip.h" #include +#include /* Management Engine is in the southbridge */ #include @@ -211,8 +213,7 @@ void sdram_initialize(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Pass console handler in pei_data */ @@ -234,7 +235,8 @@ void sdram_initialize(struct pei_data *pei_data) default: printk(BIOS_ERR, "MRC returned %x.\n", rv); } - die("Nonzero MRC return value.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Nonzero MRC return value.\n"); } } else { die("UEFI PEI System Agent not found.\n"); @@ -275,6 +277,89 @@ struct mrc_var_data { u32 reserved[4]; } __packed; +static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; + + if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { + const struct device *dev = pcidev_on_root(1, 0); + pei_data->pcie_init = dev && dev->enabled; + } else { + pei_data->pcie_init = 0; + } +} + +static void southbridge_fill_pei_data(struct pei_data *pei_data) +{ + const struct device *dev = pcidev_on_root(0x19, 0); + + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->gbe_enable = dev && dev->enabled; +} + +static void devicetree_fill_pei_data(struct pei_data *pei_data) +{ + const struct northbridge_intel_sandybridge_config *cfg; + + const struct device *dev = pcidev_on_root(0, 0); + if (!dev || !dev->chip_info) + return; + + cfg = dev->chip_info; + + switch (cfg->max_mem_clock_mhz) { + /* MRC only supports fixed numbers of frequencies */ + default: + printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); + /* fallthrough */ + case 400: + pei_data->max_ddr3_freq = 800; + break; + case 533: + pei_data->max_ddr3_freq = 1066; + break; + case 666: + pei_data->max_ddr3_freq = 1333; + break; + case 800: + pei_data->max_ddr3_freq = 1600; + break; + + } + + memcpy(pei_data->spd_addresses, cfg->spd_addresses, + sizeof(pei_data->spd_addresses)); + + memcpy(pei_data->ts_addresses, cfg->ts_addresses, + sizeof(pei_data->ts_addresses)); + + pei_data->ec_present = cfg->ec_present; + pei_data->ddr3lv_support = cfg->ddr3lv_support; + + pei_data->nmode = cfg->nmode; + pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; + + memcpy(pei_data->usb_port_config, cfg->usb_port_config, + sizeof(pei_data->usb_port_config)); + + pei_data->usb3.mode = cfg->usb3.mode; + pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; + pei_data->usb3.preboot_support = cfg->usb3.preboot_support; + pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -285,9 +370,37 @@ void perform_raminit(int s3resume) if (!mainboard_should_reset_usb(s3resume)) enable_usb_bar(); + memset(&pei_data, 0, sizeof(pei_data)); + pei_data.pei_version = PEI_VERSION, + + northbridge_fill_pei_data(&pei_data); + southbridge_fill_pei_data(&pei_data); + devicetree_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data); post_code(0x3a); + + /* Fill after mainboard_fill_pei_data as it might provide spd_data */ + pei_data.dimm_channel0_disabled = + (!pei_data.spd_addresses[0] && !pei_data.spd_data[0][0]) + + (!pei_data.spd_addresses[1] && !pei_data.spd_data[1][0]) * 2; + + pei_data.dimm_channel1_disabled = + (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + + (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; + + /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ + for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { + if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { + memcpy(pei_data.spd_data[0], pei_data.spd_data[i], + sizeof(pei_data.spd_data[0])); + } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { + if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], + sizeof(pei_data.spd_data[0])) != 0) + die("Onboard SPDs must match each other"); + } + } + pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); @@ -309,7 +422,6 @@ void perform_raminit(int s3resume) if (s3resume && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3fab3be85d4..76b30883887 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include #include @@ -29,6 +29,7 @@ #include #include #include +#include static void early_pch_reset_pmcon(void) { @@ -47,10 +48,8 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; - if (MCHBAR16(SSKPD) == 0xCAFE) { - outb(0x6, 0xcf9); - halt (); - } + if (MCHBAR16(SSKPD) == 0xCAFE) + system_reset(); if (bist == 0) enable_lapic(); @@ -80,6 +79,9 @@ void mainboard_romstage_entry(unsigned long bist) s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e315fa463f1..77165f69316 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -52,8 +52,6 @@ #define IOMMU_BASE1 0xfed90000ULL #define IOMMU_BASE2 0xfed91000ULL -#include - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include @@ -177,12 +175,23 @@ enum platform_type { #define DMIPVCCCTL 0x00c /* 16bit */ #define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP 0x2 #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP 0x2 + +#define DMIVCPRCTL 0x02c /* 32bit */ + +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP 0x2 + +#define DMIVCMRCTL 0x0038 /* 32 bit */ +#define DMIVCMRSTS 0x003e /* 16 bit */ +#define VCMNP 0x2 #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -192,7 +201,7 @@ enum platform_type { #define DMILCAP 0x084 /* 32bit */ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ - +#define TXTRN (1 << 11) #define DMICTL1 0x0f0 /* 32bit */ #define DMICTL2 0x0fc /* 32bit */ @@ -211,6 +220,7 @@ void sandybridge_early_initialization(void); void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); +void early_init_dmi(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index fb04fd8582b..a91d227c7af 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -25,11 +25,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; u32 pciexbar = 0; u32 length = 0; - dev = pcidev_on_root(0, 0); if (!decode_pciebar(&pciexbar, &length)) return current; diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ce184405319..ed372b538f2 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -282,16 +282,12 @@ int do_write_training(struct sysinfo *s) u8 dq_lower[TOTAL_BYTELANES]; u8 dq_upper[TOTAL_BYTELANES]; struct dll_setting dq_setting[TOTAL_BYTELANES]; - u8 dq_average; - u32 dq_absolute; printk(BIOS_DEBUG, "Starting DQ write training\n"); FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { printk(BIOS_DEBUG, "Doing DQ write training on CH%d\n", channel); - dq_average = 0; - dq_absolute = 0; /* Start all lanes at DQS values */ FOR_EACH_BYTELANE(lane) { dqset(channel, lane, &s->dqs_settings[channel][lane]); diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d019ffd7f50..a58f2ba6e9d 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -150,7 +150,6 @@ static void init_egress(void) static void init_dmi(void) { u32 reg32; - u16 reg16; /* Assume IGD present */ @@ -224,9 +223,11 @@ static void init_dmi(void) /* ASPM on DMI link */ RCBA16(0x1a8) &= ~0x3; - reg16 = RCBA16(0x1a8); + /* FIXME: Do we need to read RCBA16(0x1a8)? */ + RCBA16(0x1a8); RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10); - reg32 = RCBA32(0x2010); + /* FIXME: Do we need to read RCBA32(0x2010)? */ + RCBA32(0x2010); /* Set up VC1 max time */ RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; @@ -240,7 +241,8 @@ static void init_dmi(void) DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; DMIBAR32(0x88) &= ~0x3; DMIBAR32(0x88) |= 0x3; - reg16 = DMIBAR16(0x88); + /* FIXME: Do we need to read RCBA16(0x88)? */ + DMIBAR16(0x88); } static void x4x_prepare_resume(int s3resume) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index c4e8bf1cdd4..61731fee3ed 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "chip.h" #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4943428d0eb..bd6536ab6fa 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -14,14 +14,13 @@ * GNU General Public License for more details. */ -#include #include #include +#include #include #include #include #include -#include #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include /* smbus_read_byte */ #else @@ -33,6 +32,7 @@ #include #include #include +#include #include "iomap.h" #include "x4x.h" @@ -623,9 +623,7 @@ static void checkreset_ddr2(int boot_path) reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - printk(BIOS_DEBUG, "Reset...\n"); - outb(0xe, 0xcf9); - asm ("hlt"); + full_reset(); } pmcon2 |= 0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); @@ -654,13 +652,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map) if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) { if (boot_path == BOOT_PATH_RESUME) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } else if (boot_path == BOOT_PATH_WARM_RESET) { /* On warm reset some of dram calibrations fail and therefore requiring valid cached settings */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } ctrl_cached = NULL; } else { @@ -728,8 +724,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) &s, sizeof(s)); if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } timestamp_add_now(TS_AFTER_INITRAM); diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index f1726231081..422b0ffa163 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1317,7 +1317,6 @@ static u32 mirror_shift_bit(const u32 data, u8 bit) void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { u32 addr = test_address(ch, r); - volatile u32 rubbish; u8 data8 = cmd; u32 data32; @@ -1337,7 +1336,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) } data32 <<= 3; - rubbish = read32((void *)((data32 | addr))); + read32((void *)((data32 | addr))); udelay(10); MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD); MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 7c49838d138..36a6ebd259c 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -41,7 +41,6 @@ static inline void barrier(void) static u8 sampledqs(u32 addr, u8 lane, u8 channel) { - volatile u32 strobe; u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; /* Reset the DQS probe */ @@ -50,7 +49,8 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel) MCHBAR8(RESET_CNTL(channel)) |= 0x2; udelay(2); barrier(); - strobe = read32((u32 *)addr); + /* Read strobe */ + read32((u32 *)addr); barrier(); return (MCHBAR8(sample_offset) >> 6) & 1; } diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 18d9635379a..0c3b7bfc761 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -17,11 +17,12 @@ #define __SIMPLE_DEVICE__ -#include "vx900.h" - #include #include #include +#include + +#include "vx900.h" #define MCU PCI_DEV(0, 0, 3) diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index afd35a18e8d..07a9a71f73d 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include + #include "vx900.h" #ifdef __SIMPLE_DEVICE__ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index e03470c7044..4f79ed35b0e 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -554,7 +554,6 @@ static u8 vx900_get_CWL(u8 CAS) static void vx900_dram_timing(ramctr_timing * ctrl) { u8 reg8, val, tFAW, tRRD; - u32 val32; /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066) so make sure * we cap it if we have faster DIMMs. @@ -569,8 +568,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl) ctrl->tCK = TCK_266MHZ; } - val32 = (1000 << 8) / ctrl->tCK; - printram("Selected DRAM frequency: %u MHz\n", val32); + printram("Selected DRAM frequency: %u MHz\n", (1000 << 8) / ctrl->tCK); /* Find CAS and CWL latencies */ val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 9e306388925..96d821ac4d6 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -28,7 +28,6 @@ #include #include -#include u32 vx900_get_tolm(void); void vx900_set_chrome9hd_fb_size(u32 size_mb); diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index e466eb87aab..4698a4dc8c9 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -22,6 +22,7 @@ #include #if CONFIG(VBOOT) #include +#include #include #endif diff --git a/src/security/tpm/tss/vendor/cr50/Kconfig b/src/security/tpm/tss/vendor/cr50/Kconfig index 4d40c08da65..4a2ad4f8801 100644 --- a/src/security/tpm/tss/vendor/cr50/Kconfig +++ b/src/security/tpm/tss/vendor/cr50/Kconfig @@ -16,12 +16,12 @@ config TPM_CR50 bool default y if MAINBOARD_HAS_I2C_TPM_CR50 || MAINBOARD_HAS_SPI_TPM_CR50 - select POWER_OFF_ON_CR50_UPDATE if ARCH_X86 if TPM_CR50 config POWER_OFF_ON_CR50_UPDATE bool + default y if ARCH_X86 help Power off machine while waiting for CR50 update to take effect. diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 4815cb10f97..66bcc1ed6f2 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -169,17 +169,15 @@ config VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT reboots caused after vboot verification is run. e.g. reboots caused by FSP components on Intel platforms. -config VBOOT_OPROM_MATTERS +config VBOOT_MUST_REQUEST_DISPLAY bool default y if VGA_ROM_RUN default n help Set this option to indicate to vboot that this platform will skip its display initialization on a normal (non-recovery, non-developer) boot. - Vboot calls this "oprom matters" because on x86 devices this - traditionally meant that the video option ROM will not be loaded, but - it works functionally the same for other platforms that can skip their - native display initialization code instead. + Unless display is specifically requested, the video option ROM is not + loaded, and any other native display initialization code is not run. config VBOOT_HAS_REC_HASH_SPACE bool diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6d2096ddb0a..9ce724ed54d 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -70,6 +70,7 @@ ramstage-y += vboot_common.c postcar-y += vboot_common.c ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) +bootblock-y += vboot_crtm.c verstage-y += vboot_crtm.c romstage-y += vboot_crtm.c ramstage-y += vboot_crtm.c diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 6ea2c13a970..62d2e20f03a 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -37,6 +37,7 @@ #include #include +#include struct vb2_context; enum vb2_pcr_digest; diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 1d6525f966c..68749f008ba 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#define NEED_VB20_INTERNALS /* Peeking into vb2_shared_data */ + #include #include #include @@ -162,10 +164,8 @@ int vboot_recovery_mode_memory_retrain(void) int vboot_developer_mode_enabled(void) { - if (cbmem_possibly_online() && vboot_handoff_check_developer_flag()) - return 1; - - return 0; + return cbmem_possibly_online() && + vboot_get_working_data()->flags & VBOOT_WD_FLAG_DEVELOPER_MODE; } #if CONFIG(VBOOT_NO_BOARD_SUPPORT) diff --git a/src/security/vboot/gbb.c b/src/security/vboot/gbb.c index 8f57c798b2c..52930336663 100644 --- a/src/security/vboot/gbb.c +++ b/src/security/vboot/gbb.c @@ -13,17 +13,19 @@ * GNU General Public License for more details. */ +#define NEED_VB20_INTERNALS /* Peeking into vb2_gbb_header */ + #include #include #include -#include #include #include +#include #define GBB_FMAP_REGION_NAME "GBB" /* Copy of GBB header read from boot media. */ -static GoogleBinaryBlockHeader gbb_header; +static struct vb2_gbb_header gbb_header; /* * Read "GBB" region from SPI flash to obtain GBB header and validate @@ -45,13 +47,14 @@ static int gbb_init(void) return 1; if (rdev_readat(&gbb_rdev, &gbb_header, 0, - sizeof(GoogleBinaryBlockHeader)) != - sizeof(GoogleBinaryBlockHeader)) { + sizeof(struct vb2_gbb_header)) != + sizeof(struct vb2_gbb_header)) { printk(BIOS_ERR, "%s: Failure to read GBB header!\n", __func__); return 1; } - if (memcmp(gbb_header.signature, GBB_SIGNATURE, GBB_SIGNATURE_SIZE)) { + if (memcmp(gbb_header.signature, VB2_GBB_SIGNATURE, + VB2_GBB_SIGNATURE_SIZE)) { printk(BIOS_ERR, "%s: Signature check failed!\n", __func__); return 1; } diff --git a/src/security/vboot/gbb.h b/src/security/vboot/gbb.h index 550548d6131..389242a3a2c 100644 --- a/src/security/vboot/gbb.h +++ b/src/security/vboot/gbb.h @@ -18,7 +18,7 @@ #include -/* In order to use GBB_FLAG_* macros from vboot, include gbb_header.h. */ +/* In order to use VB2_GBB_FLAG_* macros from vboot, include vb2_api.h. */ /* * Read flags field from GBB header. diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 27317ad32d3..acb6dbbd025 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -16,6 +16,8 @@ #ifndef __VBOOT_MISC_H__ #define __VBOOT_MISC_H__ +#include +#include #include struct vb2_context; @@ -34,11 +36,20 @@ struct selected_region { */ struct vboot_working_data { struct selected_region selected_region; + uint32_t flags; /* offset of the buffer from the start of this struct */ - uint32_t buffer_offset; - uint32_t buffer_size; + uint16_t buffer_offset; + uint16_t buffer_size; }; +/* + * Definitions for vboot_working_data.flags values. + */ +/* vboot requests display initialization from coreboot. */ +#define VBOOT_WD_FLAG_DISPLAY_INIT (1 << 0) +/* vboot has selected developer mode. */ +#define VBOOT_WD_FLAG_DEVELOPER_MODE (1 << 1) + /* * Source: security/vboot/common.c */ @@ -59,13 +70,62 @@ int vboot_is_slot_selected(void); void vboot_fill_handoff(void); /* - * Source: security/vboot/vboot_loader.c + * Source: security/vboot/bootmode.c */ -int vboot_logic_executed(void); +void vboot_save_recovery_reason_vbnv(void); /* - * Source: security/vboot/bootmode.c + * The stage loading code is compiled and entered from multiple stages. The + * helper functions below attempt to provide more clarity on when certain + * code should be called. They are implemented inline for better compile-time + * code elimination. */ -void vboot_save_recovery_reason_vbnv(void); + +static inline int verification_should_run(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_VERSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return ENV_ROMSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + return ENV_BOOTBLOCK; + else + dead_code(); +} + +static inline int verstage_should_load(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_BOOTBLOCK; + else + return 0; +} + +static inline int vboot_logic_executed(void) +{ + extern int vboot_executed; /* should not be globally accessible */ + + /* If we are in the stage that runs verification, or in the stage that + both loads the verstage and is returned to from it afterwards, we + need to check a global to see if verfication has run. */ + if (verification_should_run() || + (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) + return car_get_var(vboot_executed); + + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { + /* All other stages are "after the bootblock" */ + return !ENV_BOOTBLOCK; + } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + /* Post-RAM stages are "after the romstage" */ +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } else { + dead_code(); + } +} + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index b99941875c2..0c4f33bc119 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,13 +140,6 @@ int get_recovery_mode_from_vbnv(void) return vbnv_data(RECOVERY_OFFSET); } -/* Read the BOOT_OPROM_NEEDED flag from VBNV. */ -int vboot_wants_oprom(void) -{ - vbnv_setup(); - return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; -} - /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index c8e689fa04c..a2f0b4c9781 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -25,7 +25,6 @@ int verify_vbnv(uint8_t *vbnv_copy); void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); -int vboot_wants_oprom(void); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void); diff --git a/src/security/vboot/vbnv_flash.c b/src/security/vboot/vbnv_flash.c index 85cd04a8e5d..908846fe70f 100644 --- a/src/security/vboot/vbnv_flash.c +++ b/src/security/vboot/vbnv_flash.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a9326e4ff46..a3c2490c0d6 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -31,7 +31,7 @@ #define BOOT_OFFSET 1 #define BOOT_DEBUG_RESET_MODE 0x80 #define BOOT_DISABLE_DEV_REQUEST 0x40 -#define BOOT_OPROM_NEEDED 0x20 +#define BOOT_DISPLAY_REQUEST 0x20 #define BOOT_TRY_B_COUNT_MASK 0x0F #define RECOVERY_OFFSET 2 diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 5e95c6215c0..ff8e6c896ce 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -18,12 +18,12 @@ #include #include #include -#include #include #include #include #include #include +#include int vboot_named_region_device(const char *name, struct region_device *rdev) { @@ -42,7 +42,7 @@ int vboot_can_enable_udc(void) if (!vboot_developer_mode_enabled()) return 0; /* Enable if GBB flag is set */ - if (gbb_is_flag_set(GBB_FLAG_ENABLE_UDC)) + if (gbb_is_flag_set(VB2_GBB_FLAG_ENABLE_UDC)) return 1; /* Enable if VBNV flag is set */ if (vbnv_udc_enable_flag()) @@ -85,17 +85,7 @@ static int vboot_get_handoff_flag(uint32_t flag) if (vboot_get_handoff_info((void **)&vbho, NULL)) return 0; - return !!(vbho->init_params.out_flags & flag); -} - -int vboot_handoff_skip_display_init(void) -{ - return !vboot_get_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY); -} - -int vboot_handoff_check_developer_flag(void) -{ - return vboot_get_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); + return !!(vbho->out_flags & flag); } int vboot_handoff_check_recovery_flag(void) diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 8c92437a3c6..a785a8ba346 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -39,7 +39,8 @@ int vboot_check_recovery_request(void); * vboot shared data as well as the flags from VbInit. */ struct vboot_handoff { - VbInitParams init_params; + uint32_t reserved0; /* originally from VbInitParams */ + uint32_t out_flags; uint32_t selected_firmware; char shared_data[VB_SHARED_DATA_MIN_SIZE]; } __packed; @@ -60,9 +61,7 @@ int vboot_get_handoff_info(void **addr, uint32_t *size); * Returns 0 for flag if false * Returns value read for other fields */ -int vboot_handoff_skip_display_init(void); int vboot_handoff_check_recovery_flag(void); -int vboot_handoff_check_developer_flag(void); int vboot_handoff_get_recovery_reason(void); /* ============================ VBOOT REBOOT ============================== */ diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index e675edbf03b..64cb4f2b40c 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -46,8 +46,7 @@ */ uint32_t vboot_init_crtm(void); -#if (CONFIG(VBOOT_MEASURED_BOOT) && \ -!ENV_BOOTBLOCK && !ENV_DECOMPRESSOR && !ENV_SMM) +#if CONFIG(VBOOT_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) * fh is the cbfs file handle to measure diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 047fcafb3d8..8a6b3d61e88 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -13,11 +13,8 @@ * GNU General Public License for more details. */ -/* This needs to be pulled in first so that the handoff code below and - * peek into the vb2 data structures. Additionally, vboot doesn't currently - * include what it uses in its own headers. Provide the types it's after. - * TODO: fix this necessity. */ -#define NEED_VB20_INTERNALS +#define NEED_VB20_INTERNALS /* Peeking into vb2_shared_data */ + #include #include #include @@ -43,7 +40,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, { VbSharedDataHeader *vb_sd = (VbSharedDataHeader *)vboot_handoff->shared_data; - uint32_t *oflags = &vboot_handoff->init_params.out_flags; + uint32_t *oflags = &vboot_handoff->out_flags; vb_sd->flags |= VBSD_BOOT_FIRMWARE_VBOOT2; @@ -64,30 +61,13 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, vb_sd->flags |= VBSD_BOOT_REC_SWITCH_ON; *oflags |= VB_INIT_OUT_ENABLE_RECOVERY; *oflags |= VB_INIT_OUT_CLEAR_RAM; - *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; - *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; } if (vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { *oflags |= VB_INIT_OUT_ENABLE_DEVELOPER; *oflags |= VB_INIT_OUT_CLEAR_RAM; - *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; - *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } - /* TODO: Set these in depthcharge */ - if (CONFIG(VBOOT_OPROM_MATTERS)) { - vb_sd->flags |= VBSD_OPROM_MATTERS; - /* - * Inform vboot if the display was enabled by dev/rec - * mode or was requested by vboot kernel phase. - */ - if ((*oflags & VB_INIT_OUT_ENABLE_DISPLAY) || - vboot_wants_oprom()) { - vb_sd->flags |= VBSD_OPROM_LOADED; - *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; - } - } /* In vboot1, VBSD_FWB_TRIED is * set only if B is booted as explicitly requested. Therefore, if B is diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 0640ebd173f..13503074250 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -36,53 +36,7 @@ _Static_assert(!CONFIG(VBOOT_RETURN_FROM_VERSTAGE) || CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); -/* The stage loading code is compiled and entered from multiple stages. The - * helper functions below attempt to provide more clarity on when certain - * code should be called. */ - -static int verification_should_run(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_VERSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) - return ENV_ROMSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - return ENV_BOOTBLOCK; - else - die("impossible!"); -} - -static int verstage_should_load(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_BOOTBLOCK; - else - return 0; -} - -static int vboot_executed CAR_GLOBAL; - -int vboot_logic_executed(void) -{ - /* If we are in a stage that would load the verstage or execute the - vboot logic directly, we store the answer in a global. */ - if (verstage_should_load() || verification_should_run()) - return car_get_var(vboot_executed); - - if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { - /* All other stages are "after the bootblock" */ - return !ENV_BOOTBLOCK; - } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif - } else { - die("impossible!"); - } -} +int vboot_executed CAR_GLOBAL; static void vboot_prepare(void) { diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2a8e6192892..626310010c8 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -320,7 +320,8 @@ void verstage_main(void) if (CONFIG(VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { if (vboot_init_crtm() != VB2_SUCCESS) - die("Initializing measured boot mode failed!"); + die_with_post_code(POST_INVALID_ROM, + "Initializing measured boot mode failed!"); } if (get_recovery_mode_switch()) { @@ -336,10 +337,22 @@ void verstage_main(void) if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; + /* Mainboard/SoC always initializes display. */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + ctx.flags |= VB2_CONTEXT_DISPLAY_INIT; + /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(&ctx); + /* Jot down some information from vboot which may be required later on + in coreboot boot flow. */ + if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + /* Mainboard/SoC should initialize display. */ + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; + if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; + if (rv) { /* * If vb2api_fw_phase1 fails, check for return value. @@ -383,7 +396,8 @@ void verstage_main(void) printk(BIOS_INFO, "Phase 4\n"); rv = locate_firmware(&ctx, &fw_main); if (rv) - die("Failed to read FMAP to locate firmware"); + die_with_post_code(POST_INVALID_ROM, + "Failed to read FMAP to locate firmware"); rv = hash_body(&ctx, &fw_main); save_if_needed(&ctx); diff --git a/src/soc/amd/common/block/acpi/halt.c b/src/soc/amd/common/block/acpi/halt.c index 8f36efb0425..200b3c12f55 100644 --- a/src/soc/amd/common/block/acpi/halt.c +++ b/src/soc/amd/common/block/acpi/halt.c @@ -15,6 +15,7 @@ #include #include +#include #include void poweroff(void) diff --git a/src/soc/amd/common/block/acpimmio/Kconfig b/src/soc/amd/common/block/acpimmio/Kconfig new file mode 100644 index 00000000000..f14cc0c2270 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_ACPIMMIO + bool + default n + help + Select this option to enable hardware blocks in the AcpiMmio + address space (0xfed8xxxx). diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc new file mode 100644 index 00000000000..9517b10b8a5 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c new file mode 100644 index 00000000000..7d4c4c5df14 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -0,0 +1,379 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void enable_acpimmio_decode(void) +{ + uint32_t dw; + + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER); + dw |= ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); +} + +/* PM registers are accessed a byte at a time via CD6/CD7 */ +uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +} + +uint16_t pm_io_read16(uint8_t reg) +{ + return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); +} + +uint32_t pm_io_read32(uint8_t reg) +{ + return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); +} + +void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +} + +void pm_io_write16(uint8_t reg, uint16_t value) +{ + pm_io_write8(reg, value & 0xff); + value >>= 8; + pm_io_write8(reg + sizeof(uint8_t), value & 0xff); +} + +void pm_io_write32(uint8_t reg, uint32_t value) +{ + pm_io_write16(reg, value & 0xffff); + value >>= 16; + pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); +} + +/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ + +/* smi read/write - access registers at 0xfed80200 */ + +uint8_t smi_read8(uint8_t offset) +{ + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint16_t smi_read16(uint8_t offset) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint32_t smi_read32(uint8_t offset) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +void smi_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +/* pm read/write - access registers at 0xfed80300 */ + +u8 pm_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u16 pm_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u32 pm_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +/* pm2 read/write - access registers at 0xfed80400 - currently unused */ + +/* biosram read/write - access registers at 0xfed80500 */ + +uint8_t biosram_read8(uint8_t offset) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); +} + +uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ +{ + int i; + uint16_t value = 0; + for (i = sizeof(value) - 1 ; i >= 0 ; i--) + value = (value << 8) | biosram_read8(offset + i); + return value; +} + +uint32_t biosram_read32(uint8_t offset) +{ + uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; + return value | biosram_read16(offset); +} + +void biosram_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); +} + +void biosram_write16(uint8_t offset, uint16_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +void biosram_write32(uint8_t offset, uint32_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +/* cmosram read/write - access registers at 0xfed80600 - currently unused */ + +/* cmos read/write - access registers at 0xfed80700 - currently unused */ + +/* acpi read/write - access registers at 0xfed80800 */ + +u8 acpi_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u16 acpi_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u32 acpi_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +void acpi_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +/* asf read/write - access registers at 0xfed80900 - not currently used */ + +u8 asf_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +u16 asf_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +void asf_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +void asf_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ + +u8 smbus_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +u16 smbus_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +void smbus_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +void smbus_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +/* wdt read/write - access registers at 0xfed80b00 - not currently used */ + +/* hpet read/write - access registers at 0xfed80c00 - not currently used */ + +/* iomux read/write - access registers at 0xfed80d00 */ + +u8 iomux_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u16 iomux_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u32 iomux_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +void iomux_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +/* misc read/write - access registers at 0xfed80e00 */ + +u8 misc_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u16 misc_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +void misc_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +/* dpvga read/write - access registers at 0xfed81400 - not currently used */ + +/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ +/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ +/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ + +/* xhci_pm read/write - access registers at 0xfed81c00 */ + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +/* acdc_tmr read/write - access registers at 0xfed81d00 */ + +/* aoac read/write - access registers at 0xfed81e00 - not currently used */ + +u8 aoac_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +void aoac_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h new file mode 100644 index 00000000000..e1cf7cbdc23 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPIMMIO_H__ +#define __AMDBLOCKS_ACPIMMIO_H__ + +void enable_acpimmio_decode(void); +uint8_t pm_io_read8(uint8_t reg); +uint16_t pm_io_read16(uint8_t reg); +uint32_t pm_io_read32(uint8_t reg); +void pm_io_write8(uint8_t reg, uint8_t value); +void pm_io_write16(uint8_t reg, uint16_t value); +void pm_io_write32(uint8_t reg, uint32_t value); +uint8_t smi_read8(uint8_t offset); +uint16_t smi_read16(uint8_t offset); +uint32_t smi_read32(uint8_t offset); +void smi_write8(uint8_t offset, uint8_t value); +void smi_write16(uint8_t offset, uint16_t value); +void smi_write32(uint8_t offset, uint32_t value); +uint8_t pm_read8(uint8_t reg); +uint16_t pm_read16(uint8_t reg); +uint32_t pm_read32(uint8_t reg); +void pm_write8(uint8_t reg, uint8_t value); +void pm_write16(uint8_t reg, uint16_t value); +void pm_write32(uint8_t reg, uint32_t value); +uint8_t pm2_read8(uint8_t reg); +uint16_t pm2_read16(uint8_t reg); +uint32_t pm2_read32(uint8_t reg); +void pm2_write8(uint8_t reg, uint8_t value); +void pm2_write16(uint8_t reg, uint16_t value); +void pm2_write32(uint8_t reg, uint32_t value); +uint8_t biosram_read8(uint8_t offset); +void biosram_write8(uint8_t offset, uint8_t value); +uint16_t biosram_read16(uint8_t offset); +uint32_t biosram_read32(uint8_t offset); +void biosram_write16(uint8_t offset, uint16_t value); +void biosram_write32(uint8_t offset, uint32_t value); +uint8_t acpi_read8(uint8_t reg); +uint16_t acpi_read16(uint8_t reg); +uint32_t acpi_read32(uint8_t reg); +void acpi_write8(uint8_t reg, uint8_t value); +void acpi_write16(uint8_t reg, uint16_t value); +void acpi_write32(uint8_t reg, uint32_t value); +uint8_t asf_read8(uint8_t reg); +uint16_t asf_read16(uint8_t reg); +uint32_t asf_read32(uint8_t reg); +void asf_write8(uint8_t reg, uint8_t value); +void asf_write16(uint8_t reg, uint16_t value); +void asf_write32(uint8_t reg, uint32_t value); +uint8_t smbus_read8(uint8_t reg); +uint16_t smbus_read16(uint8_t reg); +void smbus_write8(uint8_t reg, uint8_t value); +void smbus_write16(uint8_t reg, uint16_t value); +uint8_t wdt_read8(uint8_t reg); +uint16_t wdt_read16(uint8_t reg); +uint32_t wdt_read32(uint8_t reg); +void wdt_write8(uint8_t reg, uint8_t value); +void wdt_write16(uint8_t reg, uint16_t value); +void wdt_write32(uint8_t reg, uint32_t value); +uint8_t hpet_read8(uint8_t reg); +uint16_t hpet_read16(uint8_t reg); +uint32_t hpet_read32(uint8_t reg); +void hpet_write8(uint8_t reg, uint8_t value); +void hpet_write16(uint8_t reg, uint16_t value); +void hpet_write32(uint8_t reg, uint32_t value); +uint8_t iomux_read8(uint8_t reg); +uint16_t iomux_read16(uint8_t reg); +uint32_t iomux_read32(uint8_t reg); +void iomux_write8(uint8_t reg, uint8_t value); +void iomux_write16(uint8_t reg, uint16_t value); +void iomux_write32(uint8_t reg, uint32_t value); +uint8_t misc_read8(uint8_t reg); +uint16_t misc_read16(uint8_t reg); +uint32_t misc_read32(uint8_t reg); +void misc_write8(uint8_t reg, uint8_t value); +void misc_write16(uint8_t reg, uint16_t value); +void misc_write32(uint8_t reg, uint32_t value); +uint8_t xhci_pm_read8(uint8_t reg); +uint16_t xhci_pm_read16(uint8_t reg); +uint32_t xhci_pm_read32(uint8_t reg); +void xhci_pm_write8(uint8_t reg, uint8_t value); +void xhci_pm_write16(uint8_t reg, uint16_t value); +void xhci_pm_write32(uint8_t reg, uint32_t value); +uint8_t aoac_read8(uint8_t reg); +void aoac_write8(uint8_t reg, uint8_t value); + +#endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h new file mode 100644 index 00000000000..755af52d4f2 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__ +#define __AMDBLOCKS_ACPIMMIO_MAP_H__ + +/* IO index/data for accessing PMIO prior to enabling MMIO decode */ +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +/* TODO: In the event this is ported backward far enough, earlier devices + * enable the decode in PMx24 instead. All discrete FCHs and the Kabini + * SoC fall into this category. Kabini's successor, Mullins, uses this + * newer method. + */ +#define ACPIMMIO_DECODE_REGISTER 0x4 +#define ACPIMMIO_DECODE_EN BIT(0) + +/* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled + * in PMx24[1] (older implementations) and PMx04[1] (newer implementations). + * PM registers are also accessible via IO CD6/CD7. + * + * All products do not support all blocks below, however AMD has avoided + * redefining addresses and consumes new ranges as necessary. + * + * Definitions within each block are not guaranteed to remain consistent + * across family/model products. + */ + +#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 +#define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_SMI_BASE 0xfed80200 +#define ACPIMMIO_PMIO_BASE 0xfed80300 +#define ACPIMMIO_PMIO2_BASE 0xfed80400 +#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 +#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 +#define ACPIMMIO_CMOS_BASE 0xfed80700 +#define ACPIMMIO_ACPI_BASE 0xfed80800 +#define ACPIMMIO_ASF_BASE 0xfed80900 +#define ACPIMMIO_SMBUS_BASE 0xfed80a00 +#define ACPIMMIO_WDT_BASE 0xfed80b00 +#define ACPIMMIO_HPET_BASE 0xfed80c00 +#define ACPIMMIO_IOMUX_BASE 0xfed80d00 +#define ACPIMMIO_MISC_BASE 0xfed80e00 +#define ACPIMMIO_DPVGA_BASE 0xfed81400 +#define ACPIMMIO_GPIO0_BASE 0xfed81500 +#define ACPIMMIO_GPIO1_BASE 0xfed81600 +#define ACPIMMIO_GPIO2_BASE 0xfed81700 +#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 +#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 +#define ACPIMMIO_AOAC_BASE 0xfed81e00 + +#endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 2f3b8a62686..04db4242cf1 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -34,22 +34,11 @@ enum { /* Return current dispatcher or NULL on error. */ MODULE_ENTRY agesa_get_dispatcher(void); +AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func); AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams); -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); void *agesawrapper_getlateinitptr(int pick); -AGESA_STATUS agesawrapper_amdinitrtb(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amds3finalrestore(void); -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); void amd_initcpuio(void); diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index 1188f054f5b..86e32aff798 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -42,11 +42,11 @@ static const char *decodeAGESA_STATUS(AGESA_STATUS sret) return statusStrings[sret]; } -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) +static inline u32 do_agesawrapper(AGESA_STRUCT_NAME func, const char *name) { AGESA_STATUS ret; printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); + ret = agesa_execute_state(func); printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", name, decodeAGESA_STATUS(ret)); return (u32)ret; diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 25a564b457b..512b0b8c040 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,7 +18,7 @@ #include #include -#include +#include /* Extra, Special Purpose Registers in the PSP PCI Config Space */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 1b9e0fca51b..a39e29ff481 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Kyösti Mälkki + * Copyright (C) 2018 - 2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -40,99 +41,97 @@ static void *AcpiAlib; static void *AcpiIvrs; static void *AcpiCrat; -static AGESA_STATUS agesawrapper_readeventlog(uint8_t HeapStatus) +static AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, + AMD_CONFIG_PARAMS *StdHeader) { - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams = { - .StdHeader.CalloutPtr = &GetBiosCallout, - .StdHeader.HeapStatus = HeapStatus, - }; - - Status = AmdReadEventLog(&AmdEventParams); - if (AmdEventParams.EventClass) - printk(BIOS_DEBUG, "AGESA Event Log:\n"); - - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, " Class = %x, Info = %x," - " Param1 = 0x%x, Param2 = 0x%x" - " Param3 = 0x%x, Param4 = 0x%x\n", - (u32)AmdEventParams.EventClass, - (u32)AmdEventParams.EventInfo, - (u32)AmdEventParams.DataParam1, - (u32)AmdEventParams.DataParam2, - (u32)AmdEventParams.DataParam3, - (u32)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } + MODULE_ENTRY dispatcher = agesa_get_dispatcher(); - return Status; + if (!dispatcher) + return AGESA_UNSUPPORTED; + + StdHeader->Func = func; + return dispatcher(StdHeader); } -static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) +static AGESA_STATUS amd_dispatch(void *Params) { + AMD_CONFIG_PARAMS *StdHeader = Params; + return module_dispatch(StdHeader->Func, StdHeader); +} + +AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) +{ + AMD_CONFIG_PARAMS *StdHeader = (void *)ApExeParams; + return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); +} + +static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip, + AGESA_STRUCT_NAME func, void *buf, size_t len) +{ + AGESA_STATUS status; + /* Should clone entire StdHeader here. */ - interface_struct->StdHeader.CalloutPtr = &GetBiosCallout; + memset(aip, 0, sizeof(*aip)); + aip->StdHeader.CalloutPtr = &GetBiosCallout; + + /* If we provide the buffer, API expects it to have + StdHeader already filled. */ + if (buf != NULL && len >= sizeof(aip->StdHeader)) { + memcpy(buf, &aip->StdHeader, sizeof(aip->StdHeader)); + aip->AllocationMethod = ByHost; + aip->NewStructPtr = buf; + aip->NewStructSize = len; + } else { + if (ENV_ROMSTAGE) + aip->AllocationMethod = PreMemHeap; + if (ENV_RAMSTAGE) + aip->AllocationMethod = PostMemDram; + } - AGESA_STATUS status = AmdCreateStruct(interface_struct); + aip->AgesaFunctionName = func; + status = module_dispatch(AMD_CREATE_STRUCT, &aip->StdHeader); if (status != AGESA_SUCCESS) { printk(BIOS_ERR, "Error: AmdCreateStruct() for 0x%x returned 0x%x. " "Proper system initialization may not be possible.\n", - interface_struct->AgesaFunctionName, status); + aip->AgesaFunctionName, status); } - if (!interface_struct->NewStructPtr) /* Avoid NULL pointer usage */ + if (!aip->NewStructPtr) die("No AGESA structure created"); - return interface_struct->NewStructPtr; + return status; } -AGESA_STATUS agesawrapper_amdinitreset(void) +static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) { - AGESA_STATUS status; - AMD_RESET_PARAMS _ResetParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RESET, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_RESET_PARAMS), - .NewStructPtr = &_ResetParams, - }; + return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader); +} - AMD_RESET_PARAMS *ResetParams = create_struct(&AmdParamStruct); +static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams) +{ + AGESA_STATUS status; SetFchResetParams(&ResetParams->FchInterface); timestamp_add_now(TS_AGESA_INIT_RESET_START); - status = AmdInitReset(ResetParams); + status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); return status; } -AGESA_STATUS agesawrapper_amdinitearly(void) +static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_EARLY, - .AllocationMethod = PreMemHeap, - }; - - AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct); soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_START); - status = AmdInitEarly(EarlyParams); + status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - return status; } @@ -169,15 +168,9 @@ static void print_init_post_settings(AMD_POST_PARAMS *parms) uma_size / MiB, uma_start); } -AGESA_STATUS agesawrapper_amdinitpost(void) +static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_POST, - .AllocationMethod = PreMemHeap, - }; - - AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct); PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; @@ -193,7 +186,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) ); timestamp_add_now(TS_AGESA_INIT_POST_START); - status = AmdInitPost(PostParams); + status = amd_dispatch(PostParams); timestamp_add_now(TS_AGESA_INIT_POST_DONE); /* @@ -217,34 +210,20 @@ AGESA_STATUS agesawrapper_amdinitpost(void) print_init_post_settings(PostParams); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(PostParams->StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - return status; } -AGESA_STATUS agesawrapper_amdinitenv(void) +static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_ENV, - .AllocationMethod = PostMemDram, - }; - - AMD_ENV_PARAMS *EnvParams = create_struct(&AmdParamStruct); SetFchEnvParams(&EnvParams->FchInterface); SetNbEnvParams(&EnvParams->GnbEnvConfiguration); timestamp_add_now(TS_AGESA_INIT_ENV_START); - status = AmdInitEnv(EnvParams); + status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(EnvParams->StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - return status; } @@ -274,46 +253,26 @@ void *agesawrapper_getlateinitptr(int pick) } } -AGESA_STATUS agesawrapper_amdinitmid(void) +static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_MID, - .AllocationMethod = PostMemDram, - }; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); - AMD_MID_PARAMS *MidParams = create_struct(&AmdParamStruct); - SetFchMidParams(&MidParams->FchInterface); SetNbMidParams(&MidParams->GnbMidConfiguration); timestamp_add_now(TS_AGESA_INIT_MID_START); - status = AmdInitMid(MidParams); + status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - return status; } -AGESA_STATUS agesawrapper_amdinitlate(void) +static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_LATE, - .AllocationMethod = PostMemDram, - }; - - /* - * NOTE: if not call amdcreatestruct, the initializer - * (AmdInitLateInitializer) would not be called. - */ - AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { @@ -323,14 +282,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void) } timestamp_add_now(TS_AGESA_INIT_LATE_START); - Status = AmdInitLate(LateParams); + Status = amd_dispatch(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(LateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - DmiTable = LateParams->DmiTable; AcpiPstate = LateParams->AcpiPState; @@ -347,128 +301,143 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib, AcpiIvrs, __func__); - AmdReleaseStruct(&AmdParamStruct); return Status; } -AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) -{ - return AmdLateRunApTask(ApExeParams); -} - -AGESA_STATUS agesawrapper_amdinitrtb(void) +static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RTB, - .AllocationMethod = PostMemDram, - }; - - AMD_RTB_PARAMS *RtbParams = create_struct(&AmdParamStruct); timestamp_add_now(TS_AGESA_INIT_RTB_START); - Status = AmdInitRtb(RtbParams); + Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - if (save_s3_info(RtbParams->S3DataBlock.NvStorage, RtbParams->S3DataBlock.NvStorageSize, RtbParams->S3DataBlock.VolatileStorage, RtbParams->S3DataBlock.VolatileStorageSize)) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); - AmdReleaseStruct(&AmdParamStruct); - return Status; } -AGESA_STATUS agesawrapper_amdinitresume(void) +static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RESUME, - .AllocationMethod = PreMemHeap, - }; size_t nv_size; - AMD_RESUME_PARAMS *InitResumeParams = create_struct(&AmdParamStruct); - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); InitResumeParams->S3DataBlock.NvStorageSize = nv_size; timestamp_add_now(TS_AGESA_INIT_RESUME_START); - status = AmdInitResume(InitResumeParams); + status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - return status; } -AGESA_STATUS agesawrapper_amds3laterestore(void) +static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - AMD_S3LATE_PARAMS _S3LateParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_S3LATE_RESTORE, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_S3LATE_PARAMS), - .NewStructPtr = &_S3LateParams, - }; size_t vol_size; amd_initcpuio(); - AMD_S3LATE_PARAMS *S3LateParams = create_struct(&AmdParamStruct); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_LATE_START); - Status = AmdS3LateRestore(S3LateParams); + Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - AmdReleaseStruct(&AmdParamStruct); - return Status; } -AGESA_STATUS agesawrapper_amds3finalrestore(void) +static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - AMD_S3FINAL_PARAMS _S3FinalParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_S3FINAL_RESTORE, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_S3FINAL_PARAMS), - .NewStructPtr = &_S3FinalParams, - }; size_t vol_size; - AMD_S3FINAL_PARAMS *S3FinalParams = create_struct(&AmdParamStruct); - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_FINAL_START); - Status = AmdS3FinalRestore(S3FinalParams); + Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); + return Status; +} + +static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) +{ + void *Params = StdHeader; + + switch (StdHeader->Func) { + case AMD_INIT_RESET: + return amd_init_reset(Params); + case AMD_INIT_EARLY: + return amd_init_early(Params); + case AMD_INIT_POST: + return amd_init_post(Params); + case AMD_INIT_RESUME: + return amd_init_resume(Params); + default: + return AGESA_UNSUPPORTED; } - AmdReleaseStruct(&AmdParamStruct); +} - return Status; +static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) +{ + void *Params = StdHeader; + + switch (StdHeader->Func) { + case AMD_INIT_ENV: + return amd_init_env(Params); + case AMD_INIT_MID: + return amd_init_mid(Params); + case AMD_INIT_LATE: + return amd_init_late(Params); + case AMD_INIT_RTB: + return amd_init_rtb(Params); + case AMD_S3LATE_RESTORE: + return amd_s3late_restore(Params); + case AMD_S3FINAL_RESTORE: + return amd_s3final_restore(Params); + default: + return AGESA_UNSUPPORTED; + } + +} + +AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) +{ + AGESA_STATUS status = AGESA_UNSUPPORTED; + AMD_CONFIG_PARAMS template = {}; + AMD_CONFIG_PARAMS *StdHeader = &template; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; + union { + AMD_RESET_PARAMS ResetParams; + AMD_S3LATE_PARAMS S3LateParams; + AMD_S3FINAL_PARAMS S3FinalParams; + } sp; + + if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || + (func == AMD_S3FINAL_RESTORE)) { + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); + } else { + amd_create_struct(aip, func, NULL, 0); + } + + StdHeader = aip->NewStructPtr; + StdHeader->Func = func; + + if (ENV_ROMSTAGE) + status = romstage_dispatch(StdHeader); + if (ENV_RAMSTAGE) + status = ramstage_dispatch(StdHeader); + + amd_release_struct(aip); + return status; } diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index fdecf005817..80c7add2614 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -179,12 +179,12 @@ static void agesawrapper_post_device(void *unused) if (acpi_is_wakeup_s3()) return; - do_agesawrapper(agesawrapper_amdinitlate, "amdinitlate"); + do_agesawrapper(AMD_INIT_LATE, "amdinitlate"); if (!acpi_s3_resume_allowed()) return; - do_agesawrapper(agesawrapper_amdinitrtb, "amdinitrtb"); + do_agesawrapper(AMD_INIT_RTB, "amdinitrtb"); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c index a2826659d33..363ba83a0fe 100644 --- a/src/soc/amd/common/block/pi/amd_resume_final.c +++ b/src/soc/amd/common/block/pi/amd_resume_final.c @@ -18,7 +18,7 @@ static void agesawrapper_s3finalrestore(void *unused) { - do_agesawrapper(agesawrapper_amds3finalrestore, "amds3finalrestore"); + do_agesawrapper(AMD_S3FINAL_RESTORE, "amds3finalrestore"); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 0b119b71d3e..6734b55fde7 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 47402b670bb..3ffaf36485c 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc index 7d950b0b3ad..9efc6bc4148 100644 --- a/src/soc/amd/common/block/s3/Makefile.inc +++ b/src/soc/amd/common/block/s3/Makefile.inc @@ -1,6 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +romstage-y += s3_resume.c +ramstage-y += s3_resume.c endif diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 1027ae0294a..c55e73499a2 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -18,15 +18,16 @@ #include #include #include +#include #include #include #include - #include #include -#include "chip.h" #include +#include "chip.h" + void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 29ab149df9a..d4e1feb2515 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PSP diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 227fb701362..4f11ea227a5 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl index d18b147d71c..8185c35ac52 100644 --- a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl +++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl @@ -19,7 +19,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_MMIO_BASE)) + Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) } /* Read pin control dword */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 114401e24b1..4c1196dad64 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -144,7 +144,7 @@ Device (MISC) Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 15e4d2f1222..1334df11c46 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,6 +56,16 @@ Device(SBUS) { /* 0:14.7 - SD Controller */ Device(SDCN) { Name(_ADR, 0x00140007) + + Method(_PS0) { + FDDC(24, 0) + } + Method(_PS3) { + FDDC(24, 3) + } + Method(_PSC) { + Return(SDTD) + } } /* end SDCN */ Name(CRES, ResourceTemplate() { @@ -286,8 +296,9 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { offset (0x1e70), /* SD D3 Control */ SDTD, 2, , 1, + SDPD, 1, + , 1, , 1, - , 2, SDRT, 1, SDSC, 1, @@ -433,7 +444,14 @@ Method(FDDC, 2, Serialized) /* todo Case(15) { STD0()} */ /* SATA */ Case(18) { U2D0()} /* EHCI */ Case(23) { U3D0()} /* XHCI */ -/* todo Case(24) { SDD0()} */ /* SD */ + Case(24) { /* SD */ + Store(0x00, SDTD) + Store(One, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(SDDS, Local0) + } + } } } else { /* put device into D3cold */ @@ -489,7 +507,14 @@ Method(FDDC, 2, Serialized) /* todo Case(15) { STD3()} */ /* SATA */ Case(18) { U2D3()} /* EHCI */ Case(23) { U3D3()} /* XHCI */ -/* todo Case(24) { SDD3()} */ /* SD */ + Case(24) { /* SD */ + Store(Zero, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(SDDS, Local0) + } + Store(0x03, SDTD) + } } /* Turn off Power */ if(LEqual(I0TD, 3)) { diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1bd8cbf2f89..7221f955f6c 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -30,6 +29,8 @@ #include #include +#include "chip.h" + /* Supplied by i2c.c */ extern struct device_operations stoneyridge_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); @@ -163,12 +164,11 @@ static void earliest_ramstage(void *unused) psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); post_code(0x47); - do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv"); + do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ post_code(0x46); - do_agesawrapper(agesawrapper_amds3laterestore, - "amds3laterestore"); + do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 92223d19626..d1a7d301997 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #define MAX_NODES 1 diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index ce84a479295..19b95508478 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -17,7 +17,6 @@ #define __SIMPLE_DEVICE__ #include -#include #include #include #include @@ -26,10 +25,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - /* Enable all of the USB controllers */ - outb(PM_USB_ENABLE, PM_INDEX); - outb(PM_USB_ALL_CONTROLLERS, PM_DATA); - + pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); return SOC_EHCI1_DEV; } diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index da1ba0bb74e..7c9680582ce 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -16,13 +16,13 @@ */ #include +#include #include -#include #include +#include #include -#include -#include #include +#include "chip.h" static const struct soc_amd_event gpio_event_table[] = { { GPIO_1, GEVENT_19 }, @@ -221,14 +221,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio) void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - uint8_t *mux_ptr; uint32_t *gpio_ptr, *inter_master; uint32_t control, control_flags, edge_level, direction; uint32_t mask, bit_edge, bit_level; uint8_t mux, index, gpio; int gevent_num; - inter_master = (uint32_t *)(uintptr_t)(GPIO_CONTROL_MMIO_BASE + inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE + GPIO_MASTER_SWITCH); direction = 0; edge_level = 0; @@ -252,9 +251,8 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) control = gpio_list_ptr[index].control; control_flags = gpio_list_ptr[index].flags; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); - write8(mux_ptr, mux & AMD_GPIO_MUX_MASK); - read8(mux_ptr); /* Flush posted write */ + iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); + iomux_read8(gpio); /* Flush posted write */ /* special case if pin 2 is assigned to wake */ if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) route_sci(GPIO_2_EVENT); @@ -316,113 +314,16 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); /* Set all SCI trigger direction (high/low) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_TRIG), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG), direction, mask); /* Set all SCI trigger level (edge/level) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL), edge_level, mask); } -/* - * I2C pins are open drain with external pull up, so in order to bit bang them - * all, SCL pins must become GPIO inputs with no pull, then they need to be - * toggled between input-no-pull and output-low. This table is for the initial - * conversion of all SCL pins to input with no pull. - */ -static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), - PAD_GPI(I2C2_SCL_PIN, PULL_NONE), - PAD_GPI(I2C3_SCL_PIN, PULL_NONE), -}; -#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) - -/* - * To program I2C pins without destroying their programming, the registers - * that will be changed need to be saved first. - */ -static void save_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - uint32_t *gpio_ptr; - uint8_t *mux_ptr; - - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); - gpio_ptr = (uint32_t *)gpio_get_address(gpio); - save_table->mux_value = read8(mux_ptr); - save_table->control_value = read32(gpio_ptr); -} - -static void restore_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - uint32_t *gpio_ptr; - uint8_t *mux_ptr; - - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); - gpio_ptr = (uint32_t *)gpio_get_address(gpio); - write8(mux_ptr, save_table->mux_value); - read8(mux_ptr); - write32(gpio_ptr, save_table->control_value); - read32(gpio_ptr); -} - -/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -void sb_reset_i2c_slaves(void) -{ - const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct soc_amd_i2c_save save_table[saved_pins_count]; - uint8_t i, j, control; - - if (!dev || !dev->chip_info) - return; - cfg = dev->chip_info; - control = cfg->i2c_scl_reset & GPIO_I2C_MASK; - if (control == 0) - return; - - /* Save and reprogram I2C SCL pins */ - for (i = 0; i < saved_pins_count; i++) - save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); - sb_program_gpios(i2c_2_gpi, saved_pins_count); - - /* - * Toggle SCL back and forth 9 times under 100KHz. A single read is - * needed after the writes to force the posted write to complete. - */ - for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); - - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ - udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ - - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); - - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ - udelay(4); - } - - /* Restore I2C pins. */ - for (i = 0; i < saved_pins_count; i++) - restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); -} - int gpio_interrupt_status(gpio_t gpio) { uintptr_t gpio_address = gpio_get_address(gpio); diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index e99f3509ff1..c3e5539e197 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -13,12 +13,16 @@ * GNU General Public License for more details. */ +#include #include #include +#include #include +#include #include #include #include +#include #include "chip.h" #define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) @@ -140,3 +144,98 @@ struct device_operations stoneyridge_i2c_mmio_ops = { .acpi_name = i2c_acpi_name, .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, }; + +/* + * I2C pins are open drain with external pull up, so in order to bit bang them + * all, SCL pins must become GPIO inputs with no pull, then they need to be + * toggled between input-no-pull and output-low. This table is for the initial + * conversion of all SCL pins to input with no pull. + */ +static const struct soc_amd_gpio i2c_2_gpi[] = { + PAD_GPI(I2C0_SCL_PIN, PULL_NONE), + PAD_GPI(I2C1_SCL_PIN, PULL_NONE), + PAD_GPI(I2C2_SCL_PIN, PULL_NONE), + PAD_GPI(I2C3_SCL_PIN, PULL_NONE), +}; +#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) + +/* + * To program I2C pins without destroying their programming, the registers + * that will be changed need to be saved first. + */ +static void save_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + save_table->mux_value = iomux_read8(gpio); + save_table->control_value = read32(gpio_ptr); +} + +static void restore_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + iomux_write8(gpio, save_table->mux_value); + iomux_read8(gpio); + write32(gpio_ptr, save_table->control_value); + read32(gpio_ptr); +} + +/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ +void sb_reset_i2c_slaves(void) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + struct soc_amd_i2c_save save_table[saved_pins_count]; + uint8_t i, j, control; + + if (!dev || !dev->chip_info) + return; + cfg = dev->chip_info; + control = cfg->i2c_scl_reset & GPIO_I2C_MASK; + if (control == 0) + return; + + /* Save and reprogram I2C SCL pins */ + for (i = 0; i < saved_pins_count; i++) + save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); + sb_program_gpios(i2c_2_gpi, saved_pins_count); + + /* + * Toggle SCL back and forth 9 times under 100KHz. A single read is + * needed after the writes to force the posted write to complete. + */ + for (j = 0; j < 9; j++) { + if (control & GPIO_I2C0_SCL) + write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C1_SCL) + write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C2_SCL) + write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C3_SCL) + write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + + read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ + + if (control & GPIO_I2C0_SCL) + write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C1_SCL) + write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C2_SCL) + write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C3_SCL) + write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + + read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + udelay(4); + } + + /* Restore I2C pins. */ + for (i = 0; i < saved_pins_count; i++) + restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); +} diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index fe8240fb11a..26d0336d0a6 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -36,21 +36,10 @@ struct soc_amd_event { uint8_t event; }; -struct soc_amd_i2c_save { - uint32_t control_value; - uint8_t mux_value; -}; - #define GPIO_MASTER_SWITCH 0xFC #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) -#define GPIO_I2C0_SCL BIT(0) -#define GPIO_I2C1_SCL BIT(1) -#define GPIO_I2C2_SCL BIT(2) -#define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - #define GPIO_TOTAL_PINS 149 #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ @@ -186,15 +175,6 @@ struct soc_amd_i2c_save { #define GPIO_147 147 #define GPIO_148 148 -#define I2C0_SCL_PIN GPIO_145 -#define I2C1_SCL_PIN GPIO_147 -#define I2C2_SCL_PIN GPIO_113 -#define I2C3_SCL_PIN GPIO_19 - -#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) -#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) -#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) #define GPIO_SCL_HIGH 0 #define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE @@ -373,11 +353,6 @@ struct soc_amd_i2c_save { #define GPIO_148_IOMUX_I2C1_SDA 0 #define GPIO_148_IOMUX_GPIOxx 1 -#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx -#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx -#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx -#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx - enum { GEVENT_0, GEVENT_1, @@ -599,7 +574,6 @@ uintptr_t gpio_get_address(gpio_t gpio_num); * @return none */ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); -void sb_reset_i2c_slaves(void); /* Return the interrupt status and clear if set. */ int gpio_interrupt_status(gpio_t gpio); diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h new file mode 100644 index 00000000000..62575d0fb84 --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_I2C_H__ +#define __STONEYRIDGE_I2C_H__ + +#include + +struct soc_amd_i2c_save { + uint32_t control_value; + uint8_t mux_value; +}; + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_113 +#define I2C3_SCL_PIN GPIO_19 + +#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) +#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) +#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) +#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void sb_reset_i2c_slaves(void); + +#endif /* __STONEYRIDGE_I2C_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 613dd044f60..1caef3362fc 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,30 +22,19 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +#include + /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */ -#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define APU_SMI_BASE 0xfed80200 -#define PM_MMIO_BASE 0xfed80300 -#define BIOSRAM_MMIO_BASE 0xfed80500 -#define ACPI_REG_MMIO_BASE 0xfed80800 -#define ASF_MMIO_BASE 0xfed80900 -#define SMBUS_MMIO_BASE 0xfed80a00 -#define GPIO_IOMUX_MMIO_BASE 0xfed80d00 -#define MISC_MMIO_BASE 0xfed80e00 -#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 -#define GPIO_CONTROL_MMIO_BASE 0xfed81500 -#define AOAC_MMIO_BASE 0xfed81e00 - #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 @@ -68,8 +57,6 @@ #define PM2_DATA 0xcd1 #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 563dae09e11..60a6ea22bbe 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -18,6 +18,7 @@ #define __PI_STONEYRIDGE_NORTHBRIDGE_H__ #include +#include /* D0F0 - Root Complex */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9fa93c82451..6734efb04d1 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -483,7 +483,6 @@ void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_lpc_port80(void); void sb_lpc_decode(void); -void sb_acpi_mmio_decode(void); void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); @@ -491,42 +490,8 @@ void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); -u8 pm_read8(u8 reg); -u16 pm_read16(u8 reg); -u32 pm_read32(u8 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -void pm_write32(u8 reg, u32 value); -u8 acpi_read8(u8 reg); -u16 acpi_read16(u8 reg); -u32 acpi_read32(u8 reg); -void acpi_write8(u8 reg, u8 value); -void acpi_write16(u8 reg, u16 value); -void acpi_write32(u8 reg, u32 value); -u32 misc_read32(u8 reg); -void misc_write32(u8 reg, u32 value); -uint8_t smi_read8(uint8_t offset); -uint16_t smi_read16(uint8_t offset); -uint32_t smi_read32(uint8_t offset); -void smi_write8(uint8_t offset, uint8_t value); -void smi_write16(uint8_t offset, uint16_t value); -void smi_write32(uint8_t offset, uint32_t value); -uint8_t biosram_read8(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); -uint16_t biosram_read16(uint8_t offset); -void biosram_write16(uint8_t offset, uint16_t value); -uint32_t biosram_read32(uint8_t offset); -void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); -void xhci_pm_write8(uint8_t reg, uint8_t value); -uint8_t xhci_pm_read8(uint8_t reg); -void xhci_pm_write16(uint8_t reg, uint16_t value); -uint16_t xhci_pm_read16(uint8_t reg); -void xhci_pm_write32(uint8_t reg, uint32_t value); -uint32_t xhci_pm_read32(uint8_t reg); -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value); -uint8_t smbus_read8(uint32_t mmio, uint8_t reg); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index e3475eebcb6..3ace1fdce65 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -25,9 +25,9 @@ #include #include #include -#include #include #include +#include #include #include #include @@ -36,31 +36,22 @@ static void lpc_init(struct device *dev) { u8 byte; - u32 dword; - - /* - * Enable the LPC Controller - * SMBus register 0x64 is not defined in public datasheet. - */ - dword = pci_read_config32(SOC_SMBUS_DEV, 0x64); - dword |= 1 << 20; - pci_write_config32(SOC_SMBUS_DEV, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL); + byte = pci_read_config8(dev, LPC_PCI_CONTROL); byte |= LEGACY_DMA_EN; - pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte); + pci_write_config8(dev, LPC_PCI_CONTROL, byte); /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; - pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte); + pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); /* Disable LPC MSI Capability */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS); + byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); @@ -70,15 +61,15 @@ static void lpc_init(struct device *dev) * interrupt and visit LPC. */ byte &= ~LPC_NOHOG; - pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte); + pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* * Enable hand-instance of the pulse generator and SPI * controller prefetch of flash. */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL); + byte = pci_read_config8(dev, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; - pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte); + pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); @@ -162,9 +153,8 @@ static void lpc_set_resources(struct device *dev) pci_dev_set_resources(dev); } -static void set_child_resource(struct device *child, - u32 *reg, - u32 *reg_x) +static void set_child_resource(struct device *dev, struct device *child, + u32 *reg, u32 *reg_x) { struct resource *res; u32 base, end; @@ -273,7 +263,7 @@ static void set_child_resource(struct device *child, wideio_index = sb_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { /* preserve wide IO related bits. */ - *reg_x = pci_read_config32(SOC_LPC_DEV, + *reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); printk(BIOS_DEBUG, @@ -309,11 +299,8 @@ static void lpc_enable_childrens_resources(struct device *dev) for (child = link->children; child; child = child->sibling) { if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - set_child_resource(child, - ®, - ®_x); - } + && (child->path.type == DEVICE_PATH_PNP)) + set_child_resource(dev, child, ®, ®_x); } } pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); @@ -326,12 +313,6 @@ static void lpc_enable_resources(struct device *dev) lpc_enable_childrens_resources(dev); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 927cce0c1f7..5985832c81e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -13,13 +13,11 @@ * GNU General Public License for more details. */ - #include #include #include #include #include -#include #include #include #include @@ -42,6 +40,8 @@ #include #include +#include "chip.h" + static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -176,6 +176,18 @@ static void northbridge_init(struct device *dev) setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); + + return current; +} + static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -391,7 +403,7 @@ void domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ if (!romstage_handoff_is_resume()) - do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid"); + do_agesawrapper(AMD_INIT_MID, "amdinitmid"); } void domain_set_resources(struct device *dev) diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index bfb5f424efc..7367251193b 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index edd5c2394e5..7c855bb1e18 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -24,7 +25,8 @@ #include #include #include -#include +#include +#include void backup_top_of_low_cacheable(uintptr_t ramtop) { diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 34aa576a095..ec5ee910d9d 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -20,6 +20,7 @@ #include #include #include +#include #include void set_warm_reset_flag(void) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index f2263b7aa91..12ee2a8aca3 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -35,6 +34,8 @@ #include #include +#include "chip.h" + void __weak mainboard_romstage_entry(int s3_resume) { /* By default, don't do anything */ @@ -65,11 +66,11 @@ static void load_smu_fw1(void) static void agesa_call(void) { post_code(0x37); - do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); + do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); post_code(0x38); /* APs will not exit amdinitearly */ - do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); + do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } static void bsp_agesa_call(void) @@ -102,7 +103,7 @@ asmlinkage void car_stage_entry(void) if (!s3_resume) { post_code(0x40); - do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost"); + do_agesawrapper(AMD_INIT_POST, "amdinitpost"); post_code(0x41); /* @@ -137,7 +138,7 @@ asmlinkage void car_stage_entry(void) } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(agesawrapper_amdinitresume, "amdinitresume"); + do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); post_code(0x61); } diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index b60f186ac89..11bf73a7231 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -16,152 +16,9 @@ #include #include #include +#include #include -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(MISC_MMIO_BASE + reg), value); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(MISC_MMIO_BASE + reg)); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(PM_MMIO_BASE + reg), value); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(PM_MMIO_BASE + reg)); -} - -u8 acpi_read8(u8 reg) -{ - return read8((void *)(ACPI_REG_MMIO_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPI_REG_MMIO_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPI_REG_MMIO_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPI_REG_MMIO_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPI_REG_MMIO_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPI_REG_MMIO_BASE + reg), value); -} - -void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(APU_SMI_BASE + offset), value); -} - -uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(APU_SMI_BASE + offset)); -} - -uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(APU_SMI_BASE + offset)); -} - -void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(APU_SMI_BASE + offset), value); -} - -uint8_t smi_read8(uint8_t offset) -{ - return read8((void *)(APU_SMI_BASE + offset)); -} - -void smi_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(APU_SMI_BASE + offset), value); -} - -uint8_t biosram_read8(uint8_t offset) -{ - return read8((void *)(BIOSRAM_MMIO_BASE + offset)); -} - -void biosram_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(BIOSRAM_MMIO_BASE + offset), value); -} - -/* BiosRam may only be accessed a byte at a time */ -uint16_t biosram_read16(uint8_t offset) -{ - int i; - uint16_t value = 0; - for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | biosram_read8(offset + i); - return value; -} - -uint32_t biosram_read32(uint8_t offset) -{ - uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; - return value | biosram_read16(offset); -} - -void biosram_write16(uint8_t offset, uint16_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -void biosram_write32(uint8_t offset, uint32_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - uint16_t pm_acpi_pm_cnt_blk(void) { return pm_read16(PM1_CNT_BLK); @@ -172,46 +29,6 @@ uint16_t pm_acpi_pm_evt_blk(void) return pm_read16(PM_EVT_BLK); } -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); -} - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); -} - -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) -{ - write8((void *)(mmio + reg), value); -} - -uint8_t smbus_read8(uint32_t mmio, uint8_t reg) -{ - return read8((void *)(mmio + reg)); -} - int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 9344b2f1805..803e6283202 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -42,9 +42,9 @@ static u32 get_sm_mmio(struct device *dev) pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, 0x90); if (res->base == SMB_BASE_ADDR) - return SMBUS_MMIO_BASE; + return ACPIMMIO_SMBUS_BASE; - return ASF_MMIO_BASE; + return ACPIMMIO_ASF_BASE; } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index c4a022a9a96..df7a86edc7e 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -15,21 +15,52 @@ #include #include +#include +#include #include #include +static u8 controller_read8(u32 base, u8 reg) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + return smbus_read8(reg); + case ACPIMMIO_ASF_BASE: + return asf_read8(reg); + default: + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + base); + } + return 0xff; +} + +static void controller_write8(u32 base, u8 reg, u8 val) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + smbus_write8(reg, val); + break; + case ACPIMMIO_ASF_BASE: + asf_write8(reg, val); + break; + default: + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + base); + } +} + static int smbus_wait_until_ready(u32 mmio) { u32 loops; loops = SMBUS_TIMEOUT; do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; if (val == 0) { /* ready now */ return 0; } - smbus_write8(mmio, SMBHSTSTAT, val); + controller_write8(mmio, SMBHSTSTAT, val); } while (--loops); return -2; /* time out */ } @@ -41,12 +72,12 @@ static int smbus_wait_until_done(u32 mmio) do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ if (val & SMBHST_STAT_ERROR_BITS) return -5; /* error */ if (val == SMBHST_STAT_NOERROR) { - smbus_write8(mmio, SMBHSTSTAT, val); /* clear sts */ + controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ return 0; } } while (--loops); @@ -61,19 +92,19 @@ int do_smbus_recv_byte(u32 mmio, u8 device) return -2; /* not ready */ /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -86,15 +117,15 @@ int do_smbus_send_byte(u32 mmio, u8 device, u8 val) return -2; /* not ready */ /* set the command... */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) @@ -111,22 +142,22 @@ int do_smbus_read_byte(u32 mmio, u8 device, u8 address) return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -139,18 +170,18 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); /* output value */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 63b457c2c86..e57ecde5780 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -45,7 +46,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0); + error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -55,7 +56,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr); + error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index 5ddc0dda624..4a0d833c7bb 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -19,6 +19,7 @@ */ #include +#include #include #include diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 91b86e284e6..8759e2acb1f 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -21,6 +21,7 @@ #include #include #include +#include void configure_smi(uint8_t smi_num, uint8_t mode) { diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c3f4b675dc3..c3aed578ffc 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -24,6 +24,7 @@ #include #include #include +#include #include /* bits in smm_io_trap */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2f32c5c86eb..84db3dd76c5 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -14,8 +14,6 @@ */ #include - -#include #include #include #include @@ -28,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +35,7 @@ #include #include #include +#include /* * Table of devices that need their AOAC registers enabled and waited @@ -279,20 +279,18 @@ int sb_set_wideio_range(uint16_t start, uint16_t size) static void power_on_aoac_device(int aoac_device_control_register) { uint8_t byte; - uint8_t *register_pointer = (uint8_t *)(uintptr_t)AOAC_MMIO_BASE - + aoac_device_control_register; /* Power on the UART and AMBA devices */ - byte = read8(register_pointer); + byte = aoac_read8(aoac_device_control_register); byte |= FCH_AOAC_PWR_ON_DEV; - write8(register_pointer, byte); + aoac_write8(aoac_device_control_register, byte); } static bool is_aoac_device_enabled(int aoac_device_status_register) { uint8_t byte; - byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE - + aoac_device_status_register); + + byte = aoac_read8(aoac_device_status_register); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -331,11 +329,9 @@ void sb_lpc_port80(void) u8 byte; /* Enable LPC controller */ - outb(PM_LPC_GATING, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_LPC_GATING); byte |= PM_LPC_ENABLE; - outb(PM_LPC_GATING, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_LPC_GATING, byte); /* Enable port 80 LPC decode in pci function 3 configuration space. */ byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); @@ -364,18 +360,6 @@ void sb_lpc_decode(void) pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); } -void sb_acpi_mmio_decode(void) -{ - uint8_t byte; - - /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ - outb(PM_ISA_CONTROL, PM_INDEX); - byte = inb(PM_DATA); - byte |= MMIO_EN; - outb(PM_ISA_CONTROL, PM_INDEX); - outb(byte, PM_DATA); -} - static void sb_enable_cf9_io(void) { uint32_t reg = pm_read32(PM_DECODE_EN); @@ -393,14 +377,12 @@ static void sb_enable_legacy_io(void) void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; - u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE - + MISC_CLK_CNTL1); /* * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. */ - ctrl = read32(misc_clk_cntl_1_ptr); + ctrl = misc_read32(MISC_CLK_CNTL1); switch (osc) { case 1: @@ -412,7 +394,7 @@ void sb_clk_output_48Mhz(u32 osc) default: return; /* do nothing if invalid */ } - write32(misc_clk_cntl_1_ptr, ctrl); + misc_write32(MISC_CLK_CNTL1, ctrl); } static uintptr_t sb_spibase(void) @@ -632,12 +614,12 @@ static void setup_misc(int *reboot) static void fch_smbus_init(void) { pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBUS_MMIO_BASE, SMBTIMING, SMB_SPEED_400KHZ); + smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); /* Clear all SMBUS status bits */ - smbus_write8(SMBUS_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(SMBUS_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); - smbus_write8(ASF_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(ASF_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); + smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); + asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); } /* Before console init */ @@ -651,7 +633,7 @@ void bootblock_fch_early_init(void) sb_lpc_early_setup(); sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - sb_acpi_mmio_decode(); + enable_acpimmio_decode(); fch_smbus_init(); sb_enable_cf9_io(); setup_spread_spectrum(&reboot); @@ -927,9 +909,9 @@ static void set_sb_final_nvs(void) gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); - gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0; + gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); - gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index f2fa3ba267b..00f82375e83 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -22,7 +22,7 @@ #include #include #include - +#include static void set_usb_over_current(struct device *dev) { diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 6e0cb9c7313..6659cdf3bc1 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -23,7 +23,6 @@ #include #include #include -#include #define CAVM_PCCPF_XXX_VSEC_CTL 0x108 #define CAVM_PCCPF_XXX_VSEC_SCTL 0x10c diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 98166b056f7..f1e11d335b4 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -149,7 +149,7 @@ static void dt_platform_fixup_mac(struct device_tree_node *node) if (*localmac) return; if (used_mac < num_free_mac_addresses) { - const u64 genmac = next_free_mac_address + used_mac; + u64 genmac = next_free_mac_address + used_mac; dt_add_bin_prop(node, name, &genmac, 6); used_mac++; return; @@ -185,7 +185,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, size_t i; /* Set the sclk clock rate. */ - dt_node = dt_find_node_by_path(tree->root, "soc@0/sclk", NULL, NULL, 0); + dt_node = dt_find_node_by_path(tree, "/soc@0/sclk", NULL, NULL, 0); if (dt_node) { const u32 freq = thunderx_get_io_clock(); printk(BIOS_INFO, "%s: Set SCLK to %u Hz\n", __func__, freq); @@ -195,7 +195,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, __func__); /* Set refclkuaa clock rate. */ - dt_node = dt_find_node_by_path(tree->root, "soc@0/refclkuaa", NULL, + dt_node = dt_find_node_by_path(tree, "/soc@0/refclkuaa", NULL, NULL, 0); if (dt_node) { const u32 freq = uart_platform_refclk(); @@ -211,8 +211,8 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, char path[32]; const uint64_t addr = UAAx_PF_BAR0(i); /* Remove the node */ - snprintf(path, sizeof(path), "soc@0/serial@%llx", addr); - dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + snprintf(path, sizeof(path), "/soc@0/serial@%llx", addr); + dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node || uart_is_enabled(i)) { printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); continue; @@ -227,20 +227,20 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, u32 phandle = 0; const uint64_t addr = PEM_PEMX_PF_BAR0(i); /* Remove the node */ - snprintf(path, sizeof(path), "soc@0/pci@%llx", addr); - dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + snprintf(path, sizeof(path), "/soc@0/pci@%llx", addr); + dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node || bdk_pcie_is_running(0, i)) { printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); continue; } /* Store the phandle */ - phandle = dt_get_phandle(dt_node); + phandle = dt_node->phandle; printk(BIOS_INFO, "%s: Removing node %s\n", __func__, path); list_remove(&dt_node->list_node); /* Remove phandle to non existing nodes */ - snprintf(path, sizeof(path), "soc@0/smmu0@%llx", SMMU_PF_BAR0); - dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + snprintf(path, sizeof(path), "/soc@0/smmu0@%llx", SMMU_PF_BAR0); + dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node) { printk(BIOS_ERR, "%s: SMMU entry not found\n", __func__); diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index d29bcda121b..7137531d490 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index c3f08668594..0c3b367891e 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -34,16 +34,12 @@ __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } void bootblock_main(const uint64_t reg_x0, const uint64_t reg_pc) { - uint64_t base_timestamp = 0; init_timer(); - if (CONFIG(COLLECT_TIMESTAMPS)) - base_timestamp = timestamp_get(); - /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) - timestamp_init(base_timestamp); + timestamp_init(timestamp_get()); bootblock_soc_early_init(); bootblock_mainboard_early_init(); diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index aaf9085ccfa..ae2a91fe0d9 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -22,7 +22,6 @@ #include #include #include -#include /** * Get PCI BAR address from cavium specific extended capability. diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d715f39eb40..1f819eab063 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -20,6 +20,7 @@ if SOC_INTEL_APOLLOLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_NO_PCAT_8259 select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -118,7 +119,7 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS @@ -360,6 +361,11 @@ config CPU_BCLK_MHZ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xddffc000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + config APL_SKIP_SET_POWER_LIMITS bool default n diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 07cb2adef79..6208c9c739d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -18,8 +18,10 @@ #include #include +#include #include #include +#include #include #include #include @@ -34,6 +36,7 @@ #include #include #include + #include "chip.h" #define CSTATE_RES(address_space, width, offset, address) \ diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl index ec1844a512c..f3202a0c48b 100644 --- a/src/soc/intel/apollolake/acpi/platform.asl +++ b/src/soc/intel/apollolake/acpi/platform.asl @@ -18,19 +18,3 @@ /* Enable ACPI _SWS methods */ #include #include - -Name(\PICM, Zero) // IOAPIC/8259 - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c3de4ee8023..e9030dc2df6 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -50,6 +50,7 @@ #include #include #include +#include #include "chip.h" @@ -388,12 +389,16 @@ static void set_sci_irq(void) static void soc_init(void *data) { - struct global_nvs_t *gnvs; - /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + fsp_silicon_init(romstage_handoff_is_resume()); /* Restore GPIO IRQ polarities back to previous settings. */ @@ -411,7 +416,7 @@ static void soc_init(void *data) p2sb_unhide(); /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); /* Set RAPL MSR for Package power limits*/ set_power_limits(); @@ -762,6 +767,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Set VTD feature according to devicetree */ silconfig->VtdEnable = cfg->enable_vtd; + + mainboard_silicon_init_params(silconfig); } struct chip_operations soc_intel_apollolake_ops = { @@ -879,4 +886,10 @@ static void spi_flash_init_cb(void *unused) fast_spi_init(); } +__weak +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 11d15e4f13f..aad0f6b5225 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -76,7 +76,7 @@ void soc_core_init(struct device *cpu) scope. For now every CPU clears every bank. */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || acpi_get_sleep_type() == ACPI_S5) - mca_configure(NULL); + mca_configure(); /* Set core MSRs */ reg_script_run(core_msr_script); @@ -119,6 +119,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { 0, 0 }, }; diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index 265e613d61e..10b7ba635bb 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -58,6 +57,8 @@ static const struct pad_community apl_gpio_communities[] = { .gpi_status_offset = 0, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -75,6 +76,8 @@ static const struct pad_community apl_gpio_communities[] = { .gpi_status_offset = NUM_SW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -92,6 +95,8 @@ static const struct pad_community apl_gpio_communities[] = { .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -110,6 +115,8 @@ static const struct pad_community apl_gpio_communities[] = { + NUM_SW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index 037273c3fa2..014751905ff 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -58,6 +57,8 @@ static const struct pad_community glk_gpio_communities[] = { .gpi_status_offset = 0, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -75,6 +76,8 @@ static const struct pad_community glk_gpio_communities[] = { .gpi_status_offset = NUM_NW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -92,6 +95,8 @@ static const struct pad_community glk_gpio_communities[] = { .gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -110,6 +115,8 @@ static const struct pad_community glk_gpio_communities[] = { NUM_AUDIO_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 51661d0cfc0..f5136ec103b 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -26,6 +26,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/apollolake/include/soc/gpio_apl.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h index 67c8a756b6b..ecd9101e76e 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_apl.h +++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h @@ -49,6 +49,7 @@ #define PAD_CFG_BASE 0x500 +#define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x140 diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h index f1ae49e4577..54ce9526096 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_glk.h +++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h @@ -282,6 +282,7 @@ */ #define HOSTSW_OWN_REG_0 0xB0 +#define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x170 diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 8e2986d8b70..4b823652844 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -58,12 +58,4 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xddffc000 -/* UART BARs are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h new file mode 100644 index 00000000000..287f2ff9451 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/ramstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * Copyright (C) 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_RAMSTAGE_H_ +#define _SOC_APOLLOLAKE_RAMSTAGE_H_ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig); + +#endif /* _SOC_APOLLOLAKE_RAMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 038fa9fb2b5..219b6610424 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -12,7 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include #include #include #include @@ -21,11 +20,11 @@ #include #include -static size_t memory_size_mib CAR_GLOBAL; +static size_t memory_size_mib; size_t memory_in_system_in_mib(void) { - return car_get_var(memory_size_mib); + return memory_size_mib; } static void accumulate_channel_memory(int density, int dual_rank) @@ -61,7 +60,7 @@ static void accumulate_channel_memory(int density, int dual_rank) sz *= GiB / MiB; - car_set_var(memory_size_mib, car_get_var(memory_size_mib) + sz); + memory_size_mib += sz; } size_t iohole_in_mib(void) diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index a11c5d8031f..b272a99efed 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -90,6 +90,7 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) src_dimm->DimmId, dram_part_num, strlen(dram_part_num), + NULL, /* SPD not available */ memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 9bfdf0b8a51..29dcd56767c 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -96,6 +96,7 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) src_dimm->DimmId, dram_part_num, strlen(dram_part_num), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ba1433c53b7..6058e348958 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -17,13 +17,15 @@ #include #include -#include "chip.h" +#include #include #include #include #include #include +#include "chip.h" + void *cbmem_top(void) { const struct device *dev; @@ -38,7 +40,8 @@ void *cbmem_top(void) config = dev->chip_info; if (!config) - die("Failed to get chip_info\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Failed to get chip_info\n"); /* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 1c3077ed91b..614b6031c4d 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -57,17 +56,17 @@ * */ -static size_t bios_size CAR_GLOBAL; +static size_t bios_size; -static struct mem_region_device shadow_dev CAR_GLOBAL; -static struct xlate_region_device real_dev CAR_GLOBAL; +static struct mem_region_device shadow_dev; +static struct xlate_region_device real_dev; static void bios_mmap_init(void) { size_t size, start, bios_mapped_size; uintptr_t base; - size = car_get_var(bios_size); + size = bios_size; /* If bios_size is initialized, then bail out. */ if (size != 0) @@ -83,34 +82,25 @@ static void bios_mmap_init(void) */ bios_mapped_size = size - 256 * KiB; - struct mem_region_device *shadow_dev_ptr; - struct xlate_region_device *real_dev_ptr; - shadow_dev_ptr = car_get_var_ptr(&shadow_dev); - real_dev_ptr = car_get_var_ptr(&real_dev); - - mem_region_device_ro_init(shadow_dev_ptr, (void *)base, + mem_region_device_ro_init(&shadow_dev, (void *)base, bios_mapped_size); - xlate_region_device_ro_init(real_dev_ptr, &shadow_dev_ptr->rdev, + xlate_region_device_ro_init(&real_dev, &shadow_dev.rdev, start, bios_mapped_size, CONFIG_ROM_SIZE); - car_set_var(bios_size, size); + bios_size = size; } const struct region_device *boot_device_ro(void) { bios_mmap_init(); - struct xlate_region_device *real_dev_ptr; - real_dev_ptr = car_get_var_ptr(&real_dev); - - return &real_dev_ptr->rdev; + return &real_dev.rdev; } static int iafw_boot_region_properties(struct cbfs_props *props) { - struct xlate_region_device *real_dev_ptr; struct region *real_dev_reg; struct region regn; @@ -123,8 +113,7 @@ static int iafw_boot_region_properties(struct cbfs_props *props) /* Check that we are within the memory mapped area. It's too easy to forget the SRAM mapping when crafting an FMAP file. */ - real_dev_ptr = car_get_var_ptr(&real_dev); - real_dev_reg = &real_dev_ptr->sub_region; + real_dev_reg = &real_dev.sub_region; if (region_is_subregion(real_dev_reg, ®n)) { printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index c976ac2d6f0..5bf501dcfa6 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include @@ -57,7 +56,7 @@ static const uint8_t hob_variable_guid[16] = { 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, }; -static uint32_t fsp_version CAR_GLOBAL; +static uint32_t fsp_version; /* High Performance Event Timer Configuration */ #define P2SB_HPTC 0x60 @@ -236,7 +235,7 @@ asmlinkage void car_stage_entry(void) &var_size); if (new_var_data) mrc_cache_stash_data(MRC_VARIABLE_DATA, - car_get_var(fsp_version), new_var_data, + fsp_version, new_var_data, var_size); else printk(BIOS_ERR, "Failed to determine variable data\n"); @@ -410,7 +409,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); } - car_set_var(fsp_version, version); + fsp_version = version; } diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index e8e26612438..27be4e65f9c 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -20,7 +20,7 @@ * shouldn't cause any fragmentation. */ -#include +#include #include #include #include diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index a83a7e9ee6d..43c2906f151 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -43,7 +43,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_HAS_L2_ENABLE_MSR config VBOOT - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT @@ -168,4 +168,14 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "8086,0f31" + +config VGA_BIOS_FILE + string + depends on VGA_BIOS + default "pci8086,0f31.rom" + endif diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 0d4bac51406..6e6eb9cc44c 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,6 +16,8 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-y += spi.c ramstage-y += chip.c diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index d2cb589db8f..2048c138246 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "chip.h" diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3e8b6a27ef8..fffce7e317d 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -37,7 +37,6 @@ void gfx_init(void); void tco_disable(void); void punit_init(void); void set_max_freq(void); -int early_spi_read_wpsr(u8 *sr); #if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463d201..d43a6fb6e34 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -5,4 +5,3 @@ romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c -romstage-y += early_spi.c diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c deleted file mode 100644 index 72e9b2cdae1..00000000000 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ - -#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) -#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) -#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) - -/* Minimal set of commands to read wpsr from SPI. Don't use this code outside - * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. */ -int early_spi_read_wpsr(u8 *sr) -{ - int timeout = SPI_CYCLE_TIMEOUT; - - /* No address associated with rdsr */ - SPI8(OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPI8(OPMENU0) = 0x5; - - /* Start transaction */ - SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; - - /* Wait for error / complete status */ - while (timeout--) { - u16 status = SPI16(SSFS); - if (status & FLASH_CYCLE_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & CYCLE_DONE_STATUS) - break; - - udelay(SPI_CYCLE_DELAY); - } - - *sr = SPI32(FDATA0) & 0xff; - return 0; -} diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 8db47955a6b..ed5c9728a3e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -53,7 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_SMBUS config VBOOT - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT @@ -135,4 +135,18 @@ config DISABLE_HPET Enable this to disable the HPET support Solves the Linux MP-BIOS bug timer not connected. +config USE_GOOGLE_FSP + bool + help + Select this to use Google's custom Braswell FSP header/binary + instead of the public release on Github. Only google/cyan + variants require this; all other boards should use the public release. + +config FSP_HEADER_PATH + string + default "$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP + default "3rdparty/fsp/BraswellFspBinPkg/Include/" + help + Location of FSP header file FspUpdVpd.h + endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index a538f7daff6..e479a3c5e55 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -14,8 +14,13 @@ romstage-y += iosf.c romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += smbus.c +romstage-y += spi.c romstage-y += tsc_freq.c +postcar-y += memmap.c +postcar-y += iosf.c +postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c @@ -52,11 +57,12 @@ smm-y += smihandler.c smm-y += spi.c smm-y += tsc_freq.c -# cpu_microcode_bins += ??? +verstage-y += pmutil.c +verstage-y += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell +CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)) CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index c0b0b8d3d85..9bd9afc924b 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -31,7 +31,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, /* 0x00 - Operating System */ SMIF, 8, /* 0x02 - SMI function */ PRM0, 8, /* 0x03 - SMI function parameter */ @@ -55,7 +54,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CID1, 16, /* 0x1e - Wifi Domain Type */ /* Device Config */ - Offset (0x20), S5U0, 8, /* 0x20 - Enable USB0 in S5 */ S5U1, 8, /* 0x21 - Enable USB1 in S5 */ S3U0, 8, /* 0x22 - Enable USB0 in S3 */ diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 4cc93cc2d2a..f9b376ccb30 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -522,115 +523,6 @@ Device (I2C7) } } -Device (SPI1) -{ - Name (_HID, "8086228E") - Name (_UID, 1) - Name (_DDN, "SPI Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_SPI_IRQ - } - FixedDMA (0x0, 0x0, Width32Bit, ) - FixedDMA (0x1, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S9B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S9EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S9B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (PWM1) -{ - Name (_HID, "80862288") - Name (_UID, 1) - Name (_DDN, "PWM Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SAB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SAEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (PWM2) -{ - Name (_HID, "80862288") - Name (_UID, 2) - Name (_DDN, "PWM Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SBB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SBEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - Device (UAR1) { Name (_HID, "8086228A") diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index f7e31681267..9ecf67a971a 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -286,7 +286,4 @@ Scope (\_SB.PCI0) /* SCC Devices */ #include "scc.asl" - - /* LPE Device */ - #include "lpe.asl" } diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 7617d536443..900b2f33fde 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -23,6 +22,8 @@ #include #include +#include "chip.h" + static void pci_domain_set_resources(struct device *dev) { printk(BIOS_SPEW, "%s/%s (%s)\n", @@ -128,36 +129,26 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; - if (config->D0Usb2Port0PerPortRXISet != 0) - params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet; params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; - if (config->D0Usb2Port1PerPortRXISet != 0) - params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet; params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; - if (config->D0Usb2Port2PerPortRXISet != 0) - params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet; params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; - if (config->D0Usb2Port3PerPortRXISet != 0) - params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet; params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; - if (config->D0Usb2Port4PerPortRXISet != 0) - params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet; params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; @@ -265,9 +256,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, old->Usb2Port0PerPortTxPeHalf, new->Usb2Port0PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1, - old->D0Usb2Port0PerPortRXISet, - new->D0Usb2Port0PerPortRXISet); fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, old->Usb2Port1PerPortPeTxiSet, new->Usb2Port1PerPortPeTxiSet); @@ -280,9 +268,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, old->Usb2Port1PerPortTxPeHalf, new->Usb2Port1PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1, - old->D0Usb2Port1PerPortRXISet, - new->D0Usb2Port1PerPortRXISet); fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, old->Usb2Port2PerPortPeTxiSet, new->Usb2Port2PerPortPeTxiSet); @@ -295,9 +280,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, old->Usb2Port2PerPortTxPeHalf, new->Usb2Port2PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1, - old->D0Usb2Port2PerPortRXISet, - new->D0Usb2Port2PerPortRXISet); fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, old->Usb2Port3PerPortPeTxiSet, new->Usb2Port3PerPortPeTxiSet); @@ -310,9 +292,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, old->Usb2Port3PerPortTxPeHalf, new->Usb2Port3PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1, - old->D0Usb2Port3PerPortRXISet, - new->D0Usb2Port3PerPortRXISet); fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, old->Usb2Port4PerPortPeTxiSet, new->Usb2Port4PerPortPeTxiSet); @@ -325,9 +304,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, old->Usb2Port4PerPortTxPeHalf, new->Usb2Port4PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1, - old->D0Usb2Port4PerPortRXISet, - new->D0Usb2Port4PerPortRXISet); fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, old->Usb3Lane0Ow2tapgen2deemph3p5, new->Usb3Lane0Ow2tapgen2deemph3p5); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 4afaf444174..5a00328f4df 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,9 +32,6 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 -#define MEM_DDR3 0 -#define MEM_LPDDR3 1 - enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, @@ -172,11 +169,6 @@ struct soc_intel_braswell_config { UINT8 I2C4Frequency; UINT8 I2C5Frequency; UINT8 I2C6Frequency; - UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/ }; extern struct chip_operations soc_intel_braswell_ops; diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h deleted file mode 100644 index 50aabed66e8..00000000000 --- a/src/soc/intel/braswell/include/soc/pei_data.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * UEFI PEI wrapper - * - * Copyright (C) 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PEI_DATA_H_ -#define _PEI_DATA_H_ - -#include - -#define PEI_VERSION 22 - -#define ABI_X86 __attribute__((regparm(0))) - -typedef void ABI_X86(*tx_byte_func)(unsigned char byte); - -struct pei_data { - /* Chip settings */ - void *spd_data_ch0; - void *spd_data_ch1; - uint8_t spd_ch0_config; - uint8_t spd_ch1_config; - - /* System state information */ - int boot_mode; - - /* Fast boot and S3 resume MRC data */ - int saved_data_size; - const void *saved_data; - int disable_saved_data; - - /* New save data from MRC */ - int data_to_save_size; - void *data_to_save; -}; - -typedef struct pei_data PEI_DATA; - -#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index d735de58856..f197bc8e1fc 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -17,10 +17,11 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include #include #include +#include "../../chip.h" + #define V_PCH_LPC_RID_A0 0x00 // A0 Stepping #define V_PCH_LPC_RID_A1 0x04 // A1 Stepping #define V_PCH_LPC_RID_A2 0x08 // A2 Stepping diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 8fa9c8a713c..4ecbd2c1f95 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -20,18 +20,19 @@ #include #include #include -#include #include void gfx_init(void); void tco_disable(void); void punit_init(void); -int early_spi_read_wpsr(u8 *sr); -void mainboard_fill_spd_data(struct pei_data *pei_data); void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); +/* Values for FSP's PcdMemoryTypeEnable */ +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 271eefed08c..4bc621b80e1 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -16,9 +16,9 @@ #include #include +#include #include #include -#include #include #include #include @@ -364,15 +364,14 @@ int rtc_failure(void) { uint32_t gen_pmcon1; int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - if (ps != NULL) - gen_pmcon1 = ps->gen_pmcon1; - else - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + /* not usable in ramstage as GEN_PMCON1 gets reset */ + if (ENV_RAMSTAGE) + dead_code(); - rtc_fail = !!(gen_pmcon1 & RPS); + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + rtc_fail = !!(gen_pmcon1 & RPS); if (rtc_fail) printk(BIOS_DEBUG, "RTC failure.\n"); diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415dcc9..3d3e407a293 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,3 @@ -romstage-y += early_spi.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c deleted file mode 100644 index 0ca5ef521fa..00000000000 --- a/src/soc/intel/braswell/romstage/early_spi.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. All rights reserved. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */ - -#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x)))) -#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x)))) -#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x)))) - -/* - * Minimal set of commands to read wpsr from SPI. Don't use this code outside - * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - int timeout = SPI_CYCLE_TIMEOUT; - - /* No address associated with rdsr */ - SPI8(OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPI8(OPMENU0) = 0x5; - - /* Start transaction */ - SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; - - /* Wait for error / complete status */ - while (timeout--) { - u16 status = SPI16(SSFS); - if (status & FLASH_CYCLE_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & CYCLE_DONE_STATUS) - break; - - udelay(SPI_CYCLE_DELAY); - } - - *sr = SPI32(FDATA0) & 0xff; - return 0; -} diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ae2eac8e202..8dfc291d1ea 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -17,12 +17,10 @@ #include #include -#include #include #include #include #include -#include #include #include #include @@ -30,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -44,6 +41,8 @@ #include #include +#include "../chip.h" + void program_base_addresses(void) { uint32_t reg; @@ -105,48 +104,44 @@ static void soc_rtc_init(void) cmos_init(rtc_failed); } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); + memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); struct chipset_power_state *fill_power_state(void) { - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); - ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); - ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); - ps->gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - ps->gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); - - ps->prev_sleep_state = chipset_prev_sleep_state(ps); + power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); + power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); + power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + + power_state.prev_sleep_state = chipset_prev_sleep_state(&power_state); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", - ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + power_state.pm1_sts, power_state.pm1_en, power_state.pm1_cnt); printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", - ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + power_state.gpe0_sts, power_state.gpe0_en, power_state.tco_sts); printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", - ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; + power_state.prsts, power_state.gen_pmcon1, power_state.gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", power_state.prev_sleep_state); + return &power_state; } /* Return 0, 3, or 5 to indicate the previous sleep state. */ diff --git a/src/mainboard/intel/saddlebrook/pei_data.c b/src/soc/intel/braswell/smbus.c similarity index 54% rename from src/mainboard/intel/saddlebrook/pei_data.c rename to src/soc/intel/braswell/smbus.c index ac4ce95723c..7e1b0dfbb03 100644 --- a/src/mainboard/intel/saddlebrook/pei_data.c +++ b/src/soc/intel/braswell/smbus.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +14,16 @@ * GNU General Public License for more details. */ -#include -#include -#include "spd/spd.h" +#include +#include +#include -void mainboard_fill_pei_data(struct pei_data *pei_data) +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) { - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); } diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 000790d9a63..bf9f689c2a3 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -347,7 +347,7 @@ static void sc_init(struct device *dev) * Common code for the south cluster devices. */ -/* Set bit in function disble register to hide this device. */ +/* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5f503da3409..d81ab8ac951 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -43,6 +43,8 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_CONSOLE select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK config PCIEXP_ASPM bool @@ -64,21 +66,25 @@ config PCIEXP_L1_SUB_STATE bool default y -config VBOOT - select VBOOT_OPROM_MATTERS - select VBOOT_STARTS_IN_ROMSTAGE - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/broadwell/bootblock/cpu.c" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/systemagent.c" +config BROADWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Broadwell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Broadwell however uses a mrc.bin to initialse memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/pch.c" +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK config MMCONF_BASE_ADDRESS hex @@ -122,6 +128,13 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a Memory Reference Code binary" help @@ -143,6 +156,13 @@ config MRC_BIN_ADDRESS hex default 0xfffa0000 +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + endif # HAVE_MRC config PRE_GRAPHICS_DELAY diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 1caf67adf4d..a79fa464a9e 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,13 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/systemagent.c +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/x86/early_reset.S + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c @@ -32,6 +39,9 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c +bootblock-y += monotonic_timer.c +romstage-y += monotonic_timer.c +postcar-y += monotonic_timer.c ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c ramstage-y += pch.c @@ -42,6 +52,7 @@ romstage-y += pei_data.c ramstage-y += pmutil.c romstage-y += pmutil.c smm-y += pmutil.c +verstage-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c @@ -52,16 +63,21 @@ romstage-y += smbus_common.c ramstage-y += smi.c smm-y += smihandler.c ramstage-y += smmrelocate.c +bootblock-y += spi.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += stage_cache.c romstage-y += stage_cache.c postcar-y += stage_cache.c ramstage-y += systemagent.c +bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c postcar-y += tsc_freq.c +verstage-y += tsc_freq.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 2f1ac51981f..f3c35f3441f 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -19,47 +19,10 @@ #include #include #include -#include #include #include - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void bootblock_mdelay(int ms) -{ - u32 target = ms * 24 * 1000; - msr_t current; - msr_t start = rdmsr(MSR_COUNTER_24_MHZ); - - do { - current = rdmsr(MSR_COUNTER_24_MHZ); - } while ((current.lo - start.lo) < target); -} +#include +#include static void set_flex_ratio_to_tdp_nominal(void) { @@ -102,7 +65,7 @@ static void set_flex_ratio_to_tdp_nominal(void) RCBA32_OR(SOFT_RESET_CTRL, 1); /* Delay before reset to avoid potential TPM lockout */ - bootblock_mdelay(30); + mdelay(30); /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); @@ -110,26 +73,8 @@ static void set_flex_ratio_to_tdp_nominal(void) halt(); } -static void check_for_clean_reset(void) -{ - msr_t msr; - msr = rdmsr(MTRR_DEF_TYPE_MSR); - - /* Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); - } -} - -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - check_for_clean_reset(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index dc7f42a6253..590961b3617 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,6 +19,10 @@ #include #include #include +#include +#include +#include +#include /* * Enable Prefetching and Caching. @@ -66,10 +70,56 @@ static void set_spi_speed(void) SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } -static void bootblock_southbridge_init(void) +const struct reg_script pch_early_init_script[] = { + /* Setup southbridge BARs */ + REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), + REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), + REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), + REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), + REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), + + /* Set COM1/COM2 decode range */ + REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), + /* Enable legacy decode ranges */ + REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | + COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), + + /* Enable IOAPIC */ + REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), + /* Read back for posted write */ + REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), + + /* Set HPET address and enable it */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), + /* Read back for posted write */ + REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), + /* Enable HPET to start counter */ + REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), + + /* Disable reset */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), + /* TCO timer halt */ + REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), + + /* Enable upper 128 bytes of CMOS */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), + + /* Disable unused device (always) */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), + + REG_SCRIPT_END +}; + +static void pch_early_lpc(void) +{ + reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); +} + +void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); + pch_early_lpc(); } diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index e618636eb29..7aaed789ac4 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -16,8 +16,9 @@ #include #include #include +#include -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 319549df1e6..9107b23eb90 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -36,6 +36,7 @@ #include #include #include +#include #define GT_RETRY 1000 enum { @@ -513,7 +514,7 @@ static void igd_init(struct device *dev) /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { #if CONFIG(CHROMEOS) - if (display_init_required() || vboot_wants_oprom()) + if (display_init_required()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else mdelay(CONFIG_PRE_GRAPHICS_DELAY); diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 66820b21845..c0ac13497bc 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -193,4 +193,6 @@ int gpio_is_native(int gpio_num); */ unsigned int get_gpios(const int *gpio_num_array); +extern const struct gpio_config mainboard_gpio_config[]; + #endif diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 19ba2e0b643..ef8a87a4dba 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -42,7 +42,6 @@ u16 pch_type(void); int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); -void pch_log_state(void); void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 31184f9a02f..cd37cf6316b 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -18,17 +18,16 @@ #include #include +#include struct chipset_power_state; -struct pei_data; struct romstage_params { - unsigned long bist; struct chipset_power_state *power_state; - struct pei_data *pei_data; + struct pei_data pei_data; }; -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_post_raminit(struct romstage_params *params); void raminit(struct pei_data *pei_data); @@ -47,8 +46,4 @@ void intel_early_me_status(void); void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); -int early_spi_read_wpsr(u8 *sr); - -void mainboard_pre_console_init(void); #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 8438ab45db5..7679724ecec 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -502,7 +502,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) #define LPC_DEFAULT_IO_RANGE_LOWER 0 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -static inline int pch_io_range_in_default(u16 base, u16 size) +static inline int pch_io_range_in_default(int base, int size) { /* Does it start above the range? */ if (base >= LPC_DEFAULT_IO_RANGE_UPPER) diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index e1883f2ecd1..706536940de 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -23,6 +23,7 @@ #include #include #include +#include /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) @@ -31,6 +32,8 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) static uint32_t gpe0_sts[GPE0_REG_MAX]; int i; + assert(ps != NULL); + *pm1 = ps->pm1_sts & ps->pm1_en; /* Mask off GPE0 status bits that are not enabled */ diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 2d562d98efc..a53cd95cd52 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,4 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S - +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c romstage-y += pch.c romstage-y += power_state.c @@ -7,6 +6,5 @@ romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c romstage-y += smbus.c -romstage-y += spi.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index ecdadb7f9bf..ef97a1e3fa2 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -27,46 +27,6 @@ #include #include -const struct reg_script pch_early_init_script[] = { - /* Setup southbridge BARs */ - REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), - REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), - REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), - REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), - REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), - - /* Set COM1/COM2 decode range */ - REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), - /* Enable legacy decode ranges */ - REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | - COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), - - /* Enable IOAPIC */ - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), - /* Read back for posted write */ - REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), - - /* Set HPET address and enable it */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), - /* Read back for posted write */ - REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), - /* Enable HPET to start counter */ - REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), - - /* Disable reset */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), - /* TCO timer halt */ - REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), - - /* Enable upper 128 bytes of CMOS */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), - - /* Disable unused device (always) */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), - - REG_SCRIPT_END -}; - const struct reg_script pch_interrupt_init_script[] = { /* * GFX INTA -> PIRQA (MSI) @@ -132,7 +92,6 @@ static void pch_enable_lpc(void) void pch_early_init(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); pch_enable_lpc(); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8d43907f8aa..c13761df3a4 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -45,6 +45,8 @@ void raminit(struct pei_data *pei_data) struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; + struct cbfsf f; + uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -77,7 +79,10 @@ void raminit(struct pei_data *pei_data) } /* Determine if mrc.bin is in the cbfs. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ + entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); if (entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; @@ -117,6 +122,12 @@ void raminit(struct pei_data *pei_data) printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + + if (!mem_info) { + printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); /* Translate pei_memory_info struct data into memory_info struct */ mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2531665f1fb..9bca716447b 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,17 +16,18 @@ #include #include #include -#include #include #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -38,7 +39,7 @@ /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -62,35 +63,19 @@ static void platform_enter_postcar(void) run_postcar_phase(&pcf); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +/* Entry from cpu/intel/car/romstage.c. */ +void mainboard_romstage_entry(unsigned long bist) { - struct romstage_params rp = { - .bist = bist, - .pei_data = NULL, - }; + struct romstage_params rp = { 0 }; post_code(0x30); - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - /* System Agent Early Initialization */ systemagent_early_init(); /* PCH Early Initialization */ pch_early_init(); - /* Call into mainboard pre console init. Needed to enable serial port - on IT8772 */ - mainboard_pre_console_init(); - - /* Start console drivers */ - console_init(); - /* Get power state */ rp.power_state = fill_power_state(); @@ -100,47 +85,35 @@ static void romstage_main(uint64_t tsc, uint32_t bist) /* Set CPU frequency to maximum */ set_max_freq(); - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); - - platform_enter_postcar(); -} + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); -} + /* Fill in mainboard pei_date. */ + mainboard_pre_raminit(&rp); -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); - params->pei_data->boot_mode = params->power_state->prev_sleep_state; + rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; -#if CONFIG(ELOG_BOOT_COUNT) - if (params->power_state->prev_sleep_state != ACPI_S3) + if (CONFIG(ELOG_BOOT_COUNT) + && rp.power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); -#endif /* Print ME state before MRC */ intel_me_status(); /* Save ME HSIO version */ - intel_me_hsio_version(¶ms->power_state->hsio_version, - ¶ms->power_state->hsio_checksum); + intel_me_hsio_version(&rp.power_state->hsio_version, + &rp.power_state->hsio_checksum); /* Initialize RAM */ - raminit(params->pei_data); + raminit(&rp.pei_data); timestamp_add_now(TS_AFTER_INITRAM); - romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); -} + romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); -void __weak mainboard_pre_console_init(void) {} + mainboard_post_raminit(&rp); +} diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c deleted file mode 100644 index cb0509d104d..00000000000 --- a/src/soc/intel/broadwell/romstage/spi.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32 *)buffer; - u32 i; - - /* Clear status bits */ - SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - SPIBAR32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transaction */ - SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i += sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8 *)ptr32; - u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} - -/* - * Minimal set of commands to read WPSR from SPI. - * Don't use this code outside romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - int retry; - - /* No address associated with rdsr */ - SPIBAR8(SPIBAR_OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5; - - /* Start transaction */ - SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO; - - /* Wait for error / complete status */ - for (retry = SPI_RETRY; retry; retry--) { - u16 status = SPIBAR16(SPIBAR_SSFS); - if (status & SPIBAR_SSFS_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & SPIBAR_SSFS_DONE) { - break; - } - - udelay(SPI_DELAY); - } - - *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff; - return 0; -} diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 58450dd8348..a1a29b65fdd 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 026aaf20ffd..76906b25480 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -27,8 +27,6 @@ config SOC_INTEL_WHISKEYLAKE bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE - select FSP_PEIM_TO_PEIM_INTERFACE - select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help Intel Whiskeylake support @@ -36,12 +34,6 @@ config SOC_INTEL_COMETLAKE bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE - # TODO: - # Delete FSP_PEIM_TO_PEIM_INTERFACE and - # USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection - # and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready - select FSP_PEIM_TO_PEIM_INTERFACE - select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help Intel Cometlake support @@ -98,6 +90,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA @@ -190,6 +183,11 @@ config MAX_ROOT_PORTS default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config MAX_PCIE_CLOCKS + int + default 16 if SOC_INTEL_CANNONLAKE_PCH_H + default 6 + config SMM_TSEG_SIZE hex default 0x800000 @@ -225,6 +223,11 @@ config SOC_INTEL_I2C_DEV_MAX default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex @@ -239,7 +242,7 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS @@ -298,6 +301,17 @@ config FSP_HEADER_PATH config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + +config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT + int "Debug Consent for CNL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 7ad0c7c82c4..13289448b6a 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += lpc.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 43d91d3f83e..ff9da451c81 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -37,6 +37,8 @@ #include #include +#include "chip.h" + /* * List of supported C-states in this processor. */ @@ -302,13 +304,6 @@ static unsigned long soc_fill_dmar(unsigned long current) current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU); @@ -342,6 +337,13 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + return current; } @@ -359,6 +361,7 @@ unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, printk(BIOS_DEBUG, "ACPI: * DMAR\n"); acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 85158069b61..93bce2644ec 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +External(\_SB.MS0X, MethodObj) + scope(\_SB) { Device(LPID) { @@ -62,12 +64,20 @@ scope(\_SB) */ If(Arg2 == 5) { \_SB.PCI0.LPCB.EC0.S0IX(1) + /* provide board level s0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } } /* * Function 6. */ If(Arg2 == 6) { \_SB.PCI0.LPCB.EC0.S0IX(0) + /* provide board level s0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } } } Return(Buffer(One) {0x00}) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 1c7fd7f082f..c43d6d8bd12 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -120,7 +120,8 @@ static void soc_config_acpibase(void) pmc_base_reg = get_pmc_reg_base(); if (!pmc_base_reg) - die("Invalid PMC base address\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Invalid PMC base address\n"); pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 845e9ef34ff..faddbd5a243 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -27,6 +26,8 @@ #include #include +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -165,6 +166,27 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) gpio_configure_pads(cfg, num_pads); } +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const struct device *dev; + dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); + if (!dev || !dev->chip_info) + return; + + const config_t *config = dev->chip_info; + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -175,6 +197,8 @@ void soc_init_pre_device(void *chip_info) /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); + + soc_fill_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 58b540cac09..0d51c1ca5c0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,7 +20,9 @@ #include #include +#include #include +#include #include #include #include @@ -167,10 +169,10 @@ struct soc_intel_cannonlake_config { /* PCIe output clocks type to Pcie devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ @@ -292,15 +294,6 @@ struct soc_intel_cannonlake_config { */ uint8_t PchPmSlpAMinAssert; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - } DebugConsent; /* * SerialIO device mode selection: * @@ -352,9 +345,6 @@ struct soc_intel_cannonlake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; - /* Intel VT configuration */ - uint8_t VtdDisable; - /* * Acoustic Noise Mitigation * 0b - Disable @@ -409,6 +399,28 @@ struct soc_intel_cannonlake_config { /* Unlock all GPIO Pads */ uint8_t PchUnlockGpioPads; + + /* Enable GBE wakeup */ + uint8_t LanWakeFromDeepSx; + uint8_t WolEnableOverride; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index db001b82aea..d3e5e837fde 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -20,7 +20,7 @@ #include static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *board_cfg) + const struct cnl_mb_cfg *board_cfg) { /* * DqByteMapChx expects 12 bytes of data, but the last 6 bytes @@ -29,47 +29,58 @@ static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, */ memset(&mem_cfg->DqByteMapCh0, 0, sizeof(mem_cfg->DqByteMapCh0)); memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], - sizeof(board_cfg->dq_map[DDR_CH0])); + sizeof(board_cfg->dq_map[DDR_CH0])); memset(&mem_cfg->DqByteMapCh1, 0, sizeof(mem_cfg->DqByteMapCh1)); memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], - sizeof(board_cfg->dq_map[DDR_CH1])); + sizeof(board_cfg->dq_map[DDR_CH1])); memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], - sizeof(board_cfg->dqs_map[DDR_CH0])); + sizeof(board_cfg->dqs_map[DDR_CH0])); memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], - sizeof(board_cfg->dqs_map[DDR_CH1])); + sizeof(board_cfg->dqs_map[DDR_CH1])); memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); + sizeof(mem_cfg->RcompResistor)); /* Early cannonlake requires rcomp targets to be 0 */ memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, - sizeof(mem_cfg->RcompTarget)); + sizeof(mem_cfg->RcompTarget)); } -static void meminit_memcfg_spd(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) +/* + * Initialize default memory settings using spd data contained in a buffer. + */ +static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot, + size_t spd_data_len, uintptr_t spd_data_ptr) { + static size_t last_set_spd_data_len = 0; + + assert(spd_data_ptr != 0 && spd_data_len != 0); + + if (last_set_spd_data_len != 0 && + last_set_spd_data_len != spd_data_len) + die("spd data length disparity among slots"); + mem_cfg->MemorySpdDataLen = spd_data_len; + last_set_spd_data_len = spd_data_len; - if (cnl_cfg->channel_empty[0] == 0) + switch (mem_slot) { + case 0: mem_cfg->MemorySpdPtr00 = spd_data_ptr; - - if (cnl_cfg->channel_empty[1] == 0) + break; + case 1: + mem_cfg->MemorySpdPtr01 = spd_data_ptr; + break; + case 2: mem_cfg->MemorySpdPtr10 = spd_data_ptr; -} - -/* - * Initialize default memory settings using spd data contained in a buffer. - */ -static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) -{ - assert(spd_data_ptr && spd_data_len); - meminit_memcfg_spd(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); + break; + case 3: + mem_cfg->MemorySpdPtr11 = spd_data_ptr; + break; + default: + die("nonexistent memory slot"); + } } /* @@ -78,54 +89,67 @@ static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, * in spd/Makefile.inc. */ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - int spd_index) + int spd_index, uint8_t mem_slot) { - size_t spd_data_len; - uintptr_t spd_data_ptr; - struct region_device spd_rdev; - - printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); - meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); + static size_t spd_data_len; + static uintptr_t spd_data_ptr; + static int last_spd_index; + + assert(mem_slot < NUM_DIMM_SLOT); + + if ((spd_data_ptr == 0) || (last_spd_index != spd_index)) { + struct region_device spd_rdev; + + printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + last_spd_index = spd_index; + } + + meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); } /* Initialize onboard memory configurations for CannonLake */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd) + const struct cnl_mb_cfg *cnl_cfg) { - bool OnModuleSpd = false; + const struct spd_info *spdi; + /* Early Command Training Enabled */ mem_cfg->ECT = cnl_cfg->ect; mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved; mem_cfg->CaVrefConfig = cnl_cfg->vref_ca_config; - /* Spd pointer will only be used if all smbus slave address of memory - * sockets on the platform is empty */ - for (int i = 0; i < ARRAY_SIZE(mem_cfg->SpdAddressTable); i++) { - if (spd->spd_smbus_address[i] != 0) { - mem_cfg->SpdAddressTable[i] = spd->spd_smbus_address[i]; - OnModuleSpd = true; + for (int i = 0; i < NUM_DIMM_SLOT; i++) { + spdi = &(cnl_cfg->spd[i]); + switch (spdi->read_type) { + case NOT_EXISTING: + break; + case READ_SMBUS: + mem_cfg->SpdAddressTable[i] = + spdi->spd_spec.spd_smbus_address; + break; + case READ_SPD_CBFS: + meminit_cbfs_spd_index(mem_cfg, + spdi->spd_spec.spd_index, i); + break; + case READ_SPD_MEMPTR: + meminit_spd_data(mem_cfg, i, + spdi->spd_spec.spd_data_ptr_info.spd_data_len, + spdi->spd_spec.spd_data_ptr_info.spd_data_ptr); + break; + default: + die("no valid way to read mem info"); } - } - if (!OnModuleSpd) { - if (spd->spd_by_index) { - meminit_cbfs_spd_index(mem_cfg, cnl_cfg, - spd->spd_spec.spd_index); - } else { - meminit_spd_data(mem_cfg, cnl_cfg, - spd->spd_spec.spd_data_ptr_info.spd_data_len, - spd->spd_spec.spd_data_ptr_info.spd_data_ptr); - } + meminit_memcfg(mem_cfg, cnl_cfg); } - - meminit_memcfg(mem_cfg, cnl_cfg); - } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 34b7891ea8b..d98e2f54865 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -35,6 +34,8 @@ #include #include +#include "chip.h" + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -412,7 +413,7 @@ void soc_core_init(struct device *cpu) /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - mca_configure(NULL); + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index e334555ac0d..4dfd15bc4a6 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -35,6 +34,8 @@ #include #include +#include "chip.h" + #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1fd42cda178..dd9388296d7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -13,20 +13,19 @@ * GNU General Public License for more details. */ -#include #include #include #include #include -#include #include -#include #include #include #include #include #include +#include "chip.h" + static const int serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -120,6 +119,28 @@ static void ignore_gbe_ltr(void) write8(pmcbase + LTR_IGN, reg8); } +static void configure_gspi_cs(int idx, const config_t *config, + uint8_t *polarity, uint8_t *enable, + uint8_t *defaultcs) +{ + struct spi_cfg cfg; + + /* If speed_mhz is set, infer that the port should be configured */ + if (config->common_soc_config.gspi[idx].speed_mhz != 0) { + if (gspi_get_soc_spi_cfg(idx, &cfg) == 0) { + if (cfg.cs_polarity == SPI_POLARITY_LOW) + *polarity = 0; + else + *polarity = 1; + + if (defaultcs != NULL) + *defaultcs = 0; + if (enable != NULL) + *enable = 1; + } + } +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -144,9 +165,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Usb3OverCurrentPin[i] = 0; } - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ @@ -216,6 +234,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->DdiPortDDdc = config->DdiPortDDdc; params->DdiPortFDdc = config->DdiPortFDdc; + /* WOL */ + params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx; + params->PchPmWolEnableOverride = config->WolEnableOverride; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; @@ -250,9 +272,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable xDCI controller if enabled in devicetree and allowed */ dev = dev_find_slot(0, PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else + params->XdciEnable = 0; /* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; @@ -260,9 +285,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); #if CONFIG(SOC_INTEL_COMETLAKE) - params->CnviMode = dev->enabled; + if (dev) + params->CnviMode = dev->enabled; + else + params->CnviMode = 0; #else - params->PchCnviMode = dev->enabled; + if (dev) + params->PchCnviMode = dev->enabled; + else + params->PchCnviMode = 0; #endif /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { @@ -348,6 +379,27 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; + + /* + * GSPI Chip Select parameters + * The GSPI driver assumes that CS0 is the used chip-select line, + * therefore only CS0 is configured below. + */ +#if CONFIG(SOC_INTEL_COMETLAKE) + configure_gspi_cs(0, config, ¶ms->SerialIoSpi0CsPolarity[0], + ¶ms->SerialIoSpi0CsEnable[0], + ¶ms->SerialIoSpiDefaultCsOutput[0]); + configure_gspi_cs(1, config, ¶ms->SerialIoSpi1CsPolarity[0], + ¶ms->SerialIoSpi1CsEnable[0], + ¶ms->SerialIoSpiDefaultCsOutput[1]); + configure_gspi_cs(2, config, ¶ms->SerialIoSpi2CsPolarity[0], + ¶ms->SerialIoSpi2CsEnable[0], + ¶ms->SerialIoSpiDefaultCsOutput[2]); +#else + for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) + configure_gspi_cs(i, config, + ¶ms->SerialIoSpiCsPolarity[0], NULL, NULL); +#endif } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 30ee9398d52..4036fdc073e 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -77,14 +77,17 @@ static const struct pad_group cnl_community4_groups[] = { INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */ }; -static const struct pad_community cnl_communities[] = { - { /* GPP A, B, G, SPI */ +static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { + /* GPP A, B, G, SPI */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, .last_pad = GPIO_RSVD_11, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -94,13 +97,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cnl_community0_groups, .num_groups = ARRAY_SIZE(cnl_community0_groups), - }, { /* GPP D, F, H, VGPIO */ + }, + /* GPP D, F, H, VGPIO */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_D0, .last_pad = vSD3_CD_B, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -110,13 +117,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, .num_groups = ARRAY_SIZE(cnl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -126,13 +137,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community2_groups, .num_groups = ARRAY_SIZE(cnl_community2_groups), - }, { /* AZA, CPU */ + }, + /* AZA, CPU */ + [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, .last_pad = GPIO_RSVD_38, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -142,13 +157,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, .num_groups = ARRAY_SIZE(cnl_community3_groups), - }, { /* GPP C, E, JTAG, HVMOS */ + }, + /* GPP C, E, JTAG, HVMOS */ + [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPIO_RSVD_27, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index d59dea5cbc9..dd9f4336452 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -80,13 +80,16 @@ static const struct pad_group cnl_community4_groups[] = { }; static const struct pad_community cnl_communities[] = { - { /* GPP A, B */ + /* GPP A, B */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, .last_pad = GPIO_RSVD_2, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -96,13 +99,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cnl_community0_groups, .num_groups = ARRAY_SIZE(cnl_community0_groups), - }, { /* GPP C, D, G */ + }, + /* GPP C, D, G */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_C0, .last_pad = vSSP2_RXD, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -112,13 +119,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, .num_groups = ARRAY_SIZE(cnl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -128,13 +139,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community2_groups, .num_groups = ARRAY_SIZE(cnl_community2_groups), - }, { /* GPP K, H, E, F */ + }, + /* GPP K, H, E, F */ + [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = GPP_K0, .last_pad = GPIO_RSVD_19, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -144,13 +159,17 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, .num_groups = ARRAY_SIZE(cnl_community3_groups), - }, { /* GPP I, J */ + }, + /* GPP I, J */ + [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPIO_RSVD_20, .last_pad = GPP_J11, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index a89dcb31fb6..2acfecc5b08 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -23,6 +23,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index c6021805924..d5f6c39f24e 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -23,6 +23,9 @@ /* Number of dq bits controlled per dqs */ #define DQ_BITS_PER_DQS 8 +/* Number of memory DIMM slots available on Cannonlake board */ +#define NUM_DIMM_SLOT 4 + /* * Number of memory packages, where a "package" represents a 64-bit solution. */ @@ -40,29 +43,46 @@ struct spd_by_pointer { uintptr_t spd_data_ptr; }; +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this slot */ + READ_SMBUS, /* Read on-module spd by SMBUS. */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + struct spd_info { - bool spd_by_index; + enum mem_info_read_type read_type; union spd_data_by { + /* To read on-module spd when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address; + + /* To identify spd file when read_type is READ_SPD_CBFS. */ int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ struct spd_by_pointer spd_data_ptr_info; } spd_spec; - uint8_t spd_smbus_address[4]; }; /* Board-specific memory dq mapping information */ struct cnl_mb_cfg { + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + struct spd_info spd[NUM_DIMM_SLOT]; + /* - * For each channel, there are 3 sets of DQ byte mappings, + * For each channel, there are 6 sets of DQ byte mappings, * where each set has a package 0 and a package 1 value (package 0 * represents the first 64-bit lpddr4 chip combination, and package 1 * represents the second 64-bit lpddr4 chip combination). * The first three sets are for CLK, CMD, and CTL. - * The fsp package actually expects 6 sets, but the last 3 sets are - * not used in CNL, so we only define the three sets that are used - * and let the meminit_lpddr4() routine take care of clearing the + * The fsp package actually expects 6 sets, even though the last 3 sets + * are not used in CNL. + * We let the meminit_lpddr4() routine take care of clearing the * unused fields for the caller. + * Note that dq_map is only used by LPDDR; it does not need to be + * initialized for designs using DDR4. */ - uint8_t dq_map[DDR_NUM_CHANNELS][3][DDR_NUM_PACKAGES]; + uint8_t dq_map[DDR_NUM_CHANNELS][6][DDR_NUM_PACKAGES]; /* * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a @@ -70,6 +90,8 @@ struct cnl_mb_cfg { * the memory part. The array index represents the dqs bit number * on the memory part, and the values in the array represent which * pin on the CPU that DRAM pin connects to. + * dqs_map is only used by LPDDR; same comments apply as for dq_map + * above. */ uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; @@ -103,26 +125,12 @@ struct cnl_mb_cfg { /* Early Command Training Enabled */ uint8_t ect; - - /* - * Flags to indicate which channels are populated. We - * currently support single or dual channel configurations. - * Set 1 to indicate that the channel is not populated Set 0 - * to indicate that the channel is populated. For example, - * dual channel memory configuration would have both - * channel_empty[0] = 0 and channel_empty[1] = 0. Note that - * this flag is only used for soldered down DRAM where we get - * SPD data from CBFS. We need the value 0 to default to - * populated in order to support existing boards. - */ - uint8_t channel_empty[2]; }; /* * Initialize default memory configurations for CannonLake. */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd); + const struct cnl_mb_cfg *cnl_cfg); #endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 8a944b1b482..5c12e4cb674 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -246,6 +246,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index e77dbf88cf6..d03723dae1f 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -320,6 +320,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index 59901440d91..698bd2a5c7e 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -355,4 +355,12 @@ #define TOTAL_PADS 275 #define SD_PWR_EN_PIN GPP_A17 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 1788e789895..5176ac734a4 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -399,4 +399,11 @@ #define TOTAL_PADS (GPD11 + 1) +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + #endif diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 100bd11356f..1ebaf3f7b68 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -29,14 +29,6 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xfe032000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h new file mode 100644 index 00000000000..5b411d36210 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CANNONLAKE_ME_H_ +#define _CANNONLAKE_ME_H_ + +void dump_me_status(void *unused); + +#endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 4a96185e6bc..486839852ce 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include #include #include #include +#include "../../chip.h" + void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c new file mode 100644 index 00000000000..c9748b73438 --- /dev/null +++ b/src/soc/intel/cannonlake/me.c @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Miscellaneous constants */ +enum { + MKHI_GEN_GROUP_ID = 0xFF, + MKHI_GET_FW_VERSION = 0x02, + ME_OPMODE_NORMAL = 0x00, + ME_WSTATE_NORMAL = 0x05, +}; + +/* HFSTS register offsets in PCI config space */ +enum { + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + +/* Host Firmware Status Register 1 */ +union hfsts1 { + uint32_t raw; + struct { + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t fw_upd_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reset_count : 4; + uint32_t boot_options : 1; + uint32_t rsvd0 : 1; + uint32_t bist_state : 1; + uint32_t bist_reset_req : 1; + uint32_t power_source : 2; + uint32_t reserved1 : 1; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union hfsts2 { + uint32_t raw; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 3 */ +union hfsts3 { + uint32_t raw; +}; + +/* Host Firmware Status Register 4 */ +union hfsts4 { + uint32_t raw; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union hfsts5 { + uint32_t raw; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union hfsts6 { + uint32_t raw; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + +/* + * From reading the documentation, this should work for both WHL and CML + * platforms. Also, calling this function from dump_me_status() does not + * work, as the ME does not respond and the command times out. + */ +static void print_me_version(void *unused) +{ + struct mkhi_hdr { + uint8_t group_id; + uint8_t command :7; + uint8_t is_resp :1; + uint8_t rsvd; + uint8_t result; + } __packed; + + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + union hfsts1 hfsts1; + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_GET_FW_VERSION, + }; + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || + (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) + goto fail; + + heci_reset(); + + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, + HECI_MKHI_ADDR)) + goto fail; + + if (!heci_receive(&resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); + +void dump_me_status(void *unused) +{ + union hfsts1 hfsts1; + union hfsts2 hfsts2; + union hfsts3 hfsts3; + union hfsts4 hfsts4; + union hfsts5 hfsts5; + union hfsts6 hfsts6; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); + hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); + hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); + hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); + hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", + hfsts1.raw); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", + hfsts2.raw); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", + hfsts3.raw); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", + hfsts4.raw); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", + hfsts5.raw); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", + hfsts6.raw); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.fw_upd_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index b2dd26dcf09..3cae54fadb5 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include @@ -28,6 +27,8 @@ #include #include +#include "chip.h" + void smm_region(void **start, size_t *size) { *start = (void *)sa_get_tseg_base(); @@ -220,7 +221,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 5cd31f9f97e..6834aa2d17f 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include @@ -27,6 +26,8 @@ #include #include +#include "chip.h" + /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 2ad2c935b77..6e492bb73ae 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -25,6 +24,8 @@ #include #include +#include "../chip.h" + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; @@ -65,10 +66,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->VmxEnable = CONFIG(ENABLE_VMX); #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - m_cfg->SkipMpInit = 0; - else - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif /* Set CpuRatio to match existing MSR value */ @@ -103,6 +101,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg, config); @@ -111,8 +110,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->SmbusEnable = 0; else m_cfg->SmbusEnable = smbus->enabled; + /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = + CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; + + /* Configure VT-d */ + tconfig->VtdDisable = 0; mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 893f37d421c..98d4c006a86 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include @@ -31,6 +29,8 @@ #include #include +#include "../chip.h" + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -111,6 +111,7 @@ static void save_dimm_info(void) src_dimm->DimmId, dram_part_num, dram_part_num_len, + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 643fad645fa..9af291700ba 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -27,6 +26,8 @@ #include #include +#include "chip.h" + #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index d850b15b345..3f01f14dcf0 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -33,8 +33,6 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - const struct soc_intel_cannonlake_config *const config = dev->chip_info; - static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -63,10 +61,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) return; - if (!(config && config->VtdDisable)) { - sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); - } } /* diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 421cafc7184..7174a9a58f8 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -24,10 +24,6 @@ #include #include -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index b5caf400975..ac2268661f6 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -51,13 +51,6 @@ config SOC_INTEL_COMMON_ACPI bool default n -config SOC_INTEL_COMMON_ACPI_EC_PTS_WAK - bool - default n - help - Set this option to have the platform level _PTS/_WAK methods call - methods provided by the Embedded Controller. - config SOC_INTEL_COMMON_NHLT bool default n @@ -68,4 +61,11 @@ config TPM_TIS_ACPI_INTERRUPT acpi_get_gpe() is used to provide interrupt status to TPM layer. This option specifies the GPE number. +config SOC_INTEL_DEBUG_CONSENT + bool "Enable SOC debug interface" + default n + help + Set this option to enable default debug interface of SoC such as DBC + or DCI. + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index 6c52bbfd775..0c0be154e6d 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -59,7 +59,7 @@ Method (APRT, 1, Serialized) #if CONFIG(DRIVERS_UART_8250MEM_32) OperationRegion (UBAR, SystemMemory, - UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24) + CONFIG_CONSOLE_UART_BASE_ADDRESS, 24) Field (UBAR, AnyAcc, NoLock, Preserve) { TDR, 8, /* Transmit Data Register BAR + 0x000 */ diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index bdc0d5c15c9..9aa2edc6df7 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -17,6 +17,9 @@ #include +External(\_SB.MPTS, MethodObj) +External(\_SB.MWAK, MethodObj) + /* Port 80 POST */ OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) @@ -34,10 +37,10 @@ Method (_PTS, 1) { Store (POST_OS_ENTER_PTS, DBG0) -#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) - /* Call EC _PTS handler */ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) -#endif + If (CondRefOf (\_SB.MPTS)) + { + \_SB.MPTS (Arg0) + } } /* The _WAK method is called on system wakeup */ @@ -46,10 +49,10 @@ Method (_WAK, 1) { Store (POST_OS_ENTER_WAKE, DBG0) -#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) - /* Call EC _WAK handler */ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -#endif + If (CondRefOf (\_SB.MWAK)) + { + \_SB.MWAK (Arg0) + } Return (Package(){0,0}) } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c872e51578e..3a34c79304f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227b491..a6c4f37cc43 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d3ee671bef2..b1648e8eedd 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -28,21 +28,8 @@ bootblock_pre_c_entry: post_code(0x20) - /* - * Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. - */ -check_for_clean_reset: - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - cmp $0, %eax - jz no_reset - /* perform warm reset */ - movw $0xcf9, %dx - movb $0x06, %al - outb %al, %dx + movl $no_reset, %esp /* return address */ + jmp check_mtrr /* Check if CPU properly reset */ no_reset: post_code(0x21) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index a7f89baafde..75e71120e04 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -300,7 +300,7 @@ uint32_t cpu_get_max_turbo_ratio(void) return msr.lo & 0xff; } -void mca_configure(void *unused) +void mca_configure(void) { msr_t msr; int i; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 342a1203e45..e98b5dd6150 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -69,6 +70,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 302e6dec05e..7bd46ceba93 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -69,9 +68,9 @@ #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) -struct cse_device { +static struct cse_device { uintptr_t sec_bar; -} g_cse CAR_GLOBAL; +} g_cse; /* * Initialize the device with provided temporary BAR. If BAR is 0 use a @@ -80,7 +79,6 @@ struct cse_device { */ void heci_init(uintptr_t tempbar) { - struct cse_device *cse = car_get_var_ptr(&g_cse); #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_CSE; #else @@ -89,7 +87,7 @@ void heci_init(uintptr_t tempbar) u8 pcireg; /* Assume it is already initialized, nothing else to do */ - if (cse->sec_bar) + if (g_cse.sec_bar) return; /* Use default pre-ram bar */ @@ -111,7 +109,7 @@ void heci_init(uintptr_t tempbar) pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, PCI_COMMAND, pcireg); - cse->sec_bar = tempbar; + g_cse.sec_bar = tempbar; } /* Get HECI BAR 0 from PCI configuration space */ @@ -130,20 +128,18 @@ static uint32_t get_cse_bar(void) static uint32_t read_bar(uint32_t offset) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return read32((void *)(cse->sec_bar + offset)); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return read32((void *)(g_cse.sec_bar + offset)); } static void write_bar(uint32_t offset, uint32_t val) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return write32((void *)(cse->sec_bar + offset), val); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return write32((void *)(g_cse.sec_bar + offset), val); } static uint32_t read_cse_csr(void) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 455b13ccb76..58e7db75a10 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -236,14 +236,13 @@ void fast_spi_cache_bios_region(void) /* Only the IFD BIOS region is memory mapped (at top of 4G) */ fast_spi_get_bios_region(&bios_size); - if (!bios_size) - return; - /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write * protection, so limit the cached bios region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); + if (!bios_size) + return; /* Round to power of two */ alignment = 1UL << (log2_ceil(bios_size)); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 97e231ca3fa..0a4344272e1 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 0065a6c54fa..7ebf05a2209 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -13,7 +13,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include +#include #include #include #include @@ -60,6 +62,10 @@ ((group) * sizeof(uint32_t))) #define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \ ((group) * sizeof(uint32_t))) +#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \ + ((group) * sizeof(uint32_t))) +#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \ + ((group) * sizeof(uint32_t))) static inline size_t relative_pad_in_comm(const struct pad_community *comm, gpio_t gpio) @@ -580,3 +586,44 @@ uint32_t __weak soc_gpio_pad_config_fixup(const struct pad_config *cfg, { return reg_val; } + +void gpi_clear_int_cfg(void) +{ + int i, group, num_groups; + uint32_t sts_value; + size_t gpio_communities; + const struct pad_community *comm; + + comm = soc_gpio_get_community(&gpio_communities); + for (i = 0; i < gpio_communities; i++, comm++) { + num_groups = comm->num_gpi_regs; + for (group = 0; group < num_groups; group++) { + /* Clear the enable register */ + pcr_write32(comm->port, GPI_IE_OFFSET(comm, group), 0); + + /* Read and clear the set status register bits*/ + sts_value = pcr_read32(comm->port, + GPI_IS_OFFSET(comm, group)); + pcr_write32(comm->port, + GPI_IS_OFFSET(comm, group), sts_value); + } + } +} + +/* The function performs GPIO Power Management programming. */ +void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num) +{ + int i; + size_t gpio_communities; + const uint8_t misccfg_pm_mask = ~MISCCFG_ENABLE_GPIO_PM_CONFIG; + const struct pad_community *comm; + + comm = soc_gpio_get_community(&gpio_communities); + if (gpio_communities != num) + die("Incorrect GPIO community count!\n"); + + /* Program GPIO_MISCCFG */ + for (i = 0; i < num; i++, comm++) + pcr_rmw8(comm->port, GPIO_MISCCFG, + misccfg_pm_mask, misccfg_pm_values[i]); +} diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a15cf9..4cea21b075c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -58,7 +58,8 @@ uintptr_t graphics_get_memory_base(void) */ uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2); if (!memory_base) - die("GMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GMADR is not programmed!"); return memory_base; } @@ -74,7 +75,8 @@ static uintptr_t graphics_get_gtt_base(void) if (!gtt_base) { gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0); if (!gtt_base) - die("GTTMMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GTTMMADR is not programmed!"); } return gtt_base; } diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 81eb7eedec2..17532bf6db7 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -262,15 +261,13 @@ static uint32_t gspi_get_bus_clk_mhz(unsigned int gspi_bus) return cfg[gspi_bus].speed_mhz; } -static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] CAR_GLOBAL; +static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus) { - uintptr_t *base = car_get_var_ptr(gspi_base); + if (!gspi_base[gspi_bus]) + gspi_base[gspi_bus] = gspi_calc_base_addr(gspi_bus); - if (!base[gspi_bus]) - base[gspi_bus] = gspi_calc_base_addr(gspi_bus); - - return base[gspi_bus]; + return gspi_base[gspi_bus]; } /* Parameters for GSPI controller operation. */ @@ -437,9 +434,11 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus) { const uint32_t ref_clk_mhz = CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ; - const uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); + uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); + + if (!gspi_clk_mhz) + gspi_clk_mhz = 1; - assert(gspi_clk_mhz != 0); assert(ref_clk_mhz != 0); return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; } diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 70ad2536075..8630fd1eb59 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -159,6 +159,6 @@ uint32_t cpu_get_power_max(void); uint32_t cpu_get_max_turbo_ratio(void); /* Configure Machine Check Architecture support */ -void mca_configure(void *unused); +void mca_configure(void); #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/early_mmc.h new file mode 100644 index 00000000000..39aaf58fcf0 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/early_mmc.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H +#define SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H + +#include + +/* + * Following should be defined in soc/iomap.h + * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's + PCI BAR. + */ + +/* + * Structure for the following delay registers + * emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h + * emmc_tx_data_cntl2: Tx Delay Control 2 (Tx_DATA_dly_2)-Offset 828h + * emmc_rx_cmd_data_cntl1: Rx CMD Data Delay Control 1 + * (Rx_CMD_Data_dly_1)-Offset 82Ch + * emmc_rx_cmd_data_cntl2: Rx CMD Data Path Delay Control 2 + * (Rx_CMD_Data_dly_2)-Offset 834h + * emmc_rx_strobe_cntl: Rx Strobe Delay Control + * (Rx_Strobe_Ctrl_Path)-Offset 830h + * emmc_tx_cmd_cntl: Tx CMD Delay Control (Tx_CMD_dly)-Offset 820h + */ +struct mmc_dll_params { + uint32_t emmc_tx_data_cntl1; + uint32_t emmc_tx_data_cntl2; + uint32_t emmc_rx_cmd_data_cntl1; + uint32_t emmc_rx_cmd_data_cntl2; + uint32_t emmc_rx_strobe_cntl; + uint32_t emmc_tx_cmd_cntl; +}; + +/* + * SOC specific API to get mmc min max frequencies. + * returns 0, if able to get f_min, f_max; otherwise returns -1 + */ +int soc_get_mmc_frequencies(uint32_t *f_min, uint32_t *f_max); +/* + * SOC specific API to configure mmc gpios. + * returns 0, if able to configure gpios; otherwise returns -1 + */ +int soc_configure_mmc_gpios(void); +/* + * SOC specific API to get mmc delay register settings. + * returns 0, if able to get register settings; otherwise returns -1 + */ +int soc_get_mmc_dll(struct mmc_dll_params *params); + +#if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE) +/* + * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card. + * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS + * and sets it to 1. Payload can start by sending CMD1, there is no need to + * send CMD0 and wait for the card to be ready. + * In case of failure: It returns -1 and doesn't add cbmem entry. Payload + * should do complete initialization starting with CMD0. + */ +int early_mmc_wake_hw(void); +#else +static inline int early_mmc_wake_hw(void) +{ + return -1; +} +#endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */ +#endif /* SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 11a03d029cd..a2cccc7cd2e 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -23,6 +23,23 @@ #ifndef __ACPI__ #include +/* GPIO community IOSF sideband clock gating */ +#define MISCCFG_GPSIDEDPCGEN (1 << 5) +/* GPIO community RCOMP clock gating */ +#define MISCCFG_GPRCOMPCDLCGEN (1 << 4) +/* GPIO community RTC clock gating */ +#define MISCCFG_GPRTCDLCGEN (1 << 3) +/* GFX controller clock gating */ +#define MISCCFG_GSXSLCGEN (1 << 2) +/* GPIO community partition clock gating */ +#define MISCCFG_GPDPCGEN (1 << 1) +/* GPIO community local clock gating */ +#define MISCCFG_GPDLCGEN (1 << 0) +/* Enable GPIO community power management configuration */ +#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \ + MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ + | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) + /* * GPIO numbers may not be contiguous and instead will have a different * starting pin number for each pad group. @@ -105,8 +122,10 @@ struct pad_community { gpio_t first_pad; /* first pad in community */ gpio_t last_pad; /* last pad in community */ uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */ - uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI EN Reg 0 */ - uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI STS Reg 0 */ + uint16_t gpi_int_sts_reg_0; /* offset to GPI Int STS Reg 0 */ + uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */ + uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */ + uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */ uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */ uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ @@ -207,5 +226,14 @@ uint8_t gpio_get_pad_portid(const gpio_t pad); uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val); +/* + * Function to reset/clear the GPI Interrupt Enable & Status registers for + * all GPIO pad communities. + */ +void gpi_clear_int_cfg(void); + +/* The function performs GPIO Power Management programming. */ +void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 0ad3e5c32a8..e1ddd4babba 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -264,10 +264,16 @@ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) -/* No Connect configuration for unused pad. - * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term +/* + * No Connect configuration for unused pad. + * Both TX and RX are disabled. RX disabling is done to avoid unnecessary + * setting of GPI_STS. */ -#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) +#define PAD_NC(pad, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ + PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) @@ -385,6 +391,13 @@ PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) +/* GPI, GPIO Driver, SCI interrupt */ +#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index ca5568996f5..eb38f13a71e 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -30,7 +30,4 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); /* Check if controller is in reset. */ bool lpss_is_controller_in_reset(uintptr_t base); -/* Read LPSS CLK register */ -uint32_t lpss_clk_read(uintptr_t base); - #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 3c7467da57d..0f37a64345b 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 #define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index ad2ddf4b280..55f259db7cf 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -91,10 +91,4 @@ struct device *uart_get_device(void); */ struct device *soc_uart_console_to_device(int uart_console); -/* - * Set UART to legacy mode - * Put UART in byte access mode for 16550 compatibility - */ -void soc_uart_set_legacy_mode(void); - #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d5f76f3a7b5..86547a443fc 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -125,8 +125,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_C236, + PCI_DEVICE_ID_INTEL_KBP_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_H110, + PCI_DEVICE_ID_INTEL_SPT_H_H170, + PCI_DEVICE_ID_INTEL_SPT_H_Z170, + PCI_DEVICE_ID_INTEL_SPT_H_Q170, + PCI_DEVICE_ID_INTEL_SPT_H_Q150, + PCI_DEVICE_ID_INTEL_SPT_H_B150, PCI_DEVICE_ID_INTEL_SPT_H_QM170, PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index b3836377363..c67c43532ca 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -80,6 +80,9 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size) /* Each IO range register can only open a 256-byte window. */ window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE); + if (!window_size) + return; + /* Window size must be a power of two for the AMASK to work. */ alignment = 1UL << (log2_ceil(window_size)); window_size = ALIGN_UP(window_size, alignment); diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 1168871d097..6b6d17b1061 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -69,12 +69,3 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val) write32(addr, clk_sel); } - -uint32_t lpss_clk_read(uintptr_t base) -{ - uint8_t *addr = (void *)base; - - addr += LPSS_CLOCK_CTL_REG; - - return read32(addr); -} diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1d7c091a694..24cde1b6c98 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -36,7 +36,8 @@ static pci_devfn_t p2sb_get_device(void) pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); if (dev == PCI_DEV_INVALID) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n"); return dev; } @@ -45,7 +46,8 @@ static struct device *p2sb_get_device(void) { struct device *dev = PCH_DEV_P2SB; if (!dev) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n"); return dev; } @@ -99,7 +101,8 @@ void p2sb_unhide(void) if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) - die("Unable to unhide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to unhide PCH_DEV_P2SB device !\n"); } void p2sb_hide(void) @@ -108,7 +111,8 @@ void p2sb_hide(void) if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != 0xFFFF) - die("Unable to hide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to hide PCH_DEV_P2SB device !\n"); } static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 43543a1cc50..eaaf1252eac 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -91,7 +91,8 @@ static void pch_pmc_read_resources(struct device *dev) struct pmc_resource_config *config = &pmc_cfg; if (pmc_soc_get_resources(config) < 0) - die("Unable to get PMC controller resource information!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to get PMC controller resource information!"); /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index f58d36246e0..564aacb55e1 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -27,7 +26,7 @@ #include #include -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; struct chipset_power_state *pmc_get_power_state(void) { @@ -38,7 +37,7 @@ struct chipset_power_state *pmc_get_power_state(void) /* cbmem is online but ptr is not populated yet */ if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) - return car_get_var_ptr(&power_state); + return &power_state; return ptr; } @@ -46,16 +45,14 @@ struct chipset_power_state *pmc_get_power_state(void) static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); + memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 0a402137bcc..06ad8e4fa8e 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_SCS bool help Intel Processor common storage and communication subsystem support + +config SOC_INTEL_COMMON_EARLY_MMC_WAKE + bool + default n + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC + select SDHCI_CONTROLLER + help + Send CMD1 early in romstage to improve boot time. It requires emmc + DLL tuning parameters to be added to devicetree.cb diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index 1c2a6c6692f..1160802d032 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c +romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c new file mode 100644 index 00000000000..8f47ec7d9e9 --- /dev/null +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EMMC_TX_CMD_CNTL_OFFSET 0x820 +#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 +#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 +#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C +#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 +#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 + +void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr) +{ + uint32_t f_min, f_max; + + if (soc_get_mmc_frequencies(&f_min, &f_max) < 0) { + printk(BIOS_ERR, + "MMC early init: failed to get mmc frequencies\n"); + return; + } + + ctrlr->f_min = f_min; + ctrlr->f_max = f_max; +} + +static void enable_mmc_controller_bar(void) +{ + pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, + PRERAM_MMC_BASE_ADDRESS); + pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +static void disable_mmc_controller_bar(void) +{ + pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, 0); + pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); +} + +static int set_mmc_dll(void *ioaddr) +{ + struct mmc_dll_params dll_params; + + if (soc_get_mmc_dll(&dll_params) < 0) { + printk(BIOS_ERR, + "MMC early init: failed to get mmc DLL parameters\n"); + return -1; + } + + write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET, + dll_params.emmc_tx_data_cntl1); + write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET, + dll_params.emmc_tx_data_cntl2); + write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET, + dll_params.emmc_rx_cmd_data_cntl1); + write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET, + dll_params.emmc_rx_cmd_data_cntl2); + write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET, + dll_params.emmc_rx_strobe_cntl); + write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET, + dll_params.emmc_tx_cmd_cntl); + + return 0; +} + +static void set_early_mmc_wake_status(int32_t status) +{ + int32_t *ms_cbmem; + + ms_cbmem = cbmem_add(CBMEM_ID_MMC_STATUS, sizeof(int)); + + if (ms_cbmem == NULL) { + printk(BIOS_ERR, + "%s: Failed to add early mmc wake status to cbmem!\n", + __func__); + return; + } + + *ms_cbmem = status; +} + +int early_mmc_wake_hw(void) +{ + struct storage_media media; + struct sd_mmc_ctrlr *mmc_ctrlr; + struct sdhci_ctrlr *sdhci_ctrlr; + int err; + + if (acpi_is_wakeup_s3()) + return -1; + + /* Configure mmc gpios */ + if (soc_configure_mmc_gpios() < 0) { + printk(BIOS_ERR, + "%s: MMC early init: failed to configure mmc gpios\n", + __func__); + return -1; + } + /* Setup pci bar */ + enable_mmc_controller_bar(); + + /* Initialize sdhci */ + mmc_ctrlr = new_pci_sdhci_controller(PCH_DEV_EMMC); + if (mmc_ctrlr == NULL) + goto out_err; + + sdhci_ctrlr = container_of(mmc_ctrlr, struct sdhci_ctrlr, sd_mmc_ctrlr); + + /* set emmc DLL tuning parameters */ + if (set_mmc_dll(sdhci_ctrlr->ioaddr) < 0) + goto out_err; + + memset(&media, 0, sizeof(media)); + media.ctrlr = mmc_ctrlr; + SET_BUS_WIDTH(mmc_ctrlr, 1); + /* + * Set clock to 1 so that the driver can choose minimum frequency + * possible + */ + SET_CLOCK(mmc_ctrlr, 1); + + /* Reset emmc, send CMD0 */ + if (sd_mmc_go_idle(&media)) + goto out_err; + + /* Send CMD1 */ + err = mmc_send_op_cond(&media); + if (err != 0 && err != CARD_IN_PROGRESS) + goto out_err; + + disable_mmc_controller_bar(); + + set_early_mmc_wake_status(1); + return 0; + +out_err: + + disable_mmc_controller_bar(); + return -1; +} diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 3a4a5332805..60714d9ce28 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -101,8 +100,8 @@ void prmrr_core_configure(void) return; } - printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64); - printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64); + printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64); + printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64); /* Program core PRMRR MSRs. * - Set cache writeback mem attrib in PRMRR base MSR diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 0f91156566e..281a7f76559 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -351,6 +351,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_KBL_ID_H, PCI_DEVICE_ID_INTEL_KBL_U_R, PCI_DEVICE_ID_INTEL_KBL_ID_DT, + PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, PCI_DEVICE_ID_INTEL_CFL_ID_S, diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 61f14a935c9..c12c64ab535 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" -#if !ENV_RAMSTAGE +#if ENV_BOOTBLOCK void bootblock_systemagent_early_init(void) { uint32_t reg; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index b89bf6f31e1..9d820ffd7ef 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -44,11 +43,12 @@ static void uart_lpss_init(uintptr_t baseaddr) CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); } -#if CONFIG(DRIVERS_UART_8250MEM) +#if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) uintptr_t uart_platform_base(int idx) { - /* return Base address for UART console index */ - return UART_BASE_0_ADDR(idx); + if (idx == CONFIG_UART_FOR_CONSOLE) + return CONFIG_CONSOLE_UART_BASE_ADDRESS; + return 0; } #endif @@ -137,12 +137,7 @@ static void uart_configure_gpio_pads(void) void uart_bootblock_init(void) { /* Program UART BAR0, command, reset and clock register */ - uart_common_init(uart_get_device(), - UART_BASE(CONFIG_UART_FOR_CONSOLE)); - - if (!CONFIG(DRIVERS_UART_8250MEM_32)) - /* Put UART in byte access mode for 16550 compatibility */ - soc_uart_set_legacy_mode(); + uart_common_init(uart_get_device(), CONFIG_CONSOLE_UART_BASE_ADDRESS); /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); @@ -159,8 +154,8 @@ static void uart_read_resources(struct device *dev) uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ - res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE); - res->size = UART_BASE_SIZE; + res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS; + res->size = 0x1000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/common/block/vmx/Kconfig b/src/soc/intel/common/block/vmx/Kconfig deleted file mode 100644 index f8dce0791fd..00000000000 --- a/src/soc/intel/common/block/vmx/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_VMX - bool "Enable VMX for virtualization" - default n diff --git a/src/soc/intel/common/block/vmx/Makefile.inc b/src/soc/intel/common/block/vmx/Makefile.inc deleted file mode 100644 index 861e2f97d20..00000000000 --- a/src/soc/intel/common/block/vmx/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_VMX) += vmx.c diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c deleted file mode 100644 index d0086d080ef..00000000000 --- a/src/soc/intel/common/block/vmx/vmx.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static bool vmx_param_valid; -static struct vmx_param g_vmx_param; - -static const struct vmx_param *get_vmx_param(void) -{ - if (vmx_param_valid) - return &g_vmx_param; - - memset(&g_vmx_param, 0, sizeof(g_vmx_param)); - if (soc_fill_vmx_param(&g_vmx_param) < 0) { - printk(BIOS_ERR, "VMX : Failed to get soc vmx param\n"); - return NULL; - } - vmx_param_valid = true; - printk(BIOS_INFO, "VMX : param.enable = %d\n", g_vmx_param.enable); - - return &g_vmx_param; -} - -static int soc_vmx_enabled(void) -{ - const struct vmx_param *vmx_param = get_vmx_param(); - return vmx_param ? vmx_param->enable : 0; -} - -void vmx_configure(void *unused) -{ - msr_t msr; - uint32_t feature_flag; - - feature_flag = cpu_get_feature_flags_ecx(); - - if (!soc_vmx_enabled() || !(feature_flag & CPUID_VMX)) { - printk(BIOS_ERR, "VMX: pre-conditions not met\n"); - return; - } - - msr = rdmsr(IA32_FEATURE_CONTROL); - - /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { - /* Enable VMX */ - msr.lo |= FEATURE_ENABLE_VMX; - wrmsr(IA32_FEATURE_CONTROL, msr); - } - - /* Report current status */ - msr = rdmsr(IA32_FEATURE_CONTROL); - printk(BIOS_DEBUG, "VMX status: %s, %s\n", - (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", - (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked"); -} diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 0b1be8817eb..d89e9d58271 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -22,7 +22,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - u16 data_width) + const u8 *module_serial_num, u16 data_width) { dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; @@ -34,6 +34,9 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, module_part_num, min(sizeof(dimm->module_part_number), module_part_number_size)); + if (module_serial_num) + memcpy(dimm->serial, module_serial_num, + DIMM_INFO_SERIAL_SIZE); switch (data_width) { case 8: dimm->bus_width = MEMORY_BUS_WIDTH_8; diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 33b5d0df04f..5824f5d6654 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -19,10 +19,13 @@ #include #include +/* Offset info DIMM_INFO SpdSave for start of serial number */ +#define SPD_SAVE_OFFSET_SERIAL 5 + /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - u16 data_width); + const u8 *module_serial_num, u16 data_width); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index f3e91ff451d..e969a044a12 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -26,7 +26,7 @@ #include #include #include - +#include #include #include #include diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index f16ee20620f..57e3a2e49bf 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -37,8 +37,8 @@ const FSPT_UPD temp_ram_init_params = { .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, .CodeRegionBase = - (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), - .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE, + (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, .Reserved1 = {0}, }, .FsptConfig = { diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index ce6df68f9fa..fc1024afa7f 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -38,7 +38,6 @@ static struct smm_relocation_attrs relo_attrs; static void dnv_configure_mca(void) { msr_t msr; - int num_banks; struct cpuid_result cpuid_regs; /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE @@ -48,7 +47,6 @@ static void dnv_configure_mca(void) return; msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { /* Enable all error logging */ msr.lo = msr.hi = 0xffffffff; @@ -58,7 +56,7 @@ static void dnv_configure_mca(void) /* TODO(adurbin): This should only be done on a cold boot. Also, some of these banks are core vs package scope. For now every CPU clears every bank. */ - mca_configure(NULL); + mca_configure(); } static void denverton_core_init(struct device *cpu) diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 30851fd75b9..64099583a3a 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -59,6 +58,8 @@ static const struct pad_community dnv_gpio_communities[] = { NUM_SC0_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -76,6 +77,8 @@ static const struct pad_community dnv_gpio_communities[] = { .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -93,6 +96,8 @@ static const struct pad_community dnv_gpio_communities[] = { .gpi_status_offset = NUM_NC_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -110,6 +115,8 @@ static const struct pad_community dnv_gpio_communities[] = { .gpi_status_offset = 0, .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/denverton_ns/include/soc/hob_mem.h b/src/soc/intel/denverton_ns/include/soc/hob_mem.h index d98295b6f29..44d73fa428f 100644 --- a/src/soc/intel/denverton_ns/include/soc/hob_mem.h +++ b/src/soc/intel/denverton_ns/include/soc/hob_mem.h @@ -19,6 +19,7 @@ #ifndef _DENVERTON_NS_HOB_MEM_H #define _DENVERTON_NS_HOB_MEM_H +#include #include void soc_display_fsp_smbios_memory_info_hob( diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 5ed635d9431..ca2b353b0f3 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += spi.c +romstage-y += spi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c ramstage-y += chip.c ramstage-y += iosf.c diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index 68f56261d3a..3ea91e3b5e5 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h index 7b3a3c89186..f0ae0b37ad3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ b/src/soc/intel/fsp_baytrail/include/soc/i2c.h @@ -16,7 +16,6 @@ #ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ #define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ -#include #include #include diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index c46b09ef97c..52f4dc9d63e 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -208,7 +208,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Uh Oh! fsp_early_init should not return here.\n"); } /******************************************************************************* @@ -217,7 +218,6 @@ void main(FSP_INFO_HEADER *fsp_info_header) */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; uint32_t prev_sleep_state; @@ -244,7 +244,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4c); - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); + cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 4734e0e023a..356b855f3be 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -42,9 +42,6 @@ #include "chip.h" #include -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 - typedef struct soc_intel_fsp_baytrail_config config_t; static inline void @@ -101,7 +98,7 @@ static void sc_enable_ioapic(struct device *dev) reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) - die("APIC Error\n"); + die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 979ee573bbc..9375d195474 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -15,7 +15,7 @@ */ /* This file is derived from the flashrom project. */ - +#include #include #include #include @@ -33,7 +33,7 @@ typedef struct spi_slave ich_spi_slave; -static int ichspi_lock = 0; +static int g_ichspi_lock CAR_GLOBAL = 0; typedef struct ich9_spi_regs { uint32_t bfpr; @@ -81,7 +81,7 @@ typedef struct ich_spi_controller { uint16_t *control; } ich_spi_controller; -static ich_spi_controller cntlr; +static ich_spi_controller g_cntlr CAR_GLOBAL; enum { SPIS_SCIP = 0x0001, @@ -239,18 +239,19 @@ static ich9_spi_regs *spi_regs(void) void spi_init(void) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); ich9_spi_regs *ich9_spi = spi_regs(); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.preop = &ich9_spi->preop; + car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->preop = &ich9_spi->preop; } typedef struct spi_transaction { @@ -311,17 +312,18 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[cntlr->menubytes]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ichspi_lock) { + if (!car_get_var(g_ichspi_lock)) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); + writew_(optypes, cntlr->optype); return 0; } else { /* The lock is on. See if what we need is on the menu. */ @@ -332,20 +334,20 @@ static int spi_setup_opcode(spi_transaction *trans) if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == cntlr->menubytes) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; } - optypes = readw_(cntlr.optype); + optypes = readw_(cntlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -391,14 +393,15 @@ static int spi_setup_offset(spi_transaction *trans) */ static int ich_status_poll(uint16_t bitmask, int wait_til_set) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 40000; /* This will result in 400 ms */ uint16_t status = 0; while (timeout--) { - status = readw_(cntlr.status); + status = readw_(cntlr->status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr.status); + writew_((status & bitmask), cntlr->status); return status; } udelay(10); @@ -412,6 +415,7 @@ static int ich_status_poll(uint16_t bitmask, int wait_til_set) static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -437,7 +441,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -445,13 +449,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if ((with_address = spi_setup_offset(&trans)) < 0) return -1; - if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { + if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { /* * Treat Write Enable as Atomic Pre-Op if possible * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - writew_(trans.opcode, cntlr.preop); + writew_(trans.opcode, cntlr->preop); return 0; } @@ -459,13 +463,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) + if (readw_(cntlr->preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); /* * This is a 'no data' command (like Write Enable), its @@ -473,7 +477,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -495,7 +499,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr.databytes) { + if (trans.bytesout > cntlr->databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -509,28 +513,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = min(trans.bytesout, cntlr->databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = min(trans.bytesin, cntlr->databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); + write_reg(trans.out, cntlr->data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); + control &= ~((cntlr->databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -543,7 +547,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); + read_reg(cntlr->data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -552,7 +556,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); + writew_(0, cntlr->preop); return 0; } diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index a0c9ee538ef..fef7773cf97 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -38,9 +38,10 @@ #include #include #include -#include #include +#include "chip.h" + uint16_t get_pmbase(void) { return ACPI_BASE_ADDRESS; @@ -433,7 +434,7 @@ static void generate_P_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_step; int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; + int ratio, power, clock; int turbo; u32 control_status; msr_t msr; @@ -448,7 +449,6 @@ static void generate_P_state_entries(int core, int cores_per_package) msr = rdmsr(MSR_PLATFORM_INFO); ratio_min = (msr.hi >> 8) & 0xff; // LFM ratio_max = (msr.lo >> 8) & 0xff; // HFM - clock_max = (ratio_max * 100); /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index ba825f4aae3..a0b3f7ca6cd 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -22,7 +22,8 @@ #include #include #include -#include + +#include "chip.h" static void pci_domain_set_resources(struct device *dev) { diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index fd8ca38ab6d..edb313e7d5d 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -25,9 +25,10 @@ #include #include #include -#include #include +#include "../chip.h" + /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index a75dabd2256..38cd9476c59 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -84,7 +84,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Uh Oh! fsp_early_init should not return here.\n"); } /******************************************************************************* @@ -93,7 +94,6 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; post_code(0x4a); @@ -112,7 +112,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4d); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index a1e183adca2..2f87cad9dab 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -32,7 +32,8 @@ #include #include #include -#include + +#include "chip.h" typedef struct soc_intel_fsp_broadwell_de_config config_t; diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 2e9e3e251fd..052e37dadbb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -137,6 +138,11 @@ config SOC_INTEL_UART_DEV_MAX int default 3 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex @@ -151,7 +157,7 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 74c9182067e..cd6a6ba8422 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += uart.c ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 1ad89600c1b..f16469eb633 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -32,6 +31,8 @@ #include #include +#include "chip.h" + /* * List of supported C-states in this processor. */ diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 2d35f5bf39c..094079140d0 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 0e4388efd62..2616db17684 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include @@ -29,6 +27,8 @@ #include #include +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -103,6 +103,27 @@ const char *soc_acpi_name(const struct device *dev) } #endif +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const struct device *dev; + dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); + if (!dev || !dev->chip_info) + return; + + const config_t *config = dev->chip_info; + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -117,6 +138,8 @@ void soc_init_pre_device(void *chip_info) /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + soc_fill_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 3e2b78acd68..77611262a3f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -263,6 +264,25 @@ struct soc_intel_icelake_config { FORCE_ENABLE, FORCE_DISABLE, } CnviBtAudioOffload; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; }; typedef struct soc_intel_icelake_config config_t; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 62bcff68442..527b989e1a2 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -33,6 +32,8 @@ #include #include +#include "chip.h" + static void soc_fsp_load(void) { fsps_load(romstage_handoff_is_resume()); @@ -191,7 +192,7 @@ void soc_core_init(struct device *cpu) /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - mca_configure(NULL); + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c new file mode 100644 index 00000000000..2ec6b410dfa --- /dev/null +++ b/src/soc/intel/icelake/elog.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Intel Corporation. + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_a & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_a & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_a & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); + +void elog_gsmi_cb_platform_log_wake_source(void) +{ + struct chipset_power_state ps; + pmc_fill_pm_reg_info(&ps); + pch_log_wake_source(&ps); +} diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 3ada73d79c6..e061cda2f09 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -34,6 +33,8 @@ #include #include +#include "chip.h" + #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) @@ -86,6 +87,8 @@ static void pch_finalize(void) } pch_handle_sideband(config); + + pmc_clear_pmcon_sts(); } static void soc_finalize(void *unused) diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index 53620054ce8..96c5c838ada 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -76,14 +76,17 @@ static const struct pad_group icl_community5_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */ }; -static const struct pad_community icl_communities[] = { - { /* GPP G, B, A */ +static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { + /* GPP G, B, A */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_G0, .last_pad = GPP_A23, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -93,13 +96,17 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = icl_community0_groups, .num_groups = ARRAY_SIZE(icl_community0_groups), - }, { /* GPP H, D, F */ + }, + /* GPP H, D, F */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_H0, .last_pad = GPP_F19, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -109,13 +116,17 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community1_groups, .num_groups = ARRAY_SIZE(icl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -125,13 +136,17 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community2_groups, .num_groups = ARRAY_SIZE(icl_community2_groups), - }, { /* GPP C, E */ + }, + /* GPP C, E */ + [COMM_3] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPP_E23, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -141,13 +156,17 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community4_groups, .num_groups = ARRAY_SIZE(icl_community4_groups), - }, { /* GPP R, S */ + }, + /* GPP R, S */ + [COMM_4] = { .port = PID_GPIOCOM5, .first_pad = GPP_R0, .last_pad = GPP_S7, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 35fe8b62364..0fbddf06e9d 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -23,6 +23,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 86d5fb26710..6ecda855d64 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -265,6 +265,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h index e3eaf62d5c4..887e378e073 100644 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h @@ -21,17 +21,18 @@ * The GPIO groups are accessed through register blocks called * communities. */ -#define GPP_G 0 -#define GPP_B 1 -#define GPP_A 2 -#define GPP_H 3 -#define GPP_D 4 -#define GPP_F 5 -#define GPD 6 -#define GPP_C 7 -#define GPP_E 8 -#define GPP_R 9 -#define GPP_S 0xA +#define GPP_G 0x0 +#define GPP_B 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPP_S 0x4 +#define GPD 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_F 0x8 +#define GPP_VGPIO 0x9 +#define GPP_C 0xA +#define GPP_E 0xB #define GPIO_NUM_GROUPS 11 #define GPIO_MAX_NUM_PER_GROUP 24 @@ -280,4 +281,12 @@ #define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1) #define TOTAL_PADS 205 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + #endif diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 7c42b577301..218b8bfa60b 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -28,14 +28,6 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xfe032000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h index d5478d26e9d..e1560c1657d 100644 --- a/src/soc/intel/icelake/include/soc/pch.h +++ b/src/soc/intel/icelake/include/soc/pch.h @@ -26,6 +26,4 @@ #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 -void pch_log_state(void); - #endif diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 9caf49fa9af..44888ec7472 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -168,5 +168,8 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h index d0b500d1353..d78380a6dc3 100644 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ b/src/soc/intel/icelake/include/soc/ramstage.h @@ -16,11 +16,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include #include #include #include +#include "../../chip.h" + void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c index 8fe05072554..3d058242798 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/lpc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 821162e768e..f4467084ea9 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -27,6 +26,8 @@ #include #include +#include "chip.h" + void smm_region(void **start, size_t *size) { *start = (void *)sa_get_tseg_base(); @@ -219,7 +220,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index ac48da24f8a..8f61d70955c 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -25,6 +24,8 @@ #include #include +#include "chip.h" + /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 96ff52d1229..1c477835558 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -141,6 +141,20 @@ void pmc_set_disb(void) write8(addr, disb_val); } +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE @@ -196,3 +210,67 @@ int vbnv_cmos_failed(void) { return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); } + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_a & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index 9fc199deeec..28e7eada551 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -14,6 +14,5 @@ # romstage-y += fsp_params.c -romstage-y += power_state.c romstage-y += romstage.c romstage-y += systemagent.c diff --git a/src/soc/intel/icelake/romstage/power_state.c b/src/soc/intel/icelake/romstage/power_state.c deleted file mode 100644 index 40775509e4f..00000000000 --- a/src/soc/intel/icelake/romstage/power_state.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static inline int deep_s3_enabled(void) -{ - uint32_t deep_s3_pol; - - deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); - return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); -} - -/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) -{ - - /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ - if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = ACPI_S5; - - /* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. - */ - if (prev_sleep_state == ACPI_S3) { - /* PWR_FLR represents deep sleep power well loss. */ - uint32_t mask = PWR_FLR; - - /* If deep s3 isn't enabled check the suspend well too. */ - if (!deep_s3_enabled()) - mask |= SUS_PWR_FLR; - - if (ps->gen_pmcon_b & mask) - prev_sleep_state = ACPI_S5; - } - - return prev_sleep_state; -} - -void soc_fill_power_state(struct chipset_power_state *ps) -{ - uint8_t *pmc; - - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); - - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); - - pmc = pmc_mmio_regs(); - ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); - ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); - ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); - ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); - - printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", - ps->gblrst_cause[0], ps->gblrst_cause[1]); -} diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index a61370a1ee6..179d99cff67 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include @@ -31,6 +29,8 @@ #include #include +#include "../chip.h" + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -96,6 +96,7 @@ static void save_dimm_info(void) src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index ddf642003f0..5c00b63720b 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -25,6 +24,8 @@ #include #include +#include "chip.h" + #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 7903667e9e2..930e78ed5e8 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 421cafc7184..7174a9a58f8 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -24,10 +24,6 @@ #include #include -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 83bed34347d..2cb5adf4f29 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 595c818593b..bb1a26437fb 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -38,7 +38,8 @@ static void i2c_disable(I2C_REGS *regs) while (status & IC_ENABLE_CONTROLLER) { udelay(1); if (--timeout == 0) - die("ERROR - I2C failed to disable!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - I2C failed to disable!\n"); status = regs->ic_enable_status; } diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 67e37de9430..56be795dcd7 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -18,11 +18,12 @@ #define _SOC_RAMSTAGE_H_ #include -#include #include #include #include +#include "../../chip.h" + void mainboard_gpio_i2c_init(struct device *dev); asmlinkage void chipset_teardown_car(void); diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fb8a844815d..c7de080146d 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,7 +25,7 @@ #include #include -asmlinkage void *car_stage_c_entry(void); +asmlinkage void car_stage_c_entry(void); void clear_smi_and_wake_events(void); void disable_rom_shadow(void); void *locate_rmu_file(size_t *rmu_file_len); diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index 62c9e792368..1c93f1cdf0e 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -48,9 +48,4 @@ struct log_entry { #define LOG_ENTRIES 256 -extern struct log_entry log[LOG_ENTRIES]; -extern uint8_t log_index; -extern int log_full; -extern long log_start_time; - #endif /* __STORAGE_TEST_H__ */ diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d51587143b9..c9847eaac70 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,12 +29,6 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry -#if CONFIG(PLATFORM_USES_FSP1_1) -#if !ENV_VERSTAGE -#include "src/drivers/intel/fsp1_1/after_raminit.S" -#endif -#endif - /* The code should never reach this point */ movb $0x69, %ah jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 31e130a3985..5ebbacbd2a7 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include "../chip.h" @@ -26,7 +26,7 @@ #include #include -asmlinkage void *car_stage_c_entry(void) +asmlinkage void car_stage_c_entry(void) { struct postcar_frame pcf; bool s3wake; @@ -83,23 +83,21 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); - return NULL; } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; struct chipset_power_state *get_power_state(void) { - return (struct chipset_power_state *)car_get_var_ptr(&power_state); + return &power_state; } int fill_power_state(void) { - struct chipset_power_state *ps = get_power_state(); - - ps->prev_sleep_state = 0; - printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps->prev_sleep_state; + power_state.prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", + power_state.prev_sleep_state); + return power_state.prev_sleep_state; } void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) @@ -117,7 +115,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) /* Locate the RMU data file in flash */ rmu_data = locate_rmu_file(&rmu_data_len); if (!rmu_data) - die("Microcode file (rmu.bin) not found."); + die_with_post_code(POST_INVALID_CBFS, + "Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ dev = pcidev_path_on_root(LPC_DEV_FUNC); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index f2a280effb4..4ac580eb287 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/quark/spi.c b/src/soc/intel/quark/spi.c index 7ffa203bdc5..0bd0473db5f 100644 --- a/src/soc/intel/quark/spi.c +++ b/src/soc/intel/quark/spi.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index bdf86b1f129..653466a6d93 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -29,13 +28,13 @@ #include #if CONFIG(STORAGE_LOG) -struct log_entry log[LOG_ENTRIES] CAR_GLOBAL; -uint8_t log_index CAR_GLOBAL; -int log_full CAR_GLOBAL; -long log_start_time CAR_GLOBAL; +struct log_entry log[LOG_ENTRIES]; +uint8_t log_index; +int log_full; +long log_start_time; #endif -static uint8_t drivers_storage[256] CAR_GLOBAL; +static uint8_t drivers_storage[256]; #define STORAGE_DEBUG BIOS_DEBUG #define LOG_DEBUG (CONFIG(STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) @@ -175,7 +174,7 @@ void storage_test(uint32_t bar, int full_initialization) /* Get the structure addresses */ media = NULL; if (ENV_ROMSTAGE) - media = car_get_var_ptr(drivers_storage); + media = (struct storage_media *)drivers_storage; else media = cbmem_find(CBMEM_ID_STORAGE_DATA); sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); @@ -255,7 +254,7 @@ static void copy_storage_structures(int is_recovery) sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); /* Migrate the data into CBMEM */ - memcpy(media, car_get_var_ptr(drivers_storage), size); + memcpy(media, drivers_storage, size); media->ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr; } diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 5116f3ab251..626b5f80f08 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -106,7 +106,7 @@ config CHROMEOS config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS @@ -289,6 +289,11 @@ config CPU_BCLK_MHZ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe030000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ee2c928464e..e9f555f13c1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -35,7 +35,6 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += memmap.c romstage-y += me.c -romstage-y += pei_data.c romstage-y += pmc.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -58,7 +57,6 @@ ramstage-y += lpc.c ramstage-y += me.c ramstage-y += memmap.c ramstage-y += p2sb.c -ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 26a131ddc26..bd944dac16e 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -51,6 +50,8 @@ #include #include +#include "chip.h" + /* * List of suported C-states in this processor. */ diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 0f6c8a85d43..c95a8d80e84 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ #include -#include #include #include #include @@ -37,6 +36,8 @@ #include #include +#include "../chip.h" + #define PCR_DMI_DMICTL 0x2234 #define PCR_DMI_DMICTL_SRLOCK (1 << 31) #define PCR_DMI_ACPIBA 0x27B4 diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index f79343508b0..1e81809b4f5 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -59,6 +59,7 @@ static struct { { PCI_DEVICE_ID_INTEL_KBL_ID_H, "Kabylake-H" }, { PCI_DEVICE_ID_INTEL_KBL_ID_S, "Kabylake-S" }, { PCI_DEVICE_ID_INTEL_KBL_ID_DT, "Kabylake DT" }, + { PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, "Kabylake DT 2" }, }; static struct { @@ -71,6 +72,11 @@ static struct { { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_H110, "Skylake PCH-H H110" }, + { PCI_DEVICE_ID_INTEL_SPT_H_H170, "Skylake PCH-H H170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_Z170, "Skylake PCH-H Z170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_Q170, "Skylake PCH-H Q170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_Q150, "Skylake PCH-H Q150" }, + { PCI_DEVICE_ID_INTEL_SPT_H_B150, "Skylake PCH-H B150" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9094348e787..6f90178f524 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -33,6 +32,8 @@ #include #include +#include "chip.h" + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e76b24..a537165dd9b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -34,6 +34,7 @@ #include #include #include +#include #define MAX_PEG_PORTS 3 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index c16a913218a..d179598699e 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -42,6 +41,8 @@ #include #include +#include "chip.h" + struct pcie_entry { unsigned int devfn; unsigned int func_count; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3e77b03c3fe..a63809bd7e2 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -15,13 +15,11 @@ * GNU General Public License for more details. */ -#include #include #include #include #include #include -#include #include #include #include @@ -47,6 +45,8 @@ #include #include +#include "chip.h" + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -428,7 +428,7 @@ void soc_core_init(struct device *cpu) /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - mca_configure(NULL); + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index c69dffbe41b..34738f28f15 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -18,10 +18,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -41,6 +39,8 @@ #include #include +#include "chip.h" + #define PSF_BASE_ADDRESS 0xA00 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) @@ -141,9 +141,6 @@ static void soc_finalize(void *unused) pch_finalize_script(dev); - printk(BIOS_DEBUG, "Clearing MCA.\n"); - mp_run_on_all_cpus(mca_configure, NULL, 17 * USECS_PER_SEC); - soc_lockdown(dev); printk(BIOS_DEBUG, "Finalizing SMM.\n"); diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 3d66fa46020..67edeae126a 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -74,6 +73,8 @@ static const struct pad_community skl_gpio_communities[] = { .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -94,6 +95,8 @@ static const struct pad_community skl_gpio_communities[] = { .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -115,6 +118,8 @@ static const struct pad_community skl_gpio_communities[] = { .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -131,6 +136,8 @@ static const struct pad_community skl_gpio_communities[] = { .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67ab88a..f563c113024 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -25,6 +25,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h index 3ab0efa7e56..2071d58b49e 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include #include #include #include +#include "../../../chip.h" + #define FSP_SIL_UPD SILICON_INIT_UPD #define FSP_MEM_UPD MEMORY_INIT_UPD diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h index 36825f7aeaa..386931043dc 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -24,6 +24,4 @@ void intel_early_me_status(void); void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index e75b3500495..e5660a6f66c 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include #include #include #include +#include "../../../chip.h" + #define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 1c143a2c43c..321d3c20c34 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -225,6 +225,8 @@ #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 #define HOSTSW_OWN_REG_0 0xd0 #define PAD_CFG_BASE 0x400 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 628a272a546..c73d766953a 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -25,13 +25,6 @@ #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -#define UART_BASE_SIZE 0x1000 -#define UART_BASE_0_ADDRESS 0xfe030000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index d95bcaf2598..e2bf5a119c6 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -20,7 +20,6 @@ #include -void pch_log_state(void); #if ENV_RAMSTAGE void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h deleted file mode 100644 index 02e04c6c023..00000000000 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * UEFI PEI wrapper - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PEI_DATA_H_ -#define _PEI_DATA_H_ - -#include - -#define PEI_VERSION 22 - -#define ABI_X86 __attribute__((regparm(0))) - -typedef void ABI_X86(*tx_byte_func)(unsigned char byte); - -struct pei_data { - uint32_t pei_version; - - int boot_mode; - int ec_present; - - /* Console output function */ - tx_byte_func tx_byte; - - /* - * DIMM SPD data for memory down configurations - * [CHANNEL][SLOT][SPD] - */ - uint8_t spd_data[2][2][512]; - - /* - * LPDDR3 DQ byte map - * [CHANNEL][ITERATION][2] - * - * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) - * DQByteMap[0] - ClkDQByteMap: - * - If clock is per rank, program to [0xFF, 0xFF] - * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] - * - If clock is shared by 2 ranks but does not go to all bytes, - * Entry[i] defines which DQ bytes Group i services - * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB - * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB - * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB - * For DDR, DQByteMap[3:1] = [0xFF, 0] - * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] - * since we have 1 CTL / rank - * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] - * since we have 1 CA Vref - */ - uint8_t dq_map[2][12]; - - /* - * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins - * [CHANNEL][MAX_BYTES] - */ - uint8_t dqs_map[2][8]; - uint16_t RcompResistor[3]; - uint16_t RcompTarget[5]; - /* Data read from flash and passed into MRC */ - const void *saved_data; - int saved_data_size; - - /* Disable use of saved data (can be set by mainboard) */ - int disable_saved_data; - - /* Data from MRC that should be saved to flash */ - void *data_to_save; - int data_to_save_size; - int mem_cfg_id; -} __packed; - -typedef struct pei_data PEI_DATA; - -#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 8e53f54b750..d7dec65f585 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -48,9 +48,17 @@ bool soc_is_vtd_capable(void); -static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +static const struct sa_mmio_descriptor soc_gfxvt_mmio_descriptor = { + GFXVTBAR, + GFXVT_BASE_ADDRESS, + GFXVT_BASE_SIZE, + "GFXVTBAR" }; +static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = { + VTVC0BAR, + VTVC0_BASE_ADDRESS, + VTVC0_BASE_SIZE, + "VTVC0BAR" +}; #endif diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 60a7070408f..ff7edbc95a5 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -29,6 +28,8 @@ #include #include +#include "chip.h" + size_t mmap_region_granularity(void) { if (CONFIG(HAVE_SMI_HANDLER)) @@ -169,13 +170,13 @@ static size_t get_prmrr_size(uintptr_t dram_base, } /* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) +static size_t calculate_traditional_mem_size(uintptr_t dram_base) { + const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); uintptr_t traditional_mem_base = dram_base; size_t traditional_mem_size; - if (dev->enabled) { + if (igd_dev && igd_dev->enabled) { /* Read BDSM from Host Bridge */ traditional_mem_base -= sa_get_dsm_size(); @@ -199,9 +200,9 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, * Calculate Intel Reserved Memory size based on * PRMRR size, Trace Hub config and PTT selection. */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) +static size_t calculate_reserved_mem_size(uintptr_t dram_base) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); uintptr_t reserve_mem_base = dram_base; size_t reserve_mem_size; const struct soc_intel_skylake_config *config; @@ -258,20 +259,15 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, static uintptr_t calculate_dram_base(size_t *reserved_mem_size) { uintptr_t dram_base; - const struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); - if (!dev) - die("ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); + dram_base -= calculate_traditional_mem_size(dram_base); /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); + *reserved_mem_size = calculate_reserved_mem_size(dram_base); dram_base -= *reserved_mem_size; diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c deleted file mode 100644 index a2887ac4c4f..00000000000 --- a/src/soc/intel/skylake/pei_data.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void ABI_X86 send_to_console(unsigned char b) -{ - console_tx_byte(b); -} - -void soc_fill_pei_data(struct pei_data *pei_data) -{ - const struct device *dev; - const struct soc_intel_skylake_config *config; - - /* Set the parameters for MemoryInit */ - dev = dev_find_slot(0, PCH_DEVFN_LPC); - config = dev->chip_info; - - pei_data->pei_version = PEI_VERSION; - pei_data->tx_byte = &send_to_console; - - /* Force a full memory train if RMT is enabled */ - pei_data->disable_saved_data = config->Rmt; -} diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 5ff05c26c25..01def44b069 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include @@ -28,6 +27,8 @@ #include #include +#include "chip.h" + void pmc_set_disb(void) { /* Set the DISB after DRAM init */ diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 8bfbfea66ab..e929ebaf177 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index d8188f69245..29c4774dc12 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -15,9 +15,7 @@ */ #include -#include #include -#include #include #include #include @@ -27,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -37,14 +34,19 @@ #include #include +#include "../chip.h" + /* SOC initialization before RAM is enabled */ void soc_pre_ram_init(struct romstage_params *params) { /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - /* Prepare to initialize memory */ - soc_fill_pei_data(params->pei_data); + const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *const config = + dev ? dev->chip_info : NULL; + /* Force a full memory train if RMT is enabled */ + params->disable_saved_data = config && config->Rmt; } /* UPD parameters to be initialized before MemoryInit */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index dcfc3632ca2..04c369beb8a 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -14,13 +14,11 @@ */ #include -#include #include #include #include #include #include -#include #include #include #include @@ -37,6 +35,8 @@ #include #include +#include "../chip.h" + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -125,6 +125,7 @@ static void save_dimm_info(void) src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } @@ -263,14 +264,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, int i; uint32_t mask = 0; - /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. - */ - m_cfg->IgdDvmt50PreAlloc = 2; m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -310,14 +303,20 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, * the FSP does not initialize this device */ m_cfg->InternalGfx = 0; - if (config->PrimaryDisplay == Display_iGFX) - m_cfg->PrimaryDisplay = Display_Auto; - else - m_cfg->PrimaryDisplay = config->PrimaryDisplay; + m_cfg->IgdDvmt50PreAlloc = 0; } else { m_cfg->InternalGfx = 1; - m_cfg->PrimaryDisplay = config->PrimaryDisplay; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake + * does not have access to the bios_reserved range so it always + * assumes 8MB is used and so the kernel will avoid the last + * 8MB of the stolen window. With the default stolen size of + * 32MB(-8MB) there is not enough space for FBC to work with + * a high resolution panel + */ + m_cfg->IgdDvmt50PreAlloc = 2; } + m_cfg->PrimaryDisplay = config->PrimaryDisplay; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 00a27827230..71a9bee1e0e 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,11 +26,12 @@ static void systemagent_vtd_init(void) { - const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; - if (dev) - config = dev->chip_info; + if (root_dev) + config = root_dev->chip_info; if (config && config->ignore_vtd) return; @@ -39,7 +40,10 @@ static void systemagent_vtd_init(void) if (!vtd_capable) return; - sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); + if (igd_dev && igd_dev->enabled) + sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1); + + sa_set_mch_bar(&soc_vtvc0_mmio_descriptor, 1); } void systemagent_early_init(void) diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 12c6abe4fd7..571d3e7b44c 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -35,7 +35,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) gpio->pin_count = 1; gpio->pins[0] = config->sdcard_cd_gpio_default; } else - gpio = &config->sdcard_cd_gpio; + *gpio = config->sdcard_cd_gpio; return 0; } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index fa0cd5e6dbb..bfaadfd3a96 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -42,6 +42,7 @@ bool soc_is_vtd_capable(void) */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { + struct device *const igd_dev = SA_DEV_IGD; static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -56,9 +57,14 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); - if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) - sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, - ARRAY_SIZE(soc_vtd_resources)); + if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) { + if (igd_dev && igd_dev->enabled) + sa_add_fixed_mmio_resources(dev, index, + &soc_gfxvt_mmio_descriptor, 1); + + sa_add_fixed_mmio_resources(dev, index, + &soc_vtvc0_mmio_descriptor, 1); + } } /* diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c index 711b714b049..97cd1b77793 100644 --- a/src/soc/intel/skylake/thermal.c +++ b/src/soc/intel/skylake/thermal.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -23,6 +22,8 @@ #include #include +#include "chip.h" + #define MAX_TRIP_TEMP 205 #define DEFAULT_TRIP_TEMP 50 diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 1b2a7428df8..8b7c99eae52 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -24,10 +24,6 @@ #include #include -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { { @@ -55,17 +51,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 480371b67c9..d0ffa86c485 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -69,5 +69,6 @@ void pll_set_pcw_change(const struct pll *pll); void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); +void mt_pll_raise_ca53_freq(u32 freq); #endif diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index d039e0becff..ff5dd34d89a 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -16,7 +16,6 @@ #ifndef SOC_MEDIATEK_RTC_COMMON_H #define SOC_MEDIATEK_RTC_COMMON_H -#include #include #include #include diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 0968d2f59fa..a63fe8927b8 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -16,6 +16,7 @@ #include #include #include +#include #define GENMASK(h, l) (BIT(h + 1) - BIT(l)) diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 1b8bc5d3a08..6785c0a0bd0 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -14,7 +14,6 @@ */ #include -#include #include #include diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 3e7186ae8e3..71ed95a228e 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index b0d6fa0fade..e966b8e58bd 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -16,7 +16,7 @@ config SOC_MEDIATEK_MT8173 if SOC_MEDIATEK_MT8173 config VBOOT - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 0b78c3ea64e..f8896d391aa 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -19,6 +19,7 @@ #include #include #include +#include #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 529ebde3f1a..0a8e69be1e9 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index d4cd02aa09f..be84668abee 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 2d998947bbf..3395539bf1f 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index 4106d2a9242..480ffbfb2d6 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -292,7 +292,6 @@ enum { void mt_pll_post_init(void); void mt_pll_set_aud_div(u32 rate); void mt_pll_enable_ssusb_clk(void); -void mt_pll_raise_ca53_freq(u32 freq); void mt_mem_pll_set_clk_cfg(void); void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params); void mt_mem_pll_config_post(void); diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index c59fa3f528e..e1c1bff6d53 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -16,11 +16,10 @@ #include #include #include -#include - #include #include #include +#include enum mux_id { TOP_AXI_SEL, @@ -432,7 +431,8 @@ void mt_pll_set_aud_div(u32 rate) } } -void mt_pll_raise_ca53_freq(u32 freq) { +void mt_pll_raise_ca53_freq(u32 freq) +{ pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index 469653a26c7..af88343c14f 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 79e5732c2f8..9ad4caa89c8 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -18,6 +18,7 @@ #include #include #include +#include #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 6582e4e43c7..f96282cf625 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -14,7 +14,7 @@ config SOC_MEDIATEK_MT8183 if SOC_MEDIATEK_MT8183 config VBOOT - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 3fce0a81fd4..5392a9e6358 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -32,6 +32,7 @@ romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c romstage-y += mt8183.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index caf9a0346a4..a167d2b58e1 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 5a5f58db3b2..2a72e2c61c2 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -244,7 +244,7 @@ enum { /* PLL rate */ enum { - ARMPLL_LL_HZ = 1100 * MHz, + ARMPLL_LL_HZ = 1417 * MHz, ARMPLL_L_HZ = 1200 * MHz, CCIPLL_HZ = 598 * 2 * MHz, MAINPLL_HZ = 1092 * MHz, diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 3dc9fe23b42..705424337f5 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -13,9 +13,10 @@ * GNU General Public License for more details. */ -#include +#include #include #include +#include static struct pmic_setting init_setting[] = { /* [15:0]: TMA_KEY */ @@ -493,6 +494,10 @@ static struct pmic_setting init_setting[] = { /* [2:1]: RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL */ /* [2:2]: RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL */ {0x1B6C, 0x6, 0x6, 0}, + + /* Vproc11/Vproc12 to 1.05V */ + {0x13a6, 0x58, 0x7F, 0}, + {0x140a, 0x58, 0x7F, 0}, }; static struct pmic_setting lp_setting[] = { @@ -771,13 +776,18 @@ static void mt6358_lp_setting(void) void mt6358_init(void) { + struct stopwatch voltage_settled; + if (pwrap_init()) die("ERROR - Failed to initialize pmic wrap!"); pmic_set_power_hold(true); pmic_wdt_set(); mt6358_init_setting(); + stopwatch_init_usecs_expire(&voltage_settled, 200); wk_sleep_voltage_by_ddr(); wk_power_down_seq(); mt6358_lp_setting(); + while (!stopwatch_expired(&voltage_settled)) + /* wait for voltages to settle */; } diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de7fb9..07ce6603f67 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -356,4 +356,21 @@ void mt_pll_init(void) /* enable [14] dramc_pll104m_ck */ setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* enable audio clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + + /* enable intbus clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + + /* enable infra clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + + /* enable mtkaif 26m clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); +} + +void mt_pll_raise_ca53_freq(u32 freq) +{ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); } diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index eecb59b0278..475d50e210b 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -18,7 +18,7 @@ config SOC_NVIDIA_TEGRA124 if SOC_NVIDIA_TEGRA124 config VBOOT - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 8883baa3585..6750aa9f9a6 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -18,7 +18,7 @@ if SOC_NVIDIA_TEGRA210 config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 76054f01561..ae20d44d16d 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -12,9 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include #include #include -#include #include #include #include @@ -24,14 +25,15 @@ #include #include #include -#include "chip.h" #include #include #include #include #include +#include + +#include "chip.h" #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" -#include struct tegra_mipi_device mipi_device_data[NUM_DSI]; diff --git a/src/soc/nvidia/tegra210/funitcfg.c b/src/soc/nvidia/tegra210/funitcfg.c index a218862f3ef..887f9f08014 100644 --- a/src/soc/nvidia/tegra210/funitcfg.c +++ b/src/soc/nvidia/tegra210/funitcfg.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 1093479d5ff..3cb94ce8d33 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -19,6 +19,7 @@ #include #include +#include /* * The DMA engine operates on 4 bytes at a time, so make sure any data diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4e6bdf0242d..4e56730d3b2 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include #include - #include #include #include @@ -25,6 +23,7 @@ #include #include #include +#include int mipi_dphy_set_timing(struct tegra_dsi *dsi) { diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 54f42047020..13fa1c6a024 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index edb052df6bd..9310e0cc093 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -26,9 +26,8 @@ #include #include #include -#include -#include #include +#include #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig new file mode 100644 index 00000000000..8a1f6d62fd7 --- /dev/null +++ b/src/soc/qualcomm/common/Kconfig @@ -0,0 +1,15 @@ + +config SOC_QUALCOMM_COMMON + bool + default n + help + Selected by platforms that use the common code. + +if SOC_QUALCOMM_COMMON + +config QC_SDI_ENABLE + bool + default n + prompt "Debug Build: enable SDI" + +endif diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h new file mode 100644 index 00000000000..ee781224bd4 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_MMU_COMMON_H_ +#define _SOC_QUALCOMM_MMU_COMMON_H_ + +#include +#include + +#define CACHED_RAM (MA_MEM | MA_S | MA_RW) +#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC) +#define DEV_MEM (MA_DEV | MA_S | MA_RW) + +static struct region * const ddr_region = (struct region *)_ddr_information; + +void soc_mmu_dram_config_post_dram_init(void); +void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); + +#endif /* _SOC_QUALCOMM_MMU_COMMON_H_ */ diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h new file mode 100644 index 00000000000..19ec083bfd1 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCLIB_COMMON_H__ +#define _SOC_QUALCOMM_QCLIB_COMMON_H__ + +/* coreboot & QCLib I/F definitions */ + +/* string field lengths */ +#define QCLIB_MAGIC_NUMBER_LENGTH 8 +#define QCLIB_FMAP_NAME_LENGTH 24 +#define QCLIB_TE_NAME_LENGTH 24 + +/* FMAP_REGION names */ +#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" +#define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG" + +/* TE_NAME (table entry name) */ +#define QCLIB_TE_DDR_INFORMATION "ddr_information" +#define QCLIB_TE_QCLIB_LOG_BUFFER "qclib_log_buffer" +#define QCLIB_TE_DCB_SETTINGS "dcb_settings" +#define QCLIB_TE_CDT_SETTINGS "cdt_settings" +#define QCLIB_TE_PMIC_SETTINGS "pmic_settings" +#define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" +#define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data" +#define QCLIB_TE_QCSDI "qcsdi" + +/* BA_BMASK_VALUES (blob_attributes bit mask values) */ +#define QCLIB_BA_SAVE_TO_STORAGE 0x00000001 + +struct qclib_cb_if_table_entry { + char name[QCLIB_TE_NAME_LENGTH]; /* 0x00 TE_NAME */ + uint64_t blob_address; /* 0x18 blob addr in SRAM */ + uint32_t size; /* 0x20 blob size in SRAM */ + uint32_t blob_attributes; /* 0x24 BA_BMASK_VALUES */ +}; + +/* GA_BMASK_VALUES (global_attributes bit mask values) */ +#define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001 + +#define QCLIB_INTERFACE_VERSION 0x00000001 +#define QCLIB_MAX_NUMBER_OF_ENTRIES 16 + +#define QCLIB_MAGIC_NUMBER "QCLIB_CB" + +struct qclib_cb_if_table { + char magic[8]; /* 0x00 */ + uint32_t version; /* 0x08 */ + uint32_t num_entries; /* 0x0C */ + uint32_t max_entries; /* 0x10 */ + uint32_t global_attributes; /* 0x14 */ + uint64_t reserved; /* 0x18 */ + struct qclib_cb_if_table_entry + te[QCLIB_MAX_NUMBER_OF_ENTRIES]; /* 0x20 */ +}; + +extern struct qclib_cb_if_table qclib_cb_if_table; + +void qclib_add_if_table_entry(const char *name, void *base, + uint32_t size, uint32_t attrs); +void qclib_load_and_run(void); +int qclib_soc_blob_load(void); + +#endif // _SOC_QUALCOMM_QCLIB_COMMON_H_ diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h new file mode 100644 index 00000000000..ffa535c493f --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SYMBOLS_COMMON_H_ +#define _SOC_QUALCOMM_SYMBOLS_COMMON_H_ + +#include + +DECLARE_REGION(ddr_training); +DECLARE_REGION(qclib_serial_log); +DECLARE_REGION(ddr_information); + +#endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c new file mode 100644 index 00000000000..79d2eb72710 --- /dev/null +++ b/src/soc/qualcomm/common/mmu.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +__weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ } + +void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) +{ + mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + soc_mmu_dram_config_post_dram_init(); +} diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c new file mode 100644 index 00000000000..73c525001e3 --- /dev/null +++ b/src/soc/qualcomm/common/qclib.c @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct qclib_cb_if_table qclib_cb_if_table = { + .magic = QCLIB_MAGIC_NUMBER, + .version = QCLIB_INTERFACE_VERSION, + .num_entries = 0, + .max_entries = QCLIB_MAX_NUMBER_OF_ENTRIES, + .global_attributes = 0, + .reserved = 0, +}; + +void qclib_add_if_table_entry(const char *name, void *base, + uint32_t size, uint32_t attrs) +{ + struct qclib_cb_if_table_entry *te = + &qclib_cb_if_table.te[qclib_cb_if_table.num_entries++]; + assert(qclib_cb_if_table.num_entries <= qclib_cb_if_table.max_entries); + strncpy(te->name, name, sizeof(te->name)); + te->blob_address = (uintptr_t)base; + te->size = size; + te->blob_attributes = attrs; +} + +static void write_ddr_information(struct qclib_cb_if_table_entry *te) +{ + uint64_t ddr_size; + + /* Save DDR info in SRAM region to share with ramstage */ + ddr_region->offset = te->blob_address; + ddr_size = te->size; + ddr_region->size = ddr_size * MiB; + + /* Use DDR info to configure MMU */ + qc_mmu_dram_config_post_dram_init((void *)ddr_region->offset, + (size_t)ddr_region->size); +} + +static void write_qclib_log_to_cbmemc(struct qclib_cb_if_table_entry *te) +{ + int i; + char *ptr = (char *)te->blob_address; + + for (i = 0; i < te->size; i++) + __cbmemc_tx_byte(*ptr++); +} + +static void write_table_entry(struct qclib_cb_if_table_entry *te) +{ + + if (!strncmp(QCLIB_TE_DDR_INFORMATION, te->name, + sizeof(te->name))) { + + write_ddr_information(te); + + } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, + sizeof(te->name))) { + + assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, + (const void *)te->blob_address, te->size)); + + } else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, + sizeof(te->name))) { + + assert(fmap_overwrite_area(QCLIB_FR_LIMITS_CFG_DATA, + (const void *)te->blob_address, te->size)); + + } else if (!strncmp(QCLIB_TE_QCLIB_LOG_BUFFER, te->name, + sizeof(te->name))) { + + write_qclib_log_to_cbmemc(te); + + } else { + + printk(BIOS_WARNING, "%s write not implemented\n", te->name); + printk(BIOS_WARNING, " blob_address[%llx]..size[%x]\n", + te->blob_address, te->size); + + } +} + +static void dump_te_table(void) +{ + struct qclib_cb_if_table_entry *te; + int i; + + for (i = 0; i < qclib_cb_if_table.num_entries; i++) { + te = &qclib_cb_if_table.te[i]; + printk(BIOS_DEBUG, "[%s][%llx][%x][%x]\n", + te->name, te->blob_address, + te->size, te->blob_attributes); + } +} + +__weak int qclib_soc_blob_load(void) { return 0; } + +void qclib_load_and_run(void) +{ + int i; + ssize_t ssize; + struct mmu_context pre_qclib_mmu_context; + + /* zero ddr_information SRAM region, needs new data each boot */ + memset(ddr_region, 0, sizeof(struct region)); + + /* output area, QCLib copies console log buffer out */ + if (CONFIG(CONSOLE_CBMEM)) + qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER, + _qclib_serial_log, + REGION_SIZE(qclib_serial_log), 0); + + /* output area, QCLib fills in DDR details */ + qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0); + + /* Attempt to load DDR Training Blob */ + ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training, + REGION_SIZE(ddr_training)); + if (ssize < 0) + goto fail; + qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, + _ddr_training, ssize, 0); + + /* hook for SoC specific binary blob loads */ + if (qclib_soc_blob_load()) { + printk(BIOS_ERR, "qclib_soc_blob_load failed\n"); + goto fail; + } + + /* Enable QCLib serial output, based on Kconfig */ + if (CONFIG(CONSOLE_SERIAL)) + qclib_cb_if_table.global_attributes = + QCLIB_GA_ENABLE_UART_LOGGING; + + if (CONFIG(QC_SDI_ENABLE)) { + struct prog qcsdi = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi"); + + /* Attempt to load QCSDI elf */ + if (prog_locate(&qcsdi)) + goto fail; + + if (cbfs_prog_stage_load(&qcsdi)) + goto fail; + + qclib_add_if_table_entry(QCLIB_TE_QCSDI, prog_entry(&qcsdi), + prog_size(&qcsdi), 0); + printk(BIOS_INFO, "qcsdi.entry[%p]\n", qcsdi.entry); + } + + dump_te_table(); + + /* Attempt to load QCLib elf */ + struct prog qclib = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qclib"); + + if (prog_locate(&qclib)) + goto fail; + + if (cbfs_prog_stage_load(&qclib)) + goto fail; + + prog_set_entry(&qclib, prog_entry(&qclib), &qclib_cb_if_table); + + printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize DDR\n"); + printk(BIOS_DEBUG, "Global Attributes[%x]..Table Entries Count[%d]\n", + qclib_cb_if_table.global_attributes, + qclib_cb_if_table.num_entries); + printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", + prog_entry(&qclib), prog_entry_arg(&qclib)); + + /* back-up mmu context before disabling mmu and executing qclib */ + mmu_save_context(&pre_qclib_mmu_context); + /* disable mmu before jumping to qclib. mmu_disable also + flushes and invalidates caches before disabling mmu. */ + mmu_disable(); + + prog_run(&qclib); + + /* Before returning, QCLib flushes cache and disables mmu. + Explicitly disable mmu (flush, invalidate and disable mmu) + before re-enabling mmu with backed-up mmu context */ + mmu_disable(); + mmu_restore_context(&pre_qclib_mmu_context); + mmu_enable(); + + /* step through I/F table, handling return values */ + for (i = 0; i < qclib_cb_if_table.num_entries; i++) + if (qclib_cb_if_table.te[i].blob_attributes & + QCLIB_BA_SAVE_TO_STORAGE) + write_table_entry(&qclib_cb_if_table.te[i]); + + /* confirm that we received valid ddr information from QCLib */ + assert((uintptr_t)_dram == region_offset(ddr_region) && + region_sz(ddr_region) >= (u8 *)cbmem_top() - _dram); + + printk(BIOS_DEBUG, "QCLib completed\n\n\n"); + + return; + +fail: + die("Couldn't run QCLib.\n"); +} diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 72e05faf22e..90744d5285c 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -47,7 +47,7 @@ config SBL_ELF config SBL_UTIL_PATH depends on USE_BLOBS string "Path for utils to combine SBL_ELF and bootblock" - default "util/ipqheader" + default "util/qualcomm" help Path for utils to combine SBL_ELF and bootblock diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index f5c9943cfa6..f20dada0b06 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -29,7 +29,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include #include #include #include diff --git a/src/soc/qualcomm/ipq40xx/mbn_header.h b/src/soc/qualcomm/ipq40xx/mbn_header.h index cedcf125845..a48de1c8832 100644 --- a/src/soc/qualcomm/ipq40xx/mbn_header.h +++ b/src/soc/qualcomm/ipq40xx/mbn_header.h @@ -18,7 +18,7 @@ #include -/* QCA firmware blob header gleaned from util/ipqheader/ipqheader.py */ +/* QCA firmware blob header gleaned from util/qualcomm/ipqheader.py */ struct mbn_header { u32 mbn_type; diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 9d1f92d48a1..438bd14757c 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -478,8 +478,7 @@ qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE)); - if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) - && (curr_state & QUP_STATE_VALID_MASK)) { + if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) { /* * For PAUSE_STATE to RESET_STATE transition, * two writes of 10[binary]) are required for the diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 109eda9fc09..b68e1cb8640 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -648,8 +648,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) { struct ipq_spi_slave *ds = NULL; int i; - unsigned int bus = slave->bus; - unsigned int cs = slave->cs; + int bus = slave->bus; + int cs = slave->cs; if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI) || ((bus == BLSP0_SPI) && (cs > 2)) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 8a428b2f0d2..1fd134a7b36 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -62,14 +62,14 @@ ifeq ($(CONFIG_USE_BLOBS),y) # Add MBN header to allow SBL3 to start coreboot bootblock $(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin @printf " ADD MBN $(subst $(obj)/,,$(@))\n" - ./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp + ./util/qualcomm/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp @mv $@.tmp $@ # Create a complete bootblock which will start up the system $(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ $(objcbfs)/bootblock.mbn @printf " MBNCAT $(subst $(obj)/,,$(@))\n" - @util/ipqheader/mbncat.py -o $@.tmp $^ + @util/qualcomm/mbncat.py -o $@.tmp $^ @mv $@.tmp $@ endif diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index cd57591bebf..c81373fade9 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. */ -#include #include #include #include diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index 482deadfe7d..7ecc1eee168 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -34,6 +34,7 @@ #define __IPQ860X_CLOCK_H_ #include +#include /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h index 1e6a32f732d..c7b38d3a812 100644 --- a/src/soc/qualcomm/ipq806x/mbn_header.h +++ b/src/soc/qualcomm/ipq806x/mbn_header.h @@ -18,7 +18,7 @@ #include -/* Qualcomm firmware blob header gleaned from util/ipqheader/ipqheader.py */ +/* Qualcomm firmware blob header gleaned from util/qualcomm/ipqheader.py */ struct mbn_header { u32 mbn_type; diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 872b264cfa5..3ceb84d8815 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -379,8 +379,7 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE)); - if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) - && (curr_state & QUP_STATE_VALID_MASK)) { + if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) { /* * For PAUSE_STATE to RESET_STATE transition, * two writes of 10[binary]) are required for the diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 657734524cc..2657b9c574a 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -760,8 +760,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) { struct ipq_spi_slave *ds = NULL; int i; - unsigned int bus = slave->bus; - unsigned int cs = slave->cs; + int bus = slave->bus; + int cs = slave->cs; /* * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index fe2d673d47b..66c31034fa7 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -33,7 +33,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 3e8c1ba5be7..aa867c2f25e 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -11,6 +11,7 @@ config SOC_QUALCOMM_QCS405 select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select HAVE_UART_SPECIAL if SOC_QUALCOMM_QCS405 @@ -18,4 +19,13 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK + +config QCS405_BLSP_SPI + bool + default y + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 5 endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 4df5246e3c4..c64e5bcf580 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,12 +8,14 @@ bootblock-y += spi.c bootblock-y += mmu.c bootblock-y += gpio.c bootblock-y += clock.c +bootblock-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c verstage-y += clock.c +verstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ romstage-y += timer.c @@ -22,6 +24,7 @@ romstage-y += cbmem.c romstage-y += gpio.c romstage-y += clock.c romstage-y += usb.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ ramstage-y += soc.c @@ -31,6 +34,7 @@ ramstage-y += cbmem.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += usb.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index cd7c1f2f417..302652ba71e 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -12,14 +12,13 @@ * GNU General Public License for more details. */ +#include #include #include -#include #include #include #include #include - #include #define DIV(div) (div ? (2*div - 1) : 0) @@ -211,11 +210,38 @@ void clock_configure_uart(uint32_t hz) clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg)); } -void clock_configure_spi(int blsp, uint32_t hz) +void clock_configure_spi(int blsp, int qup, uint32_t hz) { - struct qcs405_clock *spi_clk = (blsp == 1) ? - (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk - : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + struct qcs405_clock *spi_clk = 0; + + if (blsp == 1) { + switch (qup) { + case 0: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup0_spi_clk; + break; + case 1: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup1_spi_clk; + break; + case 2: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup2_spi_clk; + break; + case 3: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup3_spi_clk; + break; + case 4: + spi_clk = (struct qcs405_clock *) + &gcc->blsp1_qup4_spi_clk; + break; + } + } else if (blsp == 2) + spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } @@ -230,38 +256,66 @@ void clock_disable_uart(void) clock_disable(&gcc->blsp1_uart2_apps_cbcr); } -void clock_enable_spi(int blsp) +void clock_enable_spi(int blsp, int qup) { - (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); } -void clock_disable_spi(int blsp) +void clock_disable_spi(int blsp, int qup) { - (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr) - : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr); + if (blsp == 1) { + switch (qup) { + case 0: + clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr); + break; + case 1: + clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr); + break; + case 2: + clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr); + break; + case 3: + clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr); + break; + case 4: + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + break; + } + } else if (blsp == 2) + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + else + printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + } void clock_init(void) { - clock_configure_gpll0(); - - clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, - ARRAY_SIZE(uart_cfg)); - - clock_enable(&gcc->blsp1_uart2_apps_cbcr); clock_enable_vote(&gcc->blsp1_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP1_AHB_CLK_ENA); - clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); - - clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000, - ARRAY_SIZE(spi_cfg)); - clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); clock_enable_vote(&gcc->blsp2_ahb_cbcr, &gcc->gcc_apcs_clock_branch_en_vote, BLSP2_AHB_CLK_ENA); diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index 5904cb3dc5b..7b2238d77ff 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -15,10 +15,8 @@ #include #include -#include #include #include - #include void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, @@ -73,3 +71,28 @@ void gpio_output(gpio_t gpio, int value) gpio_configure(gpio, GPIO_FUNC_GPIO, GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); } + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_DISABLE); + + clrsetbits_le32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); + clrsetbits_le32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(®s->intr_status) & GPIO_INTR_STATUS_MASK)) + return 0; + + write32(®s->intr_status, GPIO_INTR_STATUS_DISABLE); + return 1; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h new file mode 100644 index 00000000000..6e55d7dd379 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef __BLSP_H_ +#define __BLSP_H_ + +typedef enum { + BLSP_QUP_ID_0, + BLSP_QUP_ID_1, + BLSP_QUP_ID_2, + BLSP_QUP_ID_3, +} blsp_qup_id_t; + +typedef enum { + BLSP_SUCCESS = 0, + BLSP_ID_ERROR, + BLSP_ERROR, + BLSP_UNSUPPORTED +} blsp_return_t; + +typedef enum { + BLSP_PROTO_I2C_UIM = 1, + BLSP_PROTO_I2C_ONLY, + BLSP_PROTO_SPI_ONLY, + BLSP_PROTO_UART_FLOW_CTL, + BLSP_PROTO_UIM, + BLSP_PROTO_I2C_UART, +} blsp_protocol_t; + +blsp_return_t blsp_i2c_init(blsp_qup_id_t id); +int blsp_i2c_init_board(blsp_qup_id_t id); + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h new file mode 100644 index 00000000000..8e33f4b9600 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _QCS405_CDP_H_ +#define _QCS405_CDP_H_ + +#include + +unsigned int smem_get_board_machtype(void); + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +typedef struct { + gpio_t gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0, + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + unsigned int count; + uint8_t addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + unsigned int base; + int unit; + unsigned int is_macsec; + unsigned int mac_pwr0; + unsigned int mac_pwr1; + unsigned int mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +enum gale_board_id { + BOARD_ID_GALE_PROTO = 0, + BOARD_ID_GALE_EVT = 1, + BOARD_ID_GALE_EVT2_0 = 2, + BOARD_ID_GALE_EVT2_1 = 6, + BOARD_ID_GALE_EVT3 = 5, +}; + +/* Board specific parameters */ +typedef struct { +} __packed board_ipq40xx_params_t; + +extern board_ipq40xx_params_t *gboard_param; + +unsigned int get_board_index(unsigned int machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count); + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index d0f307b308a..8638128b15c 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -21,7 +21,6 @@ #define BLSP2_AHB_CLK_ENA 20 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_800MHZ 1 -#define REG(addr) ((void *)addr) /** * USB BCR registers @@ -66,28 +65,48 @@ struct qcs405_gcc { u32 blsp1_bcr; u32 blsp1_sleep_cbcr; u32 blsp1_ahb_cbcr; - u8 _res1[0x3028 - 0x100c]; + struct qcs405_rcg gcc_blsp_uart_sim_rcg; + u8 _res1[0x2000 - 0x1014]; + u32 blsp1_qup1_bcr; + u32 blsp1_qup1_spi_apps_cbcr; + u8 _res2[0x2024 - 0x2008]; + struct qcs405_clock blsp1_qup1_spi_clk; + u8 _res3[0x3008-0x2038]; + u32 blsp1_qup2_bcr; + u32 blsp1_qup2_spi_apps_cbcr; + u8 _res4[0x3014 - 0x3010]; + struct qcs405_clock blsp1_qup2_spi_clk; u32 blsp1_uart2_bcr; u32 blsp1_uart2_apps_cbcr; u32 blsp1_uart2_sim_cbcr; struct qcs405_clock blsp1_uart2_apps_clk; - u8 _res2[0x5018 - 0x3048]; + u8 _res5[0x4018 - 0x3048]; + u32 blsp1_qup3_bcr; + u32 blsp1_qup3_spi_apps_cbcr; + u8 _res6[0x4024 - 0x4020]; + struct qcs405_clock blsp1_qup3_spi_clk; + u8 _res7[0x5018 - 0x4038]; u32 blsp1_qup4_bcr; u32 blsp1_qup4_spi_apps_cbcr; - u8 _res3[0x5024 - 0x5020]; + u8 _res8[0x5024 - 0x5020]; struct qcs405_clock blsp1_qup4_spi_clk; - u8 _res4[0xB000 - 0x5038]; + u8 _res9[0x6020 - 0x5038]; + u32 blsp1_qup0_bcr; + u32 blsp1_qup0_spi_apps_cbcr; + u8 _res10[0x6034 - 0x6028]; + struct qcs405_clock blsp1_qup0_spi_clk; + u8 _res11[0xB000 - 0x6048]; u32 blsp2_bcr; u32 blsp2_sleep_cbcr; u32 blsp2_ahb_cbcr; - u8 _res5[0xC000 - 0xB00C]; + u8 _res12[0xC000 - 0xB00C]; u32 blsp2_qup0_bcr; u32 blsp2_qup0_spi_apps_cbcr; - u8 _res6[0xC024 - 0xC008]; + u8 _res13[0xC024 - 0xC008]; struct qcs405_clock blsp2_qup0_spi_clk; - u8 _res7[0x21000 - 0xC038]; + u8 _res14[0x21000 - 0xC038]; struct qcs405_gpll gpll0; - u8 _res8[0x45004 - 0x21024]; + u8 _res15[0x45004 - 0x21024]; u32 gcc_apcs_clock_branch_en_vote; }; @@ -160,10 +179,10 @@ void clock_reset_aop(void); int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_uart(uint32_t hz); -void clock_configure_spi(int blsp, uint32_t hz); +void clock_configure_spi(int blsp, int qup, uint32_t hz); void clock_enable_uart(void); void clock_disable_uart(void); -void clock_enable_spi(int blsp); -void clock_disable_spi(int blsp); +void clock_enable_spi(int blsp, int qup); +void clock_disable_spi(int blsp, int qup); #endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index fce435056f1..232e05e672c 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -30,6 +30,26 @@ typedef struct { #define TLMM_GPIO_IN_OUT_OFF 0x4 #define TLMM_GPIO_ID_STATUS_OFF 0x10 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + /* GPIO TLMM: Direction */ #define GPIO_INPUT 0 #define GPIO_OUTPUT 1 @@ -304,12 +324,23 @@ enum { PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), }; +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + struct tlmm_gpio { uint32_t cfg; uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; }; void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); #endif // _SOC_QUALCOMM_QCS405_GPIO_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h new file mode 100644 index 00000000000..2ed3e10f76a --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2012 - 2013, 2015, 2019 The Linux Foundation. + * All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_QCS405_IOMAP_H_ +#define __SOC_QUALCOMM_QCS405_IOMAP_H_ + +#include +#include +#include + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v, a) write32((void *)a, v) +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) + +#define GCC_CLK_CTL_REG ((void *)0x01800000u) +#define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG +#define GCC_CLK_BRANCH_ENA (GCC_CLK_CTL_REG + 0x6000) +#define IMEM_AXI (1 << 17) +#define SYS_NOC_APSS_AHB (1 << 16) +#define BIMC_AXI_M0 (1 << 15) +#define APSS_AHB (1 << 14) +#define APSS_AXI (1 << 13) +#define MPM_AHB (1 << 12) +#define GMEM_SYS_NOC_AXI (1 << 11) +#define BLSP1_AHB (1 << 10) +#define BLSP1_SLEEP (1 << 9) +#define PRNG_AHB (1 << 8) +#define BOOT_ROM_AHB (1 << 7) +#define MSG_RAM_AHB (1 << 6) +#define TLMM_AHB (1 << 5) +#define TLMM (1 << 4) +#define SPMI_PCNOC_AHB (1 << 3) +#define CRYPTO (1 << 2) +#define CRYPTO_AXI (1 << 1) +#define CRYPTO_AHB (1 << 0) + +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x2008) +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x200c) +#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x2010) +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x3010) +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x3000) +#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x3004) + +#define GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u) +#define GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000) +#define GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008) +#define GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c) +#define GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000) +#define GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004) + +#define GCNT_PSHOLD ((void *)0x004AB000u) + +/* RPM interface constants */ +#define RPM_INT ((void *)0x63020) +#define RPM_INT_ACK ((void *)0x63060) +#define RPM_SIGNAL_COOKIE ((void *)0x47C20) +#define RPM_SIGNAL_ENTRY ((void *)0x47C24) +#define RPM_FW_MAGIC_NUM 0x4D505242 + +#define TLMM_BASE_ADDR ((void *)0x01000000) +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x)) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) + +/* Yes, this is not a typo... host2 is actually mapped before host1. */ +#define USB_HOST2_XHCI_BASE 0x10000000 +#define USB_HOST2_DWC3_BASE 0x1000C100 +#define USB_HOST2_PHY_BASE 0x100F8800 +#define USB_HOST1_XHCI_BASE 0x11000000 +#define USB_HOST1_DWC3_BASE 0x1100C100 +#define USB_HOST1_PHY_BASE 0x110F8800 + +#define UART1_DM_BASE ((void *)0x078af000) +#define UART2_DM_BASE ((void *)0x078B1000) + +enum { + BLSP1_UART1, + BLSP1_UART2, +}; + +#define GCC_BLSP1_UART_BCR_BASE (GCC_CLK_CTL_REG + 0x2038) +#define GCC_BLSP1_UART_BCR(x) (GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0) +#define GCC_BLSP1_UART_APPS_CBCR(x) (GCC_BLSP1_UART_BCR(x) + 4) +#define GCC_BLSP1_UART_APPS_CMD_RCGR(x) (GCC_BLSP1_UART_APPS_CBCR(x) + 8) +#define GCC_BLSP1_UART_APPS_CFG_RCGR(x) (GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_M(x) (GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_N(x) (GCC_BLSP1_UART_APPS_M(x) + 4) +#define GCC_BLSP1_UART_APPS_D(x) (GCC_BLSP1_UART_APPS_N(x) + 4) +#define GCC_BLSP1_UART_MISC(x) (GCC_BLSP1_UART_APPS_D(x) + 4) + +#define BLSP1_QUP0_BASE ((void *)0x078B5000) +#define BLSP1_QUP1_BASE ((void *)0x078B6000) +#define BLSP1_QUP2_BASE ((void *)0x078B7000) +#define BLSP1_QUP3_BASE ((void *)0x078B8000) + +#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100) +#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000) + +static inline void *blsp_qup_base(blsp_qup_id_t id) +{ + switch (id) { + case BLSP_QUP_ID_0: return BLSP1_QUP0_BASE; + case BLSP_QUP_ID_1: return BLSP1_QUP1_BASE; + case BLSP_QUP_ID_2: return BLSP1_QUP2_BASE; + case BLSP_QUP_ID_3: return BLSP1_QUP3_BASE; + } + return NULL; +} + +#define BLSP_MINI_CORE_SHIFT 8 +#define BLSP_MINI_CORE_I2C (0x2u << BLSP_MINI_CORE_SHIFT) +#define BLSP_MINI_CORE_MASK (0xfu << BLSP_MINI_CORE_SHIFT) + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h new file mode 100644 index 00000000000..f8f9c759725 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __QUP_H__ +#define __QUP_H__ + + +/* QUP block registers */ +#define QUP_CONFIG 0x000 +#define QUP_STATE 0x004 +#define QUP_IO_MODES 0x008 +#define QUP_SW_RESET 0x00C +#define QUP_TRANSFER_CANCEL 0x014 +#define QUP_OPERATIONAL 0x018 +#define QUP_ERROR_FLAGS 0x01C +#define QUP_ERROR_FLAGS_EN 0x020 +#define QUP_TEST_CTRL 0x024 +#define QUP_OPERATIONAL_MASK 0x028 +#define QUP_HW_VERSION 0x030 +#define QUP_MX_OUTPUT_COUNT 0x100 +#define QUP_MX_OUTPUT_CNT_CURRENT 0x104 +#define QUP_OUTPUT_DEBUG 0x108 +#define QUP_OUTPUT_FIFO_WORD_CNT 0x10C +#define QUP_OUTPUT_FIFO 0x110 +#define QUP_OUTPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_MX_WRITE_COUNT 0x150 +#define QUP_MX_WRITE_CNT_CURRENT 0x154 +#define QUP_MX_INPUT_COUNT 0x200 +#define QUP_MX_INPUT_CNT_CURRENT 0x204 +#define QUP_MX_READ_COUNT 0x208 +#define QUP_MX_READ_CNT_CURRENT 0x20C +#define QUP_INPUT_DEBUG 0x210 +#define QUP_INPUT_FIFO_WORD_CNT 0x214 +#define QUP_INPUT_FIFO 0x218 +#define QUP_INPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_I2C_MASTER_CLK_CTL 0x400 +#define QUP_I2C_MASTER_STATUS 0x404 +#define QUP_I2C_MASTER_CONFIG 0x408 +#define QUP_I2C_MASTER_BUS_CLEAR 0x40C +#define QUP_I2C_MASTER_LOCAL_ID 0x410 +#define QUP_I2C_MASTER_COMMAND 0x414 + +#define OUTPUT_FIFO_FULL (1<<6) +#define INPUT_FIFO_NOT_EMPTY (1<<5) +#define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) +#define INPUT_SERVICE_FLAG (1<<9) +#define OUTPUT_SERVICE_FLAG (1<<8) +#define QUP_UNPACK_EN (1<<14) +#define QUP_PACK_EN (1<<15) +#define QUP_OUTPUT_BIT_SHIFT_EN (1<<16) + +#define QUP_MODE_MASK (0x03) +#define QUP_OUTPUT_MODE_SHFT (10) +#define QUP_INPUT_MODE_SHFT (12) + +#define QUP_FS_DIVIDER_MASK (0xFF) + +#define QUP_APP_CLK_ON_EN (1 << 12) +#define QUP_CORE_CLK_ON_EN (1 << 13) +#define QUP_MINI_CORE_PROTO_SHFT (8) +#define QUP_MINI_CORE_PROTO_MASK (0x0F) + +/* Mini-core states */ +#define QUP_STATE_RESET 0x0 +#define QUP_STATE_RUN 0x1 +#define QUP_STATE_PAUSE 0x3 +#define QUP_STATE_VALID (1<<2) +#define QUP_STATE_MASK 0x3 +#define QUP_STATE_VALID_MASK (1<<2) + +/* Tags for output FIFO */ +#define QUP_I2C_1CLK_NOOP_SEQ 0x1 /*MSB 8-bit NOP, LSB 8-bits 1 clk.*/ +#define QUP_I2C_START_SEQ (0x1 << 8) +#define QUP_I2C_DATA_SEQ (0x2 << 8) +#define QUP_I2C_STOP_SEQ (0x3 << 8) +#define QUP_I2C_RECV_SEQ (0x4 << 8) + +/* Tags for input FIFO */ +#define QUP_I2C_MIDATA_SEQ (0x5 << 8) +#define QUP_I2C_MISTOP_SEQ (0x6 << 8) +#define QUP_I2C_MINACK_SEQ (0x7 << 8) + +#define QUP_I2C_ADDR(x) ((x & 0xFF) << 1) +#define QUP_I2C_DATA(x) (x & 0xFF) +#define QUP_I2C_MI_TAG(x) (x & 0xFF00) +#define QUP_I2C_SLAVE_READ (0x1) + +/*Bit vals for I2C_MASTER_CLK_CTL register */ +#define QUP_HS_DIVIDER_SHFT (8) +#define QUP_DIVIDER_MIN_VAL (0x3) + +/* Bit masks for I2C_MASTER_STATUS register */ +#define QUP_I2C_INVALID_READ_SEQ (1 << 25) +#define QUP_I2C_INVALID_READ_ADDR (1 << 24) +#define QUP_I2C_INVALID_TAG (1 << 23) +#define QUP_I2C_FAILED_MASK (0x3 << 6) +#define QUP_I2C_INVALID_WRITE (1 << 5) +#define QUP_I2C_ARB_LOST (1 << 4) +#define QUP_I2C_PACKET_NACK (1 << 3) +#define QUP_I2C_BUS_ERROR (1 << 2) + +typedef enum { + QUP_SUCCESS = 0, + QUP_ERR_BAD_PARAM, + QUP_ERR_STATE_SET, + QUP_ERR_TIMEOUT, + QUP_ERR_UNSUPPORTED, + QUP_ERR_I2C_FAILED, + QUP_ERR_I2C_ARB_LOST, + QUP_ERR_I2C_BUS_ERROR, + QUP_ERR_I2C_INVALID_SLAVE_ADDR, + QUP_ERR_XFER_FAIL, + QUP_ERR_I2C_NACK, + QUP_ERR_I2C_INVALID_WRITE, + QUP_ERR_I2C_INVALID_TAG, + QUP_ERR_UNDEFINED, +} qup_return_t; + +typedef enum { + QUP_MINICORE_SPI = 1, + QUP_MINICORE_I2C_MASTER, + QUP_MINICORE_I2C_SLAVE +} qup_protocol_t; + +typedef enum { + QUP_MODE_FIFO = 0, + QUP_MODE_BLOCK, + QUP_MODE_DATAMOVER, +} qup_mode_t; + +typedef struct { + qup_protocol_t protocol; + unsigned int clk_frequency; + unsigned int src_frequency; + qup_mode_t mode; + unsigned int initialized; +} qup_config_t; + +typedef struct { + qup_protocol_t protocol; + union { + struct { + uint8_t addr; + uint8_t *data; + unsigned int data_len; + } iic; + struct { + void *in; + void *out; + unsigned int size; + } spi; + } p; +} qup_data_t; + +/* + * Initialize BLSP QUP block for FIFO I2C transfers. + * id[IN]: BLSP for which QUP is to be initialized. + * config_ptr[IN]: configurations parameters for the QUP. + * + * return: QUP_SUCCESS, if initialization succeeds. + */ +qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr); + +/* + * Set QUP state to run, pause, reset. + * id[IN]: BLSP block for which QUP state is to be set. + * state[IN]: New state to transition to. + * + * return: QUP_SUCCESS, if state transition succeeds. + */ +qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state); + +/* + * Reset the status bits set during an i2c transfer. + * id[IN]: BLSP block for which i2c status bits are to be cleared. + * + * return: QUP_SUCCESS, if status bits are cleared successfully. + */ +qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id); + +/* + * Send data to the peripheral on the bus. + * id[IN]: BLSP block for which data is to be sent. + * p_tx_obj[IN]: Data to be sent to the slave on the bus. + * stop_seq[IN]: When set to non-zero QUP engine sends i2c stop sequnce. + * + * return: QUP_SUCCESS, when data is sent successfully to the peripheral. + */ +qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq); + +/* + * Receive data from peripheral on the bus. + * id[IN]: BLSP block from which data is to be received. + * p_tx_obj[IN]: length of data to be received, slave address. + * [OUT]: buffer filled with data from slave. + * + * return: QUP_SUCCESS, when data is received successfully. + */ +qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_tx_obj); + +#endif //__QUP_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h new file mode 100644 index 00000000000..12f7fd97c7c --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -0,0 +1,210 @@ +/* + * Register definitions for the IPQ BLSP SPI Controller + * + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _QCS405_SPI_H_ +#define _QCS405_SPI_H_ + +#include +#include +#include + +#define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP4_QUP_REG_BASE ((void *)0x78b9000u) +#define BLSP5_QUP_REG_BASE ((void *)0x7af5000u) + +#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP4_SPI_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000300) +#define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300) + +#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP4_SPI_IO_CONTROL_REG (BLSP4_QUP_REG_BASE + 0x00000304) +#define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304) + +#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP4_SPI_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x00000308) +#define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308) + +#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP4_SPI_DEASSERT_WAIT_REG (BLSP4_QUP_REG_BASE + 0x00000310) +#define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) +#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP4_SPI_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x0000030c) +#define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c) + +#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP4_QUP_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000000) +#define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000) + +#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP4_QUP_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x0000001c) +#define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c) + +#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP4_QUP_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x00000020) +#define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020) + +#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP4_QUP_OPERATIONAL_MASK (BLSP4_QUP_REG_BASE + 0x00000028) +#define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028) + +#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP4_QUP_OPERATIONAL_REG (BLSP4_QUP_REG_BASE + 0x00000018) +#define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018) + +#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP4_QUP_IO_MODES_REG (BLSP4_QUP_REG_BASE + 0x00000008) +#define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008) + +#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP4_QUP_STATE_REG (BLSP4_QUP_REG_BASE + 0x00000004) +#define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004) + +#define BLSP0_QUP_INPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP4_QUP_INPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP5_QUP_INPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c)) + +#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP4_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c)) + +#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP4_QUP_MX_INPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000200) +#define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200) + +#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP4_QUP_MX_OUTPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000100) +#define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100) + +#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP4_QUP_SW_RESET_REG (BLSP4_QUP_REG_BASE + 0x0000000c) +#define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c) + +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define QUP_CONF_INPUT_MSK (1 << 7) +#define QUP_CONF_INPUT_ENA (0 << 7) +#define QUP_CONF_NO_INPUT (1 << 7) +#define QUP_CONF_OUTPUT_MSK (1 << 6) +#define QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_CONF_NO_OUTPUT (1 << 6) +#define QUP_CONF_N_MASK 0x1F +#define QUP_CONF_N_SPI_8_BIT_WORD 0x07 + +#define SPI_CONFIG_INPUT_FIRST (1 << 9) +#define SPI_CONFIG_INPUT_FIRST_BACK (0 << 9) +#define SPI_CONFIG_LOOP_BACK_MSK (1 << 8) +#define SPI_CONFIG_NO_LOOP_BACK (0 << 8) +#define SPI_CONFIG_NO_SLAVE_OPER_MSK (1 << 5) +#define SPI_CONFIG_NO_SLAVE_OPER (0 << 5) + +#define SPI_IO_CTRL_CLK_ALWAYS_ON (0 << 9) +#define SPI_IO_CTRL_MX_CS_MODE (1 << 8) +#define SPI_IO_CTRL_NO_TRI_STATE (1 << 0) +#define SPI_IO_CTRL_FORCE_CS_MSK (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_EN (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_DIS (0 << 11) +#define SPI_IO_CTRL_CLOCK_IDLE_HIGH (1 << 10) + +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN (1 << 16) +#define QUP_IO_MODES_INPUT_MODE_MSK (0x03 << 12) +#define QUP_IO_MODES_INPUT_BLOCK_MODE (0x01 << 12) +#define QUP_IO_MODES_OUTPUT_MODE_MSK (0x03 << 10) +#define QUP_IO_MODES_OUTPUT_BLOCK_MODE (0x01 << 10) + +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 + +#define MAX_COUNT_SIZE 0xffff + +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 +#define BLSP0_SPI 0 +#define BLSP4_SPI 4 +#define BLSP5_SPI 5 + +struct blsp_spi { + void *spi_config; + void *io_control; + void *error_flags; + void *error_flags_en; + void *qup_config; + void *qup_error_flags; + void *qup_error_flags_en; + void *qup_operational; + void *qup_io_modes; + void *qup_state; + void *qup_input_fifo; + void *qup_output_fifo; + void *qup_mx_input_count; + void *qup_mx_output_count; + void *qup_sw_reset; + void *qup_ns_reg; + void *qup_md_reg; + void *qup_op_mask; + void *qup_deassert_wait; +}; + + +#define SUCCESS 0 + +#define DUMMY_DATA_VAL 0 +#define TIMEOUT_CNT 100 + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning + * (count function disabled) and does not hold significance in the count. */ +#define MAX_PACKET_COUNT ((64 * KiB) - 1) + + +struct qcs_spi_slave { + struct spi_slave slave; + const struct blsp_spi *regs; + unsigned int mode; + unsigned int initialized; + unsigned long freq; + int allocated; +}; + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/uart.h b/src/soc/qualcomm/qcs405/include/soc/uart.h new file mode 100644 index 00000000000..5c8a361c7b3 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/uart.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.* + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#define PERIPH_BLK_BLSP 1 + +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos))) + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \ + (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +void qcs405_uart_init(void); + +#endif /* __UART_DM_H__ */ diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index c04b15d3c82..13b9daef9db 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -1,49 +1,783 @@ /* - * This file is part of the coreboot project. + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include +#include + +static const struct blsp_spi spi_reg[] = { + /* BLSP0 registers for SPI interface */ + { + BLSP0_SPI_CONFIG_REG, + BLSP0_SPI_IO_CONTROL_REG, + BLSP0_SPI_ERROR_FLAGS_REG, + BLSP0_SPI_ERROR_FLAGS_EN_REG, + BLSP0_QUP_CONFIG_REG, + BLSP0_QUP_ERROR_FLAGS_REG, + BLSP0_QUP_ERROR_FLAGS_EN_REG, + BLSP0_QUP_OPERATIONAL_REG, + BLSP0_QUP_IO_MODES_REG, + BLSP0_QUP_STATE_REG, + BLSP0_QUP_INPUT_FIFOc_REG(0), + BLSP0_QUP_OUTPUT_FIFOc_REG(0), + BLSP0_QUP_MX_INPUT_COUNT_REG, + BLSP0_QUP_MX_OUTPUT_COUNT_REG, + BLSP0_QUP_SW_RESET_REG, + 0, + 0, + BLSP0_QUP_OPERATIONAL_MASK, + BLSP0_SPI_DEASSERT_WAIT_REG, + }, + {0}, {0}, {0}, + /* BLSP4 registers for SPI interface */ + { + BLSP4_SPI_CONFIG_REG, + BLSP4_SPI_IO_CONTROL_REG, + BLSP4_SPI_ERROR_FLAGS_REG, + BLSP4_SPI_ERROR_FLAGS_EN_REG, + BLSP4_QUP_CONFIG_REG, + BLSP4_QUP_ERROR_FLAGS_REG, + BLSP4_QUP_ERROR_FLAGS_EN_REG, + BLSP4_QUP_OPERATIONAL_REG, + BLSP4_QUP_IO_MODES_REG, + BLSP4_QUP_STATE_REG, + BLSP4_QUP_INPUT_FIFOc_REG(0), + BLSP4_QUP_OUTPUT_FIFOc_REG(0), + BLSP4_QUP_MX_INPUT_COUNT_REG, + BLSP4_QUP_MX_OUTPUT_COUNT_REG, + BLSP4_QUP_SW_RESET_REG, + 0, + 0, + BLSP4_QUP_OPERATIONAL_MASK, + BLSP4_SPI_DEASSERT_WAIT_REG, + }, + /* BLSP5 registers for SPI interface */ + { + BLSP5_SPI_CONFIG_REG, + BLSP5_SPI_IO_CONTROL_REG, + BLSP5_SPI_ERROR_FLAGS_REG, + BLSP5_SPI_ERROR_FLAGS_EN_REG, + BLSP5_QUP_CONFIG_REG, + BLSP5_QUP_ERROR_FLAGS_REG, + BLSP5_QUP_ERROR_FLAGS_EN_REG, + BLSP5_QUP_OPERATIONAL_REG, + BLSP5_QUP_IO_MODES_REG, + BLSP5_QUP_STATE_REG, + BLSP5_QUP_INPUT_FIFOc_REG(0), + BLSP5_QUP_OUTPUT_FIFOc_REG(0), + BLSP5_QUP_MX_INPUT_COUNT_REG, + BLSP5_QUP_MX_OUTPUT_COUNT_REG, + BLSP5_QUP_SW_RESET_REG, + 0, + 0, + BLSP5_QUP_OPERATIONAL_MASK, + BLSP5_SPI_DEASSERT_WAIT_REG, + }, +}; + +static int check_bit_state(void *reg_addr, int mask, + int val, int us_delay) +{ + unsigned int count = TIMEOUT_CNT; + + while ((read32(reg_addr) & mask) != val) { + count--; + if (count == 0) + return -ETIMEDOUT; + udelay(us_delay); + } + + return SUCCESS; +} + +/* + * Check whether QUPn State is valid + */ +static int check_qup_state_valid(struct qcs_spi_slave *ds) +{ + return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK, + QUP_STATE_VALID, 1); +} + +/* + * Configure QUPn Core state + */ +static int config_spi_state(struct qcs_spi_slave *ds, unsigned int state) +{ + uint32_t val; + int ret = SUCCESS; + + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + + switch (state) { + case QUP_STATE_RUN: + /* Set the state to RUN */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RUN); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + case QUP_STATE_RESET: + /* Set the state to RESET */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RESET); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + default: + printk(BIOS_ERR, "unsupported QUP SPI state : %d\n", state); + ret = -EINVAL; + break; + } + + return ret; +} + +/* + * Set QUPn SPI Mode + */ +static void spi_set_mode(struct qcs_spi_slave *ds, unsigned int mode) +{ + unsigned int clk_idle_state; + unsigned int input_first_mode; + uint32_t val; + + switch (mode) { + case SPI_MODE0: + clk_idle_state = 0; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE1: + clk_idle_state = 0; + input_first_mode = 0; + break; + case SPI_MODE2: + clk_idle_state = 1; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE3: + clk_idle_state = 1; + input_first_mode = 0; + break; + default: + printk(BIOS_ERR, "unsupported spi mode : %d\n", mode); + return; + } + + val = read32(ds->regs->spi_config); + val |= input_first_mode; + write32(ds->regs->spi_config, val); + val = read32(ds->regs->io_control); + + if (clk_idle_state) + val |= SPI_IO_CTRL_CLOCK_IDLE_HIGH; + else + val &= ~SPI_IO_CTRL_CLOCK_IDLE_HIGH; + + write32(ds->regs->io_control, val); +} + +/* + * Reset entire QUP and all mini cores + */ +static void spi_reset(struct qcs_spi_slave *ds) +{ + write32(ds->regs->qup_sw_reset, 0x1); + udelay(5); + check_qup_state_valid(ds); +} + +static struct qcs_spi_slave spi_slave_pool[3]; + +static struct qcs_spi_slave *to_qcs_spi(const struct spi_slave *slave) +{ + struct qcs_spi_slave *ds; + size_t i; + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + ds = spi_slave_pool + i; + + if (!ds->allocated) + continue; + + if ((ds->slave.bus == slave->bus) && + (ds->slave.cs == slave->cs)) + return ds; + } + + return NULL; +} + +static void write_force_cs(const struct spi_slave *slave, int assert) +{ + struct qcs_spi_slave *ds = to_qcs_spi(slave); + if (assert) + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); + else + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); +} + +/* + * BLSP QUPn SPI Hardware Initialisation + */ +static int spi_hw_init(struct qcs_spi_slave *ds) +{ + int ret; + + ds->initialized = 0; + + /* QUPn module configuration */ + spi_reset(ds); + + /* Set the QUPn state */ + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret) + return ret; + + /* + * Configure Mini core to SPI core with Input Output enabled, + * SPI master, N = 8 bits + */ + clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + QUP_CONF_INPUT_MSK | + QUP_CONF_OUTPUT_MSK | + QUP_CONF_N_MASK, + QUP_CONFIG_MINI_CORE_SPI | + QUP_CONF_INPUT_ENA | + QUP_CONF_OUTPUT_ENA | + QUP_CONF_N_SPI_8_BIT_WORD); + + /* + * Configure Input first SPI protocol, + * SPI master mode and no loopback + */ + clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + SPI_CONFIG_NO_SLAVE_OPER_MSK, + SPI_CONFIG_NO_LOOP_BACK | + SPI_CONFIG_NO_SLAVE_OPER); + + /* + * Configure SPI IO Control Register + * CLK_ALWAYS_ON = 0 + * MX_CS_MODE = 0 + * NO_TRI_STATE = 1 + */ + write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON | + SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); + + /* + * Configure SPI IO Modes. + * OUTPUT_BIT_SHIFT_EN = 1 + * INPUT_MODE = Block Mode + * OUTPUT MODE = Block Mode + */ + clrsetbits_le32(ds->regs->qup_io_modes, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | + QUP_IO_MODES_INPUT_MODE_MSK | + QUP_IO_MODES_OUTPUT_MODE_MSK, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN | + QUP_IO_MODES_INPUT_BLOCK_MODE | + QUP_IO_MODES_OUTPUT_BLOCK_MODE); + + spi_set_mode(ds, ds->mode); + + /* Disable Error mask */ + write32(ds->regs->error_flags_en, 0); + write32(ds->regs->qup_error_flags_en, 0); + write32(ds->regs->qup_deassert_wait, 0); + + ds->initialized = 1; + + return SUCCESS; +} static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { - return 0; + struct qcs_spi_slave *ds = to_qcs_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch (slave->bus) { + case 4: + gpio_configure + (GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI + gpio_configure + (GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO + gpio_configure + (GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); // CS + gpio_configure + (GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK + break; + case 5: + gpio_configure + (GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI + gpio_configure + (GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO + gpio_configure + (GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS + gpio_configure + (GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d " + "(Supported buses 0, 1, 2, 3, 4, 5)\n", slave->bus); + break; + } + write_force_cs(slave, 1); + + return SUCCESS; } static void spi_ctrlr_release_bus(const struct spi_slave *slave) { + struct qcs_spi_slave *ds = to_qcs_spi(slave); + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +/* + * Function to write data to OUTPUT FIFO + */ +static void spi_write_byte(struct qcs_spi_slave *ds, unsigned char data) +{ + /* Wait for space in the FIFO */ + while ((read32(ds->regs->qup_operational) & OUTPUT_FIFO_FULL)) + udelay(1); + + /* Write the byte of data */ + write32(ds->regs->qup_output_fifo, data); +} + +/* + * Function to read data from Input FIFO + */ +static unsigned char spi_read_byte(struct qcs_spi_slave *ds) +{ + /* Wait for Data in FIFO */ + while (!(read32(ds->regs->qup_operational) & INPUT_FIFO_NOT_EMPTY)) + udelay(1); + + /* Read a byte of data */ + return read32(ds->regs->qup_input_fifo) & 0xff; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int check_fifo_status(void *reg_addr) +{ + unsigned int count = TIMEOUT_CNT; + unsigned int status_flag; + unsigned int val; + + do { + val = read32(reg_addr); + count--; + if (count == 0) + return -ETIMEDOUT; + status_flag = ((val & OUTPUT_SERVICE_FLAG) | + (val & INPUT_SERVICE_FLAG)); + } while (!status_flag); + + return SUCCESS; +} + +/* + * Function to configure Input and Output enable/disable + */ +static void enable_io_config(struct qcs_spi_slave *ds, + uint32_t write_cnt, uint32_t read_cnt) +{ + + if (write_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); + } + + if (read_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); + } +} + +/* + * Function to read bytes number of data from the Input FIFO + */ +static int __blsp_spi_read(struct qcs_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + struct stopwatch sw; + + /* Configure no of bytes to read */ + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, 0, bytes); + + write32(ds->regs->qup_mx_input_count, bytes); + + state_config = config_spi_state(ds, QUP_STATE_RUN); + if (state_config) + return state_config; + + while (bytes) { + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will + * read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ? + SPI_INPUT_BLOCK_SIZE : bytes); + + for (i = 0; i < fifo_count; i++) { + *data_buffer = spi_read_byte(ds); + data_buffer++; + bytes--; + } + } + } + + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout\n"); + ret = -ETIMEDOUT; + goto out; + } + } while (!(val & MAX_INPUT_DONE_FLAG)); + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + return ret; +} + +static int blsp_spi_read(struct qcs_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) { + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_read(ds, data_buffer, length); + if (ret != SUCCESS) + return ret; + + data_buffer += length; + bytes -= length; + } + return 0; } +/* + * Function to write data to the Output FIFO + */ +static int __blsp_spi_write(struct qcs_spi_slave *ds, const u8 *cmd_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int write_len = bytes; + unsigned int read_len = bytes; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + struct stopwatch sw; + + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); + /* No of bytes to be written in Output FIFO */ + write32(ds->regs->qup_mx_output_count, bytes); + write32(ds->regs->qup_mx_input_count, bytes); + state_config = config_spi_state(ds, QUP_STATE_RUN); + + if (state_config) + return state_config; + + /* + * read_len considered to ensure that we read the dummy data for the + * write we performed. This is needed to ensure with WR-RD transaction + * to get the actual data on the subsequent read cycle that happens + */ + while (write_len || read_len) { + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & OUTPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will write + * expected output data + */ + val &= OUTPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (write_len > SPI_OUTPUT_BLOCK_SIZE) + fifo_count = SPI_OUTPUT_BLOCK_SIZE; + else + fifo_count = write_len; + + for (i = 0; i < fifo_count; i++) { + /* Write actual data to output FIFO */ + spi_write_byte(ds, *cmd_buffer); + cmd_buffer++; + write_len--; + } + } + + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software + * will read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (read_len > SPI_INPUT_BLOCK_SIZE) + fifo_count = SPI_INPUT_BLOCK_SIZE; + else + fifo_count = read_len; + + for (i = 0; i < fifo_count; i++) { + /* Read dummy data for the data written */ + (void)spi_read_byte(ds); + + /* Decrement the read count after reading the + * dummy data from the device. This is to make + * sure we read dummy data before we write the + * data to fifo + */ + read_len--; + } + } + } + + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout\n"); + ret = -ETIMEDOUT; + goto out; + } + + } while (!(val & MAX_OUTPUT_DONE_FLAG)); + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int blsp_spi_write(struct qcs_spi_slave *ds, u8 *cmd_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_write(ds, cmd_buffer, length); + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success\n"); + return ret; + } + + cmd_buffer += length; + bytes -= length; + } + + return 0; +} + +/* + * This function is invoked with either tx_buf or rx_buf. + * Calling this function with both null does a chip select change. + */ +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + struct qcs_spi_slave *ds = to_qcs_spi(slave); + u8 *txp = (u8 *)dout; + u8 *rxp = (u8 *)din; + int ret; + + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret != SUCCESS) + return ret; + + if (dout != NULL) { + ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + if (ret != SUCCESS) + goto out; + } + + if (din != NULL) { + ret = blsp_spi_read(ds, rxp, in_bytes); + if (ret != SUCCESS) + goto out; + } + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct qcs_spi_slave *ds = NULL; + int i; + unsigned int bus = slave->bus; + unsigned int cs = slave->cs; + int qup = 0; + int blsp = 2; + + if (((bus != BLSP4_SPI) && (bus != BLSP5_SPI)) || cs != 0) { + printk(BIOS_ERR, + "SPI error: unsupported bus %d or cs %d\n", bus, cs); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = &spi_reg[bus]; + ds->mode = SPI_MODE0; + ds->freq = 50000000; + + if (bus == BLSP4_SPI) { + ds->freq = 1000000; + qup = 4; + blsp = 1; + } + + clock_configure_spi(blsp, qup, ds->freq); + clock_enable_spi(blsp, qup); + + ds->allocated = 1; + + return 0; + } + + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); + return -1; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); +} + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, - .max_xfer_size = 65535, + .xfer_vector = xfer_vectors, + .max_xfer_size = MAX_PACKET_COUNT, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, + .bus_start = BLSP5_SPI, + .bus_end = BLSP5_SPI, + }, + { + .ctrlr = &spi_ctrlr, + .bus_start = BLSP4_SPI, + .bus_end = BLSP4_SPI, }, }; diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c new file mode 100644 index 00000000000..4a4331220ac --- /dev/null +++ b/src/soc/qualcomm/qcs405/uart.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK boot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FIFO_DATA_SIZE 4 + +typedef struct { + void *uart_dm_base; + unsigned int blsp_uart; + gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +} uart_params_t; + +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_configure(gpio->gpio, gpio->func, + gpio->pull, gpio->drvstr, gpio->enable); + gpio++; + } +} + +static const uart_params_t uart_board_param = { + .uart_dm_base = UART2_DM_BASE, + .blsp_uart = BLSP1_UART2, + .dbg_uart_gpio = { + { + .gpio = GPIO(17), + .func = 1, + .dir = GPIO_OUTPUT, + .pull = GPIO_PULL_UP, + .enable = GPIO_OUTPUT + }, + { + .gpio = GPIO(18), + .func = 1, + .dir = GPIO_INPUT, + .pull = GPIO_NO_PULL, + .enable = GPIO_INPUT + }, + }, +}; + +/** + * @brief msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @param uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); + + /* Enable receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); + + /* Clear stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + /* Enable stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +#if CONFIG(DRIVERS_UART) +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +/* Received data is valid or not */ +static int valid_data = 0; + +/* Received data */ +static unsigned int word = 0; + + +void uart_tx_byte(int idx, unsigned char data) +{ + int num_of_chars = 1; + void *base = uart_board_param.uart_dm_base; + + /* Wait until transmit FIFO is empty. */ + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); + + /* And now write the character(s) */ + write32(MSM_BOOT_UART_DM_TF(base, 0), data); +} +#endif /* CONFIG_SERIAL_UART */ + +/** + * @brief msm_boot_uart_dm_reset - resets UART controller + * @param base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * @brief msm_boot_uart_dm_init - initilaizes UART controller + * @param uart_dm_base: UART controller base address + */ +unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); + + /* Configure Interrupt Mask register IMR */ + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); + + /* RX watermark value */ + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); + + /* Enable transmitter */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * @brief qcs405_uart_init - initializes UART + * + * Initializes clocks, GPIO and UART controller. + */ +void uart_init(int idx) +{ + /* Note int idx isn't used in this driver. */ + void *dm_base; + + dm_base = uart_board_param.uart_dm_base; + + if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == 0xFF) + return; /* UART must have been already initialized. */ + + clock_configure_uart(1843200); + clock_enable_uart(); + + ipq_configure_gpio(uart_board_param.dbg_uart_gpio, + NO_OF_DBG_UART_GPIOS); + + write32(MSM_BOOT_UART_DM_CSR(dm_base), 0xFF); + + /* Initialize UART_DM */ + msm_boot_uart_dm_init(dm_base); +} + +/* for the benefit of non-console uart init */ +void qcs405_uart_init(void) +{ + uart_init(0); +} + +/** + * @brief uart_tx_flush - transmits a string of data + * @param idx: string to transmit + */ +void uart_tx_flush(int idx) +{ + void *base = uart_board_param.uart_dm_base; + + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + ; +} + +#if CONFIG(DRIVERS_UART) +/** + * qcs405_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +uint8_t uart_rx_byte(int idx) +{ + uint8_t byte; + + byte = (uint8_t)(word & 0xff); + word = word >> 8; + valid_data--; + + return byte; +} +#endif + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint64_t)UART2_DM_BASE; + serial.baud = get_uart_baudrate(); + serial.regwidth = 1; + + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index c0e3294e39e..f6268c95bab 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -10,14 +10,16 @@ config SOC_QUALCOMM_SDM845 select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON if SOC_QUALCOMM_SDM845 config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_MIGRATE_WORKING_DATA config SDM845_QSPI bool diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 896ae58e5fa..78b3568a8b7 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -24,6 +24,11 @@ romstage-y += timer.c romstage-y += gpio.c romstage-y += clock.c romstage-$(CONFIG_SDM845_QSPI) += qspi.c +romstage-y += usb.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c ################################################################################ ramstage-y += soc.c @@ -33,10 +38,12 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_SDM845_QSPI) += qspi.c +ramstage-y += usb.c ################################################################################ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index 382e5a691e5..addac5ef404 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index 5a94e23e96a..bf4b30b32b7 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -25,4 +25,23 @@ #define GCC_BASE 0x00100000 #define AOSS_CC_BASE 0x0C2F0000 +/* + * USB BASE ADDRESSES + */ +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e2000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e2200 +#define QUSB_SEC_PHY_BASE 0x088e3000 +#define QUSB_SEC_PHY_DIG_BASE 0x088e3200 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define QMP_UNIPHY_QSERDES_COM_REG_BASE 0x088eb000 +#define QMP_UNIPHY_QSERDES_TX_REG_BASE 0x088eb200 +#define QMP_UNIPHY_QSERDES_RX_REG_BASE 0x088eb400 +#define QMP_UNIPHY_PCS_REG_BASE 0x088eb800 +#define USB_HOST0_DWC3_BASE 0x0a60c100 +#define USB_HOST1_DWC3_BASE 0x0a80c100 + #endif /* __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index 9f0533f33f4..6aee9c14f34 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -74,7 +74,14 @@ struct sdm845_gpll { struct sdm845_gcc { struct sdm845_gpll gpll0; - u8 _res0[0x17000 - 0x1000]; + u8 _res0[0xf000 - 0x1000]; + u32 usb30_prim_bcr; + u8 _res1[0x10000 - 0xf004]; + u32 usb30_sec_bcr; + u8 _res2[0x12000 - 0x10004]; + u32 qusb2phy_prim_bcr; + u32 qusb2phy_sec_bcr; + u8 _res3[0x17000 - 0x12008]; u32 qup_wrap0_bcr; u32 qup_wrap0_m_ahb_cbcr; u32 qup_wrap0_s_ahb_cbcr; @@ -82,9 +89,9 @@ struct sdm845_gcc { u32 qup_wrap0_core_cdivr; u32 qup_wrap0_core_2x_cbcr; struct sdm845_rcg qup_wrap0_core_2x; - u8 _res1[0x17030 - 0x17020]; + u8 _res4[0x17030 - 0x17020]; struct sdm845_qupv3_clock qup_wrap0_s[8]; - u8 _res2[0x18000 - 0x179b0]; + u8 _res5[0x18000 - 0x179b0]; u32 qup_wrap1_bcr; u32 qup_wrap1_core_2x_cbcr; u32 qup_wrap1_core_cbcr; @@ -92,14 +99,28 @@ struct sdm845_gcc { u32 qup_wrap1_s_ahb_cbcr; struct sdm845_qupv3_clock qup_wrap1_s[8]; u32 qup_wrap1_core_cdivr; - u8 _res4[0x4B000 - 0x18998]; + u8 _res6[0x4B000 - 0x18998]; u32 qspi_cnoc_ahb_cbcr; u32 qspi_core_cbcr; struct sdm845_rcg qspi_core; - u8 _res5[0x5200c-0x4b010]; + u8 _res7[0x50000-0x4b010]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u32 usb3_phy_sec_bcr; + u32 usb3phy_phy_sec_bcr; + u8 _res8[0x5200c-0x50014]; u32 apcs_clk_br_en1; - u8 _res6[0x1000000-0x52010]; + u8 _res9[0x1000000-0x52010]; }; +check_member(sdm845_gcc, usb30_prim_bcr, 0xf000); +check_member(sdm845_gcc, usb30_sec_bcr, 0x10000); +check_member(sdm845_gcc, qusb2phy_prim_bcr, 0x12000); +check_member(sdm845_gcc, qusb2phy_sec_bcr, 0x12004); +check_member(sdm845_gcc, usb3phy_phy_prim_bcr, 0x50004); +check_member(sdm845_gcc, usb3_phy_prim_bcr, 0x50000); +check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c); +check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010); check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c); struct sdm845_aoss { diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h new file mode 100644 index 00000000000..309193cf436 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/efuse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ + +/** + * USB EFUSE registers + */ +struct qfprom_corr { + u8 rsvd[0x41E8 - 0x0]; + u32 qusb_hstx_trim_lsb; + u32 qusb_hstx_trim_msb; +}; + +check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x41E8); +check_member(qfprom_corr, qusb_hstx_trim_msb, 0x41EC); +#endif /* __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 7063c6910e3..b1b633317fa 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -28,11 +28,12 @@ SECTIONS { SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 0x2000) + DMA_COHERENT(0x14699000, 8K) + REGION(qcsdi, 0x146AC000, 44K, 4K) SSRAM_END(0x146C0000) BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 4096) + REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) BOOTBLOCK(0x14816000, 40K) TTB(0x14820000, 56K) VBOOT2_WORK(0x1482E000, 12K) @@ -40,15 +41,19 @@ SECTIONS TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0xA2400, 0x100) - REGION(qclib, 0x148F2000, 0x80000, 4096) - REGION(dcb, 0x14972000, 0x4000, 4096) - REGION(pmic, 0x14976000, 0xA000, 4096) + REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + REGION(ddr_information, 0x148EDF00, 256, 256) + REGION(limits_cfg, 0x148EE000, 4K, 4K) + REGION(qclib_serial_log, 0x148EF000, 4K, 4K) + REGION(ddr_training, 0x148F0000, 8K, 4K) + REGION(qclib, 0x148F2000, 512K, 4K) + REGION(dcb, 0x14972000, 16K, 4K) + REGION(pmic, 0x14976000, 40K, 4K) BSRAM_END(0x14980000) DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index 299700a63fe..c9883bc0bfe 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -16,8 +16,6 @@ #ifndef _SOC_QUALCOMM_SDM845_MMU_H__ #define _SOC_QUALCOMM_SDM845_MMU_H__ -#define DRAMSIZE4GB 0x100000000 - void sdm845_mmu_init(void); #endif // _SOC_QUALCOMM_SDM845_MMU_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index 1c14c03d016..e7bf1b2aea8 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -17,10 +17,12 @@ #define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #include -#include DECLARE_REGION(ssram) DECLARE_REGION(bsram) DECLARE_REGION(dram_reserved) +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); #endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h new file mode 100644 index 00000000000..b6576767632 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/usb.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +#ifndef _SDM845_USB_H_ +#define _SDM845_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x20 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x0 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0x30 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x0 + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +void setup_usb_host0(struct usb_board_data *data); +void setup_usb_host1(struct usb_board_data *data); +/* Call reset_ before setup_ */ +void reset_usb0(void); +void reset_usb1(void); + +#endif /* _SDM845_USB_H_ */ diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index ef6c058ab3c..ec5fa55de28 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -17,12 +17,9 @@ #include #include #include +#include #include -#define CACHED_RAM (MA_MEM | MA_S | MA_RW) -#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC) -#define DEV_MEM (MA_DEV | MA_S | MA_RW) - void sdm845_mmu_init(void) { mmu_init(); diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c new file mode 100644 index 00000000000..9c05452c9e7 --- /dev/null +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index bc7235f3ed4..ef283c0eae2 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -16,11 +16,13 @@ #include #include #include +#include #include static void soc_read_resources(struct device *dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, REGION_SIZE(dram_reserved) / KiB); } diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c new file mode 100644 index 00000000000..c7d65e6b426 --- /dev/null +++ b/src/soc/qualcomm/sdm845/usb.c @@ -0,0 +1,915 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +/* Only for QMP V3 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1; + u32 com_ssc_step_size2; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[20]; + u32 com_cp_ctrl_mode0; + u8 _reserved4[4]; + u32 com_pll_rctrl_mode0; + u8 _reserved5[4]; + u32 com_pll_cctrl_mode0; + u8 _reserved6[12]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u8 _reserved8[12]; + u32 com_dec_start_mode0; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u8 _reserved10[20]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[16]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u8 _reserved12[60]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[8]; + u32 com_coreclk_div_mode0; + u8 _reserved14[8]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; +}; +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); + +/* Only for QMP V3 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[68]; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[20]; + u32 tx_highz_drvr_en; + u8 _reserved3[40]; + u32 tx_lane_mode_1; + u8 _reserved4[20]; + u32 tx_rcv_detect_lvl_2; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); + +/* Only for QMP V3 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[8]; + u32 rx_ucdr_fo_gain; + u32 rx_ucdr_so_gain_half; + u8 _reserved2[32]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturtn_and_en; + u8 _reserved3[12]; + u32 rx_ucdr_pi_cntrls; + u8 _reserved4[120]; + u32 rx_vga_cal_ctrl2; + u8 _reserved5[16]; + u32 rx_rx_equ_adap_ctrl2; + u32 rx_rx_equ_adap_ctrl3; + u32 rx_rx_equ_adap_ctrl4; + u8 _reserved6[24]; + u32 rx_rx_eq_offset_adap_ctrl1; + u32 rx_rx_offset_adap_ctrl2; + u32 rx_sigdet_enables; + u32 rx_sigdet_ctrl; + u8 _reserved7[4]; + u32 rx_sigdet_deglitch_ctrl; + u32 rx_rx_band; + u8 _reserved8[80]; + u32 rx_rx_mode_00; +}; +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); + +/* Only for QMP V3 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u32 pcs_power_down_control; + u32 pcs_start_control; + u32 pcs_txmgn_v0; + u32 pcs_txmgn_v1; + u32 pcs_txmgn_v2; + u32 pcs_txmgn_v3; + u32 pcs_txmgn_v4; + u32 pcs_txmgn_ls; + u32 pcs_txdeemph_m6db_v0; + u32 pcs_txdeemph_m3p5db_v0; + u32 pcs_txdeemph_m6db_v1; + u32 pcs_txdeemph_m3p5db_v1; + u32 pcs_txdeemph_m6db_v2; + u32 pcs_txdeemph_m3p5db_v2; + u32 pcs_txdeemph_m6db_v3; + u32 pcs_txdeemph_m3p5db_v3; + u32 pcs_txdeemph_m6db_v4; + u32 pcs_txdeemph_m3p5db_v4; + u32 pcs_txdeemph_m6db_ls; + u32 pcs_txdeemph_m3p5db_ls; + u8 _reserved1[8]; + u32 pcs_rate_slew_cntrl; + u8 _reserved2[4]; + u32 pcs_power_state_config2; + u8 _reserved3[8]; + u32 pcs_rcvr_dtct_dly_p1u2_l; + u32 pcs_rcvr_dtct_dly_p1u2_h; + u32 pcs_rcvr_dtct_dly_u3_l; + u32 pcs_rcvr_dtct_dly_u3_h; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u32 pcs_tsync_rsync_time; + u8 _reserved4[16]; + u32 pcs_pwrup_reset_dly_time_auxclk; + u8 _reserved5[12]; + u32 pcs_lfps_ecstart_eqtlock; + u8 _reserved6[4]; + u32 pcs_rxeqtraining_wait_time; + u32 pcs_rxeqtraining_run_time; + u8 _reserved7[4]; + u32 pcs_fll_ctrl1; + u32 pcs_fll_ctrl2; + u32 pcs_fll_cnt_val_l; + u32 pcs_fll_cnt_val_h_tol; + u32 pcs_fll_man_code; + u32 pcs_autonomous_mode_ctrl; + u8 _reserved8[152]; + u32 pcs_ready_status; + u8 _reserved9[96]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved10[48]; + u32 pcs_refgen_req_config1; + u32 pcs_refgen_req_config2; +}; +check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); +check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); +check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); +check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); +check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); +check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); +check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); +check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; + +static struct usb3_phy_qserdes_com_reg_layout *const + uniphy_qserdes_com_reg_layout = + (void *)QMP_UNIPHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout + *const uniphy_qserdes_tx_reg_layout = + (void *)QMP_UNIPHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout + *const uniphy_qserdes_rx_reg_layout = + (void *)QMP_UNIPHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const uniphy_pcs_reg_layout = + (void *)QMP_UNIPHY_PCS_REG_BASE; + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[60]; + u32 usb2i2cctl; + u8 reserved4[60]; + u32 usb2phyacc; + u8 reserved5[60]; + u32 usb3pipectl; + u8 reserved6[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, + {&qserdes_com_reg_layout->com_clk_select, 0x30}, + {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&qserdes_com_reg_layout->com_cmn_config, 0x16}, + {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, + {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, + {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, + {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { + {&uniphy_qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&uniphy_qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&uniphy_qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x04}, + {&uniphy_qserdes_com_reg_layout->com_clk_select, 0x30}, + {&uniphy_qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&uniphy_qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&uniphy_qserdes_com_reg_layout->com_cmn_config, 0x06}, + {&uniphy_qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&uniphy_qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&uniphy_qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&uniphy_qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&uniphy_qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&uniphy_qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&uniphy_qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&uniphy_qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&uniphy_qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&uniphy_qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&uniphy_qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&uniphy_qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&uniphy_qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&uniphy_qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&uniphy_qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { + {&uniphy_qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&uniphy_qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&uniphy_qserdes_tx_reg_layout->tx_lane_mode_1, 0xc6}, + {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x06}, + {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { + {&uniphy_qserdes_rx_reg_layout->rx_vga_cal_ctrl2, 0x0c}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_mode_00, 0x50}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0e}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&uniphy_qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&uniphy_qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x1c}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&uniphy_qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { + /* FLL settings */ + {&uniphy_pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&uniphy_pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&uniphy_pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&uniphy_pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&uniphy_pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&uniphy_pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&uniphy_pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&uniphy_pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v2, 0xb5}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v3, 0x4c}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v4, 0x64}, + {&uniphy_pcs_reg_layout->pcs_txmgn_ls, 0x6a}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&uniphy_pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&uniphy_pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&uniphy_pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&uniphy_pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&uniphy_pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, + {&uniphy_pcs_reg_layout->pcs_refgen_req_config1, 0x21}, + {&uniphy_pcs_reg_layout->pcs_refgen_req_config2, 0x60}, +}; + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_qusb_phy_pll *qusb_phy_pll; + struct usb_qusb_phy_dig *qusb_phy_dig; + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; + + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; + struct usb_board_data *board_data; + u32 efuse_offset; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, + .efuse_offset = 25, +}; +static struct usb_dwc3_cfg usb_port1 = { + .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_SEC_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_SEC_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_UNIPHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_sec_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_sec_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3phy_phy_sec_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_sec_bcr, + .efuse_offset = 30, +}; + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert QUSB PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + +void reset_usb1(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(1)\n"); + + reset_usb(&usb_port1); +} +/* + * Update board specific PHY tuning override values that specified from + * board file. + */ +static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + /* Override preemphasis value */ + write32(&dwc3->qusb_phy_dig->tune1, + dwc3->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + dwc3->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&dwc3->qusb_phy_dig->imp_ctrl1, + dwc3->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ +static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) +{ + /* + * Efuse registers 4 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 4 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 4; + int bit_pos = dwc3->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + + if (bit_pos + efuse_bits > 32) { + /* + * Value split between two EFUSE registers, + * get the second part. + */ + int done_bits = 32 - bit_pos; + + bit_mask = (1 << (efuse_bits - done_bits)) - 1; + tune_val |= + (read32(&qfprom_corr_efuse->qusb_hstx_trim_msb) & + bit_mask) << done_bits; + } + + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) +{ + write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); + write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); + + if (dwc3->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(dwc3); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(dwc3); + } +} + +static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* PWR_CTRL: set the power down bit to disable the PHY */ + setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&dwc3->qusb_phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&dwc3->qusb_phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&dwc3->qusb_phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&dwc3->qusb_phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&dwc3->qusb_phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(dwc3, dwc3->qusb_phy_dig); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* power up USB3 PHY */ + write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); + qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); + qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(1000, + !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits_le32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + struct usb_board_data *board_data) +{ + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize QUSB PHY */ + hs_qusb_phy_init(dwc3); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(dwc3); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} + +void setup_usb_host0(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} + +void setup_usb_host1(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST1 controller.\n"); + setup_usb_host(&usb_port1, board_data); +} diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 98381a0d1a1..91e2de9ff4c 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index fa0990b10b3..3d7e1614e04 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -20,6 +20,7 @@ #include #include #include +#include static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index ad0453b612b..e5da05e6724 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 98016c0fc9a..e929419a14d 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -96,7 +96,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int ctrlr0 = 0; @@ -134,13 +134,13 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int rsd; /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); - assert(rsd >= 0 && rsd <= 3); + assert(rsd <= 3); clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, rsd << SPI_RXDSD_OFFSET); } diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 53666c28f31..f845f07514f 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,11 +30,12 @@ config SOC_ROCKCHIP_RK3288 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select NO_BOOTBLOCK_CONSOLE if SOC_ROCKCHIP_RK3288 config VBOOT - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index 90275ff94e9..c429258e100 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 425d302fbbc..b4de270fc54 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -20,7 +20,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index a34105d9acb..3223a4ddd46 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 6e45df30a21..897a5979d4c 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -17,9 +17,10 @@ config SOC_ROCKCHIP_RK3399 if SOC_ROCKCHIP_RK3399 config VBOOT + select VBOOT_MIGRATE_WORKING_DATA select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_OPROM_MATTERS + select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK config PMIC_BUS diff --git a/src/soc/rockchip/rk3399/bl31_plat_params.c b/src/soc/rockchip/rk3399/bl31_plat_params.c index 647566ba2d9..9c11552301f 100644 --- a/src/soc/rockchip/rk3399/bl31_plat_params.c +++ b/src/soc/rockchip/rk3399/bl31_plat_params.c @@ -15,7 +15,6 @@ */ #include -#include #include #include diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 73fc499d1c6..293057a091b 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -20,8 +20,8 @@ SECTIONS { DRAM_START(0x00000000) BL31(0, 0x100000) - POSTRAM_CBFS_CACHE(0x00100000, 1M) - RAMSTAGE(0x00300000, 256K) + POSTRAM_CBFS_CACHE(0x00100000, 8M) + RAMSTAGE(0x00900000, 2M) DMA_COHERENT(0x10000000, 2M) /* 8K of special SRAM in PMU power domain. */ diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index f304d8fcd0f..43ab7b914f8 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -17,6 +17,7 @@ #define __RK_MIPI_H #include +#include struct rk_mipi_regs { u32 dsi_version; diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index ee8cc2e4452..1f3f02cbee2 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -14,20 +14,19 @@ */ #include -#include #include #include #include #include #include #include -#include #include #include #include #include #include #include +#include #include static struct rk_mipi_dsi rk_mipi[2] = { diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index d5aeccdec62..7ec24648a22 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index 9fef9ae377b..e4316725793 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/samsung/exynos5250/pinmux.c b/src/soc/samsung/exynos5250/pinmux.c index 10c8c953cd9..9ddbea56b2a 100644 --- a/src/soc/samsung/exynos5250/pinmux.c +++ b/src/soc/samsung/exynos5250/pinmux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index a1e92a08bc4..ba3f9a3c874 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c index d8c13780a49..999afa0247c 100644 --- a/src/soc/samsung/exynos5420/pinmux.c +++ b/src/soc/samsung/exynos5420/pinmux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 753a24be194..1903f6b3b90 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -206,7 +206,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) static int spi_ctrlr_setup(const struct spi_slave *slave) { - ASSERT(slave->bus >= 0 && slave->bus < 3); + ASSERT(slave->bus < 3); struct exynos_spi_slave *eslave; eslave = to_exynos_spi(slave); diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 8a07565c9a4..efc35bd8d17 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -18,7 +18,7 @@ #include #include "hudson.h" #include - +#include #include extern FCH_DATA_BLOCK InitEnvCfgDefault; diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index cb2fbe727d5..8eb36f46ee6 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -15,12 +15,11 @@ #include #include - +#include /* warning: Porting.h includes an open #pragma pack(1) */ #include #include #include - #include /*----------------------------------------------------------------------------- diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index 2e6781ae003..cabb31b52b4 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -12,7 +12,9 @@ */ #include +#include #include + #include "amd8111_smbus.h" #define SMBUS_IO_BASE 0x0f00 diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 04b8abcc675..7ea2caa83bd 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -53,7 +53,6 @@ typedef union _PCI_ADDR { #define IMC_ENABLE_OVER_WRITE 0x01 #endif -#include #include "AmdSbLib.h" #include "Amd.h" #include diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 2dc3438c08d..b837b4cfc95 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -354,12 +354,3 @@ Scope(\){ PWDA, 1, } } - -Scope(\_SB) { - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } -} /* End Scope(_SB) */ diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 660553fbd8e..f5c11d4ce09 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -49,7 +49,6 @@ typedef union _PCI_ADDR { #endif #define FIXUP_PTR(ptr) ptr -#include #include "AmdSbLib.h" #include "Amd.h" #include "Hudson-2.h" diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index bc7e742b285..353d5771e0d 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -13,12 +13,12 @@ * GNU General Public License for more details. */ - +#include #include + #include "SbPlatform.h" #include "platform_cfg.h" - /** * @brief South Bridge CIMx configuration * diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 103db988ef7..f10a459bfd5 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -100,7 +100,6 @@ void write_pci_cfg_irqs(void) u16 target_pin = 0; /* Pin we will search our tables for */ u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ u16 devfn = 0; /* A PCI Device and Function number */ u8 bridged_device = 0; /* This device is on a PCI bridge */ u32 i = 0; @@ -132,7 +131,6 @@ void write_pci_cfg_irqs(void) if (int_pin < 1 || int_pin > 4) continue; /* Device has invalid INT_PIN so skip it */ - bus = target_dev->bus->secondary; devfn = target_dev->path.pci.devfn; /* diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e1ea2ce4b33..a331c572620 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -14,16 +14,16 @@ */ #include - #include #include #include - #include #include #include #include #include +#include + #include "hudson.h" #include "smbus.h" #include "smi.h" diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index abb92f29d21..5354a278226 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -27,6 +27,8 @@ #include #include #include +#include + #include "hudson.h" #include "pci_devs.h" diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index 8d67b1e6784..c49ccffc4db 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include @@ -20,7 +21,6 @@ #include #include #include - #include /*----------------------------------------------------------------------------- diff --git a/src/southbridge/amd/rs780/ht.c b/src/southbridge/amd/rs780/ht.c index 94df2337c13..8943fc13007 100644 --- a/src/southbridge/amd/rs780/ht.c +++ b/src/southbridge/amd/rs780/ht.c @@ -24,24 +24,24 @@ void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev) { struct device *cpu_f0; - u8 reg; + u32 reg32; cpu_f0 = pcidev_on_root(0x18, 0); set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21); - reg = nbpcie_p_read_index(sb_dev, 0x10); - reg |= 0x100; /* bit9=1 */ - nbpcie_p_write_index(sb_dev, 0x10, reg); + reg32 = nbpcie_p_read_index(sb_dev, 0x10); + reg32 |= 0x100; /* bit9=1 */ + nbpcie_p_write_index(sb_dev, 0x10, reg32); - reg = nbpcie_p_read_index(nb_dev, 0x10); - reg |= 0x100; /* bit9=1 */ - nbpcie_p_write_index(nb_dev, 0x10, reg); + reg32 = nbpcie_p_read_index(nb_dev, 0x10); + reg32 |= 0x100; /* bit9=1 */ + nbpcie_p_write_index(nb_dev, 0x10, reg32); /* Enable NP protocol over PCIE for memory-mapped writes targeting LPC * Set this bit to avoid a deadlock condition. */ - reg = htiu_read_index(nb_dev, 0x6); - reg |= 0x1000000; /* bit26 */ - htiu_write_index(nb_dev, 0x6, reg); + reg32 = htiu_read_index(nb_dev, 0x6); + reg32 |= 0x1000000; /* bit26 */ + htiu_write_index(nb_dev, 0x6, reg32); } static void pcie_init(struct device *dev) diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 673464318c0..0b11db3c865 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include "sb700.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 39aef639d2a..292a7f2c9e1 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -23,6 +23,8 @@ #include #include #include +#include + #include "sb700.h" static int sata_drive_detect(int portnum, uint16_t iobar) diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index da653112d74..4109e88cc3d 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -21,6 +21,8 @@ #include #include #include +#include + #include "sb700.h" static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 6a575e316c1..eaa47e3c2c4 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -17,9 +17,11 @@ #define _SB800_EARLY_SETUP_C_ #include +#include #include #include #include + #include "sb800.h" #include "smbus.c" diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index bcbfb129905..5aa6ee2ad18 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -15,7 +15,9 @@ */ #include +#include #include + #include "smbus.h" #define SMBUS_IO_BASE 0x1000 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index dae3c32c861..fc3e9fcadb6 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -44,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 7ce3da70adf..b6023b00b37 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -31,18 +31,17 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += me_status.c -ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c romstage-y += early_rcba.c +romstage-y += early_pch.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c +romstage-y += early_thermal.c early_me.c early_usb.c else romstage-y += early_me_mrc.c early_usb_mrc.c endif diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 72e284d08f3..20182192f24 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -15,6 +15,7 @@ */ /* Intel Cougar Point PCH support */ +#include Scope(\) { diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index edb514bda75..f82ed3e9790 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -179,8 +180,7 @@ int intel_early_me_init_done(u8 status) reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); - outb(0x6, 0xcf9); - halt(); + system_reset(); } if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) { diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index a50a1596689..e74c3043f04 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include /* For DMI bar. */ #include @@ -31,280 +33,147 @@ static void wait_iobp(void) { - while (read8(DEFAULT_RCBA + IOBPS) & 1) + while (RCBA8(IOBPS) & 1) ; // implement timeout? } static u32 read_iobp(u32 address) { + volatile u32 tmp; u32 ret; - write32(DEFAULT_RCBA + IOBPIRI, address); - write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) - & 0x1ff) | 0x600); + RCBA32(IOBPIRI) = address; + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); - ret = read32(DEFAULT_RCBA + IOBPD); + ret = RCBA32(IOBPD); wait_iobp(); - read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? + tmp = RCBA8(IOBPS); // call wait_iobp() instead here? return ret; } static void write_iobp(u32 address, u32 val) { + volatile u32 tmp; /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ read_iobp(address); - write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) - & 0x1ff) | 0x600); + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); - write32(DEFAULT_RCBA + IOBPD, val); + RCBA32(IOBPD) = val; wait_iobp(); - write16(DEFAULT_RCBA + IOBPS, - (read16(DEFAULT_RCBA + IOBPS) & 0x1ff) | 0x600); - read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; + + tmp = RCBA8(IOBPS); // call wait_iobp() instead here? } +void early_pch_init_native_dmi_pre(void) +{ + /* Link Capabilities Register */ + RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | + (3 << 10) | // L0s and L1 entry supported + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us -static void -init_dmi (void) + RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16); + RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2; +} + +void early_pch_init_native_dmi_post(void) { - int i; - - write32 (DEFAULT_DMIBAR + 0x0914, - read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000); - write32 (DEFAULT_DMIBAR + 0x0934, - read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000); - for (i = 0; i < 4; i++) - { - write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4), - read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff); - write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4), - read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800); - } - write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30) - & 0xfffffff) | 0x40000000); - for (i = 0; i < 2; i++) - { - write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5), - read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff); - write32 (DEFAULT_DMIBAR + 0x090c + (i << 5), - read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff); - } - write32 (DEFAULT_DMIBAR + 0x090c, - read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff); - write32 (DEFAULT_DMIBAR + 0x092c, - read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec); - read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec); - read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008 - write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec); - read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300); - read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000); - read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000); - read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400 - write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600 - write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280); - read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460 - write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c); - read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42 - - read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42 - read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b - write32 (DEFAULT_RCBA + 0x2340, 0x003a001b); - read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01 - write8 (DEFAULT_RCBA + 0x21b0, 0x02); - read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41 - write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42); - read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0088, 0x20); - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041 - read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0088, 0x20); - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 - - read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f - write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019); - read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000 - write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022); - read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000 - write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044); - read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080 - write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080); - read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0004, 0x01); - - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA + 0x0050, 0x01200654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA + 0x0050, 0x012a0654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 - read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00 - write8 (DEFAULT_RCBA + 0x1114, 0x05); - read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011 - write32 (DEFAULT_RCBA + 0x2014, 0x80000019); - read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2020, 0x81000022); - read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022 - read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2030, 0x82000044); - read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044 - read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2040, 0x87000080); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 - write32 (DEFAULT_RCBA + 0x0050, 0x812a0654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654 - read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000 + volatile u32 tmp; + + tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050) = 0x01200654; + tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050) = 0x012a0654; + tmp = RCBA32(0x0050); // !!! = 0x012a0654 + tmp = RCBA8(0x1114); // !!! = 0x00 + RCBA8(0x1114) = 0x05; + + /* + * Virtual Channel resources must match settings in DMIBAR! + * + * Some of the following settings are taken from + * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel + * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and + * serialice traces. + */ + + /* Virtual Channel 0 Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC0 and TC3 and TC4 to VC0. + */ + + RCBA32(0x2014) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + + /* Virtual Channel 1 Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC1 and TC5 to VC1. + */ + RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Read back register */ + tmp = RCBA32(0x2020); + + /* Virtual Channel private Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC2 and TC6 to VCp. + */ + RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Read back register */ + tmp = RCBA32(0x2030); + + /* Virtual Channel ME Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC7 to VCm. + */ + RCBA32(0x2040) = (1 << 31) | (7 << 24) | (0x40 << 1); + + /* Lock Virtual Channel Resource control register. */ + RCBA32(0x0050) |= 0x80000000; + /* Read back register */ + tmp = RCBA32(0x0050); + + /* Wait for virtual channels negotiation pending */ + while (RCBA16(0x201a) & VCNEGPND) + ; + while (RCBA16(0x2026) & VCNEGPND) + ; + while (RCBA16(0x2036) & VCNEGPND) + ; + while (RCBA16(0x2046) & VCNEGPND) + ; } void early_pch_init_native (void) { + volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); - write32 (DEFAULT_RCBA + 0x2088, 0x00109000); - read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x20ac, 0x40000000); - write32 (DEFAULT_RCBA + 0x100c, 0x01110000); - write8 (DEFAULT_RCBA + 0x2340, 0x1b); - read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000 - write32 (DEFAULT_RCBA + 0x2314, 0x0a280000); - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - write32 (DEFAULT_RCBA + 0x2324, 0x00854c74); - read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00 - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); + RCBA32(0x2088) = 0x00109000; + tmp = RCBA32(0x20ac); // !!! = 0x00000000 + RCBA32(0x20ac) = 0x40000000; + RCBA32(0x100c) = 0x01110000; + RCBA8(0x2340) = 0x1b; + tmp = RCBA32(0x2314); // !!! = 0x0a080000 + RCBA32(0x2314) = 0x0a280000; + tmp = RCBA32(0x2310); // !!! = 0xc809605b + RCBA32(0x2310) = 0xa809605b; + RCBA32(0x2324) = 0x00854c74; + tmp = RCBA8(0x0400); // !!! = 0x00 + tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310) = 0xa809605b; + tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310) = 0xa809605b; write_iobp(0xea007f62, 0x00590133); write_iobp(0xec007f62, 0x00590133); @@ -367,8 +236,6 @@ early_pch_init_native (void) write_iobp(0xec0007b2, 0x04514b5e); write_iobp(0xec00078c, 0x40000200); write_iobp(0xec000780, 0x02000020); - - init_dmi(); } static void pch_enable_bars(void) diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c deleted file mode 100644 index 3034930a06e..00000000000 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 17919af53a3..e5d5625cab9 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -14,11 +14,13 @@ * GNU General Public License for more details. */ -#include #include #include #include #include +#include +#include + #include "pch.h" void early_usb_init(const struct southbridge_usb_port *portmap) @@ -32,46 +34,39 @@ void early_usb_init(const struct southbridge_usb_port *portmap) 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, 0x20000353 }; int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Unlock registers. */ - outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, - DEFAULT_PMBASE | UPRWC); + write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) - write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), - currents[portmap[i].current]); + RCBA32(0x3500 + 4 * i) = currents[portmap[i].current]; for (i = 0; i < 10; i++) - write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); + RCBA32(0x3538 + 4 * i) = 0; for (i = 0; i < 8; i++) - write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); + RCBA32(0x3560 + 4 * i) = rcba_dump[i]; for (i = 0; i < 8; i++) - write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); + RCBA32(0x3580 + 4 * i) = 0; reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32(DEFAULT_RCBABASE + USBPDO, reg32); + RCBA32(USBPDO) = reg32; reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32(DEFAULT_RCBABASE + USBOCM1, reg32); + RCBA32(USBOCM1) = reg32; reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32(DEFAULT_RCBABASE + USBOCM2, reg32); + RCBA32(USBOCM2) = reg32; for (i = 0; i < 22; i++) - write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); + RCBA32(0x35a8 + 4 * i) = 0; - pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000); /* Relock registers. */ - outw(0, DEFAULT_PMBASE | UPRWC); + write_pmbase16(UPRWC, 0); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e9e49649f27..773750186f0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -436,9 +436,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) @@ -908,6 +908,12 @@ static void lpc_final(struct device *dev) if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); } } } diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 746c11a2e3e..f8540af4514 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -144,7 +144,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) } #ifndef __SMM__ -/* Set bit in Function Disble register to hide this device */ +/* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned devfn) { switch (devfn) { diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 21b603108a7..4369b5c162f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -70,13 +70,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); void early_pch_init(void); +void early_pch_init_native_dmi_pre(void); +void early_pch_init_native_dmi_post(void); struct southbridge_usb_port { @@ -310,6 +311,8 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */ +#define VCNEGPND 2 + #define TCTL 0x3000 /* 8bit */ #define NOINT 0 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index c3b82577e1d..2186287df2d 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -47,9 +47,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 91c87bf26e8..6a39873e7b1 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -20,9 +20,11 @@ #include #include #include -#include "pch.h" #include #include +#include + +#include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 0bda06e10ac..c3bd90dca8b 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -65,6 +65,10 @@ config INTEL_CHIPSET_LOCKDOWN and S3 resume (always done by coreboot). Select this to let coreboot to do this on normal boot path. +config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + bool + depends on SOUTHBRIDGE_INTEL_COMMON + if SOUTHBRIDGE_INTEL_COMMON_FINALIZE choice diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index ac339a29159..4cf6e6f57e8 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,8 +27,11 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) +verstage-y += pmbase.c romstage-y += pmbase.c ramstage-y += pmbase.c postcar-y += pmbase.c @@ -59,6 +62,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c +verstage-y += rtc.c romstage-y += rtc.c ramstage-y += rtc.c postcar-y += rtc.c diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index c0dd43984de..eb63d345208 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -61,7 +61,7 @@ config CHECK_ME default n depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) help @@ -73,7 +73,7 @@ config USE_ME_CLEANER bool "Strip down the Intel ME/TXE firmware" depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) help diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 4b08c48f270..af1eb602a00 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include "smbus.h" diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 036ac22adc4..398c6804e02 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -104,38 +104,6 @@ void southbridge_smm_init(void) write_pmbase32(SMI_EN, smi_en); } -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h new file mode 100644 index 00000000000..9d6f15326ec --- /dev/null +++ b/src/southbridge/intel/common/tco.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Elyes Haouas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H +#define SOUTHBRIDGE_INTEL_COMMON_TCO_H + +#define PMBASE_TCO_OFFSET 0x60 +#define TCO1_STS 0x04 +#define TCO1_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define SECOND_TO_STS (1 << 1) +#define TCO1_CNT 0x08 +#define TCO_TMR_HLT (1 << 11) + +#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/common/watchdog.c similarity index 67% rename from src/southbridge/intel/bd82x6x/watchdog.c rename to src/southbridge/intel/common/watchdog.c index 6373a39e47a..778a7a9f7fd 100644 --- a/src/southbridge/intel/bd82x6x/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -16,17 +16,16 @@ */ #include -#include #include #include #include +#include #include -#include - +#include #include /* - * Disable PCH watchdog timer + * Disable ICH-NM10-PCH watchdog timer */ void watchdog_off(void) { @@ -36,21 +35,25 @@ void watchdog_off(void) /* Get LPC device. */ dev = pcidev_on_root(0x1f, 0); - /* Disable interrupt. */ value = pci_read_config16(dev, PCI_COMMAND); - value |= PCI_COMMAND_INT_DISABLE; + + if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) { + /* Enable I/O space. */ + value |= PCI_COMMAND_IO; + } else { + /* Disable interrupt. */ + value |= PCI_COMMAND_INT_DISABLE; + } pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ - value = read_pmbase16(TCO1_CNT); + value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); value |= TCO_TMR_HLT; - write_pmbase16(TCO1_CNT, value); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); /* Clear TCO timeout status. */ - write_pmbase16(TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(TCO2_STS, SECOND_TO_STS); - - /* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */ + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); - printk(BIOS_DEBUG, "PCH: watchdog disabled\n"); + printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); } diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index c15c48d445d..4526cb3cf5e 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index ac5888ca38a..67a51af15a6 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -19,12 +19,11 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) ramstage-y += soc.c ramstage-y += lpc.c ramstage-y += sata.c -ramstage-y += watchdog.c ramstage-y += spi.c ramstage-y += smbus.c ramstage-y += acpi.c -romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c +romstage-y += early_usb.c early_smbus.c gpio.c early_init.c romstage-y += romstage.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/fsp_rangeley/early_spi.c b/src/southbridge/intel/fsp_rangeley/early_spi.c deleted file mode 100644 index 7b20cdb9a79..00000000000 --- a/src/southbridge/intel/fsp_rangeley/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "soc.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transaction */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 4118e5fded0..ba5e04bd3c1 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -38,9 +38,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 - typedef struct southbridge_intel_fsp_rangeley_config config_t; static void soc_enable_apic(struct device *dev) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 19e470e3098..2c2427eed1c 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -90,7 +90,6 @@ void main(FSP_INFO_HEADER *fsp_info_header) * Memory is setup and the stack is set by the FSP. */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; timestamp_add_now(TS_AFTER_INITRAM); @@ -113,7 +112,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 4c5e835c7f8..aceb425ab71 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -68,7 +68,6 @@ void soc_log_state(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void rangeley_sb_early_initialization(void); #endif #endif diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c deleted file mode 100644 index f18af8927c9..00000000000 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "soc.h" - -void watchdog_off(void) -{ - struct device *dev; - u32 value, abase; - - /* Turn off the watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= 1; - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - abase = (pci_read_config32(dev, ABASE) & ~0xf); - - /* Disable the watchdog timer. */ - value = inw(abase + 0x68); - value |= 1 << 11; - outw(value, abase + 0x68); - - /* Clear TCO timeout status. */ - outw(0x0008, abase + 0x64); - outw(0x0002, abase + 0x66); - - printk(BIOS_DEBUG, "TCO Watchdog disabled\n"); -} diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index a05e6688cc6..9515c01371a 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -33,11 +33,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *dev; /* Power management controller */ - dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a7d65c52bb8..2d6e938eba0 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -30,6 +30,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index b72ca235f5e..6e7f9bf945d 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) +bootblock-y += bootblock_gcc.c + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c @@ -30,8 +32,6 @@ ramstage-y += usb_ehci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += watchdog.c - smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 426973fc2f3..9d94d0cd257 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -23,10 +23,10 @@ static void enable_spi_prefetch(void) dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void bootblock_southbridge_init(void) diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c new file mode 100644 index 00000000000..996788888a2 --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "i82801gx.h" + +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, BIOS_CNTL); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, BIOS_CNTL, reg8); +} + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3db5d49f3f7..e44fcf51231 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -36,7 +36,6 @@ #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) -#include "chip.h" #if !defined(__SIMPLE_DEVICE__) void i82801gx_enable(struct device *dev); #endif @@ -89,12 +88,12 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) -#define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_EN (1 << 4) #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index a36237228c6..672ee432fd7 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -19,6 +19,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" typedef struct southbridge_intel_i82801gx_config config_t; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a1cc45af653..846a70997be 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -25,7 +25,6 @@ #include #include #include -#include "i82801gx.h" #include #include #include @@ -33,12 +32,15 @@ #include #include #include +#include + +#include "chip.h" +#include "i82801gx.h" #include "nvs.h" #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801gx_config config_t; @@ -167,7 +169,7 @@ static void i82801gx_gpi_routing(struct device *dev) static void i82801gx_power_options(struct device *dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16; u32 reg32; const char *state; /* Get the chip configuration */ @@ -254,18 +256,16 @@ static void i82801gx_power_options(struct device *dev) // Set the board's GPI routing. i82801gx_gpi_routing(dev); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + write_pmbase32(GPE0_EN, config->gpe0_en); + write_pmbase16(ALT_GP_SMI_EN, config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = read_pmbase32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 1); // enable C3->C0 transition on bus master reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + write_pmbase32(PM1_CNT, reg32); } static void i82801gx_configure_cstates(struct device *dev) @@ -333,10 +333,6 @@ static void enable_clock_gating(void) #if CONFIG(HAVE_SMI_HANDLER) static void i82801gx_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -351,33 +347,6 @@ static void i82801gx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif @@ -486,15 +455,15 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + u16 pmbase = lpc_get_pmbase(); fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x20; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x28; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; @@ -532,7 +501,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 0; @@ -546,21 +515,21 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 0; diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c54769fff3d..22c516581f5 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -46,9 +46,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 3e5dbc3e872..0946a9aadf3 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -19,6 +19,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" /* Low Power variant has 6 root ports. */ diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 8514b6d3bf3..b657513dcf3 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -20,6 +20,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" #include "sata.h" diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c deleted file mode 100644 index 12284b46c16..00000000000 --- a/src/southbridge/intel/i82801gx/watchdog.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void watchdog_off(void) -{ - struct device *dev; - unsigned long value, base; - - /* Turn off the ICH7 watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "ICH7 watchdog disabled\n"); -} diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 44b2cbc0e6d..5edb8a1426d 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -18,6 +18,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG @@ -29,6 +30,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select INTEL_DESCRIPTOR_MODE_CAPABLE select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG if SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 3cc7da5eadb..caa493211c9 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -29,8 +29,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += ../i82801gx/watchdog.c - ifneq ($(CONFIG_SMM_TSEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 4cc1cea02ca..c7de2a14df1 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -39,7 +39,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801ix_config config_t; @@ -370,10 +369,6 @@ static void enable_clock_gating(void) #if CONFIG(HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -393,33 +388,6 @@ static void i82801ix_lock_smm(struct device *dev) */ if (!CONFIG(PARALLEL_MP)) smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 6155c150060..49d2d36b85c 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -22,8 +22,10 @@ #include #include #include -#include "i82801ix.h" #include +#include + +#include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index be2d2897ba3..b423ecae40a 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -33,6 +33,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select ACPI_INTEL_HARDWARE_SLEEP_VALUES select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index c333566e0f6..6626bb5d330 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -29,8 +29,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += ../i82801gx/watchdog.c - smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index abfe6659891..5373ba2022e 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -40,7 +40,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801jx_config config_t; @@ -375,10 +374,6 @@ static void enable_clock_gating(void) #if CONFIG(HAVE_SMI_HANDLER) static void i82801jx_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -393,33 +388,6 @@ static void i82801jx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 8de2d7427d4..ddaa7838681 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -22,8 +22,10 @@ #include #include #include -#include "i82801jx.h" #include +#include + +#include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index bb6e22cb739..85c89799e08 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SMM select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR @@ -40,6 +41,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_INTEL_CHIPSET_LOCKDOWN select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 5c890300a4f..fccb3a86565 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -31,17 +31,13 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += ../bd82x6x/me_status.c -ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += madt.c -ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c romstage-y += ../bd82x6x/early_rcba.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c endif diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f4464f3b4dc..e7162b1e04b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -451,9 +451,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9b2dd8ac8e1..04cc21d4754 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -61,7 +61,6 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG(ELOG) void pch_log_state(void); #endif @@ -72,7 +71,6 @@ int smbus_read_byte(unsigned device, unsigned address); int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); #endif diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 112445bb652..e03f8b58845 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -21,9 +21,11 @@ #include #include #include -#include "pch.h" #include #include +#include + +#include "pch.h" typedef struct southbridge_intel_ibexpeak_config config_t; diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c deleted file mode 100644 index 4c9f2ac26d4..00000000000 --- a/src/southbridge/intel/ibexpeak/smi.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "pch.h" - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_DEBUG, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i>= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear ALT_GP_SMI_STS - * @return ALT_GP_SMI_STS register - */ -static u16 reset_alt_gp_smi_status(void) -{ - u16 reg16; - - reg16 = inl(pmbase + ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg16, pmbase + ALT_GP_SMI_STS); - - return reg16; -} - -static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) -{ - int i; - printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i>= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i); - } - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -void southbridge_smm_init(void) -{ - u32 smi_en; - u16 pm1_en; - u32 gpe0_en; - -#if CONFIG(ELOG) - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - printk(BIOS_DEBUG, "Initializing southbridge SMI..."); - - pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Disable GPE0 PME_B0 */ - gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~PME_B0_EN; - outl(gpe0_en, pmbase + GPE0_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif - smi_en |= TCO_EN; - smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif - smi_en |= SLP_SMI_EN; -#if 0 - smi_en |= BIOS_EN; -#endif - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); -} - -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index fabe1c41ba7..dbc412c072d 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -35,13 +35,7 @@ */ #include #include - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -static u8 smm_initialized = 0; +#include /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. @@ -52,193 +46,6 @@ global_nvs_t *smm_get_gnvs(void) return gnvs; } -static void alt_gpi_mask(u16 clr, u16 set) -{ - u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); - alt_gp &= ~clr; - alt_gp |= set; - outw(alt_gp, pmbase + ALT_GP_SMI_EN); -} - -static void gpe0_mask(u32 clr, u32 set) -{ - u32 gpe0 = inl(pmbase + GPE0_EN); - gpe0 &= ~clr; - gpe0 |= set; - outl(gpe0, pmbase + GPE0_EN); -} - -void gpi_route_interrupt(u8 gpi, u8 mode) -{ - u32 gpi_rout; - if (gpi >= 16) - return; - - alt_gpi_mask(1 << gpi, 0); - gpe0_mask(1 << (gpi+16), 0); - - gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); - gpi_rout &= ~(3 << (2 * gpi)); - gpi_rout |= ((mode & 3) << (2 * gpi)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); - - if (mode == GPI_IS_SCI) - gpe0_mask(0, 1 << (gpi+16)); - else if (mode == GPI_IS_SMI) - alt_gpi_mask(0, 1 << gpi); -} - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_SPEW, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); - printk(BIOS_SPEW, "\n"); - int reg16 = inw(pmbase + PM1_EN); - printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i>= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); - if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -256,53 +63,6 @@ int southbridge_io_trap_handler(int smif) return 0; } -/** - * @brief Set the EOS bit - */ -void southbridge_smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -static void busmaster_disable_on_bus(int bus) -{ - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - pci_devfn_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } -} - static void southbridge_gate_memory_reset_real(int offset, u16 use, u16 io, u16 lvl) { @@ -334,7 +94,7 @@ static void southbridge_gate_memory_reset_real(int offset, * Intel reference designs all use GPIO 60 but it is * not a requirement and boards could use a different pin. */ -static void southbridge_gate_memory_reset(void) +void southbridge_gate_memory_reset(void) { u16 gpiobase; @@ -354,377 +114,7 @@ static void southbridge_gate_memory_reset(void) gpiobase + GP_LVL); } -static void xhci_sleep(u8 slp_typ) -{ - u32 reg32, xhci_bar; - u16 reg16; - - switch (slp_typ) { - case ACPI_S3: - case ACPI_S4: - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 &= ~0x03UL; - pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - - xhci_bar = pci_read_config32(PCH_XHCI_DEV, - PCI_BASE_ADDRESS_0) & ~0xFUL; - - if ((xhci_bar + 0x4C0) & 1) - pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4D0) & 1) - pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4E0) & 1) - pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4F0) & 1) - pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 |= 0x03; - pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); - break; - - case ACPI_S5: - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 |= ((1 << 8) | 0x03); - pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); - break; - } -} - -static void southbridge_smi_sleep(void) -{ - u8 reg8; - u32 reg32; - u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - // save and recover RTC port values - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); - get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); - - /* First, disable further SMIs */ - reg8 = inb(pmbase + SMI_EN); - reg8 &= ~SLP_SMI_EN; - outb(reg8, pmbase + SMI_EN); - - /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = acpi_sleep_from_pm1(reg32); - - if (smm_get_gnvs()->xhci) - xhci_sleep(slp_typ); - - /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ); - -#if CONFIG(ELOG_GSMI) - /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif - - /* Next, do the deed. - */ - - switch (slp_typ) { - case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case ACPI_S3: - printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - /* Gate memory reset */ - southbridge_gate_memory_reset(); - - /* Invalidate the cache before going to S3 */ - wbinvd(); - break; - case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - - outl(0, pmbase + GPE0_EN); - - /* Always set the flag in case CMOS was changed on runtime. For - * "KEEP", switch to "OFF" - KEEP is software emulated - */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* also iterates over all bridges on bus 0 */ - busmaster_disable_on_bus(0); - break; - default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; - } - - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. - */ - outl(reg32 | SLP_EN, pmbase + PM1_CNT); - - /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ >= ACPI_S3) - halt(); - - /* In most sleep states, the code flow of this function ends at - * the line above. However, if we entered sleep state S1 and wake - * up again, we will continue to execute code in this function. - */ - reg32 = inl(pmbase + PM1_CNT); - if (reg32 & SCI_EN) { - /* The OS is not an ACPI OS, so we set the state to S0 */ - reg32 &= ~(SLP_EN | SLP_TYP); - outl(reg32, pmbase + PM1_CNT); - } -} - -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -#if CONFIG(ELOG_GSMI) -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} -#endif - -static void southbridge_smi_apmc(void) -{ - u32 pmctrl; - u8 reg8; - em64t101_smm_state_save_area_t *state; - - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; -#if CONFIG(ELOG_GSMI) - case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); - break; -#endif - } - - mainboard_smi_apmc(reg8); -} - -static void southbridge_smi_pm1(void) -{ - u16 pm1_sts; - - pm1_sts = reset_pm1_status(); - dump_pm1_status(pm1_sts); - - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ - if (pm1_sts & PWRBTN_STS) { - // power button pressed - u32 reg32; - reg32 = (7 << 10) | (1 << 13); -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif - outl(reg32, pmbase + PM1_CNT); - } -} - -static void southbridge_smi_gpe0(void) -{ - u32 gpe0_sts; - - gpe0_sts = reset_gpe0_status(); - dump_gpe0_status(gpe0_sts); -} - -static void southbridge_smi_gpi(void) -{ - u16 reg16; - reg16 = inw(pmbase + ALT_GP_SMI_STS); - outw(reg16, pmbase + ALT_GP_SMI_STS); - - reg16 &= inw(pmbase + ALT_GP_SMI_EN); - - mainboard_smi_gpi(reg16); - - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - - outw(reg16, pmbase + ALT_GP_SMI_STS); -} - -static void southbridge_smi_mc(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & MCSMI_EN) == 0) - return; - - printk(BIOS_DEBUG, "Microcontroller SMI.\n"); -} - - - -static void southbridge_smi_tco(void) -{ - u32 tco_sts; - - tco_sts = reset_tco_status(); - - /* Any TCO event? */ - if (!tco_sts) - return; - - if (tco_sts & (1 << 8)) { // BIOSWR - u8 bios_cntl; - - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); - - if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - */ - - /* This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); - } /* No else for now? */ - } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ - /* Handle TCO timeout */ - printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else { - dump_tco_status(tco_sts); - } -} - -static void southbridge_smi_periodic(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -static void southbridge_smi_monitor(void) +void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -778,76 +168,18 @@ static void southbridge_smi_monitor(void) #undef IOTRAP } -typedef void (*smi_handler_t)(void); - -static smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - southbridge_smi_gpi, // [10] GPI_STS - southbridge_smi_mc, // [11] MCSMI_STS - NULL, // [12] DEVMON_STS - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - southbridge_smi_monitor, // [21] MONITOR_STS - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] EL_SMI_STS - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] reserved - NULL, // [29] reserved - NULL, // [30] reserved - NULL // [31] reserved -}; - -/** - * @brief Interrupt handler for SMI# - * @param node - * @param state_save - */ -void southbridge_smi_handler(void) +void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - int i, dump = 0; - u32 smi_sts; - - /* Update global variable pmbase */ - pmbase = lpc_get_pmbase(); - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = reset_smi_status(); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 31; i++) { - if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) { - southbridge_smi[i](); - } else { - printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " - "handler available.\n", i); - dump = 1; - } - } - } - - if (dump) { - dump_smi_status(smi_sts); + em64t101_smm_state_save_area_t *state = + smi_apmc_find_state_save(apm_cnt); + if (state) { + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)((u32)state->rbx); + *smm_done = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } +} +void southbridge_finalize_all(void) +{ } diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 431744f08c5..67e20be11f1 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -42,6 +42,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select COMMON_FADT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config INTEL_LYNXPOINT_LP bool @@ -53,10 +54,6 @@ config EHCI_BAR hex default 0xe8000000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/lynxpoint/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index b18e6dafc88..3e3ef35e2d9 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) +bootblock-y += bootblock.c + ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c @@ -35,7 +37,6 @@ endif ramstage-y += rcba.c ramstage-y += me_status.c -ramstage-y += watchdog.c ramstage-y += acpi.c ramstage-$(CONFIG_ELOG) += elog.c @@ -44,8 +45,9 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c +bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c -romstage-y += early_spi.c rcba.c pmutil.c +romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c @@ -53,4 +55,7 @@ ramstage-y += lp_gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c endif +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c + endif diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 16f4ef90bc0..39e69257eb8 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -14,6 +14,7 @@ */ #include +#include #include "pch.h" /* @@ -69,7 +70,7 @@ static void set_spi_speed(void) SPIBAR8(SSFC + 2) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); @@ -78,4 +79,7 @@ static void bootblock_southbridge_init(void) /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc(); + mainboard_config_superio(); } diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 3d2d2c48faf..c36257747d2 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -104,8 +104,6 @@ int early_pch_init(const void *gpio_map, { int wake_from_s3; - pch_enable_lpc(); - pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) @@ -113,11 +111,6 @@ int early_pch_init(const void *gpio_map, #else setup_pch_gpios(gpio_map); #endif - - mainboard_config_superio(); - - console_init(); - pch_generic_setup(); /* Enable SMBus for reading SPDs. */ diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c deleted file mode 100644 index 3034930a06e..00000000000 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e8cad388d53..b0f57c122bb 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -510,9 +510,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) @@ -623,7 +623,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) #define LPC_DEFAULT_IO_RANGE_LOWER 0 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -static inline int pch_io_range_in_default(u16 base, u16 size) +static inline int pch_io_range_in_default(int base, int size) { /* Does it start above the range? */ if (base >= LPC_DEFAULT_IO_RANGE_UPPER) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 5cf67aa238d..a57bae311db 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -100,7 +100,7 @@ static void pch_enable_d3hot(struct device *dev) pci_write_config32(dev, PCH_PCS, reg32); } -/* Set bit in Function Disble register to hide this device */ +/* Set bit in function disable register to hide this device */ void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 97d0aa33b3c..93c2bc5703e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -195,7 +195,6 @@ void southbridge_smm_enable_smi(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 3c63723f726..cc494771dd6 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,6 +24,9 @@ #include #include #include +#include +#include +#include #include "pch.h" #if CONFIG(INTEL_LYNXPOINT_LP) diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c deleted file mode 100644 index 545d3d50d56..00000000000 --- a/src/southbridge/intel/lynxpoint/watchdog.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - - // - // Disable PCH Watchdog timer at SB_RCBA+0x3410 - // - // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; - // -void watchdog_off(void) -{ - struct device *dev; - unsigned long value, base; - - /* Turn off the ICH7 watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "PCH watchdog disabled\n"); -} diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 59796e1add3..02d70a694da 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -58,9 +58,6 @@ static void ck804_enable(struct device *dev) u32 reg_old, reg; u8 byte; - struct southbridge_nvidia_ck804_config *conf; - conf = dev->chip_info; - if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 1e357df85aa..156c38745ba 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -17,6 +17,7 @@ */ #include +#include #include #include diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 09414af3dec..908cdd595f8 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -17,6 +17,7 @@ #include #include +#include #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 1aef631ee6d..6416dd37b0b 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -100,10 +100,9 @@ static void lpc_init(struct device *dev) get_option(&on, "slow_cpu"); if (on) { u16 pm10_bar; - u32 dword; pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); + inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index f93ec92a701..bd49d9be5f3 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -59,8 +59,6 @@ void mcp55_enable(struct device *dev) u32 reg_old, reg; u8 byte; unsigned deviceid, vendorid, devfn; - struct southbridge_nvidia_mcp55_config *conf; - conf = dev->chip_info; int i; if (dev->device == 0x0000) { diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 5fc0ecdd7ef..ca96343858d 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,6 +14,7 @@ ## GNU General Public License for more details. ## +subdirs-y += aspeed subdirs-y += fintek subdirs-y += intel subdirs-y += ite diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc new file mode 100644 index 00000000000..6d0cc263e9a --- /dev/null +++ b/src/superio/aspeed/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## include generic fintek pre-ram stage driver +romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c +bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c + +subdirs-y += ast2400 +subdirs-y += common + +CPPFLAGS_common += -Isrc/superio/aspeed diff --git a/src/superio/aspeed/ast2400/Kconfig b/src/superio/aspeed/ast2400/Kconfig new file mode 100644 index 00000000000..1ced5afdc28 --- /dev/null +++ b/src/superio/aspeed/ast2400/Kconfig @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ASPEED_AST2400 + bool + default n + select SUPERIO_ASPEED_COMMON_PRE_RAM diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc new file mode 100644 index 00000000000..a6f8b2003a3 --- /dev/null +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h new file mode 100644 index 00000000000..aa9b0a98996 --- /dev/null +++ b/src/superio/aspeed/ast2400/ast2400.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_AST2400_H +#define SUPERIO_ASPEED_AST2400_H + +#define AST2400_SUART1 0x2 /* Com1 */ +#define AST2400_SUART2 0x3 /* Com2 */ +#define AST2400_SWAK 0x4 /* System Wake-Up control */ +#define AST2400_KBC 0x5 /* Keyboard controller */ +#define AST2400_GPIO 0x7 /* GPIO */ +#define AST2400_SUART3 0xB /* Com3 */ +#define AST2400_SUART4 0xC /* Com4 */ +#define AST2400_ILPC2AHB 0xD /* LPC 2 AHB */ +#define AST2400_MAILBOX 0xE /* Mailbox */ + +#endif /* SUPERIO_ASPEED_AST2400_H */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c new file mode 100644 index 00000000000..dcb14fa6688 --- /dev/null +++ b/src/superio/aspeed/ast2400/superio.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ast2400.h" + +static void ast2400_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case AST2400_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = ast2400_init, + .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SWAK, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 + | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, }, + { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 + | PNP_MSC0, 0xffff, 0xffff, }, + { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region + { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 + | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 + | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC + | PNP_MSCD | PNP_MSCE, }, + { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations superio_aspeed_ast2400_ops = { + CHIP_NAME("ASpeed AST2400 Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig new file mode 100644 index 00000000000..3f0dabb8534 --- /dev/null +++ b/src/superio/aspeed/common/Kconfig @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# Generic Aspeed preram driver - Just enough UART initialisation code for +# preram phase. +config SUPERIO_ASPEED_COMMON_PRE_RAM + bool + default n diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h new file mode 100644 index 00000000000..d3774eab3ee --- /dev/null +++ b/src/superio/aspeed/common/aspeed.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H +#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H + +#include +#include +#include + +void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); + +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + +#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */ diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c new file mode 100644 index 00000000000..7ac9474bcca --- /dev/null +++ b/src/superio/aspeed/common/early_serial.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * A generic pre-ram driver for Aspeed variant Super I/O chips. + * + * The following is derived directly from the vendor Aspeed's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Aspeed Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * ASPEED_ENTRY_KEY := enable configuration : 0xA5 (twice!) + * ASPEED_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include +#include +#include +#include +#include "aspeed.h" + +#define ASPEED_ENTRY_KEY 0xA5 +#define ASPEED_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0xA5' into index port dev. */ +void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(ASPEED_ENTRY_KEY, port); + outb(ASPEED_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(ASPEED_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index dec630bfa4c..8ba1cddba96 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,6 +49,12 @@ void pnp_enter_conf_mode_a0a0(struct device *dev) outb(0xa0, dev->path.pnp.port); } +void pnp_enter_conf_mode_a5a5(struct device *dev) +{ + outb(0xa5, dev->path.pnp.port); + outb(0xa5, dev->path.pnp.port); +} + void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); @@ -96,6 +103,11 @@ const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = { .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = { + .enter_conf_mode = pnp_enter_conf_mode_a5a5, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202, diff --git a/src/superio/fintek/f71808a/chip.h b/src/superio/fintek/f71808a/chip.h index f4e80ff8398..d838f3aec19 100644 --- a/src/superio/fintek/f71808a/chip.h +++ b/src/superio/fintek/f71808a/chip.h @@ -22,6 +22,13 @@ struct superio_fintek_f71808a_config { + uint8_t hwm_vt1_boundary_1_temperature; + uint8_t hwm_vt1_boundary_2_temperature; + uint8_t hwm_vt1_boundary_3_temperature; + uint8_t hwm_vt1_boundary_4_temperature; + uint8_t hwm_fan1_boundary_hysteresis; + uint8_t hwm_domain1_en; + /* Multi function registers */ uint8_t multi_function_register_0; uint8_t multi_function_register_1; diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c index a3702194cba..f5e62f942ed 100644 --- a/src/superio/fintek/f71808a/f71808a_hwm.c +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -23,6 +23,7 @@ /* Intel Ibex Peak/PECI/AMD TSI */ #define HWM_PECI_TSI_CTRL_REG 0x0a +#define HWM_DOMAIN1_EN 0x0b #define HWM_TCC_TEMPERATURE_REG 0x0c /* Fan 1 control */ @@ -33,6 +34,12 @@ #define HWM_FAN1_SEG5_SPEED_REG 0xae #define HWM_FAN1_TEMP_SRC_REG 0xaf +#define HWM_FAN1_BOUNDARY_HYSTERESIS 0x98 +#define HWM_VT1_BOUNDARY_1_TEMPERATURE 0xa6 +#define HWM_VT1_BOUNDARY_2_TEMPERATURE 0xa7 +#define HWM_VT1_BOUNDARY_3_TEMPERATURE 0xa8 +#define HWM_VT1_BOUNDARY_4_TEMPERATURE 0xa9 + /* Fan 2 control */ #define HWM_FAN2_SEG1_SPEED_REG 0xba #define HWM_FAN2_SEG2_SPEED_REG 0xbb @@ -55,6 +62,21 @@ void f71808a_hwm_init(struct device *dev) pnp_enter_conf_mode(dev); + if (reg->hwm_vt1_boundary_1_temperature) { + pnp_write_index(port, HWM_VT1_BOUNDARY_4_TEMPERATURE, + reg->hwm_vt1_boundary_4_temperature); + pnp_write_index(port, HWM_VT1_BOUNDARY_3_TEMPERATURE, + reg->hwm_vt1_boundary_3_temperature); + pnp_write_index(port, HWM_VT1_BOUNDARY_2_TEMPERATURE, + reg->hwm_vt1_boundary_2_temperature); + pnp_write_index(port, HWM_VT1_BOUNDARY_1_TEMPERATURE, + reg->hwm_vt1_boundary_1_temperature); + pnp_write_index(port, HWM_FAN1_BOUNDARY_HYSTERESIS, + reg->hwm_fan1_boundary_hysteresis); + pnp_write_index(port, HWM_DOMAIN1_EN, + reg->hwm_domain1_en); + } + pnp_write_index(port, HWM_PECI_TSI_CTRL_REG, reg->hwm_peci_tsi_ctrl); pnp_write_index(port, HWM_TCC_TEMPERATURE_REG, reg->hwm_tcc_temp); diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 634888b2177..a5cd632e490 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -23,15 +23,13 @@ static void f71863fg_init(struct device *dev) { - struct resource *res0; - if (!dev->enabled) return; switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71863FG_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); + find_resource(dev, PNP_IDX_IO0); pc_keyboard_init(NO_AUX_DEVICE); break; } diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 551abe9a5dc..8388c7aa386 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Libretrend LDA ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -31,3 +32,4 @@ subdirs-y += it8721f subdirs-y += it8728f subdirs-y += it8772f subdirs-y += it8783ef +subdirs-y += it8786e diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 6c787417238..55f765004c9 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -51,4 +51,11 @@ config SUPERIO_ITE_ENV_CTRL_5FANS bool help ITE FAN controller has 5 independent outputs. + +config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + bool + help + Slope PWM registers have no separate BIT6 and are set directly by + 7-bit values instead. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 57896e0c017..1b930368455 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -4,6 +4,7 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG * Copyright (C) 2019 Protectli + * Copyright (C) 2019 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -165,9 +166,14 @@ static void fan_smartconfig(const u16 base, const u8 fan, pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); - pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } + if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; @@ -287,6 +293,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf) for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Enable External Sensor SMBus Host if configured */ + if (conf->smbus_en) { + ite_ec_write(base, ITE_EC_INTERFACE_SELECT, + ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_SMB_ENABLE); + } + /* Enable reading of voltage pins */ ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index e29e33f54a3..20e44ad5f11 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -4,6 +4,7 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG * Copyright (C) 2019 Protectli + * Copyright (C) 2019 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,6 +51,14 @@ #define ITE_EC_FAN_PWM_SMOOTHING_256HZ (1 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_64HZ (2 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_16HZ (3 << 6) +/* ITE IT8786E PWM_SMOOTHING_FREQ */ +#define ITE_EC_FAN_ALT_PWM_SMOOTHING_16HZ (1 << 6) +#define ITE_EC_FAN_ALT_PWM_SMOOTHING_8HZ (2 << 6) +#define ITE_EC_FAN_ALT_PWM_SMOOTHING_4HZ (3 << 6) +#define ITE_EC_FAN_CTL5_SEL(FAN_CTLx) ((((FAN_CTLx)-1) & 3) << 2) +#define ITE_EC_FAN_CTL5_SEL_NONE (3 << 2) +#define ITE_EC_FAN_CTL4_SEL(FAN_CTLx) (((FAN_CTLx)-1) & 3) +#define ITE_EC_FAN_CTL4_SEL_NONE (3 << 0) #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) @@ -68,6 +77,14 @@ : (0x1b + ((x)-1)) \ ) +#define ITE_EC_FAN_TAC_CNTRL 0x0c +#define ITE_EC_TMPIN3_ENHANCED_INT_MODE (1 << 7) +#define ITE_EC_TMPIN2_ENHANCED_INT_MODE (1 << 6) +#define ITE_EC_FAN_TAC5_EN (1 << 5) +#define ITE_EC_FAN_TAC4_EN (1 << 4) +#define ITE_EC_TMPIN1_ENHANCED_INT_MODE (1 << 3) +#define ITE_EC_AMDTSI_ERR_EN (1 << 0) + #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) #define ITE_EC_FAN_MAIN_CTL_COLL_FULL_SPEED (1 << 3) @@ -185,6 +202,8 @@ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; /* Common for ITE_EC_FAN_CTL_DELTA_TEMP */ #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 923bfa3aeac..f5116e6465f 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -101,6 +101,11 @@ struct ite_ec_config { bool tmpin_beep; bool fan_beep; bool vin_beep; + + /* + * Enable SMBus for external thermal sensor. + */ + bool smbus_en; }; /* Some shorthands for device trees */ diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig new file mode 100644 index 00000000000..9d3f258a5a5 --- /dev/null +++ b/src/superio/ite/it8786e/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2018 Libretrend LDA +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8786E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc new file mode 100644 index 00000000000..560957ffc51 --- /dev/null +++ b/src/superio/ite/it8786e/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2018 Libretrend LDA +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl new file mode 100644 index 00000000000..f860da643b3 --- /dev/null +++ b/src/superio/ite/it8786e/acpi/superio.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz + * Copyright (C) 2013, 2016 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8786E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, untested + * 0x2 UARTB Implemented, untested + * 0x3 PP Not implemented + * 0x4 EC Not implemented + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Not implemented + * 0x8 UARTC Implemented, untested + * 0x9 UARTD Implemented, untested + * 0xa UARTE Not implemented + * 0xb UARTF Not implemented + * 0xc CIR Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8786E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8786E_SHOW_UARTB If defined, UARTB will be exposed. + * IT8786E_SHOW_UARTC If defined, UARTC will be exposed. + * IT8786E_SHOW_UARTD If defined, UARTD will be exposed. + * IT8786E_SHOW_KBC If defined, the KBC will be exposed. + * IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8786E +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8786E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, + 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include + +#ifdef IT8786E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include +#endif + +#ifdef IT8786E_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include +#endif + +#ifdef IT8786E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef IT8786E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include +#endif + +#ifdef IT8786E_SHOW_UARTC + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 8 + #include +#endif + +#ifdef IT8786E_SHOW_UARTD + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 9 + #include +#endif +} diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h new file mode 100644 index 00000000000..4b2e8114756 --- /dev/null +++ b/src/superio/ite/it8786e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8786E_CHIP_H +#define SUPERIO_ITE_IT8786E_CHIP_H + +#include + +struct superio_ite_it8786e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8786E_CHIP_H */ diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h new file mode 100644 index 00000000000..5f11b636909 --- /dev/null +++ b/src/superio/ite/it8786e/it8786e.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8786E_H +#define SUPERIO_ITE_IT8786E_H + +#define IT8786E_SP1 0x01 /* COM1 */ +#define IT8786E_SP2 0x02 /* COM2 */ +#define IT8786E_PP 0x03 /* Printer port */ +#define IT8786E_EC 0x04 /* Environment controller */ +#define IT8786E_KBCK 0x05 /* Keyboard */ +#define IT8786E_KBCM 0x06 /* Mouse */ +#define IT8786E_GPIO 0x07 /* GPIO */ +#define IT8786E_SP3 0x08 /* COM3 */ +#define IT8786E_SP4 0x09 /* COM4 */ +#define IT8786E_CIR 0x0a /* Consumer IR */ +#define IT8786E_SP5 0x0b /* COM5 */ +#define IT8786E_SP6 0x0c /* COM6 */ + +#include + +#endif /* SUPERIO_ITE_IT8786E_H */ diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c new file mode 100644 index 00000000000..ac9dc4bc75f --- /dev/null +++ b/src/superio/ite/it8786e/superio.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "it8786e.h" +#include "chip.h" + +static void it8786e_init(struct device *const dev) +{ + const struct superio_ite_it8786e_config *conf; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8786E_EC: + conf = dev->chip_info; + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8786E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8786e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 2 */ + { NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Printer Port */ + { NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | + PNP_MSC0, + 0x0ff8, 0x0ffc, }, + /* Environmental Controller */ + { NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | + PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | + PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB | + PNP_MSCC, + 0x0ff8, 0x0ffc, }, + /* KBC Keyboard */ + { NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | + PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | + PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | + PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, + 0x0ffc, 0x0fff, }, + /* Serial Port 3 */ + { NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 4 */ + { NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Consumer Infrared */ + { NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Serial Port 5 */ + { NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 6 */ + { NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8786e_ops = { + CHIP_NAME("ITE IT8786E Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index b200855abd7..522d64796a5 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index c02b8506d1f..42213b74ccb 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -17,7 +17,9 @@ /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ #include +#include #include + #include "lpc47n227.h" void pnp_enter_conf_state(pnp_devfn_t dev) diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 522d4150e4f..8ccb0d0ee7a 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += google subdirs-y += intel subdirs-y += siemens subdirs-y += cavium +subdirs-y += eltan diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3fe0c822405..44b3940fa7a 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -47,6 +47,15 @@ if CPU_AMD_AGESA_BINARY_PI source src/vendorcode/amd/pi/Kconfig endif +config AGESA_EXTRA_TIMESTAMPS + bool "Add instrumentation for AGESA calls" + default n + depends on !BINARYPI_LEGACY_WRAPPER + depends on DRIVERS_AMD_PI + help + Insert additional timestamps around each entrypoint into + AGESA vendorcode. + endmenu endif diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc index 78dd4fc9880..247969477cc 100644 --- a/src/vendorcode/amd/agesa/common/Makefile.inc +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesa-entry.c ramstage-y += agesa-entry.c +libagesa-y += debug_util.c libagesa-y += amdlib.c # Do not optimise performance-critical low-level IO for size with -Os, diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 00000000000..29d0841904a --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include +#include +#include + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 00000000000..a8d9a33c501 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif diff --git a/src/vendorcode/amd/agesa/f12/AMD.h b/src/vendorcode/amd/agesa/f12/AMD.h index 179c3f5da0b..31c0b347a0b 100644 --- a/src/vendorcode/amd/agesa/f12/AMD.h +++ b/src/vendorcode/amd/agesa/f12/AMD.h @@ -148,7 +148,10 @@ typedef enum { AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index f925ccb5f0f..9bc3c2600e6 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -43,13 +43,8 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c index 37c9ff19bd1..3bf8de5d71c 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c @@ -527,7 +527,6 @@ NbSmuReadEfuseField ( UINT32 Address; UINT16 Shift; ASSERT (Length <= 32); - ASSERT (Chain <= 0xff); Shift = (Offset - (Offset & ~0x7)); Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); Value = NbSmuReadEfuse (Address, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/AMD.h b/src/vendorcode/amd/agesa/f14/AMD.h index 9d443beb1ee..c1cfaa1f32c 100644 --- a/src/vendorcode/amd/agesa/f14/AMD.h +++ b/src/vendorcode/amd/agesa/f14/AMD.h @@ -147,7 +147,10 @@ typedef enum { AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index ad2d2dc63dc..da79a39f8f8 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -43,14 +43,8 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c index 76401d435c9..bf1396de556 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c @@ -506,7 +506,6 @@ NbSmuReadEfuseField ( UINT32 Address; UINT16 Shift; ASSERT (Length <= 32); - ASSERT (Chain <= 0xff); Shift = (Offset - (Offset & ~0x7)); Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); Value = NbSmuReadEfuse (Address, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/AMD.h b/src/vendorcode/amd/agesa/f15tn/AMD.h index 31d38db5563..27326ecef8d 100644 --- a/src/vendorcode/amd/agesa/f15tn/AMD.h +++ b/src/vendorcode/amd/agesa/f15tn/AMD.h @@ -144,7 +144,10 @@ typedef enum { AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h index f0d91940186..bd00756c436 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h @@ -808,9 +808,9 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; #define F15_TN_UCODE_0E #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc []; + extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc []; #undef F15_TN_UCODE_10F - #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600110F_Enc, + #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc, #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 57350d95711..1c5dc18d857 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -46,8 +46,6 @@ CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c deleted file mode 100644 index 80e60f6313e..00000000000 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Tn Microcode patch. - * - * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/TN - * @e \$Revision: 64060 $ @e \$Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0600110F for 6101 and equivalent - -CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] = -{ - 0x12, - 0x20, - 0x11, - 0x01, - 0x0f, - 0x11, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x61, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0xd4, - 0x3d, - 0x97, - 0xf0, - 0xd2, - 0x1a, - 0xcf, - 0x44, - 0x1d, - 0x45, - 0x82, - 0x13, - 0xec, - 0xcd, - 0x52, - 0x24, - 0x2d, - 0x26, - 0x73, - 0x9f, - 0x0e, - 0x38, - 0x80, - 0x5b, - 0x02, - 0x6a, - 0xd3, - 0x80, - 0x97, - 0xc0, - 0xe8, - 0x08, - 0xaf, - 0x52, - 0x2e, - 0xe4, - 0x54, - 0xa6, - 0xb3, - 0xb3, - 0x9b, - 0x21, - 0xb9, - 0xe1, - 0xa8, - 0xa4, - 0xed, - 0x9a, - 0x76, - 0xf7, - 0x62, - 0x13, - 0x3b, - 0xf8, - 0x21, - 0xc4, - 0xf3, - 0xff, - 0xb5, - 0x20, - 0xbd, - 0x8c, - 0x3a, - 0x4b, - 0x7e, - 0x44, - 0x88, - 0x9e, - 0x21, - 0xf3, - 0x32, - 0xad, - 0x96, - 0xf9, - 0x1d, - 0xe4, - 0xce, - 0xdd, - 0xb7, - 0x58, - 0x6c, - 0x3c, - 0x78, - 0x00, - 0x9f, - 0x9f, - 0x76, - 0x6e, - 0x92, - 0x80, - 0xb9, - 0x6a, - 0xcf, - 0x66, - 0x2b, - 0x7e, - 0x1d, - 0xbf, - 0x2d, - 0xca, - 0xde, - 0x58, - 0x1b, - 0xc6, - 0xb8, - 0x5e, - 0x82, - 0xc3, - 0xdf, - 0x8b, - 0xd8, - 0xdb, - 0xca, - 0x43, - 0xf2, - 0x75, - 0x40, - 0xb6, - 0xbf, - 0xdb, - 0x5f, - 0xb8, - 0xd2, - 0xdd, - 0x81, - 0xeb, - 0xa6, - 0x7f, - 0x01, - 0xbc, - 0x37, - 0x07, - 0x4e, - 0x73, - 0x13, - 0xcf, - 0x08, - 0xb9, - 0xd6, - 0xda, - 0xe6, - 0x10, - 0xd7, - 0x2c, - 0xfe, - 0x49, - 0x3e, - 0x4b, - 0xa0, - 0xfa, - 0xc1, - 0x81, - 0xe9, - 0xdb, - 0x70, - 0xfd, - 0x46, - 0xc4, - 0x44, - 0x4c, - 0x14, - 0xc2, - 0x1a, - 0x46, - 0xa5, - 0x2c, - 0xb3, - 0x04, - 0x15, - 0xda, - 0x53, - 0x74, - 0x41, - 0x61, - 0xcc, - 0xda, - 0x40, - 0x53, - 0x03, - 0x4a, - 0x51, - 0xc2, - 0x4f, - 0x81, - 0x34, - 0x89, - 0x4f, - 0x7c, - 0x7e, - 0xa0, - 0x50, - 0x7a, - 0xc8, - 0xf3, - 0xd0, - 0xfc, - 0x7f, - 0xda, - 0xa8, - 0x61, - 0x6c, - 0x46, - 0xb3, - 0xc9, - 0x05, - 0x0b, - 0x9f, - 0x5e, - 0xb1, - 0x43, - 0x9d, - 0xc0, - 0x3a, - 0xbe, - 0x6e, - 0x05, - 0x30, - 0x3d, - 0xf1, - 0xee, - 0x0e, - 0xcf, - 0x63, - 0x40, - 0xe9, - 0xd3, - 0x27, - 0x2c, - 0x0a, - 0x48, - 0xe8, - 0xae, - 0xc0, - 0x38, - 0xae, - 0x3b, - 0x41, - 0x21, - 0x5a, - 0xa2, - 0xc0, - 0x20, - 0x77, - 0x18, - 0x9b, - 0x7f, - 0xdd, - 0x95, - 0x4b, - 0x8b, - 0x83, - 0x2c, - 0xfb, - 0x49, - 0xd8, - 0x25, - 0xf2, - 0x21, - 0x6e, - 0x54, - 0xe5, - 0x01, - 0x22, - 0xd5, - 0xf8, - 0x99, - 0x1f, - 0x83, - 0x69, - 0x52, - 0xa1, - 0x9a, - 0x67, - 0x73, - 0x55, - 0xa2, - 0x98, - 0x82, - 0x8c, - 0xff, - 0xed, - 0x9c, - 0x0a, - 0x07, - 0x33, - 0x6f, - 0x16, - 0x39, - 0x79, - 0xcc, - 0xe3, - 0x5a, - 0xa0, - 0x2d, - 0xa6, - 0xdf, - 0x2e, - 0x4b, - 0xab, - 0x6c, - 0x6f, - 0xd4, - 0x6e, - 0x70, - 0x9b, - 0x9a, - 0xf3, - 0xb3, - 0x52, - 0xb8, - 0x05, - 0x53, - 0xba, - 0x79, - 0x08, - 0x6a, - 0xb1, - 0x5e, - 0xf7, - 0x85, - 0xc1, - 0xfc, - 0xd8, - 0xb5, - 0x3d, - 0xbb, - 0xb9, - 0x3d, - 0xa3, - 0x98, - 0x13, - 0x61, - 0xed, - 0x1e, - 0xc0, - 0x45, - 0x6c, - 0x98, - 0xfc, - 0x87, - 0x2c, - 0xb8, - 0x99, - 0x97, - 0xb8, - 0xc7, - 0x5f, - 0x2e, - 0x6d, - 0x28, - 0x79, - 0xaf, - 0x0b, - 0xf9, - 0x84, - 0x7e, - 0x34, - 0xd8, - 0x86, - 0x61, - 0x22, - 0xdb, - 0xf4, - 0xef, - 0x58, - 0x0d, - 0x4e, - 0xcf, - 0x02, - 0x8a, - 0xf8, - 0x17, - 0xab, - 0x7d, - 0x79, - 0x98, - 0x38, - 0x35, - 0x59, - 0xdf, - 0x03, - 0xff, - 0xed, - 0xc7, - 0x1f, - 0x25, - 0xe3, - 0x26, - 0x05, - 0xde, - 0x7f, - 0xbb, - 0xe4, - 0xff, - 0xbf, - 0x6d, - 0xc6, - 0xc2, - 0x2e, - 0x02, - 0x45, - 0x85, - 0x5f, - 0x43, - 0xdb, - 0xb8, - 0xd2, - 0x13, - 0xd7, - 0x52, - 0xde, - 0x53, - 0x49, - 0xda, - 0x7f, - 0x0b, - 0xb8, - 0x76, - 0x70, - 0xf9, - 0xfe, - 0xf0, - 0x27, - 0xb7, - 0xc9, - 0xd4, - 0x83, - 0x6d, - 0x80, - 0xaa, - 0x34, - 0x46, - 0xf5, - 0xe3, - 0x1f, - 0xd7, - 0x0f, - 0xf2, - 0xee, - 0x5a, - 0xb2, - 0xcd, - 0x08, - 0x47, - 0xe6, - 0xf7, - 0x99, - 0xd1, - 0x05, - 0x55, - 0x0f, - 0x5f, - 0x1d, - 0xab, - 0xd6, - 0xb3, - 0x32, - 0xaf, - 0xa1, - 0x57, - 0x4d, - 0x32, - 0x00, - 0x4f, - 0xf6, - 0x6f, - 0x6e, - 0x79, - 0x8a, - 0x7c, - 0xc2, - 0xef, - 0x7e, - 0xcd, - 0x83, - 0xac, - 0x85, - 0x0e, - 0x53, - 0x2c, - 0xd9, - 0x92, - 0xf5, - 0x55, - 0xf6, - 0xc9, - 0x41, - 0xed, - 0xf5, - 0x4e, - 0x41, - 0xea, - 0x97, - 0xca, - 0x3b, - 0x14, - 0xca, - 0x0d, - 0x4e, - 0xb9, - 0x5f, - 0x54, - 0x23, - 0xf1, - 0xdc, - 0x8b, - 0xa4, - 0xc1, - 0x52, - 0xe2, - 0x7a, - 0x8f, - 0xdf, - 0x3f, - 0x93, - 0xa1, - 0x84, - 0x5c, - 0xca, - 0x6a, - 0x3a, - 0x42, - 0x95, - 0x2e, - 0x71, - 0xf6, - 0xa2, - 0x88, - 0x56, - 0x32, - 0xe8, - 0x98, - 0x2a, - 0xb8, - 0xf0, - 0x65, - 0x95, - 0x01, - 0xb8, - 0xc8, - 0x23, - 0xe9, - 0x30, - 0x52, - 0x94, - 0xeb, - 0xfa, - 0x9f, - 0x67, - 0x53, - 0xf0, - 0x63, - 0x10, - 0x70, - 0x1b, - 0x01, - 0x71, - 0x21, - 0xb3, - 0x27, - 0x4e, - 0x37, - 0x04, - 0xdc, - 0x74, - 0x6f, - 0xf3, - 0x08, - 0x00, - 0x72, - 0x21, - 0x96, - 0xe5, - 0xc6, - 0x75, - 0xa8, - 0x14, - 0x6f, - 0xcf, - 0xd8, - 0x86, - 0xe3, - 0xb7, - 0xf3, - 0x8c, - 0xe4, - 0x71, - 0x03, - 0x60, - 0xd4, - 0x53, - 0xff, - 0x5a, - 0x07, - 0xc4, - 0xe5, - 0x6b, - 0xf4, - 0x8d, - 0x80, - 0x55, - 0x78, - 0x4f, - 0xf5, - 0x55, - 0x04, - 0x2e, - 0x61, - 0x05, - 0x46, - 0x51, - 0x56, - 0xf8, - 0x0a, - 0xf5, - 0x6e, - 0x08, - 0x85, - 0xfd, - 0x01, - 0x9a, - 0x90, - 0x5a, - 0xed, - 0x0e, - 0x44, - 0x49, - 0xff, - 0x48, - 0xbe, - 0x5b, - 0xc4, - 0xea, - 0xbb, - 0x38, - 0xa9, - 0x04, - 0xf3, - 0x6c, - 0x6b, - 0x41, - 0x85, - 0x59, - 0x18, - 0x38, - 0xd5, - 0x52, - 0x18, - 0x1d, - 0xdd, - 0xab, - 0x28, - 0xd9, - 0x05, - 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0x93, - 0xdd, - 0x16, - 0xed, - 0x8e, - 0x27, - 0x66, - 0x4d, - 0x59, - 0xf0, - 0x27, - 0x1b, - 0x37, - 0xa0, - 0x25, - 0x9a, - 0x62, - 0xb4, - 0x6f, - 0xbd, - 0x83, - 0x28, - 0x0b, - 0x26, - 0xa9, - 0x07, - 0xac, - 0xb5, - 0x91, - 0x93, - 0x91, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c new file mode 100644 index 00000000000..71fb1df0a8a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c @@ -0,0 +1,405 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F15Tn Microcode patch. + * + * F15Tn Microcode Patch rev 0600111F for 6101/6131 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 334098 $ @e \$Date: 2018-03-05 14:21:15 -0600 (Mon, 05 Mar 2018) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +// Encrypt Patch code 0600111F for 6101/6131 and equivalent + +CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc [IDS_PAD_4K] = +{ + 0x18, 0x20, 0x05, 0x03, 0x1f, 0x11, 0x00, 0x06, + 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xd0, 0xb7, 0x58, 0x1c, 0xca, 0xa2, 0xf2, 0x52, + 0x72, 0xa4, 0xe1, 0x1b, 0x37, 0xe0, 0x9f, 0xb3, + 0x58, 0xf4, 0x76, 0x85, 0x1a, 0x83, 0x4a, 0x89, + 0x78, 0x82, 0x4e, 0xf3, 0xa1, 0x6a, 0xb7, 0x56, + 0x93, 0xcb, 0xfa, 0x4c, 0x03, 0x6b, 0xec, 0xb5, + 0x4f, 0xc0, 0x7d, 0x46, 0x0e, 0x04, 0x96, 0xec, + 0xab, 0xc3, 0x74, 0x0c, 0x4b, 0x1c, 0x19, 0x1f, + 0x62, 0x89, 0x66, 0xe4, 0x63, 0x1f, 0x9f, 0x0b, + 0xd6, 0x35, 0x08, 0xd3, 0xa3, 0xee, 0xbd, 0xf6, + 0x6d, 0x98, 0x95, 0x28, 0x75, 0x18, 0xce, 0x98, + 0x6e, 0xf6, 0x5c, 0x71, 0xf5, 0xf0, 0xeb, 0x06, + 0x59, 0xf1, 0x40, 0x8e, 0x84, 0xfe, 0xf0, 0x49, + 0x23, 0x4b, 0xb4, 0x6f, 0x38, 0xa4, 0xd8, 0x09, + 0x9e, 0xbe, 0x63, 0x9b, 0x20, 0xf3, 0xf7, 0xc7, + 0x2c, 0x71, 0xfe, 0x6a, 0xd3, 0x98, 0xe0, 0x74, + 0xea, 0x8e, 0xd8, 0x3c, 0x42, 0x7b, 0x03, 0x2d, + 0x02, 0x28, 0xb0, 0x99, 0x0f, 0x16, 0x54, 0x31, + 0x08, 0x27, 0x27, 0xb7, 0x7c, 0x31, 0x95, 0x1b, + 0x20, 0xfc, 0x47, 0x3b, 0xc6, 0x20, 0x8e, 0xd0, + 0xe7, 0x97, 0x43, 0xb6, 0x83, 0x74, 0x12, 0x01, + 0x43, 0x70, 0xc5, 0x71, 0x37, 0xf9, 0x13, 0xa2, + 0x7c, 0x4f, 0x7c, 0xf1, 0x8f, 0xec, 0x8a, 0xeb, + 0xb6, 0x04, 0x33, 0x99, 0xdc, 0xa5, 0x32, 0x9e, + 0x5c, 0xad, 0x7b, 0xbe, 0x1b, 0x8d, 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0xd1, 0x30, + 0xc3, 0xfb, 0x24, 0xdf, 0x0c, 0xd8, 0x30, 0x54, + 0x1d, 0xad, 0xa3, 0x45, 0x9e, 0xae, 0x97, 0xc2, + 0x9f, 0xf7, 0x7b, 0x4d, 0x66, 0x8f, 0xcc, 0x86, + 0x29, 0x8d, 0xc5, 0x87, 0x61, 0x16, 0x97, 0x19, + 0x6f, 0xf7, 0x63, 0x37, 0xb1, 0x6e, 0x19, 0x04, + 0x20, 0x6f, 0x31, 0x09, 0x24, 0xf3, 0x61, 0x42, + 0x2b, 0x92, 0x44, 0x91, 0x42, 0x7f, 0xe3, 0x0d, + 0xba, 0xfb, 0x7f, 0x33, 0x88, 0xe8, 0x71, 0x25, + 0xf2, 0xbb, 0xd5, 0x25, 0x58, 0xd3, 0x2e, 0x38, + 0x4f, 0x57, 0x70, 0x32, 0xa5, 0x59, 0xe4, 0x02, + 0xbb, 0x33, 0x75, 0x35, 0xb5, 0xe1, 0x0d, 0xcd, + 0x46, 0x0f, 0x6d, 0x86, 0xd3, 0x8f, 0x1e, 0xe5, + 0xa5, 0x8b, 0x9a, 0xa7, 0x4c, 0x0b, 0xca, 0x9a, + 0x64, 0x6e, 0x2f, 0xab, 0x9f, 0x21, 0xd6, 0x8d, + 0x6b, 0x29, 0x6a, 0x78, 0xa8, 0x4c, 0x15, 0x3d, + 0x8c, 0x3b, 0xac, 0xc6, 0x70, 0xeb, 0x41, 0xbe, + 0x41, 0x74, 0x9b, 0xe5, 0x87, 0xa3, 0x1c, 0xbe, + 0x47, 0x6e, 0x2d, 0x92, 0xbe, 0x80, 0xb4, 0x92, + 0xcc, 0x9e, 0x0b, 0x05, 0x75, 0xab, 0x9b, 0x76, + 0xd1, 0xde, 0x22, 0x32, 0x78, 0x69, 0xfb, 0x1b, + 0xe8, 0x4d, 0x49, 0x97, 0x23, 0xeb, 0x51, 0x38, + 0x9a, 0x22, 0xa7, 0xc0, 0xcf, 0x25, 0x3a, 0x4e, + 0x50, 0x0d, 0xff, 0x8e, 0xb5, 0x91, 0xd3, 0x85, + 0x54, 0xe9, 0x1f, 0x70, 0xea, 0x64, 0x6a, 0x77, + 0xbe, 0xd2, 0x15, 0xce, 0x9c, 0xb0, 0x70, 0x61, + 0x8b, 0x58, 0xdb, 0x9f, 0x0a, 0xe4, 0x80, 0xb3, + 0x21, 0x44, 0x0b, 0xea, 0x43, 0xab, 0x0d, 0xf0, + 0x7e, 0xbc, 0xd5, 0xde, 0x29, 0x12, 0xcd, 0xde, + 0xd9, 0xf3, 0xf3, 0x0e, 0xf4, 0xb8, 0x3d, 0xd7, + 0x4e, 0x24, 0xcf, 0x9b, 0x4b, 0xad, 0x96, 0x1e, + 0xca, 0x6d, 0x3f, 0x9c, 0xe4, 0xb8, 0x8b, 0xf5, + 0x3a, 0x43, 0xb0, 0xce, 0x16, 0x27, 0x87, 0xe3, + 0x1b, 0x54, 0xd0, 0xed, 0x3c, 0xe2, 0xb0, 0x1f, + 0x24, 0xa3, 0x6d, 0x31, 0x00, 0x7d, 0x58, 0x69, + 0xc9, 0xc6, 0x50, 0xc8, 0x87, 0xac, 0x45, 0x54, + 0x66, 0x06, 0x7f, 0xc3, 0x51, 0xb8, 0xdf, 0x51 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc index 7d52cb6dae7..e4b04247b26 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc @@ -4,7 +4,7 @@ libagesa-y += F15TnEquivalenceTable.c libagesa-y += F15TnInitEarlyTable.c libagesa-y += F15TnIoCstate.c libagesa-y += F15TnLogicalIdTables.c -libagesa-y += F15TnMicrocodePatch0600110F_Enc.c +libagesa-y += F15TnMicrocodePatch0600111F_Enc.c libagesa-y += F15TnMicrocodePatchTables.c libagesa-y += F15TnMsrTables.c libagesa-y += F15TnPciTables.c diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c index 7b7fa0dd91a..b0f98cf01c8 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c @@ -331,7 +331,7 @@ DmiF15TnGetVoltage ( LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) { + if ((MaxVid >= 0xF8)) { Voltage = 0; } else { Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c index 5e76e9a88ac..a7cb9547dc6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c @@ -62,6 +62,9 @@ CODE_GROUP (G3_DXE) RDATA_GROUP (G3_DXE) +/* Don't warn when checking header-defined ranges that may start at 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #define FILECODE PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE /** diff --git a/src/vendorcode/amd/agesa/f16kb/AMD.h b/src/vendorcode/amd/agesa/f16kb/AMD.h index bfce993bce0..83d538f3e21 100644 --- a/src/vendorcode/amd/agesa/f16kb/AMD.h +++ b/src/vendorcode/amd/agesa/f16kb/AMD.h @@ -143,7 +143,9 @@ typedef enum { AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE ///< AmdGet2DDataEye general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 3115c4d996e..c423cf2bab5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -46,8 +46,6 @@ CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c index 45b1b8f4186..6e8e6f06abd 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c @@ -287,7 +287,7 @@ DmiF16KbGetVoltage ( LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) { + if ((MaxVid >= 0xF8)) { Voltage = 0; } else { Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c index 61876b8db58..a0a20eb3e99 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c @@ -4,16 +4,16 @@ * * AMD F16Kb Microcode patch. * - * F16Kb Microcode Patch rev 0700010B for 7001 or equivalent. + * F16Kb Microcode Patch rev 07000110 for 7001 or equivalent. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 267923 $ @e \$Date: 2013-07-15 16:49:48 -0400 (Mon, 15 Jul 2013) $ + * @e \$Revision: 334098 $ @e \$Date: 2018-02-09 14:21:15 -0400 (Fri, 09 Feb 2018) $ */ /***************************************************************************** * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -64,3468 +64,443 @@ RDATA_GROUP (G3_DXE) */ -// Encrypt Patch code 0700010B for 7001 and equivalent +// Encrypt Patch code 07000110 for 7001 and equivalent CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] = { - 0x13, - 0x20, - 0x09, - 0x07, - 0x0b, - 0x01, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x70, - 0x00, - 0x00, - 0x00, - 0xaa, - 0xaa, - 0xaa, - 0x1c, - 0x8a, - 0x19, - 0x02, - 0x24, - 0xb6, - 0x41, - 0xb0, - 0x60, - 0x6a, - 0x6e, - 0xc3, - 0xdb, - 0xae, - 0xd9, - 0xa3, - 0x9e, - 0x4c, - 0x89, - 0xd2, - 0xe6, - 0xb8, - 0xb1, - 0x81, - 0x30, - 0xbd, - 0x57, - 0x94, - 0x81, - 0xa3, - 0xbc, - 0x81, - 0x95, - 0x47, - 0xb5, - 0x93, - 0x5f, - 0x8a, - 0xf6, - 0x82, - 0xcd, - 0x0e, - 0x4d, - 0xd3, - 0x26, - 0xd8, - 0xa8, - 0x35, - 0xb7, - 0x64, - 0xba, - 0x32, - 0x33, - 0x09, - 0xfd, - 0x93, - 0xc6, - 0x49, - 0x19, - 0xe3, - 0x53, - 0xc1, - 0xb5, - 0xcc, - 0x2f, - 0xf3, - 0x52, - 0xaa, - 0xe3, - 0x9c, - 0x79, - 0x52, - 0x10, - 0x5f, - 0xff, - 0x90, - 0x29, - 0x0b, - 0xf1, - 0x7f, - 0xfa, - 0x0c, - 0x10, - 0x75, - 0x84, - 0x74, - 0x81, - 0x8b, - 0x63, - 0xb3, - 0x71, - 0x20, - 0x25, - 0xc8, - 0x16, - 0x6d, - 0xc2, - 0xcc, - 0xf7, - 0x78, - 0x30, - 0xb6, - 0x2d, - 0x81, - 0x2b, - 0xdd, - 0xc4, - 0x6b, - 0xab, - 0x31, - 0x90, - 0xa8, - 0x6d, - 0xd7, - 0x6c, - 0xae, - 0x66, - 0xe5, - 0xdf, - 0xd6, - 0x65, - 0xd4, - 0x95, - 0xe5, - 0x68, - 0xae, - 0x26, - 0xa5, - 0x48, - 0xe6, - 0xf5, - 0xf3, - 0x22, - 0x67, - 0xb9, - 0x4d, - 0x22, - 0x38, - 0x32, - 0x51, - 0x4b, - 0x8a, - 0x6b, - 0xc1, - 0x9c, - 0xd2, - 0xc3, - 0x91, - 0xb5, - 0x43, - 0xe9, - 0xcc, - 0x73, - 0x49, - 0x07, - 0x7c, - 0x7d, - 0xe8, - 0xc8, - 0x5e, - 0x56, - 0x7a, - 0x22, - 0x80, - 0xcc, - 0xbd, - 0x21, - 0x1b, - 0x32, - 0x0d, - 0xd4, - 0x92, - 0x62, - 0x37, - 0xaf, - 0xf6, - 0x18, - 0xfa, - 0x9f, - 0x9f, - 0x12, - 0x6b, - 0x4b, - 0x4f, - 0x1d, - 0x5a, - 0xca, - 0x3c, - 0x7d, - 0x7d, - 0x38, - 0x66, - 0x00, - 0x90, - 0xc5, - 0x7e, - 0x44, - 0xf3, - 0xa8, - 0x65, - 0xc3, - 0x1b, - 0x41, - 0x1d, - 0xef, - 0xb3, - 0xd4, - 0x43, - 0xb5, - 0x02, - 0x1a, - 0x0d, - 0x08, - 0x44, - 0xa5, - 0x57, - 0xa7, - 0x65, - 0x90, - 0xdc, - 0xdc, - 0x1e, - 0xdf, - 0x45, - 0x5f, - 0x88, - 0xdc, - 0x7c, - 0xd6, - 0x09, - 0x57, - 0x01, - 0x33, - 0xfc, - 0x47, - 0xad, - 0xa0, - 0x49, - 0x0c, - 0x55, - 0xc4, - 0xfd, - 0xf1, - 0x68, - 0xd2, - 0x67, - 0x0c, - 0xf1, - 0x92, - 0xa4, - 0x9b, - 0x50, - 0x34, - 0x5d, - 0xea, - 0x58, - 0x5b, - 0x2a, - 0x58, - 0x44, - 0x53, - 0xdf, - 0x59, - 0xbc, - 0x14, - 0xe3, - 0x7f, - 0xd6, - 0x4a, - 0xd6, - 0x98, - 0x59, - 0x8c, - 0xbb, - 0xce, - 0xe6, - 0x86, - 0xdb, - 0x66, - 0xbd, - 0xeb, - 0x51, - 0xf1, - 0xce, - 0x80, - 0x0f, - 0xd9, - 0x83, - 0x86, - 0x17, - 0xed, - 0x78, - 0x3e, - 0x5d, - 0xac, - 0xd1, - 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0x1f, 0xc0, 0xe7, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xfd, 0xbf, 0x07, 0x00, + 0xfc, 0xff, 0xff, 0x2f, 0xe1, 0x1f, 0xe0, 0xe7, + 0xe3, 0xff, 0xff, 0x27, 0xe1, 0xdf, 0xe9, 0xfa, + 0x2a, 0x20, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xd5, 0x52, 0x06, 0x00, + 0xfd, 0x5f, 0x3f, 0x2e, 0xc0, 0x5f, 0xda, 0xeb, + 0xfe, 0xff, 0xff, 0x00, 0xe0, 0xdb, 0xcb, 0xff, + 0xff, 0xbf, 0x07, 0x00, 0xec, 0x0e, 0xfe, 0x00, + 0xe1, 0xd7, 0x83, 0xd6, 0xf7, 0xff, 0xff, 0x2e, + 0xe1, 0x9d, 0xab, 0xfe, 0x1d, 0xa0, 0x06, 0x00, + 0x13, 0xff, 0xff, 0x2a, 0xe1, 0x1f, 0xe0, 0xe7, + 0x05, 0x0f, 0xfe, 0x00, 0xe1, 0xcf, 0x43, 0xd7, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x5b, 0x8b, 0xfe, 0x6f, 0xfa, 0xff, 0x2e, + 0xe1, 0x1f, 0xe0, 0xe7, 0x4b, 0xa0, 0x06, 0x00, + 0xff, 0xf9, 0x78, 0x00, 0xc1, 0x9f, 0xdb, 0xeb, + 0xfd, 0xff, 0x38, 0x00, 0xc1, 0x9f, 0xdb, 0xeb, + 0xd7, 0xb8, 0x06, 0x00, 0xee, 0xff, 0xff, 0x00, + 0xe1, 0xda, 0x8b, 0xfe, 0xff, 0xef, 0xff, 0x3c, + 0xe1, 0x17, 0xe0, 0xca, 0xc8, 0x58, 0x06, 0x00, + 0x9b, 0x80, 0x38, 0x00, 0xc1, 0x1d, 0xc0, 0xf3, + 0xff, 0x81, 0x7f, 0x00, 0xe0, 0x0c, 0x0b, 0xf9, + 0xff, 0xbf, 0x07, 0x00, 0x15, 0x12, 0xfe, 0x00, + 0xe1, 0xd7, 0x83, 0xd6, 0xff, 0xff, 0xff, 0x00, + 0xe1, 0xcf, 0x43, 0xd7, 0x93, 0x5f, 0x06, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xc3, 0x21, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0x9b, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xfd, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0x93, 0x5f, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf, + 0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00, + 0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00, + 0x18, 0xa0, 0xba, 0x3a, 0x3f, 0x95, 0x1c, 0x69, + 0x42, 0xac, 0xed, 0xda, 0x47, 0xb4, 0xfd, 0xc8, + 0x19, 0xf5, 0x85, 0x69, 0x6a, 0x82, 0x3b, 0xce, + 0x6e, 0x7d, 0x01, 0x4e, 0x1e, 0x5b, 0x92, 0x6c, + 0xed, 0x73, 0x65, 0xe1, 0xdf, 0xfb, 0x8e, 0x8b, + 0x5d, 0x35, 0x65, 0x6f, 0xe8, 0x1a, 0xdf, 0xc7, + 0xeb, 0xd3, 0xd6, 0x0c, 0xee, 0xfe, 0x34, 0x1f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 }; /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c index fddf8eb4031..94e32a37438 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c @@ -63,6 +63,9 @@ CODE_GROUP (G3_DXE) RDATA_GROUP (G3_DXE) +/* Don't warn when checking header-defined ranges that may start at 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #define FILECODE PROC_IDS_FAMILY_0X16_KB_IDSF16KBALLSERVICE_FILECODE /** diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c index 1302396909d..eba8263e345 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c @@ -136,7 +136,7 @@ MemPGetMaxFreqSupported ( UINT16 MaxFreqSupported; UINT16 *SpeedArray; UINT8 DDR3Voltage; - UINT8 CurrentVoltage; + INT8 CurrentVoltage; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; diff --git a/src/vendorcode/amd/pi/00630F01/AMD.h b/src/vendorcode/amd/pi/00630F01/AMD.h index 68f7c328185..f70b1285080 100644 --- a/src/vendorcode/amd/pi/00630F01/AMD.h +++ b/src/vendorcode/amd/pi/00630F01/AMD.h @@ -149,6 +149,8 @@ typedef enum { AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle AMD_S3FINAL_RESTORE = 0x00035000, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h index aa68204e8d2..54abf80af07 100644 --- a/src/vendorcode/amd/pi/00660F01/AMD.h +++ b/src/vendorcode/amd/pi/00660F01/AMD.h @@ -126,6 +126,11 @@ typedef enum ACCESS_WIDTH { AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH; +/* When AMD rolled out CarrizoPI, they made a bad choice of removing + * an entry from the middle of the enumeration list. + */ +#define AMD_S3_SAVE_REMOVED + /// AGESA struct name typedef enum { // AGESA BASIC FUNCTIONS @@ -140,6 +145,10 @@ typedef enum { AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle +#if 0 + /* This was removed, shifting everything else up.*/ + AMD_S3_SAVE = 0x0002C000, +#endif AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 0e6f2afd1c2..790955a1d0d 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -77,8 +77,8 @@ $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1) diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c deleted file mode 100644 index c42df59bd41..00000000000 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ /dev/null @@ -1,242 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#include - -CONST UINT32 ImageSignature = IMAGE_SIGNATURE; -CONST UINT32 ModuleSignature = MODULE_SIGNATURE; -CONST CHAR8 ModuleIdentifier[8] = AGESA_ID; - -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdS3FinalRestore - **********************************************************************/ -AGESA_STATUS -AmdS3FinalRestore ( - IN OUT AMD_S3FINAL_PARAMS *S3FinalParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3FinalParams->StdHeader.Func = AMD_S3FINAL_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3FinalParams); -} - -/********************************************************************** - * Interface call: AmdInitRtb - **********************************************************************/ -AGESA_STATUS -AmdInitRtb ( - IN OUT AMD_RTB_PARAMS *AmdInitRtbParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdInitRtbParams->StdHeader.Func = AMD_INIT_RTB; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdInitRtbParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdApExeParams); -} - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - Event->StdHeader.Func = AMD_READ_EVENT_LOG; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(Event); -} diff --git a/src/vendorcode/amd/pi/00730F01/AMD.h b/src/vendorcode/amd/pi/00730F01/AMD.h index 1b6fdb26e8b..13fc29afebb 100644 --- a/src/vendorcode/amd/pi/00730F01/AMD.h +++ b/src/vendorcode/amd/pi/00730F01/AMD.h @@ -148,6 +148,9 @@ typedef enum { AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE = 0x00035000, /* reserved */ + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, diff --git a/src/vendorcode/amd/pi/Lib/debug_util.c b/src/vendorcode/amd/pi/Lib/debug_util.c new file mode 100644 index 00000000000..29d0841904a --- /dev/null +++ b/src/vendorcode/amd/pi/Lib/debug_util.c @@ -0,0 +1,24 @@ + +#include +#include +#include + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/pi/Lib/debug_util.h b/src/vendorcode/amd/pi/Lib/debug_util.h new file mode 100644 index 00000000000..a8d9a33c501 --- /dev/null +++ b/src/vendorcode/amd/pi/Lib/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4c8db6ab503..4e8787bed22 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -100,8 +100,8 @@ $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1) diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc b/src/vendorcode/eltan/Kconfig similarity index 76% rename from src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc rename to src/vendorcode/eltan/Kconfig index 63976c4b793..731dd2cea3a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc +++ b/src/vendorcode/eltan/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## Copyright (C) 2014-2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,5 +13,5 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +source src/vendorcode/eltan/security/mboot/Kconfig +source src/vendorcode/eltan/security/verified_boot/Kconfig diff --git a/src/vendorcode/eltan/Makefile.inc b/src/vendorcode/eltan/Makefile.inc new file mode 100644 index 00000000000..1f6a4065cfb --- /dev/null +++ b/src/vendorcode/eltan/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += security diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig new file mode 100644 index 00000000000..2af58080da0 --- /dev/null +++ b/src/vendorcode/eltan/security/Kconfig @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +source src/vendorcode/eltan/security/mboot/Kconfig +source src/vendorcode/eltan/security/verified_boot/Kconfig diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc new file mode 100644 index 00000000000..26b324ba586 --- /dev/null +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -0,0 +1,30 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += lib +subdirs-y += verified_boot +subdirs-y += mboot + +ifeq ($(CONFIG_MBOOT), y) +CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/mboot +CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/include +endif + +ifeq ($(CONFIG_VERIFIED_BOOT), y) +CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/verified_boot +endif + +ifeq ($(CONFIG_TPM2),y) +CPPFLAGS_common += -I$(src)/security/include +endif diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl index 51159f51243..5a091ddfaac 100644 --- a/src/vendorcode/google/chromeos/acpi/amac.asl +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -16,16 +16,17 @@ /* * The Realtek r8152 driver in the Linux kernel supports a MAC address - * passthru feature which can result in the dock ethernet port using the - * same MAC address that is assigned to the internal NIC. This is done - * by calling an ACPI method at \_SB.AMAC() which returns a formatted - * string (as a buffer) containing the MAC address for the dock to use. + * dock pass-through feature which can result in the dock ethernet port + * using the same MAC address that is assigned to the internal NIC. This + * is done by calling an ACPI method at \_SB.AMAC() which returns a + * formatted string (as a buffer) containing the MAC address for the + * dock to use. * * The Linux kernel implementation can be found at * drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read() * * For Chrome OS, the policy which controls where the dock MAC address - * comes from is written into RW_VPD property "dock_passthru": + * comes from is written into RW_VPD property "dock_passthrough": * * "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac" * "ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0" @@ -39,9 +40,10 @@ Scope (\_SB) /* Format expected by the Linux kernel r8152 driver */ Name (MACA, "_AUXMAC_#XXXXXXXXXXXX#") - /* Get "dock_passthru" value from RW_VPD */ - Local0 = \VPD.VPDF ("RW", "dock_passthru") + /* Get "dock_passthrough" value from RW_VPD */ + Local0 = \VPD.VPDF ("RW", "dock_passthrough") + Local1 = Zero Switch (ToString (Local0)) { Case ("ethernet_mac0") { @@ -55,7 +57,7 @@ Scope (\_SB) Local1 = \VPD.VPDF ("RO", "dock_mac") } } - If (!Local1) { + If (Local1 == Zero) { Return (Zero) } Printf ("MAC address returned from VPD: %o", Local1) diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl index 3b262f75a88..8f8b0e571d6 100644 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ b/src/vendorcode/google/chromeos/acpi/vpd.asl @@ -139,7 +139,7 @@ Device (VPD) Local1 <<= 7 Local1 |= Local2 & 0x7f } - If (!Local1) { + If (Local1 == Zero) { Return (Zero) } @@ -162,7 +162,7 @@ Device (VPD) */ Method (VPDS, 0, Serialized) { - Name (VPKV, Package () { Zero, Zero }) + Name (VPKV, Package () { "", "" }) /* Read the VPD type and ensure it is a string */ If (^VPRB () != ^VPES) { @@ -193,14 +193,14 @@ Device (VPD) /* End address of VPD region */ ^VEND = ^VPTR + DerefOf (Local0[1]) - If (!^VPTR || !^VEND) { + If (^VPTR == Zero || ^VEND == Zero) { Printf ("Unable to find VPD region") Return (Zero) } /* Verify VPD info header and save size */ Local0 = VVPD (^VPTR) - If (!Local0) { + If (Local0 == Zero) { Printf ("VPD region %o did not verify", Arg0) Return (Zero) } @@ -213,7 +213,7 @@ Device (VPD) While (Local1 != ToString (Arg1)) { Local2 = VPDS () Local1 = DerefOf (Local2[0]) - If (!Local1) { + If (Local1 == "") { Printf ("VPD KEY %o not found", Arg1) Return (Zero) } diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index 91a10cb9aad..f2cdbfd39c5 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -23,7 +23,7 @@ #include #include -#define C50_RESET_DELAY_MS 1000 +#define CR50_RESET_DELAY_MS 1000 void __weak mainboard_prepare_cr50_reset(void) {} @@ -31,12 +31,11 @@ void __weak mainboard_prepare_cr50_reset(void) {} * Check if the Cr50 TPM state requires a chip reset of the Cr50 device. * * Returns 0 if the Cr50 TPM state is good or if the TPM_MODE command is - * unsupported. Returns 1 if the Cr50 was reset. + * unsupported. Returns 1 if the Cr50 requires a reset. */ -static int cr50_reset_if_needed(uint16_t timeout_ms) +static int cr50_is_reset_needed(void) { int ret; - int cr50_must_reset = 0; uint8_t tpm_mode; ret = tlcl_cr50_get_tpm_mode(&tpm_mode); @@ -53,7 +52,7 @@ static int cr50_reset_if_needed(uint16_t timeout_ms) * Cr50 indicated a reboot is required to restore TPM * functionality. */ - cr50_must_reset = 1; + return 1; } else if (ret != TPM_SUCCESS) { /* TPM command failed, continue booting. */ printk(BIOS_ERR, @@ -61,7 +60,8 @@ static int cr50_reset_if_needed(uint16_t timeout_ms) return 0; } - /* If the TPM mode is not enabled-tentative, then the TPM mode is locked + /* + * If the TPM mode is not enabled-tentative, then the TPM mode is locked * and cannot be changed. Perform a Cr50 reset because vboot may need * to disable TPM as part of booting an untrusted OS. * @@ -72,30 +72,17 @@ static int cr50_reset_if_needed(uint16_t timeout_ms) printk(BIOS_NOTICE, "NOTICE: Unexpected Cr50 TPM mode (%d). " "A Cr50 reset is required.\n", tpm_mode); - cr50_must_reset = 1; + return 1; } /* If TPM state is okay, no reset needed. */ - if (!cr50_must_reset) - return 0; - - ret = tlcl_cr50_immediate_reset(timeout_ms); - - if (ret != TPM_SUCCESS) { - /* TPM command failed, continue booting. */ - printk(BIOS_ERR, - "ERROR: Attempt to reset CR50 failed: %x\n", - ret); - return 0; - } - - /* Cr50 is about to be reset, caller needs to prepare */ - return 1; + return 0; } static void enable_update(void *unused) { int ret; + int cr50_reset_reqd = 0; uint8_t num_restored_headers; /* Nothing to do on recovery mode. */ @@ -112,7 +99,7 @@ static void enable_update(void *unused) } /* Reboot in 1000 ms if necessary. */ - ret = tlcl_cr50_enable_update(C50_RESET_DELAY_MS, + ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS, &num_restored_headers); if (ret != TPM_SUCCESS) { @@ -134,9 +121,10 @@ static void enable_update(void *unused) */ /* - * If the Cr50 was not reset, continue booting. + * If the Cr50 doesn't requires a reset, continue booting. */ - if (!cr50_reset_if_needed(C50_RESET_DELAY_MS)) + cr50_reset_reqd = cr50_is_reset_needed(); + if (!cr50_reset_reqd) return; printk(BIOS_INFO, "Waiting for CR50 reset to enable TPM.\n"); @@ -153,6 +141,27 @@ static void enable_update(void *unused) /* clear current post code avoid chatty eventlog on subsequent boot*/ post_code(0); + /* + * Older Cr50 firmware doesn't support the timeout parameter for the + * immediate reset request, so the reset request must be sent after + * the mainboard specific code runs. + */ + if (cr50_reset_reqd) { + ret = tlcl_cr50_immediate_reset(CR50_RESET_DELAY_MS); + + if (ret != TPM_SUCCESS) { + /* + * Reset request failed due to TPM error, continue + * booting but the current boot will likely end up at + * the recovery screen. + */ + printk(BIOS_ERR, + "ERROR: Attempt to reset CR50 failed: %x\n", + ret); + return; + } + } + if (CONFIG(POWER_OFF_ON_CR50_UPDATE)) poweroff(); halt(); diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 1213dce4ede..a4d87addff8 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -18,8 +18,9 @@ #include #include #include -#include "hwilib.h" +#include +#include "hwilib.h" #define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 265cb6f4b37..e93704ec4a3 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -181,12 +181,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { } KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" - /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. - But most systems don't have any of those. But the config needs to be set - nevertheless. So set it to southbridge subsys/subvendor. */ - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) - ich9GetFlashSize(ctx) DSDTDefines = append(DSDTDefines, @@ -308,7 +302,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { #include #include #include -#include #include #include #include diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 4683d8dd10e..fa349b906f2 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -120,6 +120,7 @@ on the vendor firmware with just one module in channel 0, slot 0, and check the the EEPROM has. Under Linux, you can use these commands to see what is on SMBus: $ sudo modprobe i2c-dev + $ sudo modprobe i2c-i801 $ sudo i2cdetect -l i2c-0 i2c i915 gmbus ssc I2C adapter i2c-1 i2c i915 gmbus vga I2C adapter @@ -267,6 +268,12 @@ If several slots are soldered there are two ways to handle them: not forget to copy the data on all the array elements that need it. * If they use different data, use several files. +If memory initialization is not working, in particular write training (timB) +on DIMM's second rank fails, try enbling rank 1 mirroring, which can't be +detected by inteltool. It is described by SPD field "Address Mapping from Edge +Connector to DRAM", byte `63` (`0x3f`). Bit 0 describes Rank 1 Mapping, +0 = standard, 1 = mirrored; set it to 1. Bits 1-7 are reserved. + ### `board_info.txt` `board_info.txt` is a text file used in the board status page to list all diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 997259815bb..170d197af4d 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -1,7 +1,6 @@ package main type sandybridgemc struct { - variant string } func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { @@ -106,7 +105,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { PutPCIDev(addr, "Host bridge") /* FIXME:XX some configs are unsupported. */ - KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true + KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true KconfigBool["USE_NATIVE_RAMINIT"] = true KconfigBool["INTEL_INT15"] = true KconfigBool["HAVE_ACPI_TABLES"] = true @@ -126,10 +125,10 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { } func init() { - RegisterPCI(0x8086, 0x0100, sandybridgemc{variant: "SANDY"}) - RegisterPCI(0x8086, 0x0104, sandybridgemc{variant: "SANDY"}) - RegisterPCI(0x8086, 0x0150, sandybridgemc{variant: "IVY"}) - RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) + RegisterPCI(0x8086, 0x0100, sandybridgemc{}) + RegisterPCI(0x8086, 0x0104, sandybridgemc{}) + RegisterPCI(0x8086, 0x0150, sandybridgemc{}) + RegisterPCI(0x8086, 0x0154, sandybridgemc{}) for _, id := range []uint16{ 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1787eb14c02..79285207b01 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -81,7 +81,6 @@ TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool TOOLCPPFLAGS += -I$(top)/src/commonlib/include TOOLCPPFLAGS += -include $(top)/src/commonlib/include/commonlib/compiler.h -TOOLCPPFLAGS += -DNEED_VB2_SHA_LIBRARY TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include # UEFI header file support. It's not pretty, but that's what we currently diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 6ccc4f904ed..5cbe1f185a6 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "common.h" #include "cbfs_image.h" @@ -1844,7 +1845,7 @@ struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file, /* Is there enough space for another attribute? */ if ((uint8_t *)attr + ntohl(attr->len) + - sizeof(struct cbfs_file_attribute) >= + sizeof(struct cbfs_file_attribute) > (uint8_t *)file + ntohl(file->offset)) return NULL; diff --git a/util/cbfstool/cbfs_sections.c b/util/cbfstool/cbfs_sections.c index 285725760b6..088534adc97 100644 --- a/util/cbfstool/cbfs_sections.c +++ b/util/cbfstool/cbfs_sections.c @@ -14,6 +14,7 @@ */ #include "cbfs_sections.h" +#include "common.h" #include #include @@ -65,6 +66,10 @@ bool fmd_process_flag_cbfs(const struct flashmap_descriptor *node) return false; list_node = (struct descriptor_node *)malloc(sizeof(*list_node)); + if (!list_node) { + ERROR("Cannot allocate CBFS flag node!\n"); + return false; + } list_node->val = node; list_node->next = NULL; diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index ae1d2127fba..52fdc9b81f4 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5ee663821af..327027a565d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -50,17 +50,17 @@ THREADS=1 GMP_VERSION=6.1.2 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 -GCC_VERSION=8.2.0 +GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 -IASL_VERSION=20190108 +IASL_VERSION=20190509 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.14.0 +CMAKE_VERSION=3.14.2 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190509_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20190108_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190509_iasl.patch index 65322554996..49df22510fd 100644 --- a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190509_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20190108_/source/compiler/asloptions.c acpica-unix2-20190108/source/compiler/asloptions.c > acpica-unix2-20190108_iasl.patch ---- acpica-unix2-20190108_/source/compiler/asloptions.c -+++ acpica-unix2-20190108/source/compiler/asloptions.c +diff -Naur acpica-unix2-20190509_/source/compiler/asloptions.c acpica-unix2-20190509/source/compiler/asloptions.c > acpica-unix2-20190509_iasl.patch +--- acpica-unix2-20190509_/source/compiler/asloptions.c ++++ acpica-unix2-20190509/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch rename to util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_gnat.patch b/util/crossgcc/patches/gcc-8.3.0_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_gnat.patch rename to util/crossgcc/patches/gcc-8.3.0_gnat.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_libgcc.patch b/util/crossgcc/patches/gcc-8.3.0_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-8.3.0_libgcc.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_nds32_ite.patch b/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_nds32_ite.patch rename to util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch diff --git a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum deleted file mode 100644 index c5cfb4c3f41..00000000000 --- a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50d96dd38b89c69260ad209cf61035cda1fcdd67 tarballs/acpica-unix2-20190108.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum new file mode 100644 index 00000000000..2f53d714fbc --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum @@ -0,0 +1 @@ +aa4d4f8051800e84a5ed5b71635594aaca749e8d tarballs/acpica-unix2-20190509.tar.gz diff --git a/util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum deleted file mode 100644 index 997b8a03fdf..00000000000 --- a/util/crossgcc/sum/cmake-3.14.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -30e5423245d98ad98f6ee0c5f73c587846b99d6b tarballs/cmake-3.14.0.tar.gz diff --git a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum new file mode 100644 index 00000000000..6369ac38dbe --- /dev/null +++ b/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum @@ -0,0 +1 @@ +94ef8e36fa93edaf6f194e0ce0065ea769b3e57c tarballs/cmake-3.14.2.tar.gz diff --git a/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum deleted file mode 100644 index 1ef301a5d31..00000000000 --- a/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -19926bdb6c4b58891015929853d41aeff019d400 tarballs/gcc-8.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum new file mode 100644 index 00000000000..b46ef8c46f6 --- /dev/null +++ b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum @@ -0,0 +1 @@ +c27f4499dd263fe4fb01bcc5565917f3698583b2 tarballs/gcc-8.3.0.tar.xz diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index bc3d46cd529..2af45c30f22 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -22,7 +22,6 @@ #include #endif #include -#include #if defined __NetBSD__ || defined __OpenBSD__ diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a97f352bdf2..6c5e7845691 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -236,7 +236,7 @@ static int get_ifd_version_from_fcba(char *image, int size) int read_freq; const fcba_t *fcba = find_fcba(image, size); const fdbar_t *fdb = find_fd(image, size); - if (!fcba) /* a valid fcba indicates a valid fdb */ + if (!fcba || !fdb) exit(EXIT_FAILURE); chipset = guess_ich_chipset(fdb); diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index ed86b23e336..27bf46dde20 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -454,6 +454,7 @@ static inline void print_cap(const char *name, int state) #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE1 0xA1F8 /* IE Lewisburg #1 */ #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE2 0xA1F9 /* IE Lewisburg #2 */ #define PCI_DEVICE_ID_INTEL_LEWISBURG_IE3 0xA1FC /* IE Lewisburg #3 */ +#define PCI_DEVICE_ID_INTEL_CANNONLAKE 0xA360 /* Cannon Lake */ #define PCI_DEV_HAS_SUPPORTED_ME(x) ( \ ((x) == PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \ @@ -505,6 +506,7 @@ static inline void print_cap(const char *name, int state) ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE1) || \ ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE2) || \ ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \ + ((x) == PCI_DEVICE_ID_INTEL_CANNONLAKE) || \ 0) #define BOOTGUARD_DISABLED 0x400000000 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index c40a3bd22bb..ef2df3cd00d 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1529,6 +1529,323 @@ int print_intel_core_msrs(void) { 0x416, "MSR_MC5_ADDR" }, }; +/* + * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes + * Page 4668 + * + * The following two tables are for the Kaby Lake processors + * 06_9EH. + * + */ + + static const msr_entry_t model96ex_global_msrs[] = { + { 0x0000, "IA32_PLATFORM_ID"}, + { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"}, + { 0x00CE, "MSR_PLATFORM_INFO"}, + { 0x0198, "IA32_PERF_STATUS"}, + { 0x01A2, "MSR_TEMPERATURE_TARGET"}, + { 0x01AD, "MSR_TURBO_RATIO_LIMIT"}, + { 0x0284, "IA32_MC4_CTL2"}, + { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"}, + { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"}, + { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"}, + { 0x0395, "MSR_UNC_PERF_FIXED_CTR"}, + { 0x060A, "MSR_PKGC3_IRTL"}, + { 0x060B, "MSR_PKGC6_IRTL"}, + { 0x060D, "MSR_PKG_C2_RESIDENCY"}, + { 0x0610, "MSR_PKG_POWER_LIMIT"}, + { 0x0614, "MSR_PKG_POWER_INFO"}, + { 0x0620, "MSR_RING_RATIO_LIMIT"}, + { 0x0638, "MSR_PP0_POWER_LIMIT"}, + { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"}, + { 0x0652, "MSR_PKG_HDC_CONFIG"}, + { 0x065C, "MSR_PLATFORM_POWER_LIMIT"}, + { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"}, + { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"}, + { 0x0770, "IA32_PM_ENABLE"}, + { 0x0DB0, "IA32_PKG_HDC_CTL"}, + { 0x03B0, "MSR_UNC_ARB_PERFCTR0"}, + { 0x03B1, "MSR_UNC_ARB_PERFCTR1"}, + { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"}, + { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"}, + { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"}, + { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"}, + { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"}, + { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"}, + { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"}, + { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"}, + { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"}, + { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"}, + { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"}, + { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"}, + { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"}, + { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"}, + { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"}, + { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"}, + { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"}, + { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"}, + { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"}, + { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"}, + }; + + static const msr_entry_t model96ex_per_core_msrs[] = { + /* Per core MSRs for Sandy Bridge and above */ + { 0x0000, "IA32_P5_MC_ADDR"}, + { 0x0001, "IA32_P5_MC_TYPE"}, + { 0x0006, "IA32_MONITOR_FILTER_SIZE"}, + { 0x0010, "IA32_TIME_STAMP_COUNTER"}, + { 0x001B, "IA32_APIC_BASE"}, + { 0x0034, "MSR_SMI_COUNT"}, + { 0x003A, "IA32_FEATURE_CONTROL"}, + { 0x008B, "IA32_BIOS_SIGN_ID"}, + { 0x00C1, "IA32_PMC0" }, + { 0x00C2, "IA32_PMC1" }, + { 0x00C3, "IA32_PMC2" }, + { 0x00C4, "IA32_PMC3" }, + { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" }, + { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"}, + { 0x00E7, "IA32_MPERF"}, + { 0x00E8, "IA32_APERF"}, + { 0x00FE, "IA32_MTRRCAP"}, + { 0x013C, "MSR_FEATURE_CONFIG"}, + { 0x0174, "IA32_SYSENTER_CS"}, + { 0x0175, "IA32_SYSENTER_ESP"}, + { 0x0176, "IA32_SYSENTER_EIP"}, + { 0x0179, "IA32_MCG_CAP"}, + { 0x017A, "IA32_MCG_STATUS"}, + { 0x0186, "IA32_PERFEVTSEL0"}, + { 0x0187, "IA32_PERFEVTSEL1"}, + { 0x0188, "IA32_PERFEVTSEL2"}, + { 0x0189, "IA32_PERFEVTSEL3"}, + { 0x0199, "IA32_PERF_CTL"}, + { 0x019A, "IA32_CLOCK_MODULATION"}, + { 0x019B, "IA32_THERM_INTERRUPT"}, + { 0x019C, "IA32_THERM_STATUS"}, + { 0x01A0, "IA32_MISC_ENABLE"}, + { 0x01A4, "IA32_MISC_FEATURE_CONTROL"}, + { 0x01A6, "MSR_OFFCORE_RSP_0"}, + { 0x01A7, "MSR_OFFCORE_RSP_1"}, + { 0x01C8, "MSR_LBR_SELECT"}, + { 0x01C9, "MSR_LASTBRANCH_TOS"}, + { 0x01D9, "IA32_DEBUGCTL"}, + { 0x01DD, "MSR_LER_FROM_LIP"}, + { 0x01DE, "MSR_LER_TO_LIP"}, + { 0x01F2, "IA32_SMRR_PHYSBASE"}, + { 0x01F3, "IA32_SMRR_PHYSMASK"}, + { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, + { 0x01F5, "MSR_PRMRR_PHYS_MASK"}, + { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, + { 0x01FB, "MSR_PRMRR_VALID_CONFIG"}, + { 0x01FC, "MSR_POWER_CTL"}, + { 0x0200, "IA32_MTRR_PHYSBASE0"}, + { 0x0201, "IA32_MTRR_PHYSBASE0"}, + { 0x0202, "IA32_MTRR_PHYSBASE1"}, + { 0x0203, "IA32_MTRR_PHYSBASE1"}, + { 0x0204, "IA32_MTRR_PHYSBASE2"}, + { 0x0205, "IA32_MTRR_PHYSBASE2"}, + { 0x0206, "IA32_MTRR_PHYSBASE3"}, + { 0x0207, "IA32_MTRR_PHYSBASE3"}, + { 0x0208, "IA32_MTRR_PHYSBASE4"}, + { 0x0209, "IA32_MTRR_PHYSBASE4"}, + { 0x020A, "IA32_MTRR_PHYSBASE5"}, + { 0x020B, "IA32_MTRR_PHYSBASE5"}, + { 0x020C, "IA32_MTRR_PHYSBASE6"}, + { 0x020D, "IA32_MTRR_PHYSBASE6"}, + { 0x020E, "IA32_MTRR_PHYSBASE7"}, + { 0x020F, "IA32_MTRR_PHYSBASE7"}, + { 0x0210, "IA32_MTRR_PHYSBASE8"}, + { 0x0211, "IA32_MTRR_PHYSBASE8"}, + { 0x0212, "IA32_MTRR_PHYSBASE9"}, + { 0x0213, "IA32_MTRR_PHYSBASE9"}, + { 0x0250, "IA32_MTRR_FIX64K_00000"}, + { 0x0258, "IA32_MTRR_FIX16K_80000"}, + { 0x0259, "IA32_MTRR_FIX16K_A0000"}, + { 0x0268, "IA32_MTRR_FIX4K_C0000"}, + { 0x0269, "IA32_MTRR_FIX4K_C8000"}, + { 0x026A, "IA32_MTRR_FIX4K_D0000"}, + { 0x026B, "IA32_MTRR_FIX4K_D8000"}, + { 0x026C, "IA32_MTRR_FIX4K_E0000"}, + { 0x026D, "IA32_MTRR_FIX4K_E8000"}, + { 0x026E, "IA32_MTRR_FIX4K_F0000"}, + { 0x026F, "IA32_MTRR_FIX4K_F8000"}, + { 0x0277, "IA32_PAT"}, + { 0x0280, "IA32_MC0_CTL2"}, + { 0x0281, "IA32_MC1_CTL2"}, + { 0x0282, "IA32_MC2_CTL2"}, + { 0x0283, "IA32_MC3_CTL2"}, + { 0x02FF, "IA32_MTRR_DEF_TYPE"}, + { 0x0309, "IA32_FIXED_CTR0"}, + { 0x030A, "IA32_FIXED_CTR1"}, + { 0x030B, "IA32_FIXED_CTR2"}, + { 0x0345, "IA32_PERF_CAPABILITIES"}, + { 0x038D, "IA32_FIXED_CTR_CTRL"}, + { 0x038E, "IA32_PERF_GLOBAL_STATUS"}, + { 0x038F, "IA32_PERF_GLOBAL_CTRL"}, + { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"}, + { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"}, + { 0x03F1, "MSR_PEBS_ENABLE"}, + { 0x03F6, "MSR_PEBS_LD_LAT"}, + { 0x03F7, "MSR_PEBS_FRONTEND"}, + { 0x03FC, "MSR_CORE_C3_RESIDENCY"}, + { 0x03FD, "MSR_CORE_C6_RESIDENCY"}, + { 0x03FE, "MSR_CORE_C7_RESIDENCY"}, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + { 0x0403, "IA32_MC0_MISC" }, + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + { 0x0407, "IA32_MC1_MISC" }, + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + { 0x040c, "IA32_MC3_CTL" }, + { 0x040d, "IA32_MC3_STATUS" }, + { 0x040e, "IA32_MC3_ADDR" }, + { 0x0410, "IA32_MC4_CTL" }, + { 0x0411, "IA32_MC4_STATUS" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x048c, "IA32_VMX_EPT_VPID_ENUM" }, + { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" }, + { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" }, + { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" }, + { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" }, + { 0x04C1, "IA32_A_PMC0"}, + { 0x04C2, "IA32_A_PMC1"}, + { 0x04C3, "IA32_A_PMC2"}, + { 0x04C4, "IA32_A_PMC3"}, + { 0x0500, "IA32_SGX_SVN_STATUS"}, + { 0x0560, "IA32_RTIT_OUTPUT_BASE"}, + { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"}, + { 0x0570, "IA32_RTIT_CTL"}, + { 0x0571, "IA32_RTIT_STATUS"}, + { 0x0572, "IA32_RTIT_CR3_MATCH"}, + { 0x0580, "IA32_RTIT_ADDR0_A"}, + { 0x0581, "IA32_RTIT_ADDR0_B"}, + { 0x0582, "IA32_RTIT_ADDR1_A"}, + { 0x0583, "IA32_RTIT_ADDR1_B"}, + { 0x0600, "IA32_DS_AREA" }, + { 0x064E, "MSR_PPERF"}, + { 0x0653, "MSR_CORE_HDC_RESIDENCY"}, + { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, + { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, + { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, + { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, + { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, + { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, + { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, + { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, + { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, + { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, + { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, + { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, + { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, + { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, + { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, + { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, + { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, + { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06E0, "IA32_TSC_DEADLINE"}, + { 0x0771, "IA32_HWP_CAPABILITIES"}, + { 0x0773, "IA32_HWP_INTERRUPT"}, + { 0x0774, "IA32_HWP_REQUEST"}, + { 0x0777, "IA32_HWP_STATUS"}, + { 0x0D90, "IA32_BNDCFGS"}, + { 0x0DA0, "IA32_XSS"}, + { 0x0DB1, "IA32_PM_CTL1"}, + { 0x0DB2, "IA32_THREAD_STALL"}, + { 0x0DC0, "IA32_LBR_INFO_0"}, + { 0x0DC1, "IA32_LBR_INFO_1"}, + { 0x0DC2, "IA32_LBR_INFO_2"}, + { 0x0DC3, "IA32_LBR_INFO_3"}, + { 0x0DC4, "IA32_LBR_INFO_4"}, + { 0x0DC5, "IA32_LBR_INFO_5"}, + { 0x0DC6, "IA32_LBR_INFO_6"}, + { 0x0DC7, "IA32_LBR_INFO_7"}, + { 0x0DC8, "IA32_LBR_INFO_8"}, + { 0x0DC9, "IA32_LBR_INFO_9"}, + { 0x0DCA, "IA32_LBR_INFO_10"}, + { 0x0DCB, "IA32_LBR_INFO_11"}, + { 0x0DCC, "IA32_LBR_INFO_12"}, + { 0x0DCD, "IA32_LBR_INFO_13"}, + { 0x0DCE, "IA32_LBR_INFO_14"}, + { 0x0DCF, "IA32_LBR_INFO_15"}, + { 0x0DD0, "IA32_LBR_INFO_16"}, + { 0x0DD1, "IA32_LBR_INFO_17"}, + { 0x0DD2, "IA32_LBR_INFO_18"}, + { 0x0DD3, "IA32_LBR_INFO_19"}, + { 0x0DD4, "IA32_LBR_INFO_20"}, + { 0x0DD5, "IA32_LBR_INFO_21"}, + { 0x0DD6, "IA32_LBR_INFO_22"}, + { 0x0DD7, "IA32_LBR_INFO_23"}, + { 0x0DD8, "IA32_LBR_INFO_24"}, + { 0x0DD9, "IA32_LBR_INFO_25"}, + { 0x0DDA, "IA32_LBR_INFO_26"}, + { 0x0DDB, "IA32_LBR_INFO_27"}, + { 0x0DDC, "IA32_LBR_INFO_28"}, + { 0x0DDD, "IA32_LBR_INFO_29"}, + { 0x0DDE, "IA32_LBR_INFO_30"}, + { 0x0DDF, "IA32_LBR_INFO_31"}, + }; + typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -1547,6 +1864,7 @@ int print_intel_core_msrs(void) { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, + { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) }, { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */ diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 41f4df90c86..e48a2c51f5f 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1026,11 +1026,16 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) break; case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_C236: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 8b328a73831..3c0fedbfbf1 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -1774,13 +1774,18 @@ void print_gpio_groups(struct pci_dev *const sb) switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_C236: community_count = ARRAY_SIZE(sunrise_communities); communities = sunrise_communities; pcr_init(sb); break; - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index e89fd3cf22c..7e025107522 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -135,6 +135,8 @@ static const struct { "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, + "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -224,18 +226,26 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE, - "Sunrise Point-LP U Base" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM, - "Sunrise Point-LP U Premium" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM, - "Sunrise Point-LP Y Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE, + "Sunrise Point-LP Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL, + "Sunrise Point-LP U Base/Skylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL, + "Sunrise Point-LP Y Premium/Skylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL, + "Sunrise Point-LP U Premium/Skylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL, + "Sunrise Point-LP U Base/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL, + "Sunrise Point-LP Y Premium/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL, + "Sunrise Point-LP U Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE, - "Sunrise Point-LP U iHDCP 2.2 Base" }, + "Sunrise Point-LP U iHDCP 2.2 Base/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM, - "Sunrise Point-LP U iHDCP 2.2 Premium" }, + "Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM, - "Sunrise Point-LP Y iHDCP 2.2 Premium" }, + "Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 25b3a1504ad..483c93099e0 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -145,9 +145,13 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL 0x9d46 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL 0x9d53 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL 0x9d58 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b @@ -271,6 +275,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ /* Intel GPUs */ diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 8ce861127bc..16c1d8920c4 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -97,6 +97,11 @@ void ivybridge_dump_timings(const char *dump_spd_file) rankmap[channel] = read_mchbar32(0xc14 + 0x100 * channel) >> 24; } + if ((rankmap[0] == 0) && (rankmap[1] == 0)) { + fputs("Error: no memory channels found\n", stderr); + exit(1); + } + two_channels = rankmap[0] && rankmap[1]; mr0[0] = read_mchbar32(0x0004); @@ -172,49 +177,52 @@ void ivybridge_dump_timings(const char *dump_spd_file) printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], reg_4004_b30[1]); + + channel = (rankmap[0] != 0) ? 0 : 1; + if (two_channels && tFAW[0] != tFAW[1]) printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]); - print_time("tFAW", tFAW[0], tCK); + print_time("tFAW", tFAW[channel], tCK); if (two_channels && tWTR[0] != tWTR[1]) printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); - print_time("tWTR", tWTR[0], tCK); + print_time("tWTR", tWTR[channel], tCK); if (two_channels && tCKE[0] != tCKE[1]) printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); - print_time("tCKE", tCKE[0], tCK); + print_time("tCKE", tCKE[channel], tCK); if (two_channels && tRTP[0] != tRTP[1]) printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); - print_time("tRTP", tRTP[0], tCK); + print_time("tRTP", tRTP[channel], tCK); if (two_channels && tRRD[0] != tRRD[1]) printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]); - print_time("tRRD", tRRD[0], tCK); + print_time("tRRD", tRRD[channel], tCK); if (two_channels && tRAS[0] != tRAS[1]) printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]); - print_time("tRAS", tRAS[0], tCK); + print_time("tRAS", tRAS[channel], tCK); if (two_channels && tCWL[0] != tCWL[1]) printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]); - print_time("tCWL", tCWL[0], tCK); + print_time("tCWL", tCWL[channel], tCK); if (two_channels && tRP[0] != tRP[1]) printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]); - print_time("tRP", tRP[0], tCK); + print_time("tRP", tRP[channel], tCK); if (two_channels && tRCD[0] != tRCD[1]) printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]); - print_time("tRCD", tRCD[0], tCK); + print_time("tRCD", tRCD[channel], tCK); if (two_channels && tXPDLL[0] != tXPDLL[1]) printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]); - print_time("tXPDLL", tXPDLL[0], tCK); + print_time("tXPDLL", tXPDLL[channel], tCK); if (two_channels && tXP[0] != tXP[1]) printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]); - print_time("tXP", tXP[0], tCK); + print_time("tXP", tXP[channel], tCK); if (two_channels && tAONPD[0] != tAONPD[1]) printf("/* tAONPD mismatch: %d, %d */\n", tAONPD[0], tAONPD[1]); - print_time("tAONPD", tAONPD[0], tCK); + print_time("tAONPD", tAONPD[channel], tCK); reg = read_mchbar32(0x4298); if (reg != read_mchbar32(0x4698) && two_channels) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index f0c756221b4..222ac8afb00 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -225,6 +225,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 5b35dbdde91..33644ab9dbe 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -270,6 +270,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -395,6 +396,7 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: dmi_registers = skylake_dmi_registers; size = ARRAY_SIZE(skylake_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -504,6 +506,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index a296b19be40..c969620fa03 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -79,9 +79,13 @@ void pcr_init(struct pci_dev *const sb) switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 359180093d6..8da12d2826e 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -745,9 +745,13 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: @@ -832,6 +836,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) break; case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_C236: acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 2); if (!acpi) { printf("PMC device not found.\n"); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index ddcd8e3ed3a..70d7cbe3ed3 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -112,9 +112,13 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index cb38c555872..da5533deaa6 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -175,9 +175,13 @@ int print_bioscntl(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: @@ -309,9 +313,13 @@ int print_spibar(struct pci_dev *sb) { case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index f8e4bda0f4c..2dfa0023f20 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -788,7 +788,20 @@ static void parse_vbt(const struct fileobject *fo, } /* Duplicate fo as caller is owner and remalloc frees the object */ - *vbt = remalloc_fo(malloc_fo_sub(fo, 0), head->vbt_size); + struct fileobject *dupfo = malloc_fo_sub(fo, 0); + if (!dupfo) { + printerr("malloc failed\n"); + return; + } + + struct fileobject *newfo = remalloc_fo(dupfo, head->vbt_size); + if (!newfo) { + printerr("remalloc failed\n"); + free_fo(dupfo); + return; + } + + *vbt = newfo; } /* Option ROM checksum */ @@ -1028,8 +1041,10 @@ static int patch_vbios(struct fileobject *fo, if (old_vbt) { if (oh->vbt_offset + vbt_size(old_vbt) == fo->size) { /* Located at the end of file - reduce file size */ - if (fo->size < vbt_size(old_vbt)) + if (fo->size < vbt_size(old_vbt)) { + free_fo(old_vbt); return 1; + } fo = remalloc_fo(fo, fo->size - vbt_size(old_vbt)); if (!fo) { printerr("Failed to allocate memory\n"); diff --git a/util/kconfig/zconf.l b/util/kconfig/zconf.l index 0b45c19db9e..f2636d2955d 100644 --- a/util/kconfig/zconf.l +++ b/util/kconfig/zconf.l @@ -273,7 +273,8 @@ FILE *zconf_fopen(const char *name) if (!f && name != NULL && name[0] != '/') { env = getenv(SRCTREE); if (env) { - sprintf(fullname, "%s/%s", env, name); + snprintf(fullname, sizeof(fullname), + "%s/%s", env, name); f = fopen(fullname, "r"); } } diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped index 72e3a5fca28..4133f71dd26 100644 --- a/util/kconfig/zconf.lex.c_shipped +++ b/util/kconfig/zconf.lex.c_shipped @@ -2351,7 +2351,8 @@ FILE *zconf_fopen(const char *name) if (!f && name != NULL && name[0] != '/') { env = getenv(SRCTREE); if (env) { - sprintf(fullname, "%s/%s", env, name); + snprintf(fullname, sizeof(fullname), + "%s/%s", env, name); f = fopen(fullname, "r"); } } diff --git a/util/lint/check-style b/util/lint/check-style index 1ac51b4d1a7..2237ed62956 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -15,7 +15,7 @@ ################################################################## # SETTINGS # set path to clang-format binary -CLANG_FORMAT="/usr/bin/clang-format" +CLANG_FORMAT="$(command -v clang-format)" # remove any older patches from previous commits. Set to true or false. # DELETE_OLD_PATCHES=false diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 265b04cef26..1affdb7b337 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -6184,16 +6184,6 @@ sub process { } } -# check for #if defined CONFIG_ || defined CONFIG__MODULE - if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { - my $config = $1; - if (WARN("PREFER_IS_ENABLED", - "Prefer IS_ENABLED() to CONFIG_ || CONFIG__MODULE\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)"; - } - } - # check for case / default statements not preceded by break/fallthrough/switch if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { my $has_break = 0; diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 502a61878bc..47f04941f28 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -93,7 +93,7 @@ sub Main { check_used_symbols(); check_for_ifdef(); check_for_def(); - check_is_enabled(); + check_config_macro(); check_selected_symbols(); # Run checks based on the data that was found @@ -213,27 +213,6 @@ sub check_for_ifdef { } } } - - my @collected_is_enabled; - if ($dont_use_git_grep) { - @collected_is_enabled = - `grep -Irn -- "\\ 0xFFFFFFFF: if zi_oob_enabled == False or curr_phdr.p_filesz != 0: - print "ERROR: File xbl_sec VAddr or PAddr is too large for conversion." + print "ERROR: File xbl_sec VAddr or PAddr is too big for conversion." exit() new_phdr.p_vaddr = phys_virt_addr new_phdr.p_paddr = phys_virt_addr if os.path.getsize(elf_in_file_xbl_sec) > 0xFFFFFFFF: - print "ERROR: File xbl_sec Filesz is too large for conversion." + print "ERROR: File xbl_sec Filesz is too big for conversion." exit() new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz diff --git a/util/ipqheader/ipqheader.py b/util/qualcomm/ipqheader.py similarity index 100% rename from util/ipqheader/ipqheader.py rename to util/qualcomm/ipqheader.py diff --git a/util/ipqheader/mbn_tools.py b/util/qualcomm/mbn_tools.py similarity index 99% rename from util/ipqheader/mbn_tools.py rename to util/qualcomm/mbn_tools.py index c66afda7b55..12dc210cac8 100755 --- a/util/ipqheader/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -6,7 +6,7 @@ # GENERAL DESCRIPTION # Contains all MBN Utilities for image generation # -# Copyright (c) 2016, The Linux Foundation. All rights reserved. +# Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -41,6 +41,7 @@ # # when who what, where, why # -------- --- --------------------------------------------------------- +# 03/22/18 thiru Added support for extended MBNV5. # 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features. # 03/18/13 dhaval Add support for hashing elf segments with SHA256 and # sync up to mpss, adsp mbn-tools @@ -166,6 +167,7 @@ MI_PBT_BOOT_SEGMENT = 0x3 MI_PBT_L4BSP_SEGMENT = 0x4 MI_PBT_SWAPPED_SEGMENT = 0x5 +MI_PBT_XBL_SEC_SEGMENT = 0x5 MI_PBT_SWAP_POOL_SEGMENT = 0x6 MI_PBT_PHDR_SEGMENT = 0x7 @@ -902,6 +904,7 @@ def image_header(env, gen_dict, code_file_name, output_file_name, secure_type, + is_ext_mbn_v5, header_format = 'reg', requires_preamble = False, preamble_file_name = None, @@ -989,6 +992,12 @@ def image_header(env, gen_dict, boot_header.cert_chain_ptr = image_dest + code_size + signature_size boot_header.cert_chain_size = cert_chain_size + if is_ext_mbn_v5 == True: + # If platform image integrity check is enabled + boot_header.flash_parti_ver = 5 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: boot_header = image_preamble(gen_dict, preamble_file_name, boot_header, num_of_pages) @@ -2051,7 +2060,7 @@ def get_hash_address(elf_file_name): curr_phdr = phdr_table[i] if curr_phdr.p_paddr > last_paddr: # Skip the demand paging segment as it would be outside the physical RAM location - if MI_PBT_SEGMENT_TYPE_VALUE(curr_phdr.p_flags) != MI_PBT_SWAPPED_SEGMENT: + if MI_PBT_SEGMENT_TYPE_VALUE(curr_phdr.p_flags) != MI_PBT_XBL_SEC_SEGMENT: last_paddr = curr_phdr.p_paddr; last_paddr_segment = i; diff --git a/util/ipqheader/mbncat.py b/util/qualcomm/mbncat.py similarity index 100% rename from util/ipqheader/mbncat.py rename to util/qualcomm/mbncat.py diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py new file mode 100755 index 00000000000..51018361e15 --- /dev/null +++ b/util/qualcomm/qgpt.py @@ -0,0 +1,234 @@ +#!/usr/bin/python +#============================================================================ +# +#/** @file qgpt.py +# +# GENERAL DESCRIPTION +# Generates QCom GPT header for wrapping Bootblock +# +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# * Neither the name of The Linux Foundation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#**/ +# + +import os +import math +import random +import re +import struct +import sys +import tempfile + +from binascii import crc32 +from optparse import OptionParser +from types import * + + +def UpdateMBR(options, GPTBlobBuffer): + i = 0x1BE + GPTBlobBuffer[i + 0] = 0x00 # not bootable + GPTBlobBuffer[i + 1] = 0x00 # head + GPTBlobBuffer[i + 2] = 0x01 # sector + GPTBlobBuffer[i + 3] = 0x00 # cylinder + GPTBlobBuffer[i + 4] = 0xEE # type + GPTBlobBuffer[i + 5] = 0xFF # head + GPTBlobBuffer[i + 6] = 0xFF # sector + GPTBlobBuffer[i + 7] = 0xFF # cylinder + GPTBlobBuffer[i + 8:i + 8 + 4] = [0x01, 0x00, 0x00, 0x00] + + GPTBlobBuffer[i + 12:i + 16] = [0x00, 0x0f, 0x00, 0x00] + + # magic byte for MBR partitioning - always at this location regardless of + # options.sector + GPTBlobBuffer[510:512] = [0x55, 0xAA] + return i + + +def UpdatePartitionEntry(options, GPTBlobBuffer): + + i = 2 * options.sector_size + # GUID of Boot Block + GPTBlobBuffer[i:i + 16] = [0x2c, 0xba, 0xa0, 0xde, 0xdd, 0xcb, 0x05, 0x48, + 0xb4, 0xf9, 0xf4, 0x28, 0x25, 0x1c, 0x3e, 0x98] + i += 16 + + #This is to set Unique Partition GUID. Below Hex Value is : 00ChezaBootblock00 + GPTBlobBuffer[i:i + 16] = [0x00, 0x43, 0x68, 0x65, 0x7a, 0x61, 0x42, 0x6f, + 0x6f, 0x74, 0x62, 0x6c, 0x6f, 0x63, 0x6b, 0x00] + i += 16 + + # LBA of BootBlock Start Content + GPTBlobBuffer[i:i + 8] = [0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # End LBA of BootBlock Content + GPTBlobBuffer[i] = options.end_lba & 0xFF + GPTBlobBuffer[i+1] = (options.end_lba>>8) & 0xFF + GPTBlobBuffer[i+2] = (options.end_lba>>16) & 0xFF + GPTBlobBuffer[i+3] = (options.end_lba>>24) & 0xFF + GPTBlobBuffer[i+4] = (options.end_lba>>32) & 0xFF + GPTBlobBuffer[i+5] = (options.end_lba>>40) & 0xFF + GPTBlobBuffer[i+6] = (options.end_lba>>48) & 0xFF + GPTBlobBuffer[i+7] = (options.end_lba>>56) & 0xFF + i += 8 + + # Attributes + GPTBlobBuffer[i:i + 8] = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Label + GPTBlobBuffer[i:i + 17] = [0x62, 0x00, 0x6f, 0x00, 0x6f, 0x00, 0x74, 0x00, + 0x62, 0x00, 0x6c, 0x00, 0x6f, 0x00, 0x63, 0x00, 0x6b] + + return i + +def UpdateGPTHeader(options, GPTBlobBuffer): + + i = options.sector_size + # Signature and Revision and HeaderSize i.e. "EFI PART" and 00 00 01 00 + # and 5C 00 00 00 + GPTBlobBuffer[i:i + 16] = [0x45, 0x46, 0x49, 0x20, 0x50, 0x41, 0x52, 0x54, + 0x00, 0x00, 0x01, 0x00, 0x5C, 0x00, 0x00, 0x00] + i += 16 + + # CRC is zeroed out till calculated later + GPTBlobBuffer[i:i + 4] = [0x00, 0x00, 0x00, 0x00] + i += 4 + + # Reserved, set to 0 + GPTBlobBuffer[i:i + 4] = [0x00, 0x00, 0x00, 0x00] + i += 4 + + # Current LBA + GPTBlobBuffer[i:i + 8] = [0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Backup LBA, No Backup Gpt Used + GPTBlobBuffer[i:i + 8] = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # First Usuable LBA (qc_sec + bootblock location) + GPTBlobBuffer[i:i + 8] = [0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Last Usuable LBA (qc_sec + bootblock end location) + GPTBlobBuffer[i] = options.end_lba & 0xFF + GPTBlobBuffer[i+1] = (options.end_lba>>8) & 0xFF + GPTBlobBuffer[i+2] = (options.end_lba>>16) & 0xFF + GPTBlobBuffer[i+3] = (options.end_lba>>24) & 0xFF + GPTBlobBuffer[i+4] = (options.end_lba>>32) & 0xFF + GPTBlobBuffer[i+5] = (options.end_lba>>40) & 0xFF + GPTBlobBuffer[i+6] = (options.end_lba>>48) & 0xFF + GPTBlobBuffer[i+7] = (options.end_lba>>56) & 0xFF + i += 8 + + # GUID + GPTBlobBuffer[i:i + 16] = [0x32,0x1B,0x10,0x98,0xE2,0xBB,0xF2,0x4B, + 0xA0,0x6E,0x2B,0xB3,0x3D,0x00,0x0C,0x20] + i += 16 + + # Partition Table Entry LBA + GPTBlobBuffer[i:i + 8] = [0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Number of Partition Entries + GPTBlobBuffer[i:i + 4] = [0x01, 0x00, 0x00, 0x00] + i += 4 + + # Size of One Partition Entry + GPTBlobBuffer[i:i + 4] = [0x80, 0x00, 0x00, 0x00] + i += 4 + + # CRC of Partition Entry + + PartEntry = GPTBlobBuffer[options.sector_size*2:options.sector_size*2 + 128] + CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in PartEntry)) + + GPTBlobBuffer[i] = CalcEntryCRC & 0xFF + GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF + GPTBlobBuffer[i+2] = (CalcEntryCRC>>16) & 0xFF + GPTBlobBuffer[i+3] = (CalcEntryCRC>>24) & 0xFF + i += 4 + + # CRC of Partition Table Header + GPTHeader = GPTBlobBuffer[options.sector_size:options.sector_size + 92] + CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in GPTHeader)) + i = options.sector_size + 16 + + GPTBlobBuffer[i] = CalcEntryCRC & 0xFF + GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF + GPTBlobBuffer[i+2] = (CalcEntryCRC>>16) & 0xFF + GPTBlobBuffer[i+3] = (CalcEntryCRC>>24) & 0xFF + + return i + + +if __name__ == '__main__': + usage = 'usage: %prog [OPTIONS] INFILE OUTFILE\n\n' + \ + 'Packages IMAGE in a GPT format.' + parser = OptionParser(usage) + parser.add_option('-s', type="int", dest='sector_size', default=4096, + help='Sector size in bytes [Default:4096(4KB)]', + metavar='SIZE') + + (options, args) = parser.parse_args() + if len(args) != 2: + print("Invalid arguments! Exiting...\n") + parser.print_help() + sys.exit(1) + + if options.sector_size != 4096 and options.sector_size != 512: + print("Invalid Sector Size") + sys.exit(1) + + options.inputfile = args[0] + options.outputfile = args[1] + + with open(options.inputfile, 'r+') as fin: + bb_buffer = fin.read() + + # Round up to next sector if bootblock size not evenly divisible + options.end_lba = ((len(bb_buffer) + options.sector_size - 1) / + options.sector_size) + # Add 3 sectors for MBR, GPT header and GPT partition entry + options.end_lba += 3 + # Subtract one because this is last usable LBA, not amount of LBAs + options.end_lba -= 1 + + GPTBlobBuffer = [0] * (options.sector_size*3) #Size of MBR+GPT+PART_ENTRY + + UpdateMBR(options, GPTBlobBuffer) + + UpdatePartitionEntry(options, GPTBlobBuffer) + + UpdateGPTHeader(options, GPTBlobBuffer) + + with open(options.outputfile, 'wb') as fout: + for b in GPTBlobBuffer: + fout.write(struct.pack("B", b)) + fout.write(bb_buffer) diff --git a/util/qualcomm/scripts/cmm/clear_bss.cmm b/util/qualcomm/scripts/cmm/clear_bss.cmm new file mode 100755 index 00000000000..16eaac71d8c --- /dev/null +++ b/util/qualcomm/scripts/cmm/clear_bss.cmm @@ -0,0 +1,16 @@ +d.a 0x80000000 mov x0,#0x8c +d.a 0x80000004 lsl x0, x0, #0x14 +d.a 0x80000008 mov x1,#0x18 +d.a 0x8000000c lsl x1,x1, #0x10 +d.a 0x80000010 mov x2,#0x0 +d.a 0x80000014 mov x3,#0x80 +d.a 0x80000018 lsl x3, x3, #0x18 +d.a 0x8000001c add x3, x3, #0x14 +d.a 0x80000020 str x2,[x0] +d.a 0x80000024 sub x1, x1, #0x8 +d.a 0x80000028 add x0, x0, #0x8 +d.a 0x8000002c cmp x1,0x0 +d.a 0x80000030 b.ne 0x20 +d.a 0x80000034 b 0x34 +r.s pc 0x80000000 +go diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm new file mode 100644 index 00000000000..166d2aa3085 --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_405.cmm @@ -0,0 +1,165 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2018, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_405.cmm +; +; Description: +; Debug coreboot 405 front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +GLOBAL &debug + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="Qcs405Pkg" + + // These settings come from .../src/soc/qualcomm/qcs405/include/soc/memlayout.ld + &BBEntryAddr=0x8c2f000 + &VEREntryAddr=0x8C00000 + &ROMEntryAddr=0x8C00000 + &QCLEntryAddr=0x1485AC00 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xf1104800 + &KernelEntryAddr=0x90080000 + + &PreRamConsoleAddr=0x8C4F400 + &VBoot2Work=0x8C47000 + &Stack=0x8C4B000 + &Ttb=0x8C39000 + &Timestamp=0x8C4F000 + &PreRamCbfsCache=0x8C57400 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + b.sel PROGRAM onchip + ;sys.u + + b.d /all + + ;go &BBEntryAddr + ;wait !run() + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + ;winclear + ;b.d /all + + if FILE.EXIST("C:\TEMP\WIN.CMM") + do C:\TEMP\WIN.CMM + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + PRINT "pbl32_to_bootblock64 jump" + do pbl32_to_bootblock64_jump.cmm + do clear_bss.cmm + WAIT 5s + b + + // Make parsing simple, upper-case parameters + &Imagename=STRING.UPR("&Imagename") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &Imagename=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index bdb0097cd3b..5959ee11e6a 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -104,6 +104,10 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName if &BBStage ( + IF "&debug"=="" + ( + d.load.binary build/coreboot.rom 0xA0000000 + ) &imgpath="build\cbfs\fallback\bootblock.elf" if (&RAMLoad) d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath @@ -114,9 +118,17 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName ;b.s run_romstage /o ;d.set &PreRamConsoleAddr++0x8000 0 d.dump &PreRamConsoleAddr /spotlight - print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" - print %String "Press enter to go to next stage" - enter + IF (STR.CP("&debug","DEBUG")) + ( + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + ELSE + ( + go + enddo + ) ) go &VEREntryAddr diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm new file mode 100644 index 00000000000..bebf85d1c4a --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm @@ -0,0 +1,15 @@ +PER.Set.simple SPR:0x36100 %Long 00c5183C +D.S AZSD:0x8600034 %LE %Long 0x8600000 +D.S AZSD:0x8600000 %LE %Long 0x1400000 +d.a 0x8600004 ldr r0,0x8600034 +d.a 0x8600008 mcr p15,0x0,r0,c12,c0,1 +d.a 0x860000c dsb +d.a 0x8600010 isb +d.a 0x8600014 mrc p15,0x0,r1,c12,c0,2 +d.a 0x8600018 orr r1,r1,0x3 +d.a 0x860001c mcr p15,0x0,r1,c12,c0,2 +d.a 0x8600020 isb +d.a 0x8600024 wfi +r.s pc 0x8600004 +go +b diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 4cb2aadcc92..2a158e5fe09 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -1990,7 +1989,7 @@ static struct occurrence *new_occurrence(struct compile_state *state) (last->line == line) && (last->function == function) && ((last->filename == filename) || - (strcmp(last->filename, filename) == 0))) + (filename != NULL && strcmp(last->filename, filename) == 0))) { get_occurrence(last); return last; @@ -6229,6 +6228,8 @@ static size_t field_offset(struct compile_state *state, size += size_of(state, member->left); member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); size += needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_UNION) { @@ -6351,10 +6352,12 @@ static size_t index_offset(struct compile_state *state, i++; member = member->right; } - size += needed_padding(state, member, size); + if (member == NULL) + internal_error(state, 0, "Member is NULL"); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } + size += needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_JOIN) { ulong_t i; @@ -6403,6 +6406,8 @@ static size_t index_reg_offset(struct compile_state *state, i++; member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } @@ -6641,6 +6646,8 @@ static struct type *reg_type( offset += size; member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); offset += reg_needed_padding(state, member, offset); member = reg_type(state, member, reg_offset - offset); break; @@ -10783,6 +10790,15 @@ static struct triple *string_constant(struct compile_state *state) } while(str < end); type->elements = ptr - buf; } while(peek(state) == TOK_LIT_STRING); + + /* buf contains the allocated buffer for the string constant. However, + if buf is NULL, then the string constant is empty, but we still + need to allocate one byte for the null character. */ + if (buf == NULL) { + buf = xmalloc(1, "string_constant"); + ptr = buf; + } + *ptr = '\0'; type->elements += 1; def = triple(state, OP_BLOBCONST, type, 0, 0); @@ -11237,6 +11253,7 @@ static struct triple *relational_expr(struct compile_state *state) arg_type = arithmetic_result(state, left, right); sign = is_signed(arg_type); + xfree(arg_type); op = -1; switch(tok) { case TOK_LESS: op = sign? OP_SLESS : OP_ULESS; break; @@ -12584,7 +12601,9 @@ static struct type *struct_declarator( } type = new_type(TYPE_BITFIELD, type, 0); type->elements = value->u.cval; - } + } else + type = clone_type(0, type); + return type; } @@ -12639,7 +12658,6 @@ static struct type *struct_or_union_specifier( done = 0; eat(state, TOK_COMMA); } - type = clone_type(0, type); type->field_ident = fident; if (*next) { *next = new_type(type_join, *next, type); @@ -14112,9 +14130,9 @@ static void compute_closure_variables(struct compile_state *state, struct block *block; struct triple *old_result, *first, *ins; size_t count, idx; - unsigned long used_indicies; + uint64_t used_indices; int i, max_index; -#define MAX_INDICIES (sizeof(used_indicies)*CHAR_BIT) +#define MAX_INDICES (sizeof(used_indices)*CHAR_BIT) #define ID_BITS(X) ((X) & (TRIPLE_FLAG_LOCAL -1)) struct { unsigned id; @@ -14184,7 +14202,7 @@ static void compute_closure_variables(struct compile_state *state, * * To gurantee that stability I lookup the variables * to see where they have been used before and - * I build my final list with the assigned indicies. + * I build my final list with the assigned indices. */ vars = 0; if (enclose_triple(old_result)) { @@ -14203,8 +14221,8 @@ static void compute_closure_variables(struct compile_state *state, ordered_triple_set(&vars, set->member); } - /* Lookup the current indicies of the live varialbe */ - used_indicies = 0; + /* Lookup the current indices of the live varialbe */ + used_indices = 0; max_index = -1; for(set = vars; set ; set = set->next) { struct triple *ins; @@ -14215,14 +14233,14 @@ static void compute_closure_variables(struct compile_state *state, if (index < 0) { continue; } - if (index >= MAX_INDICIES) { + if (index >= MAX_INDICES) { internal_error(state, ins, "index unexpectedly large"); } - if (used_indicies & (1 << index)) { + if (used_indices & ((uint64_t)1 << index)) { internal_error(state, ins, "index previously used?"); } - /* Remember which indicies have been used */ - used_indicies |= (1 << index); + /* Remember which indices have been used */ + used_indices |= ((uint64_t)1 << index); if (index > max_index) { max_index = index; } @@ -14240,31 +14258,31 @@ static void compute_closure_variables(struct compile_state *state, continue; } /* Find the lowest unused index value */ - for(index = 0; index < MAX_INDICIES; index++) { - if (!(used_indicies & ((uint64_t)1 << index))) { + for(index = 0; index < MAX_INDICES; index++) { + if (!(used_indices & ((uint64_t)1 << index))) { break; } } - if (index == MAX_INDICIES) { - internal_error(state, ins, "no free indicies?"); + if (index == MAX_INDICES) { + internal_error(state, ins, "no free indices?"); } info[ID_BITS(ins->id)].index = index; - /* Remember which indicies have been used */ - used_indicies |= (1 << index); + /* Remember which indices have been used */ + used_indices |= ((uint64_t)1 << index); if (index > max_index) { max_index = index; } } /* Build the return list of variables with positions matching - * their indicies. + * their indices. */ *enclose = 0; last_var = enclose; for(i = 0; i <= max_index; i++) { struct triple *var; var = 0; - if (used_indicies & (1 << i)) { + if (used_indices & ((uint64_t)1 << i)) { for(set = vars; set; set = set->next) { int index; index = info[ID_BITS(set->member->id)].index; @@ -20926,7 +20944,8 @@ static void scc_visit_phi(struct compile_state *state, struct scc_state *scc, } } /* meet(const, const) = const or lattice low */ - else if (!constants_equal(state, lnode->val, tmp->val)) { + else if (lnode->val != 0 && + !constants_equal(state, lnode->val, tmp->val)) { lnode->val = 0; } @@ -22151,6 +22170,7 @@ static unsigned arch_regcm_normalize(struct compile_state *state, unsigned regcm } if (class > LAST_REGC) { result &= ~mask; + continue; } for(class2 = 0; class2 <= LAST_REGC; class2++) { if ((regcm_bound[class2].first >= regcm_bound[class].first) && diff --git a/util/romcc/tests/linux_test5.c b/util/romcc/tests/linux_test5.c index cf0df46d548..e94d5d71e72 100644 --- a/util/romcc/tests/linux_test5.c +++ b/util/romcc/tests/linux_test5.c @@ -156,7 +156,7 @@ static const struct mem_param *spd_set_memclk(void) unsigned device; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -224,7 +224,7 @@ static const struct mem_param *spd_set_memclk(void) continue; } debug('D'); - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); if (value < 0) continue; debug('E'); @@ -310,7 +310,7 @@ static const struct mem_param *spd_set_memclk(void) } /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); /* All is good if the selected clock speed * is what I need or slower. diff --git a/util/romcc/tests/raminit_test6.c b/util/romcc/tests/raminit_test6.c index e99e355e33d..8048dcee896 100644 --- a/util/romcc/tests/raminit_test6.c +++ b/util/romcc/tests/raminit_test6.c @@ -1621,7 +1621,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) unsigned min_cycle_time, min_latency; int i; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [0 ] = 0x50, [1 ] = 0x60, @@ -1651,7 +1651,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value < 0) { continue; } @@ -1701,7 +1701,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value <= min_cycle_time) { diff --git a/util/romcc/tests/raminit_test7.c b/util/romcc/tests/raminit_test7.c index 184e912ffff..c768e86a3cf 100644 --- a/util/romcc/tests/raminit_test7.c +++ b/util/romcc/tests/raminit_test7.c @@ -1626,7 +1626,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) unsigned min_cycle_time, min_latency; int i; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [0 ] = 0x50, [1 ] = 0x60, @@ -1656,7 +1656,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value < 0) { continue; } @@ -1706,7 +1706,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value <= min_cycle_time) { diff --git a/util/romcc/tests/simple_test46.c b/util/romcc/tests/simple_test46.c index 0b831254a11..2d3764e4582 100644 --- a/util/romcc/tests/simple_test46.c +++ b/util/romcc/tests/simple_test46.c @@ -1,6 +1,6 @@ static void spd_set_memclk(void) { - static const int indicies[] = { 26, 23, 9 }; + static const int indices[] = { 26, 23, 9 }; int new_cycle_time, new_latency; int index; unsigned min_cycle_time, min_latency; @@ -15,7 +15,7 @@ static void spd_set_memclk(void) for(index = 0; index < 3; index++) { unsigned long loops; unsigned long address; - address = indicies[index]; + address = indices[index]; loops = 1000000; do { } while(--loops); diff --git a/util/romcc/tests/simple_test54.c b/util/romcc/tests/simple_test54.c index 37dce795c5d..b7dee66bcfe 100644 --- a/util/romcc/tests/simple_test54.c +++ b/util/romcc/tests/simple_test54.c @@ -569,7 +569,7 @@ static const struct mem_param *spd_set_memclk(void) unsigned device; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -637,7 +637,7 @@ static const struct mem_param *spd_set_memclk(void) continue; } debug('D'); - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); if (value < 0) continue; debug('E'); @@ -723,7 +723,7 @@ static const struct mem_param *spd_set_memclk(void) } /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); /* All is good if the selected clock speed * is what I need or slower. diff --git a/util/romcc/tests/simple_test87.c b/util/romcc/tests/simple_test87.c new file mode 100644 index 00000000000..6a1148c46aa --- /dev/null +++ b/util/romcc/tests/simple_test87.c @@ -0,0 +1,4 @@ +static void main(void) +{ + char *x = ""; +} diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index b3dff41e585..14ffeff9a2b 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -168,7 +168,7 @@ extern FILE *yyin, *yyout; do \ { \ /* Undo effects of setting up yytext. */ \ - int yyless_macro_arg = (n); \ + yy_size_t yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ @@ -358,8 +358,8 @@ static void yynoreturn yy_fatal_error (yyconst char* msg ); *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 37 -#define YY_END_OF_BUFFER 38 +#define YY_NUM_RULES 38 +#define YY_END_OF_BUFFER 39 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -367,24 +367,25 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[145] = +static yyconst flex_int16_t yy_accept[160] = { 0, - 0, 0, 38, 36, 1, 3, 36, 36, 36, 31, - 31, 29, 32, 36, 32, 32, 32, 36, 36, 36, - 36, 36, 36, 36, 36, 36, 36, 36, 1, 3, - 36, 0, 36, 36, 0, 2, 31, 32, 36, 36, - 36, 36, 32, 36, 36, 36, 36, 36, 36, 36, - 24, 36, 36, 36, 36, 7, 36, 36, 36, 36, - 36, 36, 35, 35, 36, 0, 30, 36, 36, 16, - 36, 36, 23, 28, 36, 36, 13, 36, 36, 22, - 36, 36, 8, 10, 12, 36, 20, 36, 21, 36, - 0, 33, 4, 36, 36, 36, 36, 36, 36, 36, - - 36, 19, 36, 36, 34, 34, 36, 36, 36, 36, - 36, 36, 36, 14, 36, 36, 36, 5, 17, 36, - 9, 36, 11, 36, 36, 36, 18, 26, 36, 36, - 36, 36, 36, 6, 36, 36, 36, 36, 36, 25, - 36, 15, 27, 0 + 0, 0, 39, 37, 1, 3, 37, 37, 37, 32, + 32, 30, 33, 37, 33, 33, 33, 37, 37, 37, + 37, 37, 37, 37, 37, 37, 37, 37, 1, 3, + 37, 0, 37, 37, 0, 2, 32, 33, 37, 37, + 37, 37, 33, 37, 37, 37, 37, 37, 37, 37, + 24, 37, 37, 37, 37, 7, 37, 37, 37, 37, + 37, 37, 37, 36, 36, 37, 0, 31, 37, 37, + 16, 37, 37, 23, 28, 37, 37, 13, 37, 37, + 22, 37, 37, 8, 10, 12, 37, 37, 20, 37, + 21, 37, 0, 34, 4, 37, 37, 37, 37, 37, + + 37, 37, 37, 19, 37, 37, 37, 35, 35, 37, + 37, 37, 37, 37, 37, 37, 14, 37, 37, 37, + 37, 5, 17, 37, 9, 37, 11, 37, 37, 37, + 37, 18, 26, 37, 37, 37, 37, 37, 37, 6, + 37, 37, 37, 37, 37, 37, 37, 25, 37, 37, + 15, 37, 27, 37, 37, 37, 37, 29, 0 } ; static yyconst YY_CHAR yy_ec[256] = @@ -427,110 +428,114 @@ static yyconst YY_CHAR yy_meta[39] = 1, 1, 1, 1, 1, 1, 1, 1 } ; -static yyconst flex_uint16_t yy_base[152] = +static yyconst flex_uint16_t yy_base[167] = { 0, - 0, 0, 212, 0, 209, 213, 207, 37, 41, 38, - 172, 0, 44, 194, 54, 78, 60, 186, 181, 45, - 188, 177, 42, 47, 182, 41, 169, 0, 199, 213, - 77, 195, 87, 91, 196, 213, 0, 88, 104, 183, - 172, 161, 93, 168, 163, 173, 164, 171, 171, 165, - 171, 156, 156, 160, 162, 0, 158, 152, 158, 155, - 161, 160, 0, 213, 101, 172, 0, 165, 145, 158, - 148, 155, 0, 0, 150, 150, 0, 148, 138, 0, - 142, 137, 0, 0, 0, 140, 0, 131, 0, 158, - 157, 0, 0, 142, 141, 134, 126, 136, 124, 130, - - 135, 0, 120, 114, 0, 213, 125, 129, 121, 123, - 119, 121, 126, 0, 110, 110, 107, 0, 0, 109, - 0, 93, 104, 98, 84, 84, 0, 0, 89, 77, - 87, 71, 66, 0, 64, 62, 50, 47, 33, 0, - 28, 0, 0, 213, 40, 129, 131, 133, 135, 137, - 139 + 0, 0, 227, 0, 224, 228, 222, 37, 41, 38, + 187, 0, 44, 209, 54, 78, 60, 201, 196, 45, + 203, 192, 42, 47, 197, 62, 184, 0, 214, 228, + 77, 210, 88, 69, 211, 228, 0, 87, 104, 198, + 187, 176, 93, 183, 178, 188, 179, 186, 186, 180, + 186, 171, 171, 175, 177, 0, 173, 167, 173, 177, + 169, 175, 174, 0, 228, 101, 186, 0, 179, 159, + 172, 162, 169, 0, 0, 164, 164, 0, 162, 152, + 0, 156, 151, 0, 0, 0, 154, 153, 0, 144, + 0, 171, 170, 0, 0, 155, 154, 147, 139, 149, + + 137, 143, 148, 0, 133, 136, 126, 0, 228, 137, + 141, 133, 135, 131, 133, 138, 0, 122, 122, 121, + 118, 0, 0, 133, 0, 117, 134, 128, 132, 113, + 113, 0, 0, 120, 112, 110, 121, 94, 95, 0, + 94, 92, 97, 86, 85, 84, 76, 0, 71, 78, + 0, 67, 0, 61, 55, 32, 29, 0, 228, 40, + 129, 131, 133, 135, 137, 139 } ; -static yyconst flex_int16_t yy_def[152] = +static yyconst flex_int16_t yy_def[167] = { 0, - 144, 1, 144, 145, 144, 144, 145, 146, 147, 145, - 10, 145, 10, 145, 10, 10, 10, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 144, 144, - 146, 148, 149, 147, 150, 144, 10, 10, 10, 145, - 145, 145, 10, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 144, 149, 151, 39, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 144, 145, 145, 145, 145, 145, 145, 145, 145, 145, - - 145, 145, 145, 145, 145, 144, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 0, 144, 144, 144, 144, 144, 144, - 144 + 159, 1, 159, 160, 159, 159, 160, 161, 162, 160, + 10, 160, 10, 160, 10, 10, 10, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 159, 159, + 161, 163, 164, 162, 165, 159, 10, 10, 10, 160, + 160, 160, 10, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 159, 164, 166, 39, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 159, 160, 160, 160, 160, 160, 160, 160, + + 160, 160, 160, 160, 160, 160, 160, 160, 159, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 0, 159, + 159, 159, 159, 159, 159, 159 } ; -static yyconst flex_uint16_t yy_nxt[252] = +static yyconst flex_uint16_t yy_nxt[267] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 143, 38, 38, + 28, 33, 35, 36, 37, 37, 37, 158, 38, 38, 38, 38, 38, 49, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 55, 142, 57, 38, 38, 38, 56, - 60, 141, 50, 51, 58, 61, 52, 41, 32, 32, - 140, 63, 139, 42, 38, 38, 38, 46, 66, 66, - 138, 28, 35, 36, 38, 38, 38, 137, 43, 38, - - 38, 38, 66, 66, 136, 90, 44, 135, 134, 45, - 67, 67, 67, 133, 67, 67, 132, 131, 130, 129, - 67, 67, 67, 67, 67, 67, 128, 127, 71, 31, - 31, 34, 34, 32, 32, 65, 65, 35, 35, 66, - 66, 126, 125, 124, 123, 122, 121, 120, 119, 118, - 117, 116, 115, 114, 113, 112, 111, 110, 109, 108, - 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, - 97, 96, 95, 94, 93, 92, 91, 89, 88, 87, - 86, 85, 84, 83, 82, 81, 80, 79, 78, 77, - 76, 75, 74, 73, 72, 70, 69, 68, 36, 64, - - 29, 62, 59, 54, 53, 48, 47, 40, 39, 30, - 29, 144, 3, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144 + 38, 38, 38, 55, 157, 57, 38, 38, 38, 56, + 35, 36, 50, 51, 58, 156, 52, 41, 32, 32, + 155, 64, 154, 42, 38, 38, 38, 46, 60, 67, + 67, 61, 28, 38, 38, 38, 62, 153, 43, 38, + + 38, 38, 67, 67, 152, 92, 44, 151, 150, 45, + 68, 68, 68, 149, 68, 68, 148, 147, 146, 145, + 68, 68, 68, 68, 68, 68, 144, 143, 72, 31, + 31, 34, 34, 32, 32, 66, 66, 35, 35, 67, + 67, 142, 141, 140, 139, 138, 137, 136, 135, 134, + 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, + 123, 122, 121, 120, 119, 118, 117, 116, 115, 114, + 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, + 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, + 93, 91, 90, 89, 88, 87, 86, 85, 84, 83, + + 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, + 71, 70, 69, 36, 65, 29, 63, 59, 54, 53, + 48, 47, 40, 39, 30, 29, 159, 3, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159 } ; -static yyconst flex_int16_t yy_chk[252] = +static yyconst flex_int16_t yy_chk[267] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 145, 8, 9, 9, 10, 10, 10, 141, 10, 10, + 160, 8, 9, 9, 10, 10, 10, 157, 10, 10, 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 23, 139, 24, 17, 17, 17, 23, - 26, 138, 20, 20, 24, 26, 20, 15, 31, 31, - 137, 31, 136, 15, 16, 16, 16, 17, 33, 33, - 135, 33, 34, 34, 38, 38, 38, 133, 16, 43, - - 43, 43, 65, 65, 132, 65, 16, 131, 130, 16, - 39, 39, 39, 129, 39, 39, 126, 125, 124, 123, - 39, 39, 39, 39, 39, 39, 122, 120, 43, 146, - 146, 147, 147, 148, 148, 149, 149, 150, 150, 151, - 151, 117, 116, 115, 113, 112, 111, 110, 109, 108, - 107, 104, 103, 101, 100, 99, 98, 97, 96, 95, - 94, 91, 90, 88, 86, 82, 81, 79, 78, 76, - 75, 72, 71, 70, 69, 68, 66, 62, 61, 60, - 59, 58, 57, 55, 54, 53, 52, 51, 50, 49, - 48, 47, 46, 45, 44, 42, 41, 40, 35, 32, - - 29, 27, 25, 22, 21, 19, 18, 14, 11, 7, - 5, 3, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144 + 15, 15, 15, 23, 156, 24, 17, 17, 17, 23, + 34, 34, 20, 20, 24, 155, 20, 15, 31, 31, + 154, 31, 152, 15, 16, 16, 16, 17, 26, 33, + 33, 26, 33, 38, 38, 38, 26, 150, 16, 43, + + 43, 43, 66, 66, 149, 66, 16, 147, 146, 16, + 39, 39, 39, 145, 39, 39, 144, 143, 142, 141, + 39, 39, 39, 39, 39, 39, 139, 138, 43, 161, + 161, 162, 162, 163, 163, 164, 164, 165, 165, 166, + 166, 137, 136, 135, 134, 131, 130, 129, 128, 127, + 126, 124, 121, 120, 119, 118, 116, 115, 114, 113, + 112, 111, 110, 107, 106, 105, 103, 102, 101, 100, + 99, 98, 97, 96, 93, 92, 90, 88, 87, 83, + 82, 80, 79, 77, 76, 73, 72, 71, 70, 69, + 67, 63, 62, 61, 60, 59, 58, 57, 55, 54, + + 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, + 42, 41, 40, 35, 32, 29, 27, 25, 22, 21, + 19, 18, 14, 11, 7, 5, 3, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159 } ; static yy_state_type yy_last_accepting_state; @@ -674,7 +679,7 @@ static int input (void ); if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ - size_t n; \ + int n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ @@ -687,7 +692,7 @@ static int input (void ); else \ { \ errno=0; \ - while ( (result = (int) fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \ + while ( (result = (int) fread(buf, 1, (yy_size_t) max_size, yyin)) == 0 && ferror(yyin)) \ { \ if( errno != EINTR) \ { \ @@ -809,13 +814,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 145 ) + if ( yy_current_state >= 160 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 213 ); + while ( yy_base[yy_current_state] != 228 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -955,11 +960,11 @@ YY_RULE_SETUP YY_BREAK case 29: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 30: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 31: YY_RULE_SETUP @@ -971,12 +976,11 @@ YY_RULE_SETUP YY_BREAK case 33: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 34: -/* rule 34 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 35: /* rule 35 can match eol */ @@ -984,11 +988,16 @@ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 36: +/* rule 36 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 37: YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} + YY_BREAK +case 38: +YY_RULE_SETUP ECHO; YY_BREAK case YY_STATE_EOF(INITIAL): @@ -1135,7 +1144,7 @@ static int yy_get_next_buffer (void) { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); - int number_to_move, i; + yy_size_t number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) @@ -1164,7 +1173,7 @@ static int yy_get_next_buffer (void) /* Try to read more data. */ /* First move last chars to start of buffer. */ - number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); + number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); @@ -1200,7 +1209,7 @@ static int yy_get_next_buffer (void) b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ - yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 ); + yyrealloc((void *) b->yy_ch_buf,(yy_size_t) (b->yy_buf_size + 2) ); } else /* Can't grow it, we don't own it. */ @@ -1246,10 +1255,10 @@ static int yy_get_next_buffer (void) else ret_val = EOB_ACT_CONTINUE_SCAN; - if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,(yy_size_t) new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); } @@ -1283,7 +1292,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 145 ) + if ( yy_current_state >= 160 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; @@ -1311,11 +1320,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 145 ) + if ( yy_current_state >= 160 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; - yy_is_jam = (yy_current_state == 144); + yy_is_jam = (yy_current_state == 159); return yy_is_jam ? 0 : yy_current_state; } @@ -1510,12 +1519,12 @@ static void yy_load_buffer_state (void) if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); - b->yy_buf_size = (yy_size_t)size; + b->yy_buf_size = size; /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ - b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 ); + b->yy_ch_buf = (char *) yyalloc((yy_size_t) (b->yy_buf_size + 2) ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); @@ -1718,7 +1727,7 @@ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); - b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */ + b->yy_buf_size = (int) (size - 2); /* "- 2" to take care of EOB's */ b->yy_buf_pos = b->yy_ch_buf = base; b->yy_is_our_buffer = 0; b->yy_input_file = NULL; @@ -1801,7 +1810,7 @@ static void yynoreturn yy_fatal_error (yyconst char* msg ) do \ { \ /* Undo effects of setting up yytext. */ \ - int yyless_macro_arg = (n); \ + yy_size_t yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4ac935e7b10..548063fd883 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -622,6 +622,22 @@ void add_register(struct chip_instance *chip_instance, char *name, char *val) } } +void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, + char *data_width) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_type' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_type = type; + dev->smbios_slot_length = length; + dev->smbios_slot_data_width = data_width; + dev->smbios_slot_designation = designation; +} + void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, int inherit) { @@ -685,7 +701,7 @@ static void pass0(FILE *fil, struct device *ptr, struct device *next) return; } - fprintf(fil, "DEVTREE_CONST static struct device %s;\n", ptr->name); + fprintf(fil, "static DEVTREE_CONST struct device %s;\n", ptr->name); if (ptr->res) fprintf(fil, "DEVTREE_CONST struct resource %s_res[];\n", ptr->name); @@ -831,7 +847,30 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) fprintf(fil, "\t.chip_info = &%s_info_%d,\n", chip_ins->chip->name_underscore, chip_ins->id); if (next) - fprintf(fil, "\t.next=&%s\n", next->name); + fprintf(fil, "\t.next=&%s,\n", next->name); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || + ptr->smbios_slot_designation || ptr->smbios_slot_length) { + fprintf(fil, "#if !DEVTREE_EARLY\n"); + fprintf(fil, "#if CONFIG(GENERATE_SMBIOS_TABLES)\n"); + } + /* SMBIOS types start at 1, if zero it hasn't been set */ + if (ptr->smbios_slot_type) + fprintf(fil, "\t.smbios_slot_type = %s,\n", + ptr->smbios_slot_type); + if (ptr->smbios_slot_data_width) + fprintf(fil, "\t.smbios_slot_data_width = %s,\n", + ptr->smbios_slot_data_width); + if (ptr->smbios_slot_designation) + fprintf(fil, "\t.smbios_slot_designation = \"%s\",\n", + ptr->smbios_slot_designation); + if (ptr->smbios_slot_length) + fprintf(fil, "\t.smbios_slot_length = %s,\n", + ptr->smbios_slot_length); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || + ptr->smbios_slot_designation || ptr->smbios_slot_length) { + fprintf(fil, "#endif\n"); + fprintf(fil, "#endif\n"); + } fprintf(fil, "};\n"); emit_resources(fil, ptr); @@ -1316,6 +1355,11 @@ int main(int argc, char **argv) override_devtree = argv[OVERRIDE_DEVICEFILE_ARG]; parse_devicetree(override_devtree, &override_root_bus); + if (!dev_has_children(&override_root_dev)) { + fprintf(stderr, "ERROR: Override tree needs at least one device!\n"); + exit(1); + } + override_devicetree(&base_root_bus, &override_root_bus); } diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 389d697a332..e6363dea839 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -141,6 +141,18 @@ struct device { struct bus *bus; /* Pointer to last bus under this device. */ struct bus *last_bus; + + /* SMBIOS slot type */ + char *smbios_slot_type; + + /* SMBIOS slot data width */ + char *smbios_slot_data_width; + + /* SMBIOS slot description for reference designation */ + char *smbios_slot_designation; + + /* SMBIOS slot length */ + char *smbios_slot_length; }; extern struct bus *root_parent; @@ -158,6 +170,9 @@ void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, void add_ioapic_info(struct bus *bus, int apicid, const char *_srcpin, int irqpin); +void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, + char *data_width); + void yyrestart(FILE *input_file); /* Add chip data to tail of queue. */ diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index b21cca54b17..87de6e2763f 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -21,40 +21,41 @@ int linenum = 0; %} %option nodebug %% -[ \t]+ {} -#.*\n {linenum++;} -\r?\n {linenum++;} -chip {return(CHIP);} -device {return(DEVICE);} -register {return(REGISTER);} -on {yylval.number=1; return(BOOL);} -off {yylval.number=0; return(BOOL);} -hidden {yylval.number=3; return(HIDDEN);} -pci {yylval.number=PCI; return(BUS);} -ioapic {yylval.number=IOAPIC; return(BUS);} -pnp {yylval.number=PNP; return(BUS);} -i2c {yylval.number=I2C; return(BUS);} -lapic {yylval.number=APIC; return(BUS);} -cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} -cpu {yylval.number=CPU; return(BUS);} -domain {yylval.number=DOMAIN; return(BUS);} -generic {yylval.number=GENERIC; return(BUS);} -mmio {yylval.number=MMIO; return(BUS);} -spi {yylval.number=SPI; return(BUS);} -usb {yylval.number=USB; return(BUS);} -irq {yylval.number=IRQ; return(RESOURCE);} -drq {yylval.number=DRQ; return(RESOURCE);} -io {yylval.number=IO; return(RESOURCE);} -ioapic_irq {return(IOAPIC_IRQ);} -inherit {return(INHERIT);} -subsystemid {return(SUBSYSTEMID);} -end {return(END);} -= {return(EQUALS);} -0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} -\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +[ \t]+ {} +#.*\n {linenum++;} +\r?\n {linenum++;} +chip {return(CHIP);} +device {return(DEVICE);} +register {return(REGISTER);} +on {yylval.number=1; return(BOOL);} +off {yylval.number=0; return(BOOL);} +hidden {yylval.number=3; return(HIDDEN);} +pci {yylval.number=PCI; return(BUS);} +ioapic {yylval.number=IOAPIC; return(BUS);} +pnp {yylval.number=PNP; return(BUS);} +i2c {yylval.number=I2C; return(BUS);} +lapic {yylval.number=APIC; return(BUS);} +cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} +cpu {yylval.number=CPU; return(BUS);} +domain {yylval.number=DOMAIN; return(BUS);} +generic {yylval.number=GENERIC; return(BUS);} +mmio {yylval.number=MMIO; return(BUS);} +spi {yylval.number=SPI; return(BUS);} +usb {yylval.number=USB; return(BUS);} +irq {yylval.number=IRQ; return(RESOURCE);} +drq {yylval.number=DRQ; return(RESOURCE);} +io {yylval.number=IO; return(RESOURCE);} +ioapic_irq {return(IOAPIC_IRQ);} +inherit {return(INHERIT);} +subsystemid {return(SUBSYSTEMID);} +end {return(END);} +smbios_slot_desc {return(SLOT_DESC);} += {return(EQUALS);} +0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} %% diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index d59a1b6883f..8e1e57de54b 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.4. */ +/* A Bison parser, made by GNU Bison 3.0.5. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -44,7 +44,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.0.4" +#define YYBISON_VERSION "3.0.5" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -144,17 +144,18 @@ extern int yydebug; DOMAIN = 275, IRQ = 276, DRQ = 277, - IO = 278, - NUMBER = 279, - SUBSYSTEMID = 280, - INHERIT = 281, - IOAPIC_IRQ = 282, - IOAPIC = 283, - PCIINT = 284, - GENERIC = 285, - SPI = 286, - USB = 287, - MMIO = 288 + SLOT_DESC = 278, + IO = 279, + NUMBER = 280, + SUBSYSTEMID = 281, + INHERIT = 282, + IOAPIC_IRQ = 283, + IOAPIC = 284, + PCIINT = 285, + GENERIC = 286, + SPI = 287, + USB = 288, + MMIO = 289 }; #endif @@ -429,21 +430,21 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 40 +#define YYLAST 43 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 34 +#define YYNTOKENS 35 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 14 +#define YYNNTS 15 /* YYNRULES -- Number of rules. */ -#define YYNRULES 24 +#define YYNRULES 28 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 43 +#define YYNSTATES 49 /* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 288 +#define YYMAXUTOK 289 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -480,7 +481,7 @@ static const yytype_uint8 yytranslate[] = 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, 33 + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 }; #if YYDEBUG @@ -488,8 +489,8 @@ static const yytype_uint8 yytranslate[] = static const yytype_uint8 yyrline[] = { 0, 36, 36, 36, 38, 38, 38, 38, 40, 40, - 40, 40, 40, 40, 42, 42, 51, 51, 59, 59, - 61, 64, 67, 70, 73 + 40, 40, 40, 40, 40, 42, 42, 51, 51, 59, + 59, 61, 64, 67, 70, 73, 76, 79, 82 }; #endif @@ -500,11 +501,12 @@ static const char *const yytname[] = { "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", "HIDDEN", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", - "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "IO", - "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", - "GENERIC", "SPI", "USB", "MMIO", "$accept", "devtree", "$@1", - "chipchildren", "devicechildren", "chip", "@2", "device", "@3", "status", - "resource", "registers", "subsystemid", "ioapic_irq", YY_NULLPTR + "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", + "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", + "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "$accept", + "devtree", "$@1", "chipchildren", "devicechildren", "chip", "@2", + "device", "@3", "status", "resource", "registers", "subsystemid", + "ioapic_irq", "smbios_slot_desc", YY_NULLPTR }; #endif @@ -516,14 +518,14 @@ static const yytype_uint16 yytoknum[] = 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288 + 285, 286, 287, 288, 289 }; # endif -#define YYPACT_NINF -10 +#define YYPACT_NINF -12 #define yypact_value_is_default(Yystate) \ - (!!((Yystate) == (-10))) + (!!((Yystate) == (-12))) #define YYTABLE_NINF -1 @@ -534,11 +536,11 @@ static const yytype_uint16 yytoknum[] = STATE-NUM. */ static const yytype_int8 yypact[] = { - -10, 11, 9, -10, 1, -10, -10, -10, 0, 5, - 3, -10, -10, -10, -10, -9, 6, 2, 7, -10, - -10, -10, -10, -10, -3, -5, -10, -1, 4, -10, - -10, -10, -10, -10, 10, 8, -4, 12, 13, 14, - -10, -10, -10 + -12, 11, 9, -12, 1, -12, -12, -12, 0, 5, + 3, -12, -12, -12, -12, -10, 6, 2, 8, -12, + -12, -12, -12, -12, -3, -1, -12, 13, 4, 7, + -12, -12, -12, -12, -12, -12, 16, 15, 10, -11, + 12, 17, -5, 14, -12, 18, -12, -12, -12 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -546,25 +548,25 @@ static const yytype_int8 yypact[] = means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, - 0, 15, 5, 4, 6, 0, 0, 0, 0, 18, - 19, 16, 21, 13, 0, 0, 17, 0, 0, 9, - 8, 10, 11, 12, 0, 0, 0, 0, 22, 0, - 20, 23, 24 + 2, 0, 0, 1, 0, 3, 15, 7, 0, 0, + 0, 16, 5, 4, 6, 0, 0, 0, 0, 19, + 20, 17, 22, 14, 0, 0, 18, 0, 0, 0, + 9, 8, 10, 11, 12, 13, 0, 0, 0, 0, + 0, 28, 23, 0, 21, 27, 24, 25, 26 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -10, -10, -10, -10, -10, -6, -10, 16, -10, -10, - -10, -10, -10, -10 + -12, -12, -12, -12, -12, -6, -12, 19, -12, -12, + -12, -12, -12, -12, -12 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { -1, 1, 2, 8, 24, 5, 7, 13, 23, 21, - 31, 14, 32, 33 + 32, 14, 33, 34, 35 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If @@ -573,46 +575,46 @@ static const yytype_int8 yydefgoto[] = static const yytype_uint8 yytable[] = { 4, 9, 12, 4, 9, 10, 25, 26, 19, 20, - 11, 3, 4, 15, 6, 17, 16, 18, 29, 34, - 22, 37, 27, 35, 28, 39, 0, 0, 36, 0, - 0, 0, 38, 0, 0, 0, 40, 0, 42, 41, - 30 + 11, 3, 4, 15, 6, 17, 16, 18, 30, 43, + 27, 22, 46, 28, 36, 29, 37, 40, 41, 38, + 45, 48, 39, 0, 0, 42, 0, 44, 0, 47, + 0, 0, 0, 31 }; static const yytype_int8 yycheck[] = { 3, 4, 8, 3, 4, 5, 9, 10, 6, 7, - 10, 0, 3, 8, 13, 24, 13, 11, 24, 24, - 13, 11, 25, 24, 27, 29, -1, -1, 24, -1, - -1, -1, 24, -1, -1, -1, 24, -1, 24, 26, - 24 + 10, 0, 3, 8, 13, 25, 13, 11, 24, 30, + 23, 13, 27, 26, 25, 28, 13, 11, 13, 25, + 13, 13, 25, -1, -1, 25, -1, 25, -1, 25, + -1, -1, -1, 24 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 35, 36, 0, 3, 39, 13, 40, 37, 4, - 5, 10, 39, 41, 45, 8, 13, 24, 11, 6, - 7, 43, 13, 42, 38, 9, 10, 25, 27, 39, - 41, 44, 46, 47, 24, 24, 24, 11, 24, 29, - 24, 26, 24 + 0, 36, 37, 0, 3, 40, 13, 41, 38, 4, + 5, 10, 40, 42, 46, 8, 13, 25, 11, 6, + 7, 44, 13, 43, 39, 9, 10, 23, 26, 28, + 40, 42, 45, 47, 48, 49, 25, 13, 25, 25, + 11, 13, 25, 30, 25, 13, 27, 25, 13 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 34, 36, 35, 37, 37, 37, 37, 38, 38, - 38, 38, 38, 38, 40, 39, 42, 41, 43, 43, - 44, 45, 46, 46, 47 + 0, 35, 37, 36, 38, 38, 38, 38, 39, 39, + 39, 39, 39, 39, 39, 41, 40, 43, 42, 44, + 44, 45, 46, 47, 47, 48, 49, 49, 49 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 0, 0, 5, 0, 7, 1, 1, - 4, 4, 3, 4, 4 + 2, 2, 2, 2, 0, 0, 5, 0, 7, 1, + 1, 4, 4, 3, 4, 4, 5, 4, 3 }; @@ -973,6 +975,7 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, case N: \ yyformat = S; \ break + default: /* Avoid compiler warnings. */ YYCASE_(0, YY_("syntax error")); YYCASE_(1, YY_("syntax error, unexpected %s")); YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); @@ -1294,7 +1297,7 @@ yyreduce: break; - case 14: + case 15: { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); @@ -1304,7 +1307,7 @@ yyreduce: break; - case 15: + case 16: { cur_chip_instance = chip_dequeue_tail(); @@ -1312,7 +1315,7 @@ yyreduce: break; - case 16: + case 17: { (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); @@ -1321,7 +1324,7 @@ yyreduce: break; - case 17: + case 18: { cur_parent = (yyvsp[-2].dev)->parent; @@ -1329,36 +1332,54 @@ yyreduce: break; - case 20: + case 21: { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 21: + case 22: { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 22: + case 23: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 23: + case 24: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 24: + case 25: { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; + case 26: + + { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } + + break; + + case 27: + + { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } + + break; + + case 28: + + { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } + + break; + default: break; diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index cabc4743b87..bcbd644b01d 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.4. */ +/* A Bison parser, made by GNU Bison 3.0.5. */ /* Bison interface for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -65,17 +65,18 @@ extern int yydebug; DOMAIN = 275, IRQ = 276, DRQ = 277, - IO = 278, - NUMBER = 279, - SUBSYSTEMID = 280, - INHERIT = 281, - IOAPIC_IRQ = 282, - IOAPIC = 283, - PCIINT = 284, - GENERIC = 285, - SPI = 286, - USB = 287, - MMIO = 288 + SLOT_DESC = 278, + IO = 279, + NUMBER = 280, + SUBSYSTEMID = 281, + INHERIT = 282, + IOAPIC_IRQ = 283, + IOAPIC = 284, + PCIINT = 285, + GENERIC = 286, + SPI = 287, + USB = 288, + MMIO = 289 }; #endif diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 3a6e9ab8a3d..0d894a9e35a 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,13 +31,13 @@ static struct chip_instance *cur_chip_instance; int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% devtree: { cur_parent = root_parent; } chip; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | /* empty */ ; chip: CHIP STRING /* == path */ { $$ = new_chip_instance($2); @@ -72,4 +72,14 @@ subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER { add_ioapic_info(cur_parent, strtol($2, NULL, 16), $3, strtol($4, NULL, 16)); }; + +smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING + { add_slot_desc(cur_parent, $2, $3, $4, $5); }; + +smbios_slot_desc: SLOT_DESC STRING STRING STRING + { add_slot_desc(cur_parent, $2, $3, $4, NULL); }; + +smbios_slot_desc: SLOT_DESC STRING STRING + { add_slot_desc(cur_parent, $2, $3, NULL, NULL); }; + %% diff --git a/util/scripts/cross-repo-cherrypick b/util/scripts/cross-repo-cherrypick index 38d4f46fe76..42b05b51318 100755 --- a/util/scripts/cross-repo-cherrypick +++ b/util/scripts/cross-repo-cherrypick @@ -1,6 +1,6 @@ #!/bin/sh -# rebase.sh - rebase helper script +# cross-repo-cherrypick - rebase helper script # # Copyright 2015, 2017 Google Inc. # @@ -22,8 +22,8 @@ BRANCH="origin/master" # git remote add ... # git checkout -b upstreaming # git cherry-pick ... -# git rebase -i --exec util/gitconfig/rebase.sh master -# Alternatively, you can run util/gitconfig/rebase.sh after every +# git rebase -i --exec util/scripts/cross-repo-cherrypick master +# Alternatively, you can run util/scripts/cross-repo-cherrypick after every # individual cherry-pick. # use $0 --cros to add a stub BUG/BRANCH/TEST block diff --git a/util/x86/x86_page_tables.go b/util/x86/x86_page_tables.go index 2dc0ed36ff4..e477b54c5e4 100644 --- a/util/x86/x86_page_tables.go +++ b/util/x86/x86_page_tables.go @@ -223,7 +223,7 @@ func (cw *cWriter) WritePageEntry(data interface{}) error { return nil } -// This map represents what the IA32_PAT MSR should be at runtime. The indicies +// This map represents what the IA32_PAT MSR should be at runtime. The indices // are what the linux kernel uses. Reserved entries are not used. // 0 WB : _PAGE_CACHE_MODE_WB // 1 WC : _PAGE_CACHE_MODE_WC @@ -523,11 +523,11 @@ func newAddrSpace(mergeFunc addrRangeMerge, metatdataBaseAddr uint64) *addressSp return as } -func (as *addressSpace) deleteEntries(indicies []int) { +func (as *addressSpace) deleteEntries(indices []int) { // deletions need to be processed in reverse order so as not // delete the wrong entries - sort.Sort(sort.Reverse(sort.IntSlice(indicies))) - for _, i := range indicies { + sort.Sort(sort.Reverse(sort.IntSlice(indices))) + for _, i := range indices { as.ranges = append(as.ranges[:i], as.ranges[i+1:]...) } } diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4a29cdd647e..7ab1cb7af83 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -227,6 +227,29 @@ GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} + +# Clang +CLANG_CC_${TARCH}:=${CLANG} +CLANG_CFLAGS_${TARCH}:=${CFLAGS_CLANG} +CLANG_CFLAGS_${TARCH}+=-Qunused-arguments -m${TWIDTH} +# tone down clang compiler warnings +CLANG_CFLAGS_${TARCH}+=-Wno-unused-variable -Wno-unused-function -Wno-tautological-compare +CLANG_CFLAGS_${TARCH}+=-Wno-shift-overflow -Wno-address-of-packed-member -Wno-initializer-overrides +CLANG_COMPILER_RT_${TARCH}:=${CC_RT_CLANG} +CLANG_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_CLANG} + +# GCC/Clang Common +ifeq (\$(CONFIG_COMPILER_GCC)\$(CONFIG_LP_COMPILER_GCC),y) + CC_${TARCH}:=\$(GCC_CC_${TARCH}) + CFLAGS_${TARCH}:=\$(GCC_CFLAGS_${TARCH}) + COMPILER_RT_${TARCH}:=\$(GCC_COMPILER_RT_${TARCH}) + COMPILER_RT_FLAGS_${TARCH}:=\$(GCC_COMPILER_RT_FLAGS_${TARCH}) +else + CC_${TARCH}:=\$(CLANG_CC_${TARCH}) + CFLAGS_${TARCH}:=\$(CLANG_CFLAGS_${TARCH}) + COMPILER_RT_${TARCH}:=\$(CLANG_COMPILER_RT_${TARCH}) + COMPILER_RT_FLAGS_${TARCH}:=\$(CLANG_COMPILER_RT_FLAGS_${TARCH}) +endif EOF # Generally the x86 should build for i686 -- no sse/mmx @@ -238,7 +261,7 @@ EOF # to use i586 instead. if [ "${TARCH}" = "x86_64" ]; then cat <