From cc8414eda175f20423d60206d54462ac948a2a8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 15 Sep 2020 13:49:42 +0200 Subject: [PATCH 01/90] src/arch/ppc64/include/arch/io.h: implement IO functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/arch/ppc64/include/arch/io.h | 43 +++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index f8c1121f1ad..9ad331c7447 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -5,31 +5,68 @@ #include +#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x0006030000000000 +#define LPC_ADDR_START 0xC0000000 +#define LPCHC_IO_SPACE 0xD0010000 +#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE - LPC_ADDR_START) + +static inline void eieio() +{ + asm volatile("eieio" ::: "memory"); +} + static inline void outb(uint8_t value, uint16_t port) { + uint8_t *l_ptr = (uint8_t *)(LPC_BASE_ADDR + port); + const uint8_t *i_ptr = (const uint8_t *)&value; + *l_ptr = *i_ptr; + eieio(); } static inline void outw(uint16_t value, uint16_t port) { + uint16_t *l_ptr = (uint16_t *)(LPC_BASE_ADDR + port); + const uint16_t *i_ptr = (const uint16_t *)&value; + *l_ptr = *i_ptr; + eieio(); } static inline void outl(uint32_t value, uint16_t port) { + uint32_t *l_ptr = (uint32_t *)(LPC_BASE_ADDR + port); + const uint32_t *i_ptr = (const uint32_t *)&value; + *l_ptr = *i_ptr; + eieio(); } static inline uint8_t inb(uint16_t port) { - return 0; + uint8_t buffer; + uint8_t *l_ptr = (uint8_t *)(LPC_BASE_ADDR + port); + uint8_t *o_ptr = (uint8_t *)&buffer; + *o_ptr = *l_ptr; + eieio(); + return buffer; } static inline uint16_t inw(uint16_t port) { - return 0; + uint16_t buffer; + uint16_t *l_ptr = (uint16_t *)(LPC_BASE_ADDR + port); + uint16_t *o_ptr = (uint16_t *)&buffer; + *o_ptr = *l_ptr; + eieio(); + return buffer; } static inline uint32_t inl(uint16_t port) { - return 0; + uint32_t buffer; + uint32_t *l_ptr = (uint32_t *)(LPC_BASE_ADDR + port); + uint32_t *o_ptr = (uint32_t *)&buffer; + *o_ptr = *l_ptr; + eieio(); + return buffer; } #endif From e5fb1edca134fbbcd549fe06275310c1869ed162 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 15 Sep 2020 17:01:57 +0200 Subject: [PATCH 02/90] mb/raptor-cs/talos-2: add basic mainboard structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/arch/ppc64/Makefile.inc | 2 + src/arch/ppc64/arch_timer.c | 7 ++++ src/arch/ppc64/include/arch/io.h | 2 +- src/cpu/power/power9/Kconfig | 9 ++++ src/cpu/power/power9/Makefile.inc | 3 ++ src/cpu/power/power9/power9.c | 25 +++++++++++ src/mainboard/raptor-cs/Kconfig | 15 +++++++ src/mainboard/raptor-cs/Kconfig.name | 2 + src/mainboard/raptor-cs/talos-2/Kconfig | 41 +++++++++++++++++++ src/mainboard/raptor-cs/talos-2/Kconfig.name | 2 + src/mainboard/raptor-cs/talos-2/Makefile.inc | 5 +++ .../raptor-cs/talos-2/board_info.txt | 2 + src/mainboard/raptor-cs/talos-2/bootblock.c | 30 ++++++++++++++ src/mainboard/raptor-cs/talos-2/cbmem.c | 11 +++++ src/mainboard/raptor-cs/talos-2/devicetree.cb | 5 +++ src/mainboard/raptor-cs/talos-2/mainboard.c | 21 ++++++++++ src/mainboard/raptor-cs/talos-2/memlayout.ld | 17 ++++++++ src/mainboard/raptor-cs/talos-2/romstage.c | 10 +++++ 18 files changed, 208 insertions(+), 1 deletion(-) create mode 100644 src/arch/ppc64/arch_timer.c create mode 100644 src/cpu/power/power9/Kconfig create mode 100644 src/cpu/power/power9/Makefile.inc create mode 100644 src/cpu/power/power9/power9.c create mode 100644 src/mainboard/raptor-cs/Kconfig create mode 100644 src/mainboard/raptor-cs/Kconfig.name create mode 100644 src/mainboard/raptor-cs/talos-2/Kconfig create mode 100644 src/mainboard/raptor-cs/talos-2/Kconfig.name create mode 100644 src/mainboard/raptor-cs/talos-2/Makefile.inc create mode 100644 src/mainboard/raptor-cs/talos-2/board_info.txt create mode 100644 src/mainboard/raptor-cs/talos-2/bootblock.c create mode 100644 src/mainboard/raptor-cs/talos-2/cbmem.c create mode 100644 src/mainboard/raptor-cs/talos-2/devicetree.cb create mode 100644 src/mainboard/raptor-cs/talos-2/mainboard.c create mode 100644 src/mainboard/raptor-cs/talos-2/memlayout.ld create mode 100644 src/mainboard/raptor-cs/talos-2/romstage.c diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index d1774a1d157..6c8f8a16e79 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -34,6 +34,7 @@ endif ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y) +romstage-y += arch_timer.c romstage-y += boot.c romstage-y += stages.c romstage-y += rom_media.c @@ -62,6 +63,7 @@ endif ################################################################################ ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y) +ramstage-y += arch_timer.c ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += boot.c diff --git a/src/arch/ppc64/arch_timer.c b/src/arch/ppc64/arch_timer.c new file mode 100644 index 00000000000..058c5ab34b3 --- /dev/null +++ b/src/arch/ppc64/arch_timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void timer_monotonic_get(struct mono_time *mt) +{ +} diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 9ad331c7447..8e9cf2f28a3 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -10,7 +10,7 @@ #define LPCHC_IO_SPACE 0xD0010000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE - LPC_ADDR_START) -static inline void eieio() +static inline void eieio(void) { asm volatile("eieio" ::: "memory"); } diff --git a/src/cpu/power/power9/Kconfig b/src/cpu/power/power9/Kconfig new file mode 100644 index 00000000000..6eaa5027c9f --- /dev/null +++ b/src/cpu/power/power9/Kconfig @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config CPU_POWER9 + bool + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 + select NO_MONOTONIC_TIMER diff --git a/src/cpu/power/power9/Makefile.inc b/src/cpu/power/power9/Makefile.inc new file mode 100644 index 00000000000..8b721e56388 --- /dev/null +++ b/src/cpu/power/power9/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += power9c.c diff --git a/src/cpu/power/power9/power9.c b/src/cpu/power/power9/power9.c new file mode 100644 index 00000000000..d86f5a3cc91 --- /dev/null +++ b/src/cpu/power/power9/power9.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static void power9_cpu_init(struct device *dev) +{ +} + +static struct device_operations cpu_dev_ops = { + .init = power9_cpu_init, +}; + +static const struct cpu_device_id cpu_table[] = { + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +struct chip_operations cpu_power8_qemu_ops = { + CHIP_NAME("POWER9 CPU") +}; diff --git a/src/mainboard/raptor-cs/Kconfig b/src/mainboard/raptor-cs/Kconfig new file mode 100644 index 00000000000..7f916bbaf37 --- /dev/null +++ b/src/mainboard/raptor-cs/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_RAPTOR_CS + +choice + prompt "Mainboard model" + +source "src/mainboard/raptor-cs/*/Kconfig.name" + +endchoice + +source "src/mainboard/raptor-cs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Raptor Computing Systems" + +endif # VENDOR_RAPTOR_CS diff --git a/src/mainboard/raptor-cs/Kconfig.name b/src/mainboard/raptor-cs/Kconfig.name new file mode 100644 index 00000000000..7f9d8d6b9bd --- /dev/null +++ b/src/mainboard/raptor-cs/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_RAPTOR_CS + bool "Raptor Computing Systems" diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig new file mode 100644 index 00000000000..5089e32a976 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -0,0 +1,41 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_RAPTOR_CS_TALOS_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_POWER9 + select BOARD_ROMSIZE_KB_4096 + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 + select SUPERIO_ASPEED_AST2400 + select BOOT_DEVICE_NOT_SPI_FLASH + select MISSING_BOARD_RESET + +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/raptor-cs/talos-2/memlayout.ld" + +config MAINBOARD_DIR + string + default "raptor-cs/talos-2" + +config MAINBOARD_PART_NUMBER + string + default "Talos II" + +config MAX_CPUS + int + default 1 + +config MAINBOARD_VENDOR + string + default "Raptor CS" + +config DRAM_SIZE_MB + int + default 32768 + +endif # BOARD_RAPTOR_CS_TALOS_2 diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig.name b/src/mainboard/raptor-cs/talos-2/Kconfig.name new file mode 100644 index 00000000000..8a75417628d --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_RAPTOR_CS_TALOS_2 + bool "Talos II" diff --git a/src/mainboard/raptor-cs/talos-2/Makefile.inc b/src/mainboard/raptor-cs/talos-2/Makefile.inc new file mode 100644 index 00000000000..3e69e6226a4 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += cbmem.c +romstage-y += romstage.c diff --git a/src/mainboard/raptor-cs/talos-2/board_info.txt b/src/mainboard/raptor-cs/talos-2/board_info.txt new file mode 100644 index 00000000000..aa2269185be --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/board_info.txt @@ -0,0 +1,2 @@ +Board name: Raptor CS Talos II +Category: desktop diff --git a/src/mainboard/raptor-cs/talos-2/bootblock.c b/src/mainboard/raptor-cs/talos-2/bootblock.c new file mode 100644 index 00000000000..e983fb660be --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/bootblock.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void bootblock_main(void); + + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_uart_pin(serial_dev); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +/* The qemu part of all this is very, very non-hardware like. + * So it gets its own bootblock. + */ +void bootblock_main(void) +{ + early_config_superio(); + if (CONFIG(BOOTBLOCK_CONSOLE)) { + console_init(); + } + + run_romstage(); +} diff --git a/src/mainboard/raptor-cs/talos-2/cbmem.c b/src/mainboard/raptor-cs/talos-2/cbmem.c new file mode 100644 index 00000000000..15c20f8de42 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/cbmem.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void *cbmem_top_chipset(void) +{ + /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + /* For now, last 1M of 4G */ + void *ptr = (void *) ((1ULL << 32) - 1048576); + return ptr; +} diff --git a/src/mainboard/raptor-cs/talos-2/devicetree.cb b/src/mainboard/raptor-cs/talos-2/devicetree.cb new file mode 100644 index 00000000000..1a090890d58 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip cpu/power/power9 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/raptor-cs/talos-2/mainboard.c b/src/mainboard/raptor-cs/talos-2/mainboard.c new file mode 100644 index 00000000000..54ae445b5fd --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/mainboard.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + + if (!dev) { + die("No dev0; die\n"); + } + + /* Where does RAM live? */ + ram_resource(dev, 0, 2048, 32768); + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld new file mode 100644 index 00000000000..90aaec631d6 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +// TODO: fill in these blanks for Power8. +SECTIONS +{ + DRAM_START(0x0) + BOOTBLOCK(0x100, 64K) + ROMSTAGE(0x20000, 128K) + STACK(0x40000, 0x3ff00) + PRERAM_CBMEM_CONSOLE(0x80000, 8K) + FMAP_CACHE(0x82000, 2K) + RAMSTAGE(0x100000, 16M) +} diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c new file mode 100644 index 00000000000..c4123152554 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void main(void) +{ + console_init(); + run_ramstage(); +} From 027459e101d3abf9b54b8e27b1069183fe7d7012 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 17 Sep 2020 16:16:28 +0200 Subject: [PATCH 03/90] src/arch/ppc64/arch_timer.c: implement timer functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/arch/ppc64/arch_timer.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/arch/ppc64/arch_timer.c b/src/arch/ppc64/arch_timer.c index 058c5ab34b3..0dc271ff64a 100644 --- a/src/arch/ppc64/arch_timer.c +++ b/src/arch/ppc64/arch_timer.c @@ -2,6 +2,43 @@ #include +/* Refer to hostboot/src/kernel/timemgr.C */ + +/* Time base frequency is 512 MHz so 512 ticks per usec */ +#define TB_TICKS_PER_USEC 512 + +static inline uint64_t get_time_base(void) +{ + uint64_t tb = 0; + asm volatile("mfspr %0, 268" : "=r" (tb)); + return tb; +} + +static struct monotonic_counter { + int initialized; + struct mono_time time; + uint64_t last_value; +} mono_counter; + void timer_monotonic_get(struct mono_time *mt) { + uint64_t current_tick; + uint64_t usecs_elapsed; + + if (!mono_counter.initialized) { + mono_counter.last_value = get_time_base(); + mono_counter.initialized = 1; + } + + current_tick = get_time_base(); + usecs_elapsed = (current_tick - mono_counter.last_value) / TB_TICKS_PER_USEC; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; } From 11ee756dda41efd8ea8f54cee8676addcaf67c7d Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Wed, 23 Sep 2020 14:40:45 +0200 Subject: [PATCH 04/90] ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment Signed-off-by: Krystian Hebel --- src/arch/ppc64/Makefile.inc | 3 +- src/arch/ppc64/bootblock.S | 34 ------------ src/arch/ppc64/bootblock_crt0.S | 55 ++++++++++++++++++++ src/mainboard/raptor-cs/talos-2/memlayout.ld | 4 +- 4 files changed, 59 insertions(+), 37 deletions(-) delete mode 100644 src/arch/ppc64/bootblock.S create mode 100644 src/arch/ppc64/bootblock_crt0.S diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 6c8f8a16e79..fd57ead1ebc 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -9,7 +9,8 @@ ppc64_asm_flags = ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y) -bootblock-y = bootblock.S stages.c +bootblock-y = bootblock_crt0.S +bootblock-y += arch_timer.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S deleted file mode 100644 index 106c61ad953..00000000000 --- a/src/arch/ppc64/bootblock.S +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Early initialization code for POWER8. - */ - -.section ".text._start", "ax", %progbits -.globl _start -.org 0x100, 0xff -_start: - b _start - .section ".id", "a", %progbits - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz "4" //COREBOOT_VERSION -vendor: - .asciz "qemu" //CONFIG_MAINBOARD_VENDOR -part: - .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor - /* Reverse offset to the part number */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part - /* of this romimage */ -.long CONFIG_ROM_SIZE - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S new file mode 100644 index 00000000000..1cdc28e22b9 --- /dev/null +++ b/src/arch/ppc64/bootblock_crt0.S @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Early initialization code for POWER8. + */ + +#define FIXUP_ENDIAN \ + tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ + b $+44; /* Skip trampoline if endian is good */ \ + .long 0xa600607d; /* mfmsr r11 */ \ + .long 0x01006b69; /* xori r11,r11,1 */ \ + .long 0x00004039; /* li r10,0 */ \ + .long 0x6401417d; /* mtmsrd r10,1 */ \ + .long 0x05009f42; /* bcl 20,31,$+4 */ \ + .long 0xa602487d; /* mflr r10 */ \ + .long 0x14004a39; /* addi r10,r10,20 */ \ + .long 0xa6035a7d; /* mtsrr0 r10 */ \ + .long 0xa6037b7d; /* mtsrr1 r11 */ \ + .long 0x2400004c /* rfid */ + +/* SBE sets HRMOR to 130MB, ie 2MB into 10MB cache. Our bootblock is loaded + * 12 KB above that address - it is used as a place for interrupt vectors in + * Hostboot, but it isn't actually a part of the HBBL partition to save space + * in PNOR image. */ + +.section ".text._start", "ax", %progbits +.globl _start +_start: + FIXUP_ENDIAN + + /* Set program priority to medium */ + or %r2, %r2, %r2 + + /* Stack */ + lis %r1, _estack@ha + addi %r1, %r1, _estack@l + + /* Clear .bss section */ + lis %r5, _bss@ha + addi %r5, %r5, _bss@l + lis %r6, _ebss@ha + addi %r6, %r6, _ebss@l + addi %r6, %r6, -1 /* end before _ebss */ +1: + dcbz 0, %r5 + addi %r5, %r5, 128 + cmpld cr7, %r5, %r6 + blt cr7, 1b + + /* Load official procedure descriptor address for main() */ + lis %r12, main@ha + addi %r12, %r12, main@l + + /* Load TOC pointer and jump to main() */ + ld %r2, 8(%r12) + b main diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index 90aaec631d6..b158b752fdb 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -4,11 +4,11 @@ #include -// TODO: fill in these blanks for Power8. +// TODO: fill in these blanks for Power9. SECTIONS { DRAM_START(0x0) - BOOTBLOCK(0x100, 64K) + BOOTBLOCK(0x3000, 64K) ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) From 2abf54cdfa679f3dca35ac48e8b70a2757a813ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 23 Sep 2020 17:10:58 +0200 Subject: [PATCH 05/90] src/arch/ppc64/include/arch/io.h: remove obsolete statements MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/arch/ppc64/include/arch/io.h | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 8e9cf2f28a3..33e231b866f 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -10,32 +10,30 @@ #define LPCHC_IO_SPACE 0xD0010000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE - LPC_ADDR_START) +/* Enforce In-order Execution of I/O */ static inline void eieio(void) { - asm volatile("eieio" ::: "memory"); + asm volatile("eieio" ::: "memory"); } static inline void outb(uint8_t value, uint16_t port) { uint8_t *l_ptr = (uint8_t *)(LPC_BASE_ADDR + port); - const uint8_t *i_ptr = (const uint8_t *)&value; - *l_ptr = *i_ptr; + *l_ptr = value; eieio(); } static inline void outw(uint16_t value, uint16_t port) { uint16_t *l_ptr = (uint16_t *)(LPC_BASE_ADDR + port); - const uint16_t *i_ptr = (const uint16_t *)&value; - *l_ptr = *i_ptr; + *l_ptr = value; eieio(); } static inline void outl(uint32_t value, uint16_t port) { uint32_t *l_ptr = (uint32_t *)(LPC_BASE_ADDR + port); - const uint32_t *i_ptr = (const uint32_t *)&value; - *l_ptr = *i_ptr; + *l_ptr = value; eieio(); } @@ -43,8 +41,7 @@ static inline uint8_t inb(uint16_t port) { uint8_t buffer; uint8_t *l_ptr = (uint8_t *)(LPC_BASE_ADDR + port); - uint8_t *o_ptr = (uint8_t *)&buffer; - *o_ptr = *l_ptr; + buffer = *l_ptr; eieio(); return buffer; } @@ -53,8 +50,7 @@ static inline uint16_t inw(uint16_t port) { uint16_t buffer; uint16_t *l_ptr = (uint16_t *)(LPC_BASE_ADDR + port); - uint16_t *o_ptr = (uint16_t *)&buffer; - *o_ptr = *l_ptr; + buffer = *l_ptr; eieio(); return buffer; } @@ -63,8 +59,7 @@ static inline uint32_t inl(uint16_t port) { uint32_t buffer; uint32_t *l_ptr = (uint32_t *)(LPC_BASE_ADDR + port); - uint32_t *o_ptr = (uint32_t *)&buffer; - *o_ptr = *l_ptr; + buffer = *l_ptr; eieio(); return buffer; } From ee55037eeeae728060e54930a21c0e87f76f1e83 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Wed, 23 Sep 2020 17:21:02 +0200 Subject: [PATCH 06/90] arch/ppc64/include/arch/io.h: use proper instructions for IO operations Those instrunctions are: * Load {byte,half,word} and Zero Caching Inhibited indeXed (l*zcix) * Store {byte,half,word} Caching Inhibited indeXed (st*cix) for in* and out*, respectively. Signed-off-by: Krystian Hebel --- src/arch/ppc64/include/arch/io.h | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 33e231b866f..1d9fbcc4561 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -18,30 +18,26 @@ static inline void eieio(void) static inline void outb(uint8_t value, uint16_t port) { - uint8_t *l_ptr = (uint8_t *)(LPC_BASE_ADDR + port); - *l_ptr = value; + asm volatile("stbcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); eieio(); } static inline void outw(uint16_t value, uint16_t port) { - uint16_t *l_ptr = (uint16_t *)(LPC_BASE_ADDR + port); - *l_ptr = value; + asm volatile("sthcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); eieio(); } static inline void outl(uint32_t value, uint16_t port) { - uint32_t *l_ptr = (uint32_t *)(LPC_BASE_ADDR + port); - *l_ptr = value; + asm volatile("stwcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); eieio(); } static inline uint8_t inb(uint16_t port) { uint8_t buffer; - uint8_t *l_ptr = (uint8_t *)(LPC_BASE_ADDR + port); - buffer = *l_ptr; + asm volatile("lbzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); eieio(); return buffer; } @@ -49,8 +45,7 @@ static inline uint8_t inb(uint16_t port) static inline uint16_t inw(uint16_t port) { uint16_t buffer; - uint16_t *l_ptr = (uint16_t *)(LPC_BASE_ADDR + port); - buffer = *l_ptr; + asm volatile("lhzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); eieio(); return buffer; } @@ -58,8 +53,7 @@ static inline uint16_t inw(uint16_t port) static inline uint32_t inl(uint16_t port) { uint32_t buffer; - uint32_t *l_ptr = (uint32_t *)(LPC_BASE_ADDR + port); - buffer = *l_ptr; + asm volatile("lwzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); eieio(); return buffer; } From ebf13afb80c0b60df45366bfd728c305d493bac4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 24 Sep 2020 15:09:40 +0200 Subject: [PATCH 07/90] Makefile.inc: compile ECC tools and inject ECC to final image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ab0e5bbb736..a8792d48098 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -503,7 +503,7 @@ endif additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ - $(objutil)/cbootimage + $(objutil)/cbootimage $(objutil)/ffs export $(COREBOOT_EXPORTS) @@ -539,6 +539,7 @@ RMODTOOL:=$(objutil)/cbfstool/rmodtool IFWITOOL:=$(objutil)/cbfstool/ifwitool IFITTOOL:=$(objutil)/cbfstool/ifittool AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress +ECCTOOL:=$(objutil)/ffs/ecc/ecc $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -580,6 +581,12 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< +$(ECCTOOL): + @printf " Compile ECCTOOL\n" + cp -r $(top)/3rdparty/ffs $(objutil) + cd $(objutil)/ffs && autoreconf -i && ./configure + +$(MAKE) -C $(objutil)/ffs + APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage @@ -676,7 +683,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(ECCTOOL) ########################################################################### # Common recipes for all stages @@ -1103,7 +1110,7 @@ else RAMSTAGE= endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $(ECCTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -1169,6 +1176,10 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE $(CBFSTOOL) $@ layout @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifeq ($(CONFIG_ARCH_PPC64),y) + $(ECCTOOL) --inject $@ --output $@.ecc --p8 +endif + cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf From c20580b8ad9950ac0b289fce4fb6640b39d05e8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 24 Sep 2020 15:10:13 +0200 Subject: [PATCH 08/90] src/mainboard/raptor-cs/talos-2/Kconfig: temporarily shrink the ROM size to 512KB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig index 5089e32a976..2e52e386219 100644 --- a/src/mainboard/raptor-cs/talos-2/Kconfig +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -5,7 +5,7 @@ if BOARD_RAPTOR_CS_TALOS_2 config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_POWER9 - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_512 select ARCH_BOOTBLOCK_PPC64 select ARCH_VERSTAGE_PPC64 select ARCH_ROMSTAGE_PPC64 From b0c62651fda95f36468f3c20e88596a761ba4457 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 24 Sep 2020 15:46:55 +0200 Subject: [PATCH 09/90] 3rdparty/sb-signing-utils: add SecureBoot utility for OpenPOWER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- .gitmodules | 3 +++ 3rdparty/sb-signing-utils | 1 + 2 files changed, 4 insertions(+) create mode 160000 3rdparty/sb-signing-utils diff --git a/.gitmodules b/.gitmodules index 8b44384202e..828730eea40 100644 --- a/.gitmodules +++ b/.gitmodules @@ -54,3 +54,6 @@ [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools url = ../9esec-security-tooling.git +[submodule "3rdparty/sb-signing-utils"] + path = 3rdparty/sb-signing-utils + url = https://github.com/open-power/sb-signing-utils.git diff --git a/3rdparty/sb-signing-utils b/3rdparty/sb-signing-utils new file mode 160000 index 00000000000..591c8f53482 --- /dev/null +++ b/3rdparty/sb-signing-utils @@ -0,0 +1 @@ +Subproject commit 591c8f53482243626901e1cc8a4ae321f314040d From e11d2eb50b016afb92cd894bc93d20e22fbdbaa6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 24 Sep 2020 16:17:25 +0200 Subject: [PATCH 10/90] Makefile.inc: add signing procedure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a8792d48098..74fbfce2bc7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -540,6 +540,7 @@ IFWITOOL:=$(objutil)/cbfstool/ifwitool IFITTOOL:=$(objutil)/cbfstool/ifittool AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress ECCTOOL:=$(objutil)/ffs/ecc/ecc +SBSINGTOOLS:=$(objutil)/sb-signing-utils $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -587,6 +588,12 @@ $(ECCTOOL): cd $(objutil)/ffs && autoreconf -i && ./configure +$(MAKE) -C $(objutil)/ffs +$(SBSINGTOOLS): + @printf " Compile SB SIGNING UTILS\n" + cp -r $(top)/3rdparty/sb-signing-utils $(objutil) + cd $(objutil)/sb-signing-utils && autoreconf -i -Wno-unsupported && ./configure + +$(MAKE) -C $(objutil)/sb-signing-utils + APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage @@ -683,7 +690,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(ECCTOOL) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(ECCTOOL) $(SBSINGTOOL) ########################################################################### # Common recipes for all stages @@ -1110,7 +1117,7 @@ else RAMSTAGE= endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $(ECCTOOL) $$(INTERMEDIATE) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $(ECCTOOL) $(SBSINGTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -1172,13 +1179,19 @@ endif endif # !CONFIG_UPDATE_IMAGE endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE mv $@.tmp $@ +ifeq ($(CONFIG_ARCH_PPC64),y) + cp -r $(top)/3rdparty/sb-signing-utils/test/keys /tmp + @printf " SBSIGN $(subst $(obj)/,,$(@))\n" + cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null + @printf " SBPRINT $(subst $(obj)/,,$(@))\n\n" + $(SBSINGTOOLS)/print-container -v -d -I $(top)/$@.signed + @printf " ECC $(subst $(obj)/,,$(@))\n" + $(ECCTOOL) --inject $@.signed --output $@.signed.ecc --p8 +endif @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ layout @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) -ifeq ($(CONFIG_ARCH_PPC64),y) - $(ECCTOOL) --inject $@ --output $@.ecc --p8 -endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage From c393292cb31766f366afd91d4a152803e7bb2ac0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 24 Sep 2020 17:53:16 +0200 Subject: [PATCH 11/90] Makefile.inc: automatically pad the coreboot to 1M before applying ECC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 74fbfce2bc7..c5a64bee712 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1185,8 +1185,10 @@ ifeq ($(CONFIG_ARCH_PPC64),y) cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null @printf " SBPRINT $(subst $(obj)/,,$(@))\n\n" $(SBSINGTOOLS)/print-container -v -d -I $(top)/$@.signed + dd if=$@.signed of=$@.signed.padded ibs=929792 conv=sync 2> /dev/null @printf " ECC $(subst $(obj)/,,$(@))\n" - $(ECCTOOL) --inject $@.signed --output $@.signed.ecc --p8 + $(ECCTOOL) --inject $@.signed.padded --output $@.signed.ecc --p8 + rm $@.signed.padded endif @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ layout From 924b6f7cabd142f078705596c61f693b3878e0d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 24 Sep 2020 18:55:49 +0200 Subject: [PATCH 12/90] Makefile.inc: fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index c5a64bee712..a5144e0b53e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1117,7 +1117,7 @@ else RAMSTAGE= endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $(ECCTOOL) $(SBSINGTOOL) $$(INTERMEDIATE) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $(ECCTOOL) $(SBSINGTOOLS) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty From 9d201f54cef9eeb928ce90a94234997d7c78705d Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 24 Sep 2020 17:54:38 +0200 Subject: [PATCH 13/90] arch/ppc64/include/arch/io.h: ignore HRMOR for MMIO operations Signed-off-by: Krystian Hebel --- src/arch/ppc64/include/arch/io.h | 3 ++- src/mainboard/raptor-cs/talos-2/memlayout.ld | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 1d9fbcc4561..85d9e97a7b8 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -5,7 +5,8 @@ #include -#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x0006030000000000 +/* Set MSB to 1 to ignore HRMOR */ +#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 #define LPC_ADDR_START 0xC0000000 #define LPCHC_IO_SPACE 0xD0010000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE - LPC_ADDR_START) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index b158b752fdb..811b64b3ac3 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -8,7 +8,7 @@ SECTIONS { DRAM_START(0x0) - BOOTBLOCK(0x3000, 64K) + BOOTBLOCK(0, 64K) ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) From d71636a8d3461efcb8a65cbf52e349522ef00015 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 24 Sep 2020 19:11:06 +0200 Subject: [PATCH 14/90] .gitmodules: use upstream for intel-sec-tools Signed-off-by: Krystian Hebel --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 828730eea40..8db01bd59c2 100644 --- a/.gitmodules +++ b/.gitmodules @@ -53,7 +53,7 @@ ignore = dirty [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools - url = ../9esec-security-tooling.git + url = https://github.com/coreboot/9esec-security-tooling.git [submodule "3rdparty/sb-signing-utils"] path = 3rdparty/sb-signing-utils url = https://github.com/open-power/sb-signing-utils.git From 446310d1657c5d4163682040247c228230f88feb Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 25 Sep 2020 12:16:01 +0200 Subject: [PATCH 15/90] drivers/uart/Kconfig: enable also for PPC64 Signed-off-by: Krystian Hebel --- src/drivers/uart/Kconfig | 2 +- src/mainboard/raptor-cs/talos-2/bootblock.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 41b870fbf78..beba4012e2f 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -5,7 +5,7 @@ config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and # should be selected by boards that have it instead. bool "Serial port on SuperIO" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_PPC64 default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y diff --git a/src/mainboard/raptor-cs/talos-2/bootblock.c b/src/mainboard/raptor-cs/talos-2/bootblock.c index e983fb660be..08db8d2ad9a 100644 --- a/src/mainboard/raptor-cs/talos-2/bootblock.c +++ b/src/mainboard/raptor-cs/talos-2/bootblock.c @@ -5,6 +5,7 @@ #include #include #include +#include void bootblock_main(void); @@ -19,7 +20,7 @@ static void early_config_superio(void) /* The qemu part of all this is very, very non-hardware like. * So it gets its own bootblock. */ -void bootblock_main(void) +void bootblock_mainboard_early_init(void) { early_config_superio(); if (CONFIG(BOOTBLOCK_CONSOLE)) { From c1afb3cbfe0c28b2f296090b0473f0f2317a204b Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 25 Sep 2020 12:21:05 +0200 Subject: [PATCH 16/90] mainboard/talos-2/bootblock.c: do not repeat what lib/bootblock does Signed-off-by: Krystian Hebel --- src/mainboard/raptor-cs/talos-2/bootblock.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/bootblock.c b/src/mainboard/raptor-cs/talos-2/bootblock.c index 08db8d2ad9a..9f25ca9aa69 100644 --- a/src/mainboard/raptor-cs/talos-2/bootblock.c +++ b/src/mainboard/raptor-cs/talos-2/bootblock.c @@ -7,25 +7,9 @@ #include #include -void bootblock_main(void); - - -static void early_config_superio(void) +void bootblock_mainboard_early_init(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); aspeed_enable_uart_pin(serial_dev); aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); } - -/* The qemu part of all this is very, very non-hardware like. - * So it gets its own bootblock. - */ -void bootblock_mainboard_early_init(void) -{ - early_config_superio(); - if (CONFIG(BOOTBLOCK_CONSOLE)) { - console_init(); - } - - run_romstage(); -} From 83fe67ad3946d676afd692025a4427aa6cacfc91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 25 Sep 2020 12:47:21 +0200 Subject: [PATCH 17/90] Makefile.inc; make the final file to be coreboot.rom with exact size of 1MB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a5144e0b53e..c59eeaa0bfa 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1179,6 +1179,10 @@ endif endif # !CONFIG_UPDATE_IMAGE endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE mv $@.tmp $@ + @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" + $(CBFSTOOL) $@ layout + @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" + $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) ifeq ($(CONFIG_ARCH_PPC64),y) cp -r $(top)/3rdparty/sb-signing-utils/test/keys /tmp @printf " SBSIGN $(subst $(obj)/,,$(@))\n" @@ -1188,12 +1192,9 @@ ifeq ($(CONFIG_ARCH_PPC64),y) dd if=$@.signed of=$@.signed.padded ibs=929792 conv=sync 2> /dev/null @printf " ECC $(subst $(obj)/,,$(@))\n" $(ECCTOOL) --inject $@.signed.padded --output $@.signed.ecc --p8 - rm $@.signed.padded + dd if=$@.signed.ecc of=$@ ibs=1M conv=sync 2> /dev/null + rm $@.signed.padded $@.signed.ecc $@.signed endif - @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" - $(CBFSTOOL) $@ layout - @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" - $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage From 4dd45b75ea2dde0007532eab55976eb0d9559360 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 25 Sep 2020 16:00:33 +0200 Subject: [PATCH 18/90] src/mainboard/raptor-cs/talos-2/bootblock.c: initialize SoL instead of UART1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/bootblock.c | 55 +++++++++++++++++++-- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/bootblock.c b/src/mainboard/raptor-cs/talos-2/bootblock.c index 9f25ca9aa69..dd5873a890a 100644 --- a/src/mainboard/raptor-cs/talos-2/bootblock.c +++ b/src/mainboard/raptor-cs/talos-2/bootblock.c @@ -9,7 +9,56 @@ void bootblock_mainboard_early_init(void) { - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); - aspeed_enable_uart_pin(serial_dev); - aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + struct config_data vuart_init[] = { + /* Activate VUART */ + [Step1] = { + .type = SIO, + .base = 0, + .reg = ACT_REG, + .and = 0, + .or = ACTIVATE_VALUE + }, + /* Configure IRQ level as low */ + [Step2] = { + .type = MEM, + .base = ASPEED_VUART_BASE, + .reg = 0x20, + .and = ~2, + .or = 0 + }, + /* Set the SerIRQ IRQ 4 */ + [Step3] = { + .type = MEM, + .base = ASPEED_VUART_BASE, + .reg = 0x24, + .and = ~0xf0, + .or = (4 << 4) + }, + [Step4] = { + .type = MEM, + .base = ASPEED_VUART_BASE, + .reg = 0x24, + .and = ~0xf0, + .or = (4 << 4) + }, + /* Configure base address low */ + [Step5] = { + .type = MEM, + .base = ASPEED_VUART_BASE, + .reg = 0x28, + .and = 0, + .or = CONFIG_TTYS0_BASE & 0xff + }, + /* Configure base address high */ + [Step6] = { + .type = MEM, + .base = ASPEED_VUART_BASE, + .reg = 0x2c, + .and = 0, + .or = (CONFIG_TTYS0_BASE >> 8) & 0xff + }, + }; + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_ILPC2AHB); + aspeed_early_config(serial_dev, vuart_init, ARRAY_SIZE(vuart_init)); } From a2a861364f946e9bd6edf3ecd4eb239f16f5bcbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 25 Sep 2020 16:13:57 +0200 Subject: [PATCH 19/90] src/mainboard/raptor-cs/talos-2/bootblock.c: drop obsolete step in SoL init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/bootblock.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/bootblock.c b/src/mainboard/raptor-cs/talos-2/bootblock.c index dd5873a890a..ee0114271ca 100644 --- a/src/mainboard/raptor-cs/talos-2/bootblock.c +++ b/src/mainboard/raptor-cs/talos-2/bootblock.c @@ -34,15 +34,8 @@ void bootblock_mainboard_early_init(void) .and = ~0xf0, .or = (4 << 4) }, - [Step4] = { - .type = MEM, - .base = ASPEED_VUART_BASE, - .reg = 0x24, - .and = ~0xf0, - .or = (4 << 4) - }, /* Configure base address low */ - [Step5] = { + [Step4] = { .type = MEM, .base = ASPEED_VUART_BASE, .reg = 0x28, @@ -50,7 +43,7 @@ void bootblock_mainboard_early_init(void) .or = CONFIG_TTYS0_BASE & 0xff }, /* Configure base address high */ - [Step6] = { + [Step5] = { .type = MEM, .base = ASPEED_VUART_BASE, .reg = 0x2c, From 8adacd62e5bf154988efd29a3f95c0cff8b6522d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 30 Sep 2020 17:35:05 +0200 Subject: [PATCH 20/90] src/arch/ppc64/include/arch/io.h: fix the LPC base address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/arch/ppc64/include/arch/io.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 85d9e97a7b8..a9287ca801a 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -7,9 +7,8 @@ /* Set MSB to 1 to ignore HRMOR */ #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 -#define LPC_ADDR_START 0xC0000000 #define LPCHC_IO_SPACE 0xD0010000 -#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE - LPC_ADDR_START) +#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) /* Enforce In-order Execution of I/O */ static inline void eieio(void) From 40bc1e1202d5451f348f033e07489c816b50963b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 30 Sep 2020 17:37:17 +0200 Subject: [PATCH 21/90] src/mainboard/raptor-cs/talos-2/bootblock.c: implement post code function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/bootblock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/raptor-cs/talos-2/bootblock.c b/src/mainboard/raptor-cs/talos-2/bootblock.c index ee0114271ca..6fe764938d3 100644 --- a/src/mainboard/raptor-cs/talos-2/bootblock.c +++ b/src/mainboard/raptor-cs/talos-2/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,11 @@ #include #include +void mainboard_post(uint8_t value) +{ + outb(value, 0x80); +} + void bootblock_mainboard_early_init(void) { struct config_data vuart_init[] = { From 53cae6b9381174af46657307fae3f0b36c11cbb3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 30 Sep 2020 18:15:28 +0200 Subject: [PATCH 22/90] .gitmodules: use full paths MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- .gitmodules | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.gitmodules b/.gitmodules index 8db01bd59c2..cdaa0f5952e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,54 +1,54 @@ [submodule "3rdparty/blobs"] path = 3rdparty/blobs - url = ../blobs.git + url = https://review.coreboot.org/blobs.git update = none ignore = dirty [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage - url = ../nvidia-cbootimage.git + url = https://review.coreboot.org/nvidia-cbootimage.git [submodule "vboot"] path = 3rdparty/vboot - url = ../vboot.git + url = https://review.coreboot.org/vboot.git [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware - url = ../arm-trusted-firmware.git + url = https://review.coreboot.org/arm-trusted-firmware.git [submodule "3rdparty/chromeec"] path = 3rdparty/chromeec - url = ../chrome-ec.git + url = https://review.coreboot.org/chrome-ec.git [submodule "libhwbase"] path = 3rdparty/libhwbase - url = ../libhwbase.git + url = https://review.coreboot.org/libhwbase.git [submodule "libgfxinit"] path = 3rdparty/libgfxinit - url = ../libgfxinit.git + url = https://review.coreboot.org/libgfxinit.git [submodule "3rdparty/fsp"] path = 3rdparty/fsp - url = ../fsp.git + url = https://review.coreboot.org/fsp.git update = none ignore = dirty [submodule "opensbi"] path = 3rdparty/opensbi - url = ../opensbi.git + url = https://review.coreboot.org/opensbi.git [submodule "intel-microcode"] path = 3rdparty/intel-microcode - url = ../intel-microcode.git + url = https://review.coreboot.org/intel-microcode.git update = none ignore = dirty [submodule "3rdparty/ffs"] path = 3rdparty/ffs - url = ../ffs.git + url = https://review.coreboot.org/ffs.git [submodule "3rdparty/amd_blobs"] path = 3rdparty/amd_blobs - url = ../amd_blobs + url = https://review.coreboot.org/amd_blobs update = none ignore = dirty [submodule "3rdparty/cmocka"] path = 3rdparty/cmocka - url = ../cmocka.git + url = https://review.coreboot.org/cmocka.git update = none [submodule "3rdparty/qc_blobs"] path = 3rdparty/qc_blobs - url = ../qc_blobs.git + url = https://review.coreboot.org/qc_blobs.git update = none ignore = dirty [submodule "3rdparty/intel-sec-tools"] From dd399cabd4e9235f31cbbe0e82de90b08e536735 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Wed, 30 Sep 2020 17:56:04 +0200 Subject: [PATCH 23/90] ppc64/byteorder.h: define use of big endian Signed-off-by: Krystian Hebel --- src/arch/ppc64/include/arch/byteorder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/ppc64/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h index 24853580441..79f15b1eb32 100644 --- a/src/arch/ppc64/include/arch/byteorder.h +++ b/src/arch/ppc64/include/arch/byteorder.h @@ -3,6 +3,6 @@ #ifndef _BYTEORDER_H #define _BYTEORDER_H -#define __LITTLE_ENDIAN 1234 +#define __BIG_ENDIAN 4321 #endif /* _BYTEORDER_H */ From bd4e7be826d187ffa55624a0fed883a9c5cb1f60 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Wed, 30 Sep 2020 18:23:14 +0200 Subject: [PATCH 24/90] src/lib/fmap.c: use le*toh() functions where needed TODO: add documentation Signed-off-by: Krystian Hebel --- src/lib/fmap.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 377123afdc3..ebcd30edcda 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "fmap_config.h" @@ -37,7 +38,8 @@ static void report(const struct fmap *fmap) print_once(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %#x.\n", fmap->name, fmap->ver_major, fmap->ver_minor, FMAP_OFFSET); print_once(BIOS_DEBUG, "FMAP: base = %#llx size = %#x #areas = %d\n", - (long long)fmap->base, fmap->size, fmap->nareas); + (long long)le64toh(fmap->base), le32toh(fmap->size), + le16toh(fmap->nareas)); fmap_print_once = 1; } @@ -170,10 +172,10 @@ int fmap_locate_area(const char *name, struct region *ar) } printk(BIOS_DEBUG, "FMAP: area %s found @ %x (%d bytes)\n", - name, area->offset, area->size); + name, le32toh(area->offset), le32toh(area->size)); - ar->offset = area->offset; - ar->size = area->size; + ar->offset = le32toh(area->offset); + ar->size = le32toh(area->size); rdev_munmap(&fmrd, area); @@ -205,8 +207,8 @@ int fmap_find_region_name(const struct region * const ar, if (area == NULL) return -1; - if ((ar->offset != area->offset) || - (ar->size != area->size)) { + if ((ar->offset != le32toh(area->offset)) || + (ar->size != le32toh(area->size))) { rdev_munmap(&fmrd, area); offset += sizeof(struct fmap_area); continue; From 4bf06656d6b84eba791390b94cdcefb2a45e720e Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Wed, 30 Sep 2020 18:24:24 +0200 Subject: [PATCH 25/90] src/lib/cbfs.c: use le*toh() functions where needed TODO: add documentation, fix endianness Signed-off-by: Krystian Hebel --- src/lib/cbfs.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index cb66f81d99a..bc48b2eeccc 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -296,12 +296,12 @@ int cbfs_prog_stage_load(struct prog *pstage) foffset = 0; foffset += sizeof(stage); - assert(fsize == stage.len); + assert(fsize == le32toh(stage.len)); /* Note: cbfs_stage fields are currently in the endianness of the * running processor. */ - load = (void *)(uintptr_t)stage.load; - entry = (void *)(uintptr_t)stage.entry; + load = (void *)(uintptr_t)le64toh(stage.load); + entry = (void *)(uintptr_t)le64toh(stage.entry); /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ @@ -314,17 +314,17 @@ int cbfs_prog_stage_load(struct prog *pstage) } fsize = cbfs_stage_load_and_decompress(fh, foffset, fsize, load, - stage.memlen, stage.compression); + le32toh(stage.memlen), le32toh(stage.compression)); if (!fsize) return -1; /* Clear area not covered by file. */ - memset(&load[fsize], 0, stage.memlen - fsize); + memset(&load[fsize], 0, le32toh(stage.memlen) - fsize); - prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); + prog_segment_loaded((uintptr_t)load, le32toh(stage.memlen), SEG_FINAL); out: - prog_set_area(pstage, load, stage.memlen); + prog_set_area(pstage, load, le32toh(stage.memlen)); prog_set_entry(pstage, entry, NULL); return 0; From b71f96c91ff5902c2e6d706b3e7d7a5c2897bcf1 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 8 Oct 2020 16:59:38 +0200 Subject: [PATCH 26/90] mainboard/talos-2/memlayout.ld: do not overwrite CBFS image For now, whole coreboot.rom is copied into the L3 cache by HBBL. This limits maximum allowed size of coreboot "ROM" to 1 MB with ECC included, so 512 K in practice. This size limit won't be an issue when CBFS will be read from PNOR directly. Signed-off-by: Krystian Hebel --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index 811b64b3ac3..250f0a1467b 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -9,9 +9,9 @@ SECTIONS { DRAM_START(0x0) BOOTBLOCK(0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - FMAP_CACHE(0x82000, 2K) - RAMSTAGE(0x100000, 16M) + ROMSTAGE(0x120000, 128K) + STACK(0x140000, 0x3ff00) + PRERAM_CBMEM_CONSOLE(0x180000, 128K) + FMAP_CACHE(0x1a0000, 2K) + RAMSTAGE(0x200000, 4M) } From fd681c90c7b0f07e22463788d77828f3f7c0293b Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 8 Oct 2020 17:04:20 +0200 Subject: [PATCH 27/90] ppc64/bootblock_crt0.S: workaround different entry point in QEMU Signed-off-by: Krystian Hebel --- src/arch/ppc64/bootblock_crt0.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S index 1cdc28e22b9..685ffbccb52 100644 --- a/src/arch/ppc64/bootblock_crt0.S +++ b/src/arch/ppc64/bootblock_crt0.S @@ -25,6 +25,11 @@ .section ".text._start", "ax", %progbits .globl _start _start: + /* QEMU with hb-mode=on starts at address 0x10, while hardware at 0x0. */ + nop + nop + nop + nop FIXUP_ENDIAN /* Set program priority to medium */ From 8adc8ce1373c8e8732ec17a1b3120990b9beeea0 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 8 Oct 2020 17:23:21 +0200 Subject: [PATCH 28/90] ppc64/bootblock_crt0.S: do not clear BSS BSS is loaded as part of the bootblock, it is zeroed in the file so it doesn't have to be cleared explicitly by the code. Code for clearing is left as a comment along with a warning about alignment requirements. Signed-off-by: Krystian Hebel --- src/arch/ppc64/bootblock_crt0.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S index 685ffbccb52..88b853dec8d 100644 --- a/src/arch/ppc64/bootblock_crt0.S +++ b/src/arch/ppc64/bootblock_crt0.S @@ -40,16 +40,21 @@ _start: addi %r1, %r1, _estack@l /* Clear .bss section */ + /* Curently not needed, .bss is zeroed in the file. If it were to be used, + * make sure that .bss is 128B aligned (size of cache line), otherwise dcbz + * will clear (part of) .opd section! */ +/* lis %r5, _bss@ha addi %r5, %r5, _bss@l lis %r6, _ebss@ha addi %r6, %r6, _ebss@l - addi %r6, %r6, -1 /* end before _ebss */ + addi %r6, %r6, -1 1: dcbz 0, %r5 addi %r5, %r5, 128 cmpld cr7, %r5, %r6 blt cr7, 1b +*/ /* Load official procedure descriptor address for main() */ lis %r12, main@ha From 5186a3e8d306851a4389367cca8ae5a4b1b793b5 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 8 Oct 2020 19:19:42 +0200 Subject: [PATCH 29/90] commonlib/lz4_wrapper.c: do not use bitfields Bitfields are not portable across systems using different endianness. Signed-off-by: Krystian Hebel --- src/commonlib/bsd/lz4_wrapper.c | 53 +++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 73185a50515..a75653e9547 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -63,8 +63,22 @@ typedef uint64_t U64; #define LZ4F_MAGICNUMBER 0x184D2204 +/* Bit field endianness is implementation-defined. Use masks instead. + * https://stackoverflow.com/a/6044223 */ +#define RESERVED0 0x03 +#define HAS_CONTENT_CHECKSUM 0x04 +#define HAS_CONTENT_SIZE 0x08 +#define HAS_BLOCK_CHECKSUM 0x10 +#define INDEPENDENT_BLOCKS 0x20 +#define VERSION 0xC0 +#define VERSION_SHIFT 6 + +#define RESERVED1_2 0x8F +#define MAX_BLOCK_SIZE 0x70 + struct lz4_frame_header { uint32_t magic; + /* union { uint8_t flags; struct { @@ -76,6 +90,9 @@ struct lz4_frame_header { uint8_t version : 2; }; }; + */ + uint8_t flags; + /* union { uint8_t block_descriptor; struct { @@ -84,11 +101,18 @@ struct lz4_frame_header { uint8_t reserved2 : 1; }; }; + */ + uint8_t block_descriptor; /* + uint64_t content_size iff has_content_size is set */ /* + uint8_t header_checksum */ } __packed; +/* These fix bit order, note we still need le32toh() for proper byte order */ +#define BH_SIZE 0x7FFFFFFF +#define NOT_COMPRESSED 0x80000000 + struct lz4_block_header { + /* union { uint32_t raw; struct { @@ -96,6 +120,8 @@ struct lz4_block_header { uint32_t not_compressed : 1; }; }; + */ + uint32_t raw; /* + size bytes of data */ /* + uint32_t block_checksum iff has_block_checksum is set */ } __packed; @@ -114,16 +140,17 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) return 0; /* input overrun */ /* We assume there's always only a single, standard frame. */ - if (le32toh(h->magic) != LZ4F_MAGICNUMBER || h->version != 1) + if (le32toh(h->magic) != LZ4F_MAGICNUMBER + || (h->flags & VERSION) != (1 << VERSION_SHIFT)) return 0; /* unknown format */ - if (h->reserved0 || h->reserved1 || h->reserved2) + if ((h->flags & RESERVED0) || (h->block_descriptor & RESERVED1_2)) return 0; /* reserved must be zero */ - if (!h->independent_blocks) + if (!(h->flags & INDEPENDENT_BLOCKS)) return 0; /* we don't support block dependency */ - has_block_checksum = h->has_block_checksum; + has_block_checksum = h->flags & HAS_BLOCK_CHECKSUM; in += sizeof(*h); - if (h->has_content_size) + if (h->flags & HAS_CONTENT_SIZE) in += sizeof(uint64_t); in += sizeof(uint8_t); } @@ -133,28 +160,28 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) break; /* input overrun */ struct lz4_block_header b = { - { .raw = le32toh(*(const uint32_t *)in) } + .raw = le32toh(*(const uint32_t *)in) }; in += sizeof(struct lz4_block_header); - if ((size_t)(in - src) + b.size > srcn) + if ((size_t)(in - src) + (b.raw & BH_SIZE) > srcn) break; /* input overrun */ - if (!b.size) { + if (!(b.raw & BH_SIZE)) { out_size = out - dst; break; /* decompression successful */ } - if (b.not_compressed) { - size_t size = MIN((uintptr_t)b.size, (uintptr_t)dst + if (b.raw & NOT_COMPRESSED) { + size_t size = MIN((uintptr_t)(b.raw & BH_SIZE), (uintptr_t)dst + dstn - (uintptr_t)out); memcpy(out, in, size); - if (size < b.size) + if (size < (b.raw & BH_SIZE)) break; /* output overrun */ out += size; } else { /* constant folding essential, do not touch params! */ - int ret = LZ4_decompress_generic(in, out, b.size, + int ret = LZ4_decompress_generic(in, out, (b.raw & BH_SIZE), dst + dstn - out, endOnInputSize, full, 0, noDict, out, NULL, 0); if (ret < 0) @@ -162,7 +189,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) out += ret; } - in += b.size; + in += (b.raw & BH_SIZE); if (has_block_checksum) in += sizeof(uint32_t); } From 1d7f24c2a0bbd5ddc98de96eb163649aa7361e21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 12 Oct 2020 16:35:41 +0200 Subject: [PATCH 30/90] src/mainboard/raptor-cs/talos-2/Kconfig: increase ROM size and separate bootblock from CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/Kconfig | 6 ++++++ src/mainboard/raptor-cs/talos-2/Kconfig | 7 ++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index d6b703ba16e..6ba6d2e5cfe 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1243,6 +1243,12 @@ config BOOTBLOCK_CUSTOM # src/lib/bootblock.c#main() C entry point. bool +config BOOTBLOCK_OUTSIDE_CBFS + bool + help + Select it on the arch, mainboard or SoC to not include the bootblock in + the main CBFS or coreboot.rom file. + config MEMLAYOUT_LD_FILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig index 2e52e386219..3879f02544c 100644 --- a/src/mainboard/raptor-cs/talos-2/Kconfig +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -5,7 +5,7 @@ if BOARD_RAPTOR_CS_TALOS_2 config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_POWER9 - select BOARD_ROMSIZE_KB_512 + select BOARD_ROMSIZE_KB_16384 select ARCH_BOOTBLOCK_PPC64 select ARCH_VERSTAGE_PPC64 select ARCH_ROMSTAGE_PPC64 @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_ASPEED_AST2400 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET + select BOOTBLOCK_OUTSIDE_CBFS config MEMLAYOUT_LD_FILE string @@ -30,6 +31,10 @@ config MAX_CPUS int default 1 +config CBFS_SIZE + hex + default 0x1000000 + config MAINBOARD_VENDOR string default "Raptor CS" From 2f8b62bedb2e32469136903bf3386d7364b2a330 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 12 Oct 2020 16:42:15 +0200 Subject: [PATCH 31/90] src/mainboard/raptor-cs/talos-2/memlayout.ld: set bootblock size to 16K MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index 250f0a1467b..79b8e4a0711 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -8,7 +8,7 @@ SECTIONS { DRAM_START(0x0) - BOOTBLOCK(0, 64K) + BOOTBLOCK(0x3000, 20K) ROMSTAGE(0x120000, 128K) STACK(0x140000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x180000, 128K) From 321ba0056422e3271bb3341c1aa540ca3ac01d6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 12 Oct 2020 16:46:57 +0200 Subject: [PATCH 32/90] Makefile.inc: sign and inject ECC to the bootblock separately from CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index c59eeaa0bfa..79dbba7e453 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1076,9 +1076,11 @@ ifeq ($(CONFIG_ARCH_X86),y) -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) - $(CBFSTOOL) $@.tmp write -u \ - -r BOOTBLOCK \ - -f $(objcbfs)/bootblock.bin + ifneq ($(CONFIG_BOOTBLOCK_OUTSIDE_CBFS),y) + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin + endif # make space for the CBFS master header pointer. "ptr_" is just # arbitrary 4 bytes that will be overwritten by add-master-header. printf "ptr_" > $@.tmp.2 @@ -1186,14 +1188,12 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE ifeq ($(CONFIG_ARCH_PPC64),y) cp -r $(top)/3rdparty/sb-signing-utils/test/keys /tmp @printf " SBSIGN $(subst $(obj)/,,$(@))\n" + cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(objcbfs)/bootblock.bin $(obj)/bootblock.signed 2> /dev/null cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null - @printf " SBPRINT $(subst $(obj)/,,$(@))\n\n" - $(SBSINGTOOLS)/print-container -v -d -I $(top)/$@.signed - dd if=$@.signed of=$@.signed.padded ibs=929792 conv=sync 2> /dev/null @printf " ECC $(subst $(obj)/,,$(@))\n" - $(ECCTOOL) --inject $@.signed.padded --output $@.signed.ecc --p8 - dd if=$@.signed.ecc of=$@ ibs=1M conv=sync 2> /dev/null - rm $@.signed.padded $@.signed.ecc $@.signed + dd if=$(obj)/bootblock.signed of=$(obj)/bootblock.signed.pad ibs=25486 conv=sync 2> /dev/null + $(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8 + rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad endif From 6661f6a987e86e731783e097c403a8d85b9356ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 12 Oct 2020 17:06:24 +0200 Subject: [PATCH 33/90] configs/config.raptor-cs-talos-2: add config for op-build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- configs/config.raptor-cs-talos-2 | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 configs/config.raptor-cs-talos-2 diff --git a/configs/config.raptor-cs-talos-2 b/configs/config.raptor-cs-talos-2 new file mode 100644 index 00000000000..3b072a1713b --- /dev/null +++ b/configs/config.raptor-cs-talos-2 @@ -0,0 +1,2 @@ +CONFIG_ANY_TOOLCHAIN=y +CONFIG_VENDOR_RAPTOR_CS=y From 9772aed70fb96ed100bac0fb85b83a6ee64d8fae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 12 Oct 2020 17:46:24 +0200 Subject: [PATCH 34/90] src/mainboard/raptor-cs/talos-2/memlayout.ld: set bootblock size to 20K and load offset to 12K MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index 79b8e4a0711..ef0197ad23c 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -9,9 +9,9 @@ SECTIONS { DRAM_START(0x0) BOOTBLOCK(0x3000, 20K) - ROMSTAGE(0x120000, 128K) - STACK(0x140000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x180000, 128K) - FMAP_CACHE(0x1a0000, 2K) - RAMSTAGE(0x200000, 4M) + ROMSTAGE(0x20000, 128K) + STACK(0x40000, 0x3ff00) + PRERAM_CBMEM_CONSOLE(0x80000, 8K) + FMAP_CACHE(0x82000, 2K) + RAMSTAGE(0x100000, 16M) } From c22fae2ddcbab2156b6cbeeeefc2f0c1bb2f20aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 12 Oct 2020 22:39:18 +0200 Subject: [PATCH 35/90] configs/config.raptor-cs-talos-2: do not use any toolchain MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- configs/config.raptor-cs-talos-2 | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/config.raptor-cs-talos-2 b/configs/config.raptor-cs-talos-2 index 3b072a1713b..2602c416bd8 100644 --- a/configs/config.raptor-cs-talos-2 +++ b/configs/config.raptor-cs-talos-2 @@ -1,2 +1 @@ -CONFIG_ANY_TOOLCHAIN=y CONFIG_VENDOR_RAPTOR_CS=y From a21f03dedda75703fa6d5680a750dcd82d400af8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 13 Oct 2020 00:29:16 +0200 Subject: [PATCH 36/90] Makefile.inc: fix syntax MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 79dbba7e453..25296e1a0db 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1076,11 +1076,11 @@ ifeq ($(CONFIG_ARCH_X86),y) -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) - ifneq ($(CONFIG_BOOTBLOCK_OUTSIDE_CBFS),y) - $(CBFSTOOL) $@.tmp write -u \ - -r BOOTBLOCK \ - -f $(objcbfs)/bootblock.bin - endif +ifneq ($(CONFIG_BOOTBLOCK_OUTSIDE_CBFS),y) + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin +else # make space for the CBFS master header pointer. "ptr_" is just # arbitrary 4 bytes that will be overwritten by add-master-header. printf "ptr_" > $@.tmp.2 @@ -1090,6 +1090,7 @@ else # ifeq ($(CONFIG_ARCH_X86),y) -t "cbfs header" \ -b -4 rm -f $@.tmp.2 +endif # ifneq ($(CONFIG_BOOTBLOCK_OUTSIDE_CBFS),y) endif # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(prebuild-files) true @@ -1188,7 +1189,7 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE ifeq ($(CONFIG_ARCH_PPC64),y) cp -r $(top)/3rdparty/sb-signing-utils/test/keys /tmp @printf " SBSIGN $(subst $(obj)/,,$(@))\n" - cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(objcbfs)/bootblock.bin $(obj)/bootblock.signed 2> /dev/null + cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$(objcbfs)/bootblock.bin $(top)/$(obj)/bootblock.signed 2> /dev/null cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null @printf " ECC $(subst $(obj)/,,$(@))\n" dd if=$(obj)/bootblock.signed of=$(obj)/bootblock.signed.pad ibs=25486 conv=sync 2> /dev/null From f7aea12722505705cc2723a363ac843e1c307738 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 26 Oct 2020 12:06:28 +0100 Subject: [PATCH 37/90] Makefile.inc,Kconfig: remove bootblock outside CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- Makefile.inc | 5 +---- src/Kconfig | 6 ------ src/mainboard/raptor-cs/talos-2/Kconfig | 1 - 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 25296e1a0db..a8425a7cab5 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1076,11 +1076,9 @@ ifeq ($(CONFIG_ARCH_X86),y) -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) -ifneq ($(CONFIG_BOOTBLOCK_OUTSIDE_CBFS),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ -f $(objcbfs)/bootblock.bin -else # make space for the CBFS master header pointer. "ptr_" is just # arbitrary 4 bytes that will be overwritten by add-master-header. printf "ptr_" > $@.tmp.2 @@ -1090,7 +1088,6 @@ else -t "cbfs header" \ -b -4 rm -f $@.tmp.2 -endif # ifneq ($(CONFIG_BOOTBLOCK_OUTSIDE_CBFS),y) endif # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(prebuild-files) true @@ -1191,7 +1188,7 @@ ifeq ($(CONFIG_ARCH_PPC64),y) @printf " SBSIGN $(subst $(obj)/,,$(@))\n" cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$(objcbfs)/bootblock.bin $(top)/$(obj)/bootblock.signed 2> /dev/null cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null - @printf " ECC $(subst $(obj)/,,$(@))\n" + @printf " ECC bootblock\n" dd if=$(obj)/bootblock.signed of=$(obj)/bootblock.signed.pad ibs=25486 conv=sync 2> /dev/null $(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8 rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad diff --git a/src/Kconfig b/src/Kconfig index 6ba6d2e5cfe..d6b703ba16e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1243,12 +1243,6 @@ config BOOTBLOCK_CUSTOM # src/lib/bootblock.c#main() C entry point. bool -config BOOTBLOCK_OUTSIDE_CBFS - bool - help - Select it on the arch, mainboard or SoC to not include the bootblock in - the main CBFS or coreboot.rom file. - config MEMLAYOUT_LD_FILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig index 3879f02544c..e827bf964f5 100644 --- a/src/mainboard/raptor-cs/talos-2/Kconfig +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_ASPEED_AST2400 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET - select BOOTBLOCK_OUTSIDE_CBFS config MEMLAYOUT_LD_FILE string From e005ddc097be4e855ee382170bfbbfbb7691e8e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 1 Dec 2020 16:00:23 +0100 Subject: [PATCH 38/90] src/mainboard/raptor-cs/talos-2/memlayout.ld: increase the bootblock size to 64K MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index ef0197ad23c..b158b752fdb 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -8,7 +8,7 @@ SECTIONS { DRAM_START(0x0) - BOOTBLOCK(0x3000, 20K) + BOOTBLOCK(0x3000, 64K) ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) From cd3211ce2b448fc2295c45b1a3d9699d5714b6a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 1 Dec 2020 18:58:38 +0100 Subject: [PATCH 39/90] src/mainboard/raptor-cs/talos-2/memlayout.ld: start bootblock at 0 as previously for HBB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index b158b752fdb..811b64b3ac3 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -8,7 +8,7 @@ SECTIONS { DRAM_START(0x0) - BOOTBLOCK(0x3000, 64K) + BOOTBLOCK(0, 64K) ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) From 0e6af4be17c03b1fe8205a50989aea417cc1b49a Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 8 Dec 2020 13:09:12 +0100 Subject: [PATCH 40/90] talos-2/memlayout.ld: add section for CBFS mcache CBFS mcache was recently introduced in [1] and following commits in that relation chain. [1] https://review.coreboot.org/c/coreboot/+/38423 Signed-off-by: Krystian Hebel --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index 811b64b3ac3..b024a29c931 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -13,5 +13,6 @@ SECTIONS STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } From a63d04b917728f38770b00a1d8deca66da415087 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 8 Dec 2020 18:20:29 +0100 Subject: [PATCH 41/90] Revert "src/lib/cbfs.c: use le*toh() functions where needed" This reverts commit 4bf06656d6b84eba791390b94cdcefb2a45e720e. Similar changes were done in [1], this has to be reverted so the fields aren't byte-swapped twice. [1] https://review.coreboot.org/c/coreboot/+/46227 --- src/lib/cbfs.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 6503c6b0cfd..9aea33d8589 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -386,17 +386,17 @@ int cbfs_prog_stage_load(struct prog *pstage) } fsize = cbfs_stage_load_and_decompress(fh, foffset, fsize, load, - le32toh(stage.memlen), le32toh(stage.compression)); + stage.memlen, stage.compression); if (!fsize) return -1; /* Clear area not covered by file. */ - memset(&load[fsize], 0, le32toh(stage.memlen) - fsize); + memset(&load[fsize], 0, stage.memlen - fsize); - prog_segment_loaded((uintptr_t)load, le32toh(stage.memlen), SEG_FINAL); + prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); out: - prog_set_area(pstage, load, le32toh(stage.memlen)); + prog_set_area(pstage, load, stage.memlen); prog_set_entry(pstage, entry, NULL); return 0; From b2268fee006db44f27ac6b9a919945946516501b Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 14 Dec 2020 14:52:50 +0100 Subject: [PATCH 42/90] src/soc/raptor-cs/*: Add file structure to soc --- src/soc/raptor-cs/Kconfig | 1 + src/soc/raptor-cs/power9/Kconfig | 6 ++++++ src/soc/raptor-cs/power9/Makefile.inc | 8 ++++++++ src/soc/raptor-cs/power9/bootblock.c | 4 ++++ src/soc/raptor-cs/power9/romstage.c | 1 + 5 files changed, 20 insertions(+) create mode 100644 src/soc/raptor-cs/Kconfig create mode 100644 src/soc/raptor-cs/power9/Kconfig create mode 100644 src/soc/raptor-cs/power9/Makefile.inc create mode 100644 src/soc/raptor-cs/power9/bootblock.c create mode 100644 src/soc/raptor-cs/power9/romstage.c diff --git a/src/soc/raptor-cs/Kconfig b/src/soc/raptor-cs/Kconfig new file mode 100644 index 00000000000..9edb3cdf98d --- /dev/null +++ b/src/soc/raptor-cs/Kconfig @@ -0,0 +1 @@ +source "src/soc/raptor-cs/*/Kconfig" diff --git a/src/soc/raptor-cs/power9/Kconfig b/src/soc/raptor-cs/power9/Kconfig new file mode 100644 index 00000000000..b7818394f27 --- /dev/null +++ b/src/soc/raptor-cs/power9/Kconfig @@ -0,0 +1,6 @@ +config SOC_RAPTOR_POWER9 + bool + select ARCH_BOOTBLOCK_POWER9 + select ARCH_VERSTAGE_POWER9 + select ARCH_ROMSTAGE_POWER9 + select ARCH_RAMSTAGE_POWER9 diff --git a/src/soc/raptor-cs/power9/Makefile.inc b/src/soc/raptor-cs/power9/Makefile.inc new file mode 100644 index 00000000000..67df8fd953b --- /dev/null +++ b/src/soc/raptor-cs/power9/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(SOC_RAPTOR_POWER9),y) + +bootblock-y += bootblock.c +romstage-y += romstage.c + +endif diff --git a/src/soc/raptor-cs/power9/bootblock.c b/src/soc/raptor-cs/power9/bootblock.c new file mode 100644 index 00000000000..9a84828a754 --- /dev/null +++ b/src/soc/raptor-cs/power9/bootblock.c @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +adadad diff --git a/src/soc/raptor-cs/power9/romstage.c b/src/soc/raptor-cs/power9/romstage.c new file mode 100644 index 00000000000..853b0877b33 --- /dev/null +++ b/src/soc/raptor-cs/power9/romstage.c @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ From b91c2597bb67227ab3d2dbfb4e9b03452addbf90 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Tue, 15 Dec 2020 14:04:41 +0100 Subject: [PATCH 43/90] src/soc/ibm/*: Add structe according to the example, rename soc vendor to ibm --- src/lib/prog_loaders.c | 4 ++++ src/soc/ibm/Kconfig | 1 + src/soc/ibm/power9/Kconfig | 15 +++++++++++++++ src/soc/{raptor-cs => ibm}/power9/Makefile.inc | 6 +++++- src/soc/{raptor-cs => ibm}/power9/bootblock.c | 5 +++-- src/soc/ibm/power9/chip.c | 6 ++++++ src/soc/ibm/power9/romstage.c | 7 +++++++ src/soc/ibm/power9/timer.c | 7 +++++++ src/soc/raptor-cs/Kconfig | 1 - src/soc/raptor-cs/power9/Kconfig | 6 ------ src/soc/raptor-cs/power9/romstage.c | 1 - 11 files changed, 48 insertions(+), 11 deletions(-) create mode 100644 src/soc/ibm/Kconfig create mode 100644 src/soc/ibm/power9/Kconfig rename src/soc/{raptor-cs => ibm}/power9/Makefile.inc (52%) rename src/soc/{raptor-cs => ibm}/power9/bootblock.c (52%) create mode 100644 src/soc/ibm/power9/chip.c create mode 100644 src/soc/ibm/power9/romstage.c create mode 100644 src/soc/ibm/power9/timer.c delete mode 100644 src/soc/raptor-cs/Kconfig delete mode 100644 src/soc/raptor-cs/power9/Kconfig delete mode 100644 src/soc/raptor-cs/power9/romstage.c diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 93efc0a2806..9ed98ee6a51 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -46,6 +46,10 @@ void run_romstage(void) vboot_run_logic(); + long long unsigned int *reg = (void *)0x000603FC0000F00F; + printk(BIOS_EMERG, "WORKING\n"); + printk(BIOS_EMERG, "SCOM:? %llX\n", *reg); + if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { if (legacy_romstage_selector(&romstage)) goto fail; diff --git a/src/soc/ibm/Kconfig b/src/soc/ibm/Kconfig new file mode 100644 index 00000000000..40a09dc19f0 --- /dev/null +++ b/src/soc/ibm/Kconfig @@ -0,0 +1 @@ +source "src/soc/ibm/*/Kconfig" diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig new file mode 100644 index 00000000000..f23e1fb7c4c --- /dev/null +++ b/src/soc/ibm/power9/Kconfig @@ -0,0 +1,15 @@ +config CPU_POWER9 + bool + help + This example SoC code along with the example/min86 mainboard + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. + +if CPU_POWER9 + # nothing here yet +endif diff --git a/src/soc/raptor-cs/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc similarity index 52% rename from src/soc/raptor-cs/power9/Makefile.inc rename to src/soc/ibm/power9/Makefile.inc index 67df8fd953b..a039023f867 100644 --- a/src/soc/raptor-cs/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -1,8 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(SOC_RAPTOR_POWER9),y) +ifeq ($(CPU_POWER9),y) bootblock-y += bootblock.c +postcar-y += exit_car.S romstage-y += romstage.c +ramstage-y += chip.c +ramstage-y += timer.c + endif diff --git a/src/soc/raptor-cs/power9/bootblock.c b/src/soc/ibm/power9/bootblock.c similarity index 52% rename from src/soc/raptor-cs/power9/bootblock.c rename to src/soc/ibm/power9/bootblock.c index 9a84828a754..54e7e5d3747 100644 --- a/src/soc/raptor-cs/power9/bootblock.c +++ b/src/soc/ibm/power9/bootblock.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - -adadad +void bootblock_soc_early_init(void) +{ +} diff --git a/src/soc/ibm/power9/chip.c b/src/soc/ibm/power9/chip.c new file mode 100644 index 00000000000..98e1d570d89 --- /dev/null +++ b/src/soc/ibm/power9/chip.c @@ -0,0 +1,6 @@ +#include + +struct chip_operations soc_ibm_power9_ops = { + CHIP_NAME("POWER9") +}; + diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c new file mode 100644 index 00000000000..91074b20125 --- /dev/null +++ b/src/soc/ibm/power9/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/ibm/power9/timer.c b/src/soc/ibm/power9/timer.c new file mode 100644 index 00000000000..9054ffd972e --- /dev/null +++ b/src/soc/ibm/power9/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void init_timer(void) +{ +} diff --git a/src/soc/raptor-cs/Kconfig b/src/soc/raptor-cs/Kconfig deleted file mode 100644 index 9edb3cdf98d..00000000000 --- a/src/soc/raptor-cs/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "src/soc/raptor-cs/*/Kconfig" diff --git a/src/soc/raptor-cs/power9/Kconfig b/src/soc/raptor-cs/power9/Kconfig deleted file mode 100644 index b7818394f27..00000000000 --- a/src/soc/raptor-cs/power9/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -config SOC_RAPTOR_POWER9 - bool - select ARCH_BOOTBLOCK_POWER9 - select ARCH_VERSTAGE_POWER9 - select ARCH_ROMSTAGE_POWER9 - select ARCH_RAMSTAGE_POWER9 diff --git a/src/soc/raptor-cs/power9/romstage.c b/src/soc/raptor-cs/power9/romstage.c deleted file mode 100644 index 853b0877b33..00000000000 --- a/src/soc/raptor-cs/power9/romstage.c +++ /dev/null @@ -1 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ From 43686917de67479ef31d87c417e810eee981f9fa Mon Sep 17 00:00:00 2001 From: IgorBagnucki <69140743+IgorBagnucki@users.noreply.github.com> Date: Tue, 15 Dec 2020 14:14:42 +0100 Subject: [PATCH 44/90] src/lib/prog_loaders.c: remove debug --- src/lib/prog_loaders.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 9ed98ee6a51..93efc0a2806 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -46,10 +46,6 @@ void run_romstage(void) vboot_run_logic(); - long long unsigned int *reg = (void *)0x000603FC0000F00F; - printk(BIOS_EMERG, "WORKING\n"); - printk(BIOS_EMERG, "SCOM:? %llX\n", *reg); - if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { if (legacy_romstage_selector(&romstage)) goto fail; From bbcf85df42d5f519868eb11fbe469c6d5da8de72 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Wed, 16 Dec 2020 08:23:40 +0100 Subject: [PATCH 45/90] src/soc/ibm/power9/*: Apply review suggestions --- src/soc/ibm/power9/Kconfig | 4 ++-- src/soc/ibm/power9/Makefile.inc | 8 ++++---- src/soc/ibm/power9/timer.c | 1 + 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig index f23e1fb7c4c..911816d7e6b 100644 --- a/src/soc/ibm/power9/Kconfig +++ b/src/soc/ibm/power9/Kconfig @@ -1,4 +1,4 @@ -config CPU_POWER9 +config CPU_IBM_POWER9 bool help This example SoC code along with the example/min86 mainboard @@ -10,6 +10,6 @@ config CPU_POWER9 the review of the actual code, and also avoid any regressions when common coreboot code changes. -if CPU_POWER9 +if CPU_IBM_POWER9 # nothing here yet endif diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index a039023f867..14ee650584f 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -1,12 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CPU_POWER9),y) +ifeq ($(CPU_IBM_POWER9),y) bootblock-y += bootblock.c -postcar-y += exit_car.S +postcar-y += exit_car.S romstage-y += romstage.c -ramstage-y += chip.c -ramstage-y += timer.c +ramstage-y += chip.c +ramstage-y += timer.c endif diff --git a/src/soc/ibm/power9/timer.c b/src/soc/ibm/power9/timer.c index 9054ffd972e..2e0289c0451 100644 --- a/src/soc/ibm/power9/timer.c +++ b/src/soc/ibm/power9/timer.c @@ -4,4 +4,5 @@ void init_timer(void) { + // no need to do anything here } From 86e260250b9d679720e0aeac3bb0149b16c36064 Mon Sep 17 00:00:00 2001 From: IgorBagnucki <69140743+IgorBagnucki@users.noreply.github.com> Date: Wed, 16 Dec 2020 14:54:00 +0100 Subject: [PATCH 46/90] src/soc/ibm/power9/Kconfig: Update help --- src/soc/ibm/power9/Kconfig | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig index 911816d7e6b..cc83b9390ad 100644 --- a/src/soc/ibm/power9/Kconfig +++ b/src/soc/ibm/power9/Kconfig @@ -1,14 +1,8 @@ config CPU_IBM_POWER9 bool help - This example SoC code along with the example/min86 mainboard - should serve as a minimal example how a buildable x86 SoC code - base can look like. - - This can serve, for instance, as a basis to add new SoCs to - coreboot. Starting with a buildable commit should help with - the review of the actual code, and also avoid any regressions - when common coreboot code changes. + This SoC is template is the minimal template working on POWER9 + Talos II platform. if CPU_IBM_POWER9 # nothing here yet From 7e24b11b1aab20152183983f5e931c27e11ffe52 Mon Sep 17 00:00:00 2001 From: IgorBagnucki <69140743+IgorBagnucki@users.noreply.github.com> Date: Wed, 16 Dec 2020 15:02:21 +0100 Subject: [PATCH 47/90] src/soc/ibm/power9/Kconfig: fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Michał Żygowski --- src/soc/ibm/power9/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig index cc83b9390ad..a94c41d606c 100644 --- a/src/soc/ibm/power9/Kconfig +++ b/src/soc/ibm/power9/Kconfig @@ -1,7 +1,7 @@ config CPU_IBM_POWER9 bool help - This SoC is template is the minimal template working on POWER9 + This SoC is the minimal template working on POWER9 Talos II platform. if CPU_IBM_POWER9 From a4489bc799e568411981de429db1a214f347d7c8 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Tue, 19 Jan 2021 14:36:03 +0100 Subject: [PATCH 48/90] src/lib/prog_loaders.c: first prototype of scom indirect --- src/lib/prog_loaders.c | 107 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 93efc0a2806..f0a3f1ac106 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -17,6 +17,7 @@ #include #include #include +#include /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = @@ -39,10 +40,116 @@ int prog_locate(struct prog *prog) return 0; } +void read_scom_direct(uint32_t, uint64_t*); +void read_scom_direct(uint32_t reg_address, uint64_t *buffer) +{ + asm volatile( + "ldcix %0, %1, %2": + "=r"(*buffer): + "b"(0x800603FC00000000), + "r"(reg_address << 3)); + eieio(); +} + +void write_scom_direct(uint32_t, uint64_t*); +void write_scom_direct(uint32_t reg_address, uint64_t *buffer) +{ + asm volatile( + "stdcix %0, %1, %2":: + "b"(*buffer), + "b"(0x800603FC00000000), + "r"(reg_address << 3)); + eieio(); +} + +#define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) +#define PPC_BITMASK(bs,be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) +#define XSCOM_ADDR_IND_FLAG PPC_BIT(0) +#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(12,31) +#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63) + +#define XSCOM_DATA_IND_READ PPC_BIT(0) +#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) +#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63) +#define XSCOM_IND_MAX_RETRIES 10 + +void write_scom_indirect(uint64_t, uint64_t); +void write_scom_indirect(uint64_t reg_address, uint64_t value) +{ + uint64_t addr; + uint64_t data; + addr = reg_address & 0x7FFFFFFF; + data = reg_address & XSCOM_ADDR_IND_ADDR; + printk(BIOS_EMERG, "----------------\n"); + printk(BIOS_EMERG, "SCOM WRITE\n\n"); + printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); + write_scom_direct(addr, &data); + for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { + printk(BIOS_EMERG, "READING addr = %llX\n", addr); + read_scom_direct(addr, &data); + printk(BIOS_EMERG, "READ data = %llX\n", data); + if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { + printk(BIOS_EMERG, "SUCCESS\n"); + printk(BIOS_EMERG, "----------------\n"); + return; + } + else if(data & XSCOM_DATA_IND_COMPLETE) { + printk(BIOS_EMERG, "FINISHED WITH ERROR\n"); + printk(BIOS_EMERG, "----------------\n"); + return; + } + } +} + +void read_scom_indirect(uint64_t, uint64_t*); +void read_scom_indirect(uint64_t reg_address, uint64_t *buffer) +{ + uint64_t addr; + uint64_t data; + addr = reg_address & 0x7FFFFFFF; + data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR); + printk(BIOS_EMERG, "----------------\n"); + printk(BIOS_EMERG, "SCOM READ\n\n"); + printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); + write_scom_direct(addr, &data); + for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { + printk(BIOS_EMERG, "READING addr = %llX\n", addr); + read_scom_direct(addr, &data); + printk(BIOS_EMERG, "READ data = %llX\n", data); + if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { + *buffer = data & XSCOM_DATA_IND_DATA; + printk(BIOS_EMERG, "SUCCESS\n"); + printk(BIOS_EMERG, "----------------\n"); + return; + } + else if(data & XSCOM_DATA_IND_COMPLETE) { + printk(BIOS_EMERG, "FINISHED WITH ERROR\n"); + printk(BIOS_EMERG, "----------------\n"); + return; + } + } + +} + void run_romstage(void) { + uint64_t buffer; + read_scom_indirect(0x8000C8000701103Full, &buffer); + buffer = 0x7777777777777777; + write_scom_indirect(0x8000C8000701103Full, buffer); + read_scom_indirect(0x8000C8000701103Full, &buffer); struct prog romstage = PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); + uint64_t buffer; + read_scom_direct(0xF0008, &buffer); + printk(BIOS_EMERG, "SCOM F0008: %llX\n", buffer); + buffer = 0xFFFFFFFFFFFFFFFF; + write_scom_direct(0xF0008, &buffer); + printk(BIOS_EMERG, "just wrote\n"); + read_scom_direct(0xF0008, &buffer); + printk(BIOS_EMERG, "SCOM F0008: %llX\n", buffer); vboot_run_logic(); From 294953dde2798f3320872ce354c33e0332b96656 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Wed, 20 Jan 2021 15:02:23 +0100 Subject: [PATCH 49/90] src/lib/prog_loaders.c: check hmer --- src/lib/prog_loaders.c | 68 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 9 deletions(-) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index f0a3f1ac106..3a2fb040ae1 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -40,6 +40,22 @@ int prog_locate(struct prog *prog) return 0; } +/* Bits in HMER/HMEER */ +#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) +#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) +#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) +#define SPR_HMER_TFAC_ERROR PPC_BIT(4) +#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) +#define SPR_HMER_XSCOM_FAIL PPC_BIT(8) +#define SPR_HMER_XSCOM_DONE PPC_BIT(9) +#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) +#define SPR_HMER_WARN_RISE PPC_BIT(14) +#define SPR_HMER_WARN_FALL PPC_BIT(15) +#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) +#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) +#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) +#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) + void read_scom_direct(uint32_t, uint64_t*); void read_scom_direct(uint32_t reg_address, uint64_t *buffer) { @@ -62,6 +78,14 @@ void write_scom_direct(uint32_t reg_address, uint64_t *buffer) eieio(); } +uint64_t read_hmer(void); +uint64_t read_hmer(void) +{ + unsigned long val; + asm volatile("mfspr %0,%1" : "=r"(val) : "i"(0x150) : "memory"); + return val; +} + #define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) #define PPC_BITMASK(bs,be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) #define XSCOM_ADDR_IND_FLAG PPC_BIT(0) @@ -82,14 +106,30 @@ void write_scom_indirect(uint64_t reg_address, uint64_t value) uint64_t data; addr = reg_address & 0x7FFFFFFF; data = reg_address & XSCOM_ADDR_IND_ADDR; + data |= value & XSCOM_ADDR_IND_DATA; printk(BIOS_EMERG, "----------------\n"); printk(BIOS_EMERG, "SCOM WRITE\n\n"); + printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); write_scom_direct(addr, &data); + printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { printk(BIOS_EMERG, "READING addr = %llX\n", addr); read_scom_direct(addr, &data); printk(BIOS_EMERG, "READ data = %llX\n", data); + printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { printk(BIOS_EMERG, "SUCCESS\n"); printk(BIOS_EMERG, "----------------\n"); @@ -112,12 +152,27 @@ void read_scom_indirect(uint64_t reg_address, uint64_t *buffer) data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR); printk(BIOS_EMERG, "----------------\n"); printk(BIOS_EMERG, "SCOM READ\n\n"); + printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); write_scom_direct(addr, &data); + printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { printk(BIOS_EMERG, "READING addr = %llX\n", addr); read_scom_direct(addr, &data); printk(BIOS_EMERG, "READ data = %llX\n", data); + printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { *buffer = data & XSCOM_DATA_IND_DATA; printk(BIOS_EMERG, "SUCCESS\n"); @@ -136,21 +191,16 @@ void read_scom_indirect(uint64_t reg_address, uint64_t *buffer) void run_romstage(void) { uint64_t buffer; + long long unsigned int hmer = 0; + asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); read_scom_indirect(0x8000C8000701103Full, &buffer); buffer = 0x7777777777777777; + asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); write_scom_indirect(0x8000C8000701103Full, buffer); + asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); read_scom_indirect(0x8000C8000701103Full, &buffer); struct prog romstage = PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); - uint64_t buffer; - read_scom_direct(0xF0008, &buffer); - printk(BIOS_EMERG, "SCOM F0008: %llX\n", buffer); - buffer = 0xFFFFFFFFFFFFFFFF; - write_scom_direct(0xF0008, &buffer); - printk(BIOS_EMERG, "just wrote\n"); - read_scom_direct(0xF0008, &buffer); - printk(BIOS_EMERG, "SCOM F0008: %llX\n", buffer); - vboot_run_logic(); if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { From 93205079d727d9b909e51a71826f2d1bcdd50ca3 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Thu, 21 Jan 2021 12:54:45 +0100 Subject: [PATCH 50/90] src/lib/prog_loaders.c:m Add debuging --- src/lib/prog_loaders.c | 77 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 67 insertions(+), 10 deletions(-) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3a2fb040ae1..13eee91fc97 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -56,8 +56,8 @@ int prog_locate(struct prog *prog) #define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) #define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) -void read_scom_direct(uint32_t, uint64_t*); -void read_scom_direct(uint32_t reg_address, uint64_t *buffer) +uint64_t read_scom_direct(uint32_t, uint64_t*); +uint64_t read_scom_direct(uint32_t reg_address, uint64_t *buffer) { asm volatile( "ldcix %0, %1, %2": @@ -65,6 +65,7 @@ void read_scom_direct(uint32_t reg_address, uint64_t *buffer) "b"(0x800603FC00000000), "r"(reg_address << 3)); eieio(); + return *buffer; } void write_scom_direct(uint32_t, uint64_t*); @@ -89,7 +90,7 @@ uint64_t read_hmer(void) #define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) #define PPC_BITMASK(bs,be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) #define XSCOM_ADDR_IND_FLAG PPC_BIT(0) -#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(12,31) +#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(11,31) #define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63) #define XSCOM_DATA_IND_READ PPC_BIT(0) @@ -104,32 +105,54 @@ void write_scom_indirect(uint64_t reg_address, uint64_t value) { uint64_t addr; uint64_t data; + uint64_t tmp; addr = reg_address & 0x7FFFFFFF; data = reg_address & XSCOM_ADDR_IND_ADDR; data |= value & XSCOM_ADDR_IND_DATA; printk(BIOS_EMERG, "----------------\n"); printk(BIOS_EMERG, "SCOM WRITE\n\n"); - printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + (long long unsigned int)read_scom_direct(0x90010, &tmp), + (long long unsigned int)read_scom_direct(0x90011, &tmp), + (long long unsigned int)read_scom_direct(0x90012, &tmp), + (long long unsigned int)read_scom_direct(0x90013, &tmp)); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } write_scom_direct(addr, &data); - printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + (long long unsigned int)read_scom_direct(0x90010, &tmp), + (long long unsigned int)read_scom_direct(0x90011, &tmp), + (long long unsigned int)read_scom_direct(0x90012, &tmp), + (long long unsigned int)read_scom_direct(0x90013, &tmp)); for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { printk(BIOS_EMERG, "READING addr = %llX\n", addr); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } read_scom_direct(addr, &data); - printk(BIOS_EMERG, "READ data = %llX\n", data); - printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + (long long unsigned int)read_scom_direct(0x90010, &tmp), + (long long unsigned int)read_scom_direct(0x90011, &tmp), + (long long unsigned int)read_scom_direct(0x90012, &tmp), + (long long unsigned int)read_scom_direct(0x90013, &tmp)); + printk(BIOS_EMERG, "READ data = %llX\n", data); if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { printk(BIOS_EMERG, "SUCCESS\n"); printk(BIOS_EMERG, "----------------\n"); @@ -148,27 +171,54 @@ void read_scom_indirect(uint64_t reg_address, uint64_t *buffer) { uint64_t addr; uint64_t data; + uint64_t tmp; addr = reg_address & 0x7FFFFFFF; data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR); printk(BIOS_EMERG, "----------------\n"); printk(BIOS_EMERG, "SCOM READ\n\n"); - printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + (long long unsigned int)read_scom_direct(0x90010, &tmp), + (long long unsigned int)read_scom_direct(0x90011, &tmp), + (long long unsigned int)read_scom_direct(0x90012, &tmp), + (long long unsigned int)read_scom_direct(0x90013, &tmp)); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } write_scom_direct(addr, &data); - printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + (long long unsigned int)read_scom_direct(0x90010, &tmp), + (long long unsigned int)read_scom_direct(0x90011, &tmp), + (long long unsigned int)read_scom_direct(0x90012, &tmp), + (long long unsigned int)read_scom_direct(0x90013, &tmp)); for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { printk(BIOS_EMERG, "READING addr = %llX\n", addr); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } read_scom_direct(addr, &data); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + (long long unsigned int)read_scom_direct(0x90010, &tmp), + (long long unsigned int)read_scom_direct(0x90011, &tmp), + (long long unsigned int)read_scom_direct(0x90012, &tmp), + (long long unsigned int)read_scom_direct(0x90013, &tmp)); printk(BIOS_EMERG, "READ data = %llX\n", data); - printk(BIOS_EMERG, "hmer = %llX, fail = %llX, done = %llX, status = %llX\n", + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, @@ -192,6 +242,13 @@ void run_romstage(void) { uint64_t buffer; long long unsigned int hmer = 0; + uint64_t tmp; + read_scom_direct(0x7000001, &tmp); + printk(BIOS_EMERG, "0x7000001 = %llX\n", tmp); + tmp = 0; + write_scom_direct(0x7000001, &tmp); + read_scom_direct(0x7000001, &tmp); + printk(BIOS_EMERG, "0x7000001 = %llX\n", tmp); asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); read_scom_indirect(0x8000C8000701103Full, &buffer); buffer = 0x7777777777777777; From 8538e8c15edc549ee08b16634cb8361f4d27406f Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Thu, 21 Jan 2021 15:10:10 +0100 Subject: [PATCH 51/90] src/mainboard/raptor-cs/talos-2/mainboard.c: implement istep reporting --- src/mainboard/raptor-cs/talos-2/mainboard.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/raptor-cs/talos-2/mainboard.c b/src/mainboard/raptor-cs/talos-2/mainboard.c index 54ae445b5fd..dee5b796fde 100644 --- a/src/mainboard/raptor-cs/talos-2/mainboard.c +++ b/src/mainboard/raptor-cs/talos-2/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,3 +20,9 @@ static void mainboard_enable(struct device *dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + +static inline void report_istep(uint8_t step, uint8_t substep) +{ + outb(step, 0x81); + outb(substep, 0x82); +} From 73a126691b0180120763b5ef9eae2357aa47ca26 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 25 Jan 2021 08:13:04 +0100 Subject: [PATCH 52/90] src/arch/ppc64/include/arch/io.h: Move report_istep() --- src/arch/ppc64/include/arch/io.h | 6 ++++++ src/mainboard/raptor-cs/talos-2/mainboard.c | 7 ------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index a9287ca801a..132a5ce353d 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -58,4 +58,10 @@ static inline uint32_t inl(uint16_t port) return buffer; } +static inline void report_istep(uint8_t step, uint8_t substep) +{ + outb(step, 0x81); + outb(substep, 0x82); +} + #endif diff --git a/src/mainboard/raptor-cs/talos-2/mainboard.c b/src/mainboard/raptor-cs/talos-2/mainboard.c index dee5b796fde..54ae445b5fd 100644 --- a/src/mainboard/raptor-cs/talos-2/mainboard.c +++ b/src/mainboard/raptor-cs/talos-2/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -20,9 +19,3 @@ static void mainboard_enable(struct device *dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - -static inline void report_istep(uint8_t step, uint8_t substep) -{ - outb(step, 0x81); - outb(substep, 0x82); -} From 0d43c169103047c43238caf9b77840c481f1b458 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 3 Feb 2021 12:25:08 +0100 Subject: [PATCH 53/90] README.md: add info about Insurgo GitHub MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index 14879c14842..d041f6c3b30 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,8 @@ +## Contributing + +All relevant chnages to OpenPOWER Talos II should go here: +https://github.com/InsurgoTech/coreboot + coreboot README =============== From f25013bccea649e1a79c04809e78a0461689629f Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 5 Feb 2021 13:40:41 +0100 Subject: [PATCH 54/90] cpu/power9: move SCOM access functions to a separate file Signed-off-by: Krystian Hebel --- src/arch/ppc64/include/arch/byteorder.h | 3 + src/cpu/power/power9/scom.c | 159 +++++++++++++++++ src/include/cpu/power/scom.h | 152 +++++++++++++++++ src/include/cpu/power/spr.h | 34 ++++ src/lib/prog_loaders.c | 216 +----------------------- 5 files changed, 349 insertions(+), 215 deletions(-) create mode 100644 src/cpu/power/power9/scom.c create mode 100644 src/include/cpu/power/scom.h create mode 100644 src/include/cpu/power/spr.h diff --git a/src/arch/ppc64/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h index 79f15b1eb32..a785db4839c 100644 --- a/src/arch/ppc64/include/arch/byteorder.h +++ b/src/arch/ppc64/include/arch/byteorder.h @@ -5,4 +5,7 @@ #define __BIG_ENDIAN 4321 +#define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) +#define PPC_BITMASK(bs,be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) + #endif /* _BYTEORDER_H */ diff --git a/src/cpu/power/power9/scom.c b/src/cpu/power/power9/scom.c new file mode 100644 index 00000000000..76269b5d3c0 --- /dev/null +++ b/src/cpu/power/power9/scom.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include // HMER +#include + +#define XSCOM_DATA_IND_READ PPC_BIT(0) +#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) +#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63) +#define XSCOM_IND_MAX_RETRIES 10 + +/* + * WARNING: + * Indirect access uses the same approach as Hostboot, yet all our tests so far + * were unsuccessful. It is possible that the devices we were trying to access + * must be initialized or otherwise enabled first. Because of that we decided to + * leave it as it is for now, with heavy debugging, and return to this when we + * are sure that it doesn't work because of error in implementation. + */ +void write_scom_indirect(uint64_t reg_address, uint64_t value) +{ + uint64_t addr; + uint64_t data; + addr = reg_address & 0x7FFFFFFF; + data = reg_address & XSCOM_ADDR_IND_ADDR; + data |= value & XSCOM_ADDR_IND_DATA; + printk(BIOS_EMERG, "----------------\n"); + printk(BIOS_EMERG, "SCOM WRITE\n\n"); + /* + * Reading 0x90013 here doesn't make sense. This register reports errors in + * the most recent XSCOM access, and is cleared as soon as a new access is + * attempted, meaning we can only see that reading 0x90013 was successful. + * It is possible to read this register through 'pdbg' from BMC which + * doesn't use XSCOM, in which case 0x90013 isn't polluted. + */ + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + read_scom_direct(0x90010), + read_scom_direct(0x90011), + read_scom_direct(0x90012), + read_scom_direct(0x90013)); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } + write_scom_direct(addr, data); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + read_scom_direct(0x90010), + read_scom_direct(0x90011), + read_scom_direct(0x90012), + read_scom_direct(0x90013)); + for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { + printk(BIOS_EMERG, "READING addr = %llX\n", addr); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } + data = read_scom_direct(addr); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + read_scom_direct(0x90010), + read_scom_direct(0x90011), + read_scom_direct(0x90012), + read_scom_direct(0x90013)); + printk(BIOS_EMERG, "READ data = %llX\n", data); + if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { + printk(BIOS_EMERG, "SUCCESS\n"); + printk(BIOS_EMERG, "----------------\n"); + return; + } + else if(data & XSCOM_DATA_IND_COMPLETE) { + printk(BIOS_EMERG, "FINISHED WITH ERROR\n"); + printk(BIOS_EMERG, "----------------\n"); + return; + } + } +} + +uint64_t read_scom_indirect(uint64_t reg_address) +{ + uint64_t addr; + uint64_t data = -1; + addr = reg_address & 0x7FFFFFFF; + data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR); + printk(BIOS_EMERG, "----------------\n"); + printk(BIOS_EMERG, "SCOM READ\n\n"); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + read_scom_direct(0x90010), + read_scom_direct(0x90011), + read_scom_direct(0x90012), + read_scom_direct(0x90013)); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } + write_scom_direct(addr, data); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + read_scom_direct(0x90010), + read_scom_direct(0x90011), + read_scom_direct(0x90012), + read_scom_direct(0x90013)); + for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { + printk(BIOS_EMERG, "READING addr = %llX\n", addr); + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } + data = read_scom_direct(addr); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", + read_scom_direct(0x90010), + read_scom_direct(0x90011), + read_scom_direct(0x90012), + read_scom_direct(0x90013)); + printk(BIOS_EMERG, "READ data = %llX\n", data); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), + read_hmer() & SPR_HMER_XSCOM_FAIL, + read_hmer() & SPR_HMER_XSCOM_DONE, + read_hmer() & SPR_HMER_XSCOM_STATUS); + if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { + printk(BIOS_EMERG, "SUCCESS\n"); + printk(BIOS_EMERG, "----------------\n"); + } + else if(data & XSCOM_DATA_IND_COMPLETE) { + printk(BIOS_EMERG, "FINISHED WITH ERROR\n"); + printk(BIOS_EMERG, "----------------\n"); + } + } + + return data & XSCOM_DATA_IND_DATA; +} diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h new file mode 100644 index 00000000000..a839f84c619 --- /dev/null +++ b/src/include/cpu/power/scom.h @@ -0,0 +1,152 @@ +#ifndef CPU_PPC64_SCOM_H +#define CPU_PPC64_SCOM_H + +#include // PPC_BIT(), PPC_BITMASK() + +// 32b SCOM address: +// +// 8 7 6 5 4 3 2 1 +// +// |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31| +// {A}{ B } { C } { D }{ E }{ F } +// +// A - Is multiCast if bit 1 = 0x1 +// B - Contains Chiplet ID (6 bits) [2:7] +// C - Contains Port Number (4 bits) [12:15] +// D - Ring (4 bits) [18:21] +// E - Sat ID (4 bits) [22:25] +// F - Sat Offset (6 bits) [26:31] +// +// For 64b SCOM address all of the fields are shifted 32b to the right: +// A - Is multiCast if bit 33 = 0x1 +// B - Contains Chiplet ID (6 bits) [34:39] +// C - Contains Port Number (4 bits) [44:47] +// D - Ring (4 bits) [50:53] +// E - Sat ID (4 bits) [54:57] +// F - Sat Offset (6 bits) [58:63] +// Higher bits specify indirect address + +#define XSCOM_ADDR_IND_FLAG PPC_BIT(0) +#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(11,31) +#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63) + +#ifndef __ASSEMBLER__ +#include +#include + +// TODO: these are probably specific to POWER9 +typedef enum +{ + PIB_CHIPLET_ID = 0x00, ///< PIB chiplet + PERV_CHIPLET_ID = 0x01, ///< TP chiplet + N0_CHIPLET_ID = 0x02, ///< Nest0 (North) chiplet + N1_CHIPLET_ID = 0x03, ///< Nest1 (East) chiplet + N2_CHIPLET_ID = 0x04, ///< Nest2 (South) chiplet + N3_CHIPLET_ID = 0x05, ///< Nest3 (West) chiplet + XB_CHIPLET_ID = 0x06, ///< XBus chiplet + MC01_CHIPLET_ID = 0x07, ///< MC01 (West) chiplet + MC23_CHIPLET_ID = 0x08, ///< MC23 (East) chiplet + OB0_CHIPLET_ID = 0x09, ///< OBus0 chiplet + OB1_CHIPLET_ID = 0x0A, ///< OBus1 chiplet (Cumulus only) + OB2_CHIPLET_ID = 0x0B, ///< OBus2 chiplet (Cumulus only) + OB3_CHIPLET_ID = 0x0C, ///< OBus3 chiplet + PCI0_CHIPLET_ID = 0x0D, ///< PCIe0 chiplet + PCI1_CHIPLET_ID = 0x0E, ///< PCIe1 chiplet + PCI2_CHIPLET_ID = 0x0F, ///< PCIe2 chiplet + EP00_CHIPLET_ID = 0x10, ///< Quad0 chiplet (EX0/1) + EP01_CHIPLET_ID = 0x11, ///< Quad1 chiplet (EX2/3) + EP02_CHIPLET_ID = 0x12, ///< Quad2 chiplet (EX4/5) + EP03_CHIPLET_ID = 0x13, ///< Quad3 chiplet (EX6/7) + EP04_CHIPLET_ID = 0x14, ///< Quad4 chiplet (EX8/9) + EP05_CHIPLET_ID = 0x15, ///< Quad5 chiplet (EX10/11) + EC00_CHIPLET_ID = 0x20, ///< Core0 chiplet (Quad0, EX0, C0) + EC01_CHIPLET_ID = 0x21, ///< Core1 chiplet (Quad0, EX0, C1) + EC02_CHIPLET_ID = 0x22, ///< Core2 chiplet (Quad0, EX1, C0) + EC03_CHIPLET_ID = 0x23, ///< Core3 chiplet (Quad0, EX1, C1) + EC04_CHIPLET_ID = 0x24, ///< Core4 chiplet (Quad1, EX2, C0) + EC05_CHIPLET_ID = 0x25, ///< Core5 chiplet (Quad1, EX2, C1) + EC06_CHIPLET_ID = 0x26, ///< Core6 chiplet (Quad1, EX3, C0) + EC07_CHIPLET_ID = 0x27, ///< Core7 chiplet (Quad1, EX3, C1) + EC08_CHIPLET_ID = 0x28, ///< Core8 chiplet (Quad2, EX4, C0) + EC09_CHIPLET_ID = 0x29, ///< Core9 chiplet (Quad2, EX4, C1) + EC10_CHIPLET_ID = 0x2A, ///< Core10 chiplet (Quad2, EX5, C0) + EC11_CHIPLET_ID = 0x2B, ///< Core11 chiplet (Quad2, EX5, C1) + EC12_CHIPLET_ID = 0x2C, ///< Core12 chiplet (Quad3, EX6, C0) + EC13_CHIPLET_ID = 0x2D, ///< Core13 chiplet (Quad3, EX6, C1) + EC14_CHIPLET_ID = 0x2E, ///< Core14 chiplet (Quad3, EX7, C0) + EC15_CHIPLET_ID = 0x2F, ///< Core15 chiplet (Quad3, EX7, C1) + EC16_CHIPLET_ID = 0x30, ///< Core16 chiplet (Quad4, EX8, C0) + EC17_CHIPLET_ID = 0x31, ///< Core17 chiplet (Quad4, EX8, C1) + EC18_CHIPLET_ID = 0x32, ///< Core18 chiplet (Quad4, EX9, C0) + EC19_CHIPLET_ID = 0x33, ///< Core19 chiplet (Quad4, EX9, C1) + EC20_CHIPLET_ID = 0x34, ///< Core20 chiplet (Quad5, EX10, C0) + EC21_CHIPLET_ID = 0x35, ///< Core21 chiplet (Quad5, EX10, C1) + EC22_CHIPLET_ID = 0x36, ///< Core22 chiplet (Quad5, EX11, C0) + EC23_CHIPLET_ID = 0x37 ///< Core23 chiplet (Quad5, EX11, C1) +} chiplet_id_t; + +static uint64_t read_scom_direct(uint64_t reg_address) +{ + uint64_t val; + asm volatile( + "ldcix %0, %1, %2": + "=r"(val): + "b"(0x800603FC00000000), + "r"(reg_address << 3)); + eieio(); + return val; +} + +static void write_scom_direct(uint64_t reg_address, uint64_t data) +{ + asm volatile( + "stdcix %0, %1, %2":: + "r"(data), + "b"(0x800603FC00000000), + "r"(reg_address << 3)); + eieio(); +} + +/* + * WARNING: + * Indirect access uses the same approach as Hostboot, yet all our tests so far + * were unsuccessful. It is possible that the devices we were trying to access + * must be initialized or otherwise enabled first. Because of that we decided to + * leave it as it is for now, with heavy debugging, and return to this when we + * are sure that it doesn't work because of error in implementation. + */ +uint64_t read_scom_indirect(uint64_t reg_address); +void write_scom_indirect(uint64_t reg_address, uint64_t data); + +static inline void write_scom(uint64_t addr, uint64_t data) +{ + if (addr & XSCOM_ADDR_IND_FLAG) + write_scom_indirect(addr, data); + else + write_scom_direct(addr, data); +} + +static inline uint64_t read_scom(uint64_t addr) +{ + if (addr & XSCOM_ADDR_IND_FLAG) + return read_scom_indirect(addr); + else + return read_scom_direct(addr); +} + +static inline void write_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t data) +{ + addr &= ~PPC_BITMASK(34,39); + addr |= ((chiplet & 0x3F) << 24); + write_scom(addr, data); +} + +static inline uint64_t read_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr) +{ + addr &= ~PPC_BITMASK(34,39); + addr |= ((chiplet & 0x3F) << 24); + return read_scom(addr); +} + +#endif /* __ASSEMBLER__ */ +#endif /* CPU_PPC64_SCOM_H */ diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h new file mode 100644 index 00000000000..843de245114 --- /dev/null +++ b/src/include/cpu/power/spr.h @@ -0,0 +1,34 @@ +#ifndef CPU_PPC64_SPR_H +#define CPU_PPC64_SPR_H + +#include // PPC_BIT() + +#define SPR_HMER 0x150 +/* Bits in HMER/HMEER */ +#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) +#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) +#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) +#define SPR_HMER_TFAC_ERROR PPC_BIT(4) +#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) +#define SPR_HMER_XSCOM_FAIL PPC_BIT(8) +#define SPR_HMER_XSCOM_DONE PPC_BIT(9) +#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) +#define SPR_HMER_WARN_RISE PPC_BIT(14) +#define SPR_HMER_WARN_FALL PPC_BIT(15) +#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) +#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) +#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) +#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) + +#ifndef __ASSEMBLER__ +#include + +static inline uint64_t read_hmer(void) +{ + uint64_t val; + asm volatile("mfspr %0,%1" : "=r"(val) : "i"(SPR_HMER) : "memory"); + return val; +} + +#endif /* __ASSEMBLER__ */ +#endif /* CPU_PPC64_SPR_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 13eee91fc97..93efc0a2806 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -17,7 +17,6 @@ #include #include #include -#include /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = @@ -40,224 +39,11 @@ int prog_locate(struct prog *prog) return 0; } -/* Bits in HMER/HMEER */ -#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) -#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) -#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) -#define SPR_HMER_TFAC_ERROR PPC_BIT(4) -#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) -#define SPR_HMER_XSCOM_FAIL PPC_BIT(8) -#define SPR_HMER_XSCOM_DONE PPC_BIT(9) -#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) -#define SPR_HMER_WARN_RISE PPC_BIT(14) -#define SPR_HMER_WARN_FALL PPC_BIT(15) -#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) -#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) -#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) -#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) - -uint64_t read_scom_direct(uint32_t, uint64_t*); -uint64_t read_scom_direct(uint32_t reg_address, uint64_t *buffer) -{ - asm volatile( - "ldcix %0, %1, %2": - "=r"(*buffer): - "b"(0x800603FC00000000), - "r"(reg_address << 3)); - eieio(); - return *buffer; -} - -void write_scom_direct(uint32_t, uint64_t*); -void write_scom_direct(uint32_t reg_address, uint64_t *buffer) -{ - asm volatile( - "stdcix %0, %1, %2":: - "b"(*buffer), - "b"(0x800603FC00000000), - "r"(reg_address << 3)); - eieio(); -} - -uint64_t read_hmer(void); -uint64_t read_hmer(void) -{ - unsigned long val; - asm volatile("mfspr %0,%1" : "=r"(val) : "i"(0x150) : "memory"); - return val; -} - -#define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) -#define PPC_BITMASK(bs,be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) -#define XSCOM_ADDR_IND_FLAG PPC_BIT(0) -#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(11,31) -#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63) - -#define XSCOM_DATA_IND_READ PPC_BIT(0) -#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) -#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) -#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) -#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63) -#define XSCOM_IND_MAX_RETRIES 10 - -void write_scom_indirect(uint64_t, uint64_t); -void write_scom_indirect(uint64_t reg_address, uint64_t value) -{ - uint64_t addr; - uint64_t data; - uint64_t tmp; - addr = reg_address & 0x7FFFFFFF; - data = reg_address & XSCOM_ADDR_IND_ADDR; - data |= value & XSCOM_ADDR_IND_DATA; - printk(BIOS_EMERG, "----------------\n"); - printk(BIOS_EMERG, "SCOM WRITE\n\n"); - printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", - (long long unsigned int)read_scom_direct(0x90010, &tmp), - (long long unsigned int)read_scom_direct(0x90011, &tmp), - (long long unsigned int)read_scom_direct(0x90012, &tmp), - (long long unsigned int)read_scom_direct(0x90013, &tmp)); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); - for(unsigned int i = 0; i < 0xFFFF; ++i) { - asm volatile("nop" :::"memory"); - } - write_scom_direct(addr, &data); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", - (long long unsigned int)read_scom_direct(0x90010, &tmp), - (long long unsigned int)read_scom_direct(0x90011, &tmp), - (long long unsigned int)read_scom_direct(0x90012, &tmp), - (long long unsigned int)read_scom_direct(0x90013, &tmp)); - for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { - printk(BIOS_EMERG, "READING addr = %llX\n", addr); - for(unsigned int i = 0; i < 0xFFFF; ++i) { - asm volatile("nop" :::"memory"); - } - read_scom_direct(addr, &data); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", - (long long unsigned int)read_scom_direct(0x90010, &tmp), - (long long unsigned int)read_scom_direct(0x90011, &tmp), - (long long unsigned int)read_scom_direct(0x90012, &tmp), - (long long unsigned int)read_scom_direct(0x90013, &tmp)); - printk(BIOS_EMERG, "READ data = %llX\n", data); - if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { - printk(BIOS_EMERG, "SUCCESS\n"); - printk(BIOS_EMERG, "----------------\n"); - return; - } - else if(data & XSCOM_DATA_IND_COMPLETE) { - printk(BIOS_EMERG, "FINISHED WITH ERROR\n"); - printk(BIOS_EMERG, "----------------\n"); - return; - } - } -} - -void read_scom_indirect(uint64_t, uint64_t*); -void read_scom_indirect(uint64_t reg_address, uint64_t *buffer) -{ - uint64_t addr; - uint64_t data; - uint64_t tmp; - addr = reg_address & 0x7FFFFFFF; - data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR); - printk(BIOS_EMERG, "----------------\n"); - printk(BIOS_EMERG, "SCOM READ\n\n"); - printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", - (long long unsigned int)read_scom_direct(0x90010, &tmp), - (long long unsigned int)read_scom_direct(0x90011, &tmp), - (long long unsigned int)read_scom_direct(0x90012, &tmp), - (long long unsigned int)read_scom_direct(0x90013, &tmp)); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); - for(unsigned int i = 0; i < 0xFFFF; ++i) { - asm volatile("nop" :::"memory"); - } - write_scom_direct(addr, &data); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", - (long long unsigned int)read_scom_direct(0x90010, &tmp), - (long long unsigned int)read_scom_direct(0x90011, &tmp), - (long long unsigned int)read_scom_direct(0x90012, &tmp), - (long long unsigned int)read_scom_direct(0x90013, &tmp)); - for(int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { - printk(BIOS_EMERG, "READING addr = %llX\n", addr); - for(unsigned int i = 0; i < 0xFFFF; ++i) { - asm volatile("nop" :::"memory"); - } - read_scom_direct(addr, &data); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - printk(BIOS_EMERG, "*0x90010 = %llX,\n*0x90011 = %llX,\n*0x90012 = %llX,\n*0x90013 = %llX\n", - (long long unsigned int)read_scom_direct(0x90010, &tmp), - (long long unsigned int)read_scom_direct(0x90011, &tmp), - (long long unsigned int)read_scom_direct(0x90012, &tmp), - (long long unsigned int)read_scom_direct(0x90013, &tmp)); - printk(BIOS_EMERG, "READ data = %llX\n", data); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), - read_hmer() & SPR_HMER_XSCOM_FAIL, - read_hmer() & SPR_HMER_XSCOM_DONE, - read_hmer() & SPR_HMER_XSCOM_STATUS); - if((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { - *buffer = data & XSCOM_DATA_IND_DATA; - printk(BIOS_EMERG, "SUCCESS\n"); - printk(BIOS_EMERG, "----------------\n"); - return; - } - else if(data & XSCOM_DATA_IND_COMPLETE) { - printk(BIOS_EMERG, "FINISHED WITH ERROR\n"); - printk(BIOS_EMERG, "----------------\n"); - return; - } - } - -} - void run_romstage(void) { - uint64_t buffer; - long long unsigned int hmer = 0; - uint64_t tmp; - read_scom_direct(0x7000001, &tmp); - printk(BIOS_EMERG, "0x7000001 = %llX\n", tmp); - tmp = 0; - write_scom_direct(0x7000001, &tmp); - read_scom_direct(0x7000001, &tmp); - printk(BIOS_EMERG, "0x7000001 = %llX\n", tmp); - asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); - read_scom_indirect(0x8000C8000701103Full, &buffer); - buffer = 0x7777777777777777; - asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); - write_scom_indirect(0x8000C8000701103Full, buffer); - asm volatile("mtspr 336, %0" :: "r" (hmer) : "memory"); - read_scom_indirect(0x8000C8000701103Full, &buffer); struct prog romstage = PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); + vboot_run_logic(); if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { From 9bd542a67ee6770942fcaf2970c8d9a31da4c16e Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 5 Feb 2021 13:48:41 +0100 Subject: [PATCH 55/90] cpu/power9: add directory to Makefile's subdirs Also fix a typo and a build issue caused by incomplete type. Signed-off-by: Krystian Hebel --- src/cpu/Makefile.inc | 1 + src/cpu/power/power9/Makefile.inc | 5 ++++- src/cpu/power/power9/power9.c | 9 +++++---- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index a072a8b2321..3a61b3eeb9d 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += intel subdirs-y += ti subdirs-$(CONFIG_ARCH_X86) += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 +subdirs-$(CONFIG_CPU_POWER9) += power/power9 $(eval $(call create_class_compiler,cpu_microcode,x86_32)) ################################################################################ diff --git a/src/cpu/power/power9/Makefile.inc b/src/cpu/power/power9/Makefile.inc index 8b721e56388..2fe9e57a96d 100644 --- a/src/cpu/power/power9/Makefile.inc +++ b/src/cpu/power/power9/Makefile.inc @@ -1,3 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -ramstage-y += power9c.c +ramstage-y += power9.c + +bootblock-y += scom.c +romstage-y += scom.c diff --git a/src/cpu/power/power9/power9.c b/src/cpu/power/power9/power9.c index d86f5a3cc91..73361fe3141 100644 --- a/src/cpu/power/power9/power9.c +++ b/src/cpu/power/power9/power9.c @@ -11,13 +11,14 @@ static struct device_operations cpu_dev_ops = { .init = power9_cpu_init, }; -static const struct cpu_device_id cpu_table[] = { - { 0, 0 }, -}; +// FIXME: cpu_device_id is not defined for ppc64 +// static const struct cpu_device_id cpu_table[] = { +// { 0, 0 }, +// }; static const struct cpu_driver driver __cpu_driver = { .ops = &cpu_dev_ops, - .id_table = cpu_table, + // .id_table = cpu_table, }; struct chip_operations cpu_power8_qemu_ops = { From 9f2de5d36f2ba8ff9c54a2ebe9d778def0aeb78f Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 5 Feb 2021 13:50:51 +0100 Subject: [PATCH 56/90] Makefile.inc: add ECC for CBFS on POWER9 This may change after final PNOR layout is established. For now it eases development and testing. Signed-off-by: Krystian Hebel --- Makefile.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 81b652ec9d3..0cda398a758 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1163,7 +1163,10 @@ ifeq ($(CONFIG_ARCH_PPC64),y) @printf " SBSIGN $(subst $(obj)/,,$(@))\n" cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$(objcbfs)/bootblock.bin $(top)/$(obj)/bootblock.signed 2> /dev/null cd $(SBSINGTOOLS) && ./sign-with-local-keys.sh $(top)/$@ $(top)/$@.signed 2> /dev/null - @printf " ECC bootblock\n" + @printf " ECC $(subst $(obj)/,,$(@))\n" + $(ECCTOOL) --inject $(top)/$@.signed --output $(top)/$@.signed.ecc --p8 + $(ECCTOOL) --inject $(top)/$@ --output $(top)/$@.ecc --p8 + @printf " ECC bootblock\n" dd if=$(obj)/bootblock.signed of=$(obj)/bootblock.signed.pad ibs=25486 conv=sync 2> /dev/null $(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8 rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad From 36e4c1f43eab6441fd8b926db582323e9c92e019 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 5 Feb 2021 17:40:38 +0100 Subject: [PATCH 57/90] tmp: move further stages higher in memory Signed-off-by: Krystian Hebel --- src/mainboard/raptor-cs/talos-2/memlayout.ld | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld index b024a29c931..c5136b9d14e 100644 --- a/src/mainboard/raptor-cs/talos-2/memlayout.ld +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -9,10 +9,10 @@ SECTIONS { DRAM_START(0x0) BOOTBLOCK(0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - FMAP_CACHE(0x82000, 2K) - CBFS_MCACHE(0x82800, 8K) - RAMSTAGE(0x100000, 16M) + ROMSTAGE(0x120000, 128K) + STACK(0x140000, 0x3ff00) + PRERAM_CBMEM_CONSOLE(0x180000, 8K) + FMAP_CACHE(0x182000, 2K) + CBFS_MCACHE(0x182800, 8K) + RAMSTAGE(0x200000, 16M) } From 3aa0f03abb86f44879a7964b595589c1db55b752 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Mon, 8 Feb 2021 12:11:23 +0100 Subject: [PATCH 58/90] arch/ppc64/bootblock_crt0.S: enable vector operations Vector operations are sometimes generated for code such as 'uint8_t x[32] = {0}', this results in an exception when vector registers (VR) are not enabled. VSR (vector-scalar register) operations are also enabled, there is no reason not to. Signed-off-by: Krystian Hebel --- src/arch/ppc64/bootblock_crt0.S | 11 +++++++++++ src/include/cpu/power/spr.h | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S index 88b853dec8d..b688b7478b7 100644 --- a/src/arch/ppc64/bootblock_crt0.S +++ b/src/arch/ppc64/bootblock_crt0.S @@ -56,6 +56,17 @@ _start: blt cr7, 1b */ + /* Enable floating point and vector operations */ + /* Vector operations are sometimes generated for code like + * 'uint8_t x[32] = {0}', this results in an exception when vector registers + * (VEC) are not enabled. VSX (vector-scalar extension) is also enabled, + * there is no reason not to. Floating point must also be enabled for VSX. + */ + mfmsr %r3 + ori %r3, %r3, 0x2000 /* FP = 1 */ + oris %r3, %r3, 0x0280 /* VEC = 1, VSX = 1 */ + mtmsr %r3 + /* Load official procedure descriptor address for main() */ lis %r12, main@ha addi %r12, %r12, main@l diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h index 843de245114..59c089d8ef9 100644 --- a/src/include/cpu/power/spr.h +++ b/src/include/cpu/power/spr.h @@ -30,5 +30,12 @@ static inline uint64_t read_hmer(void) return val; } +static inline uint64_t read_msr(void) +{ + uint64_t val; + asm volatile("mfmsr %0" : "=r"(val) :: "memory"); + return val; +} + #endif /* __ASSEMBLER__ */ #endif /* CPU_PPC64_SPR_H */ From 1cbc6a10930032294d75bb2b6b38675bef416aeb Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Thu, 11 Feb 2021 14:56:14 +0100 Subject: [PATCH 59/90] src/mainboard/raptor-cs/talos-2/romstage.c: scom_init initial --- src/cpu/power/power9/scom.c | 7 +- src/mainboard/raptor-cs/talos-2/romstage.c | 227 +++++++++++++++++++++ 2 files changed, 228 insertions(+), 6 deletions(-) diff --git a/src/cpu/power/power9/scom.c b/src/cpu/power/power9/scom.c index 76269b5d3c0..6d016fb285b 100644 --- a/src/cpu/power/power9/scom.c +++ b/src/cpu/power/power9/scom.c @@ -109,12 +109,7 @@ uint64_t read_scom_indirect(uint64_t reg_address) read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); - for(unsigned int i = 0; i < 0xFFFF; ++i) { - asm volatile("nop" :::"memory"); - } - write_scom_direct(addr, data); - printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", - read_hmer(), + for(unsigned intwrite_scom_indirect read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index c4123152554..9ffe989d318 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -3,8 +3,235 @@ #include #include +#include + +#define X0_ENABLED true +#define X2_ENABLED true +#define DD2X_PARTS true + +void istep89() +{ + printk(BIOS_EMERG, "starting istep 8.9\n"); + p9_fbc_no_hp_scom(); + printk(BIOS_EMERG, "ending istep 8.9\n"); +} + +void p9_fbc_no_hp_scom() +{ + uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom(0x501340A); // Processor bus Electrical Framer/Parser 01 configuration register + uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom(0x501340B); // Power Bus Electrical Framer/Parser 23 Configuration Register + uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom(0x501340C); // Power Bus Electrical Framer/Parser 45 Configuration Register + uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom(0x5013410); // Power Bus Electrical Link Data Buffer 01 Configuration Register + uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom(0x5013411); // Power Bus Electrical Link Data Buffer 23 Configuration Register + uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom(0x5013412); // Power Bus Electrical Link Data Buffer 45 Configuration Register + uint64_t pb_ioe_scom_pb_misc_cfg = read_scom(0x5013423); // Power Bus Electrical Miscellaneous Configuration Register + uint64_t pb_ioe_scom_pb_trace_cfg = read_scom(0x5013424); // Power Bus Electrical Link Trace Configuration Register + + if(X0_ENABLED) + { + pb_ioe_scom_pb_fp01_cfg &= 0xfff004fffff007bf; + pb_ioe_scom_pb_fp01_cfg |= 0x0002010000020000; + } + else + { + pb_ioe_scom_pb_fp01_cfg |= 0x84000000840; + } + + // if(X0_ENABLED && DD2X_PARTS) + // { + // PB_IOE_SCOM_PB_FP01_CFG.insert<4, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) + // PB_IOE_SCOM_PB_FP01_CFG.insert<36, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) + // } + // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) + // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && DD1_LO_LIMIT_P)) + // { + // PB_IOE_SCOM_PB_FP01_CFG.insert<4, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + // PB_IOE_SCOM_PB_FP01_CFG.insert<36, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + // } + // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && !DD1_LO_LIMIT_P) + // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R > DD1_LO_LIMIT_H)) + // { + // PB_IOE_SCOM_PB_FP01_CFG.insert<4, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + // PB_IOE_SCOM_PB_FP01_CFG.insert<36, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + // } + if(X2_ENABLED) + { + pb_ioe_scom_pb_fp45_cfg &= 0xfff004bffff007bf; + pb_ioe_scom_pb_fp45_cfg |= 0x0002010000020000; + } + else + { + pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; + } + if (x2_enabled && l_def_dd2x_parts) + { + pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) + pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) + } + else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R < l_def_DD1_LO_LIMIT_H) + || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && l_def_DD1_LO_LIMIT_P)) + { + pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + } + else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && !l_def_DD1_LO_LIMIT_P) + || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R > l_def_DD1_LO_LIMIT_H)) + { + pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + } + + if (l_def_X0_ENABLED)IOEL_REPLAY_THRESHOLD // FIXME: there can be some missing code + { + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFFFFFF07FFFFFFFF + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000008000000000 + } + else + { + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x000000F800000000 + } + if (l_TGT0_ATTR_CHIP_EC_FEATURE_HW384245 != 0) + { + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x3F0000003F000000 + } + else + { + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x4000000040000000 + } + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFF8080FFFF8080FF + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x003C3C00003C3C00 + + pb_ioe_scom_pb_trace_cfg &= 0x0000FFFFFFFFFFFF + pb_ioe_scom_pb_trace_cfg |= 0x4141000000000000 + } + else if (l_def_X1_ENABLED) + { + pb_ioe_scom_pb_trace_cfg &= 0xFFFF0000FFFFFFFF + pb_ioe_scom_pb_trace_cfg |= 0x0000414100000000 + } + else if (l_def_X2_ENABLED) + { + pb_ioe_scom_pb_trace_cfg &= 0xFFFFFFFF0000FFFF + pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000 + } + + if (l_def_X1_ENABLED && l_def_DD2X_PARTS) + { + PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) + PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) + } + else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R < l_def_DD1_LO_LIMIT_H) + || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && l_def_DD1_LO_LIMIT_P)) + { + PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + } + else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && !l_def_DD1_LO_LIMIT_P) + || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R > l_def_DD1_LO_LIMIT_H)) + { + PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + } + + + if(l_def_X1_ENABLED) + { + PB_IOE_SCOM_PB_FP23_CFG &= 0xfff004bffff007bf + PB_IOE_SCOM_PB_FP23_CFG |= 0x0002010000020000 + if (l_def_OPTICS_IS_A_BUS) + { + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0xFE0FFFFFFFFFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x0100000000000000 + } + else + { + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0xFE0FFFFFFFFFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x01F0000000000000 + } + if (l_TGT0_ATTR_CHIP_EC_FEATURE_HW384245 != 0) + { + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0x80FFFFFF80FFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x3F0000003F000000 + } + else + { + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0x80FFFFFF80FFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x4000000040000000 + } + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0xFF8080FFFF8080FF + PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x003C3C00003C3C00 + } + else + { + PB_IOE_SCOM_PB_FP23_CFG |= 0x0000084000000840 + } + + if(l_def_X2_ENABLED) + { + if (l_def_OPTICS_IS_A_BUS) + { + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0xFFFFFF07FFFFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x0000008000000000 + } + else + { + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x000000F800000000 + } + if (l_TGT0_ATTR_CHIP_EC_FEATURE_HW384245 != 0) + { + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0x80FFFFFF80FFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x3F0000003F000000 + } + else + { + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0x80FFFFFF80FFFFFF + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x4000000040000000 + } + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0xFF8080FFFF8080FF + PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x003C3C00003C3C00 + } + + if (l_def_X0_IS_PAIRED) + { + PB_IOE_SCOM_PB_MISC_CFG |= 0x8000000000000000 + } + else + { + PB_IOE_SCOM_PB_MISC_CFG &= 0x7FFFFFFFFFFFFFFF + } + if (l_def_X1_IS_PAIRED) + { + PB_IOE_SCOM_PB_MISC_CFG |= 0x4000000000000000 + } + else + { + PB_IOE_SCOM_PB_MISC_CFG &= 0xBFFFFFFFFFFFFFFF + } + if (l_def_X2_IS_PAIRED) + { + PB_IOE_SCOM_PB_MISC_CFG |= 0x2000000000000000 + } + else + { + PB_IOE_SCOM_PB_MISC_CFG |= 0xDFFFFFFFFFFFFFFF + } + + // REGISTERS write + TGT0[0x501340A] = PB_IOE_SCOM_PB_FP01_CFG; + TGT0[0x501340B] = PB_IOE_SCOM_PB_FP23_CFG; + TGT0[0x501340C] = pb_ioe_scom_pb_fp45_cfg; + TGT0[0x5013410] = pb_ioe_scom_pb_elink_data_01_cfg_reg; + TGT0[0x5013411] = PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG; + TGT0[0x5013412] = PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG; + TGT0[0x5013423] = PB_IOE_SCOM_PB_MISC_CFG; + TGT0[0x5013424] = pb_ioe_scom_pb_trace_cfg; +} + void main(void) { console_init(); + istep89(); run_ramstage(); } From 45d5f6588f72af10c3965d7771eb6f7a1a32138c Mon Sep 17 00:00:00 2001 From: Marek Kasiewicz Date: Tue, 20 Oct 2020 13:06:37 +0200 Subject: [PATCH 60/90] util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE Signed-off-by: Marek Kasiewicz --- util/cbfstool/flashmap/fmap.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index b7a748ce61f..429a50cdaa8 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -35,7 +35,7 @@ int fmap_size(const struct fmap *fmap) if (!fmap) return -1; - return sizeof(*fmap) + (fmap->nareas * sizeof(struct fmap_area)); + return sizeof(*fmap) + (le16toh((fmap)->nareas) * sizeof(struct fmap_area)); } /* Make a best-effort assessment if the given fmap is real */ @@ -48,7 +48,7 @@ static int is_valid_fmap(const struct fmap *fmap) return 0; /* a basic consistency check: flash should be larger than fmap */ if (fmap->size < - sizeof(*fmap) + fmap->nareas * sizeof(struct fmap_area)) + sizeof(*fmap) + le16toh((fmap)->nareas) * sizeof(struct fmap_area)) return 0; /* fmap-alikes along binary data tend to fail on having a valid, @@ -184,7 +184,7 @@ int fmap_print(const struct fmap *fmap) kv_pair_print(kv); kv_pair_free(kv); - for (i = 0; i < fmap->nareas; i++) { + for (i = 0; i < le16toh((fmap)->nareas); i++) { struct kv_pair *pair; uint16_t flags; char *str; @@ -265,8 +265,8 @@ struct fmap *fmap_create(uint64_t base, uint32_t size, uint8_t *name) memcpy(&fmap->signature, FMAP_SIGNATURE, strlen(FMAP_SIGNATURE)); fmap->ver_major = FMAP_VER_MAJOR; fmap->ver_minor = FMAP_VER_MINOR; - fmap->base = base; - fmap->size = size; + fmap->base = htole64(base); + fmap->size = htole32(size); memccpy(&fmap->name, name, '\0', FMAP_STRLEN); return fmap; @@ -289,7 +289,7 @@ int fmap_append_area(struct fmap **fmap, return -1; /* too many areas */ - if ((*fmap)->nareas >= 0xffff) + if (le16toh((*fmap)->nareas) >= 0xffff) return -1; orig_size = fmap_size(*fmap); @@ -301,12 +301,12 @@ int fmap_append_area(struct fmap **fmap, area = (struct fmap_area *)((uint8_t *)*fmap + orig_size); memset(area, 0, sizeof(*area)); - memcpy(&area->offset, &offset, sizeof(area->offset)); - memcpy(&area->size, &size, sizeof(area->size)); memccpy(&area->name, name, '\0', FMAP_STRLEN); - memcpy(&area->flags, &flags, sizeof(area->flags)); + area->offset = htole32(offset); + area->size = htole32(size); + area->flags = htole16(flags); - (*fmap)->nareas++; + (*fmap)->nareas = htole16(le16toh((*fmap)->nareas) + 1); return new_size; } @@ -319,7 +319,7 @@ const struct fmap_area *fmap_find_area(const struct fmap *fmap, if (!fmap || !name) return NULL; - for (i = 0; i < fmap->nareas; i++) { + for (i = 0; i < le16toh((fmap)->nareas); i++) { if (!strcmp((const char *)fmap->areas[i].name, name)) { area = &fmap->areas[i]; break; @@ -428,13 +428,13 @@ static int fmap_append_area_test(struct fmap **fmap) goto fmap_append_area_test_exit; } - nareas_orig = (*fmap)->nareas; + nareas_orig = le16toh((*fmap)->nareas); (*fmap)->nareas = ~(0); if (fmap_append_area(fmap, 0, 0, (const uint8_t *)"foo", 0) >= 0) { printf("FAILURE: failed to abort with too many areas\n"); goto fmap_append_area_test_exit; } - (*fmap)->nareas = nareas_orig; + (*fmap)->nareas = htole16(nareas_orig); total_size = sizeof(**fmap) + sizeof(test_area); if (fmap_append_area(fmap, @@ -447,7 +447,7 @@ static int fmap_append_area_test(struct fmap **fmap) goto fmap_append_area_test_exit; } - if ((*fmap)->nareas != 1) { + if (le16toh((*fmap)->nareas) != 1) { printf("FAILURE: failed to increment number of areas\n"); goto fmap_append_area_test_exit; } From 4531ab0dd34f78f4aac0bf12da564cf835928cc5 Mon Sep 17 00:00:00 2001 From: Marek Kasiewicz Date: Fri, 4 Dec 2020 10:11:57 +0100 Subject: [PATCH 61/90] util/cbfstool/flashmap/fmap.c: Fix endianness in test functions Signed-off-by: Marek Kasiewicz --- util/cbfstool/flashmap/fmap.c | 42 +++++++++++++++++------------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index 429a50cdaa8..b4f76366fb7 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -35,7 +35,7 @@ int fmap_size(const struct fmap *fmap) if (!fmap) return -1; - return sizeof(*fmap) + (le16toh((fmap)->nareas) * sizeof(struct fmap_area)); + return sizeof(*fmap) + (le16toh(fmap->nareas) * sizeof(struct fmap_area)); } /* Make a best-effort assessment if the given fmap is real */ @@ -47,8 +47,8 @@ static int is_valid_fmap(const struct fmap *fmap) if (fmap->ver_major != FMAP_VER_MAJOR) return 0; /* a basic consistency check: flash should be larger than fmap */ - if (fmap->size < - sizeof(*fmap) + le16toh((fmap)->nareas) * sizeof(struct fmap_area)) + if (le32toh(fmap->size) < + sizeof(*fmap) + le16toh(fmap->nareas) * sizeof(struct fmap_area)) return 0; /* fmap-alikes along binary data tend to fail on having a valid, @@ -177,14 +177,14 @@ int fmap_print(const struct fmap *fmap) kv_pair_fmt(kv, "fmap_ver_major", "%d", fmap->ver_major); kv_pair_fmt(kv, "fmap_ver_minor","%d", fmap->ver_minor); kv_pair_fmt(kv, "fmap_base", "0x%016llx", - (unsigned long long)fmap->base); - kv_pair_fmt(kv, "fmap_size", "0x%04x", fmap->size); + (unsigned long long)le64toh(fmap->base)); + kv_pair_fmt(kv, "fmap_size", "0x%04x", le32toh(fmap->size)); kv_pair_fmt(kv, "fmap_name", "%s", fmap->name); - kv_pair_fmt(kv, "fmap_nareas", "%d", fmap->nareas); + kv_pair_fmt(kv, "fmap_nareas", "%d", le16toh(fmap->nareas)); kv_pair_print(kv); kv_pair_free(kv); - for (i = 0; i < le16toh((fmap)->nareas); i++) { + for (i = 0; i < le16toh(fmap->nareas); i++) { struct kv_pair *pair; uint16_t flags; char *str; @@ -194,16 +194,16 @@ int fmap_print(const struct fmap *fmap) return -1; kv_pair_fmt(pair, "area_offset", "0x%08x", - fmap->areas[i].offset); + le32toh(fmap->areas[i].offset)); kv_pair_fmt(pair, "area_size", "0x%08x", - fmap->areas[i].size); + le32toh(fmap->areas[i].size)); kv_pair_fmt(pair, "area_name", "%s", fmap->areas[i].name); kv_pair_fmt(pair, "area_flags_raw", "0x%02x", - fmap->areas[i].flags); + le16toh(fmap->areas[i].flags)); /* Print descriptive strings for flags rather than the field */ - flags = fmap->areas[i].flags; + flags = le16toh(fmap->areas[i].flags); str = fmap_flags_to_string(flags); if (str == NULL) { kv_pair_free(pair); @@ -319,7 +319,7 @@ const struct fmap_area *fmap_find_area(const struct fmap *fmap, if (!fmap || !name) return NULL; - for (i = 0; i < le16toh((fmap)->nareas); i++) { + for (i = 0; i < le16toh(fmap->nareas); i++) { if (!strcmp((const char *)fmap->areas[i].name, name)) { area = &fmap->areas[i]; break; @@ -358,12 +358,12 @@ static struct fmap *fmap_create_test(void) goto fmap_create_test_exit; } - if (fmap->base != base) { + if (le64toh(fmap->base) != base) { printf("FAILURE: base is incorrect\n"); goto fmap_create_test_exit; } - if (fmap->size != 0x100000) { + if (le32toh(fmap->size) != 0x100000) { printf("FAILURE: size is incorrect\n"); goto fmap_create_test_exit; } @@ -373,7 +373,7 @@ static struct fmap *fmap_create_test(void) goto fmap_create_test_exit; } - if (fmap->nareas != 0) { + if (le16toh(fmap->nareas) != 0) { printf("FAILURE: number of areas is incorrect\n"); goto fmap_create_test_exit; } @@ -414,10 +414,10 @@ static int fmap_append_area_test(struct fmap **fmap) uint16_t nareas_orig; /* test_area will be used by fmap_csum_test and find_area_test */ struct fmap_area test_area = { - .offset = 0x400, - .size = 0x10000, + .offset = htole32(0x400), + .size = htole32(0x10000), .name = "test_area_1", - .flags = FMAP_AREA_STATIC, + .flags = htole16(FMAP_AREA_STATIC), }; status = fail; @@ -438,10 +438,10 @@ static int fmap_append_area_test(struct fmap **fmap) total_size = sizeof(**fmap) + sizeof(test_area); if (fmap_append_area(fmap, - test_area.offset, - test_area.size, + le32toh(test_area.offset), + le32toh(test_area.size), test_area.name, - test_area.flags + le16toh(test_area.flags) ) != total_size) { printf("failed to append area\n"); goto fmap_append_area_test_exit; From 2b08332f26f7a555a6cde74382e99fd67c162417 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 11 Feb 2021 17:15:41 +0100 Subject: [PATCH 62/90] util/cbfstool/flashmap/fmap.c: add missing htole16() This isn't necessary in this particular case, but it is safer to add this in case someone copies the code to other tests. Signed-off-by: Krystian Hebel --- util/cbfstool/flashmap/fmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index b4f76366fb7..4755a0604bb 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -429,7 +429,7 @@ static int fmap_append_area_test(struct fmap **fmap) } nareas_orig = le16toh((*fmap)->nareas); - (*fmap)->nareas = ~(0); + (*fmap)->nareas = htole16(~(0)); if (fmap_append_area(fmap, 0, 0, (const uint8_t *)"foo", 0) >= 0) { printf("FAILURE: failed to abort with too many areas\n"); goto fmap_append_area_test_exit; From 88b73d4061b5b45dc81f83f88493e628234aa788 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 12 Feb 2021 09:44:43 +0100 Subject: [PATCH 63/90] implement p9_fbc_no_hp_scom() --- src/cpu/power/power9/scom.c | 7 +- src/mainboard/raptor-cs/talos-2/romstage.c | 215 ++++++++++----------- 2 files changed, 107 insertions(+), 115 deletions(-) diff --git a/src/cpu/power/power9/scom.c b/src/cpu/power/power9/scom.c index 6d016fb285b..76269b5d3c0 100644 --- a/src/cpu/power/power9/scom.c +++ b/src/cpu/power/power9/scom.c @@ -109,7 +109,12 @@ uint64_t read_scom_indirect(uint64_t reg_address) read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); printk(BIOS_EMERG, "WRITING addr = %llX, data = %llX\n", addr, data); - for(unsigned intwrite_scom_indirect + for(unsigned int i = 0; i < 0xFFFF; ++i) { + asm volatile("nop" :::"memory"); + } + write_scom_direct(addr, data); + printk(BIOS_EMERG, "#hmer = %llX,\n#fail = %llX,\n#done = %llX,\n#status = %llX\n", + read_hmer(), read_hmer() & SPR_HMER_XSCOM_FAIL, read_hmer() & SPR_HMER_XSCOM_DONE, read_hmer() & SPR_HMER_XSCOM_STATUS); diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 9ffe989d318..58ea47f1a76 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -6,16 +6,27 @@ #include #define X0_ENABLED true +#define X1_ENABLED true #define X2_ENABLED true +#define X0_IS_PAIRED true +#define X1_IS_PAIRED true +#define X2_IS_PAIRED true #define DD2X_PARTS true +#define OPTICS_IS_A_BUS true void istep89() { printk(BIOS_EMERG, "starting istep 8.9\n"); p9_fbc_no_hp_scom(); + p9_fbc_ioe_tl_scom(); printk(BIOS_EMERG, "ending istep 8.9\n"); } +void p9_fbc_ioe_tl_scom() +{ + return; +} + void p9_fbc_no_hp_scom() { uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom(0x501340A); // Processor bus Electrical Framer/Parser 01 configuration register @@ -63,170 +74,146 @@ void p9_fbc_no_hp_scom() { pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; } - if (x2_enabled && l_def_dd2x_parts) - { - pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) - pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) - } - else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R < l_def_DD1_LO_LIMIT_H) - || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && l_def_DD1_LO_LIMIT_P)) - { - pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - } - else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && !l_def_DD1_LO_LIMIT_P) - || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R > l_def_DD1_LO_LIMIT_H)) - { - pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - } - - if (l_def_X0_ENABLED)IOEL_REPLAY_THRESHOLD // FIXME: there can be some missing code - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFFFFFF07FFFFFFFF - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000008000000000 - } - else - { - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x000000F800000000 - } - if (l_TGT0_ATTR_CHIP_EC_FEATURE_HW384245 != 0) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x3F0000003F000000 - } - else - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x4000000040000000 - } - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFF8080FFFF8080FF - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x003C3C00003C3C00 + // if (X2_ENABLED && DD2X_PARTS) + // { + // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) + // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) + // } + // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) + // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && DD1_LO_LIMIT_P)) + // { + // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) + // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) + // } + // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && !DD1_LO_LIMIT_P) + // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R > DD1_LO_LIMIT_H)) + // { + // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) + // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) + // } - pb_ioe_scom_pb_trace_cfg &= 0x0000FFFFFFFFFFFF - pb_ioe_scom_pb_trace_cfg |= 0x4141000000000000 - } - else if (l_def_X1_ENABLED) + if (X0_ENABLED && OPTICS_IS_A_BUS) { - pb_ioe_scom_pb_trace_cfg &= 0xFFFF0000FFFFFFFF - pb_ioe_scom_pb_trace_cfg |= 0x0000414100000000 + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFFFFFF07FFFFFFFF; + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001000000000; } - else if (l_def_X2_ENABLED) + else if(X0_ENABLED) { - pb_ioe_scom_pb_trace_cfg &= 0xFFFFFFFF0000FFFF - pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000 + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001F00000000; } - if (l_def_X1_ENABLED && l_def_DD2X_PARTS) + if (X0_ENABLED) { - PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) - PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF; + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x4000000040000000; + + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFF8080FFFF8080FF; + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x003C3C00003C3C00; + + pb_ioe_scom_pb_trace_cfg &= 0x0000FFFFFFFFFFFF; + pb_ioe_scom_pb_trace_cfg |= 0x4141000000000000; } - else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R < l_def_DD1_LO_LIMIT_H) - || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && l_def_DD1_LO_LIMIT_P)) + else if (X1_ENABLED) { - PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + pb_ioe_scom_pb_trace_cfg &= 0xFFFF0000FFFFFFFF; + pb_ioe_scom_pb_trace_cfg |= 0x0000414100000000; } - else if ((l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R == l_def_DD1_LO_LIMIT_H && !l_def_DD1_LO_LIMIT_P) - || (l_def_X0_ENABLED && l_def_DD1_PARTS && l_def_DD1_LO_LIMIT_R > l_def_DD1_LO_LIMIT_H)) + else if (X2_ENABLED) { - PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) + pb_ioe_scom_pb_trace_cfg &= 0xFFFFFFFF0000FFFF; + pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000; } + // if (X1_ENABLED && DD2X_PARTS) + // { + // PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x15 - (DD2_LO_LIMIT_N / DD2_LO_LIMIT_D)); + // PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x15 - (DD2_LO_LIMIT_N / DD2_LO_LIMIT_D)); + // } + // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) + // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && DD1_LO_LIMIT_P)) + // { + // PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); + // PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); + // } + // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && !DD1_LO_LIMIT_P) + // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R > DD1_LO_LIMIT_H)) + // { + // PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); + // PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); + // } + - if(l_def_X1_ENABLED) + if(X1_ENABLED) { - PB_IOE_SCOM_PB_FP23_CFG &= 0xfff004bffff007bf - PB_IOE_SCOM_PB_FP23_CFG |= 0x0002010000020000 - if (l_def_OPTICS_IS_A_BUS) - { - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0xFE0FFFFFFFFFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x0100000000000000 - } - else - { - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0xFE0FFFFFFFFFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x01F0000000000000 - } - if (l_TGT0_ATTR_CHIP_EC_FEATURE_HW384245 != 0) + pb_ioe_scom_pb_fp23_cfg &= 0xfff004bffff007bf; + pb_ioe_scom_pb_fp23_cfg |= 0x0002010000020000; + if (OPTICS_IS_A_BUS) { - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0x80FFFFFF80FFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x3F0000003F000000 + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x0100000000000000; } else { - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0x80FFFFFF80FFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x4000000040000000 + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x01F0000000000000; } - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG &= 0xFF8080FFFF8080FF - PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG |= 0x003C3C00003C3C00 + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0x808080FF808080FF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x403C3C00403C3C00; } else { - PB_IOE_SCOM_PB_FP23_CFG |= 0x0000084000000840 + pb_ioe_scom_pb_fp23_cfg |= 0x0000084000000840; } - if(l_def_X2_ENABLED) + if(X2_ENABLED) { - if (l_def_OPTICS_IS_A_BUS) - { - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0xFFFFFF07FFFFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x0000008000000000 - } - else - { - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x000000F800000000 - } - if (l_TGT0_ATTR_CHIP_EC_FEATURE_HW384245 != 0) + if (OPTICS_IS_A_BUS) { - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0x80FFFFFF80FFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x3F0000003F000000 + pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0xFFFFFF07FFFFFFFF; + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x0000008000000000; } else { - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0x80FFFFFF80FFFFFF - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x4000000040000000 + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x000000F800000000; } - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG &= 0xFF8080FFFF8080FF - PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG |= 0x003C3C00003C3C00 + pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0x808080FF808080FF; + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x403C3C00403C3C00; } - if (l_def_X0_IS_PAIRED) + if(X0_IS_PAIRED) { - PB_IOE_SCOM_PB_MISC_CFG |= 0x8000000000000000 + pb_ioe_scom_pb_misc_cfg |= 0x8000000000000000; } else { - PB_IOE_SCOM_PB_MISC_CFG &= 0x7FFFFFFFFFFFFFFF + pb_ioe_scom_pb_misc_cfg &= 0x7FFFFFFFFFFFFFFF; } - if (l_def_X1_IS_PAIRED) + if(X1_IS_PAIRED) { - PB_IOE_SCOM_PB_MISC_CFG |= 0x4000000000000000 + pb_ioe_scom_pb_misc_cfg |= 0x4000000000000000; } else { - PB_IOE_SCOM_PB_MISC_CFG &= 0xBFFFFFFFFFFFFFFF + pb_ioe_scom_pb_misc_cfg &= 0xBFFFFFFFFFFFFFFF; } - if (l_def_X2_IS_PAIRED) + if(X2_IS_PAIRED) { - PB_IOE_SCOM_PB_MISC_CFG |= 0x2000000000000000 + pb_ioe_scom_pb_misc_cfg |= 0x2000000000000000; } else { - PB_IOE_SCOM_PB_MISC_CFG |= 0xDFFFFFFFFFFFFFFF + pb_ioe_scom_pb_misc_cfg &= 0xDFFFFFFFFFFFFFFF; } // REGISTERS write - TGT0[0x501340A] = PB_IOE_SCOM_PB_FP01_CFG; - TGT0[0x501340B] = PB_IOE_SCOM_PB_FP23_CFG; - TGT0[0x501340C] = pb_ioe_scom_pb_fp45_cfg; - TGT0[0x5013410] = pb_ioe_scom_pb_elink_data_01_cfg_reg; - TGT0[0x5013411] = PB_IOE_SCOM_PB_ELINK_DATA_23_CFG_REG; - TGT0[0x5013412] = PB_IOE_SCOM_PB_ELINK_DATA_45_CFG_REG; - TGT0[0x5013423] = PB_IOE_SCOM_PB_MISC_CFG; - TGT0[0x5013424] = pb_ioe_scom_pb_trace_cfg; + write_scom(0x501340A, pb_ioe_scom_pb_fp01_cfg); + write_scom(0x501340B, pb_ioe_scom_pb_fp23_cfg); + write_scom(0x501340C, pb_ioe_scom_pb_fp45_cfg); + write_scom(0x5013410, pb_ioe_scom_pb_elink_data_01_cfg_reg); + write_scom(0x5013411, pb_ioe_scom_pb_elink_data_23_cfg_reg); + write_scom(0x5013412, pb_ioe_scom_pb_elink_data_45_cfg_reg); + write_scom(0x5013423, pb_ioe_scom_pb_misc_cfg); + write_scom(0x5013424, pb_ioe_scom_pb_trace_cfg); } void main(void) From 3fd5f536196bc9582a8813822c2e0f15cdb713c1 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 15 Feb 2021 14:58:27 +0100 Subject: [PATCH 64/90] continue scom_init implementation --- src/mainboard/raptor-cs/talos-2/romstage.c | 346 +++++++++++++++++++-- 1 file changed, 317 insertions(+), 29 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 58ea47f1a76..10f8f61e8f0 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -5,38 +5,326 @@ #include -#define X0_ENABLED true -#define X1_ENABLED true -#define X2_ENABLED true -#define X0_IS_PAIRED true -#define X1_IS_PAIRED true -#define X2_IS_PAIRED true -#define DD2X_PARTS true -#define OPTICS_IS_A_BUS true - -void istep89() +#define X0_ENABLED (true) +#define X1_ENABLED (true) +#define X2_ENABLED (true) +#define X0_IS_PAIRED (true) +#define X1_IS_PAIRED (true) +#define X2_IS_PAIRED (true) +#define DD2X_PARTS (true) +#define OPTICS_IS_A_BUS (true) +#define ATTR_PROC_FABRIC_A_LINKS_CNFG (0) +#define ATTR_PROC_FABRIC_X_LINKS_CNFG (0) + +#define EPS_TYPE_LE (0x01), +#define EPS_TYPE_HE (0x02), +#define EPS_TYPE_HE_F8 (0x03) +#define ATTR_PROC_EPS_TABLE_TYPE (EPS_TYPE_LE) // default value + +#define CHIP_IS_NODE (0x01) +#define CHIP_IS_GROUP (0x02) +#define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) // default value + +// Power Bus PB West Mode Configuration Register +#define PB_WEST_MODE_CFG (0x501180A) +// Power Bus PB CENT Mode Register +#define PB_CENT_MODE_CFG (0x5011C0A) +// Power Bus PB CENT GP command RATE DP0 Register +#define PB_CENT_GP_COMMAND_RATE_DP0 (0x5011C26) +// Power Bus PB CENT GP command RATE DP1 Register +#define PB_CENT_GP_COMMAND_RATE_DP1 (0x5011C27) +// Power Bus PB CENT RGP command RATE DP0 Register +#define PB_CENT_RGP_COMMAND_RATE_DP0 (0x5011C28) +// Power Bus PB CENT RGP command RATE DP1 Register +#define PB_CENT_RGP_COMMAND_RATE_DP1 (0x5011C29) +// Power Bus PB CENT SP command RATE DP0 Register +#define PB_CENT_SP_COMMAND_RATE_DP0 (0x5011C2A) +// Power Bus PB CENT SP command RATE DP1 Register +#define PB_CENT_SP_COMMAND_RATE_DP1 (0x5011C2B) +// Power Bus PB East Mode Configuration Register +#define PB_EAST_MODE_CFG (0x501200A) +// Power bus Electrical Framer/Parser 01 configuration register +#define PB_ELE_PB_FRAMER_PARSER_01_CFG (0x501340A) +// Power Bus Electrical Framer/Parser 23 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_23_CFG (0x501340B) +// Power Bus Electrical Framer/Parser 45 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_45_CFG (0x501340C) +// Power Bus Electrical Link Data Buffer 01 Configuration Register +#define PB_ELE_PB_DATA_BUFF_01_CFG (0x5013410) +// Power Bus Electrical Link Data Buffer 23 Configuration Register +#define PB_ELE_PB_DATA_BUFF_23_CFG (0x5013411) +// Power Bus Electrical Link Data Buffer 45 Configuration Register +#define PB_ELE_PB_DATA_BUFF_45_CFG (0x5013412) +// Power Bus Electrical Miscellaneous Configuration Register +#define PB_ELE_MISC_CFG (0x5013423) +// Power Bus Electrical Link Trace Configuration Register +#define PB_ELE_LINK_TRACE_CFG (0x5013424) + +#define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) +#define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) +#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) +#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) +#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) +#define P9_FBC_UTILS_MAX_ELECTRICAL_LINKS (3) +#define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) +#define FBC_IOE_TL_FIR_MASK_X1_NF (0x0018030300000440ULL) +#define FBC_IOE_TL_FIR_MASK_X2_NF (0x000300C0C0000220ULL) +#define PU_PB_IOE_FIR_MASK_REG (0x5013403) + +uint64_t xbusChiplets[] = {0x06}; +#define ARRAY_LENGTH(a) (sizeof(a)/sizeof(*a)) + +#define FBC_IOE_DL_FIR_ACTION0 (0) +#define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) +#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) +#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) +#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) +#define XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG (0x6011803) + +#define PB_ELE_CONFIG_REG (0x601180A) +#define PB_ELE_REPLAY_TRESHOLD_REG (0x6011818) +#define PB_ELE_ECC_TRESHOLD_REG (0x6011819) + +#define BOTH (0x0) +#define EVEN_ONLY (0x1) +#define ODD_ONLY (0x2) +#define NONE (0x3) +#define ATTR_LINK_TRAIN BOTH + +void p9_fbc_ioe_tl_scom(void); +void istep89(void); +void p9_fbc_no_hp_scom(void); +void tl_fir(void); +void p9_fbc_ioe_dl_scom(uint64_t TGT0, uint64_t &TGT1); + +void istep89(void) { printk(BIOS_EMERG, "starting istep 8.9\n"); p9_fbc_no_hp_scom(); p9_fbc_ioe_tl_scom(); + + // setup IOE (XBUS FBC IO) DL SCOMs + for(size_t xbusChipletIndex = 0; xbusChipletIndex < ARRAY_LENGTH(xbusChiplets); ++xbusChipletIndex) + { + p9_fbc_ioe_dl_scom(xbusChiplets[xbusChipletIndex], i_target); + write_scom_for_chiplet(xbusChipletIndex, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); + write_scom_for_chiplet(xbusChipletIndex, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); + write_scom_for_chiplet(xbusChipletIndex, XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); + } + + // set FBC optics config mode attribute + l_obus_chiplets = i_target.getChildren(); + + for l_iter in l_obus_chiplets: + { + uint8_t l_unit_pos; + l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[l_iter]; + l_fbc_optics_cfg_mode[l_unit_pos] = fapi2::ATTR_OPTICS_CONFIG_MODE[l_iter]; + } + fapi2::ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE[i_target] = l_fbc_optics_cfg_mode; printk(BIOS_EMERG, "ending istep 8.9\n"); } -void p9_fbc_ioe_tl_scom() +void p9_fbc_ioe_dl_scom(uint64_t TGT0, uint64_t TGT1) +{ + // REGISTERS read + uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, 0x601180A); // ELL Configuration Register + uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, 0x6011818); // ELL Replay Threshold Register + uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, 0x6011819); // ELL SL ECC Threshold Register + if (ATTR_LINK_TRAIN == BOTH) + { + pb_ioe_ll0_ioel_config |= 0x8000000000000000; + } + else + { + pb_ioe_ll0_ioel_config &= 0x7FFFFFFFFFFFFFFF; + } + pb_ioe_ll0_ioel_config &= 0xFFEFFFFFFFFFFFFF; + pb_ioe_ll0_ioel_config |= 0x280F000F00000000; + pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x0070000000000000; + pb_ioe_ll0_ioel_replay_threshold &= 0x0FFFFFFFFFFFFFFF; + pb_ioe_ll0_ioel_replay_threshold |= 0x6FE0000000000000; + + pb_ioe_ll0_ioel_sl_ecc_threshold &= 0x7FFFFFFFFFFFFFFF; + pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F00000000000000; + // REGISTERS write + TGT0[0x601180A] = pb_ioe_ll0_ioel_config; + TGT0[0x6011818] = pb_ioe_ll0_ioel_replay_threshold; + TGT0[0x6011819] = pb_ioe_ll0_ioel_sl_ecc_threshold; +} + +void tl_fir(void) +{ + write_scom(PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); + write_scom(PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); + uint64_t l_fir_mask = FBC_IOE_TL_FIR_MASK; + + if (len(l_xbusChiplets) == 0) + { + // no valid links, mask + // l_fir_mask.flush<1>(); + l_fir_mask = 0xFFFFFFFFFFFFFFFF; + } + else + { + bool l_x_functional[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = + { + false, + false, + false + }; + uint64_t l_x_non_functional_mask[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = + { + FBC_IOE_TL_FIR_MASK_X0_NF, + FBC_IOE_TL_FIR_MASK_X1_NF, + FBC_IOE_TL_FIR_MASK_X2_NF + }; + for l_iter in l_xbusChiplets: + { + uint8_t l_unit_pos; + l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[l_iter]; + l_x_functional[l_unit_pos] = true; + } + + for(unsigned int ll = 0; ll < P9_FBC_UTILS_MAX_ELECTRICAL_LINKS; ++ll) + { + if (!l_x_functional[ll]) + { + l_fir_mask |= l_x_non_functional_mask[ll]; + } + } + // shoudn't this happen for no xbus chiplets too? + write_scom(PU_PB_IOE_FIR_MASK_REG, l_fir_mask); + } +} + +void p9_fbc_no_hp_scom(void) { - return; + uint64_t is_flat_8 = false; + + // REGISTERS read + uint64_t pb_com_pb_west_mode = read_scom(PB_WEST_MODE_CFG); + uint64_t pb_com_pb_cent_mode = read_scom(PB_CENT_MODE_CFG); + uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom(PB_CENT_GP_COMMAND_RATE_DP0); + uint64_t pb_com_pb_cent_gp_cmd_rate_dp1 = read_scom(PB_CENT_GP_COMMAND_RATE_DP1); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP0); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP1); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom(PB_CENT_SP_COMMAND_RATE_DP0); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom(PB_CENT_SP_COMMAND_RATE_DP1); + uint64_t pb_com_pb_east_mode = read_scom(PB_EAST_MODE_CFG); + + if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP + || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) + { + pb_com_pb_cent_gp_cmd_rate_dp0 = 0; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP + && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) + { + pb_com_pb_cent_gp_cmd_rate_dp0 = 0x030406171C243448; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0x040508191F283A50; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) + { + pb_com_pb_cent_gp_cmd_rate_dp0 = 0x0304062832405C80; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0x0405082F3B4C6D98; + } + + if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406080A0C1218; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508080A0C1218; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x030406080A0C1218; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x030406080A0C1218; + } + else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 3) + || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304060D10141D28; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405080D10141D28; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x05070A0D10141D28; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x05070A0D10141D28; + } + else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && is_flat_8) + || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3)) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406171C243448; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508191F283A50; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x080C12171C243448; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A0D14191F283A50; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304062832405C80; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405082F3B4C6D98; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x08141F2832405C80; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A18252F3B4C6D98; + } + + if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0 && ATTR_PROC_FABRIC_A_LINKS_CNFG == 0) + { + pb_com_pb_east_mode |= 0x0300000000000000; + } + else + { + pb_com_pb_east_mode &= 0xF1FFFFFFFFFFFFFF; + } + if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && is_flat_8) + { + pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_west_mode |= 0x00003E8000000000; + pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_cent_mode |= 0x00003E8000000000; + pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_east_mode |= 0x00003E8000000000; + } + else + { + pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_west_mode |= 0x0000FAFC00000000; + pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_cent_mode |= 0x00007EFC00000000; + pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_east_mode |= 0x000007EFC0000000; + } + + pb_com_pb_west_mode &= 0xFFFFFFFC0FFFFFFF; + pb_com_pb_west_mode |= 0x00000002a0000000; + pb_com_pb_cent_mode &= 0xFFFFFFFC0FFFFFFF; + pb_com_pb_cent_mode |= 0x00000002a0000000; + pb_com_pb_east_mode &= 0xFFFFFFFC0FFFFFFF; + pb_com_pb_east_mode |= 0x00000002a0000000; + + // REGISTERS write + write_scom(PB_WEST_MODE_CFG, pb_com_pb_west_mode); + write_scom(PB_CENT_MODE_CFG, pb_com_pb_cent_mode); + write_scom(PB_CENT_GP_COMMAND_RATE_DP0, pb_com_pb_cent_gp_cmd_rate_dp0); + write_scom(PB_CENT_GP_COMMAND_RATE_DP1, pb_com_pb_cent_gp_cmd_rate_dp1); + write_scom(PB_CENT_RGP_COMMAND_RATE_DP0, pb_com_pb_cent_rgp_cmd_rate_dp0); + write_scom(PB_CENT_RGP_COMMAND_RATE_DP1, pb_com_pb_cent_rgp_cmd_rate_dp1); + write_scom(PB_CENT_SP_COMMAND_RATE_DP0, pb_com_pb_cent_sp_cmd_rate_dp0); + write_scom(PB_CENT_SP_COMMAND_RATE_DP1, pb_com_pb_cent_sp_cmd_rate_dp1); + write_scom(PB_EAST_MODE_CFG, pb_com_pb_east_mode); } -void p9_fbc_no_hp_scom() +void p9_fbc_ioe_tl_scom(void) { - uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom(0x501340A); // Processor bus Electrical Framer/Parser 01 configuration register - uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom(0x501340B); // Power Bus Electrical Framer/Parser 23 Configuration Register - uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom(0x501340C); // Power Bus Electrical Framer/Parser 45 Configuration Register - uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom(0x5013410); // Power Bus Electrical Link Data Buffer 01 Configuration Register - uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom(0x5013411); // Power Bus Electrical Link Data Buffer 23 Configuration Register - uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom(0x5013412); // Power Bus Electrical Link Data Buffer 45 Configuration Register - uint64_t pb_ioe_scom_pb_misc_cfg = read_scom(0x5013423); // Power Bus Electrical Miscellaneous Configuration Register - uint64_t pb_ioe_scom_pb_trace_cfg = read_scom(0x5013424); // Power Bus Electrical Link Trace Configuration Register + uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom(PB_ELE_PB_FRAMER_PARSER_01_CFG); + uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom(PB_ELE_PB_FRAMER_PARSER_23_CFG); + uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom(PB_ELE_PB_FRAMER_PARSER_45_CFG); + uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom(PB_ELE_PB_DATA_BUFF_01_CFG); + uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom(PB_ELE_PB_DATA_BUFF_23_CFG); + uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom(PB_ELE_PB_DATA_BUFF_45_CFG); + uint64_t pb_ioe_scom_pb_misc_cfg = read_scom(PB_ELE_MISC_CFG); + uint64_t pb_ioe_scom_pb_trace_cfg = read_scom(PB_ELE_LINK_TRACE_CFG); if(X0_ENABLED) { @@ -206,14 +494,14 @@ void p9_fbc_no_hp_scom() } // REGISTERS write - write_scom(0x501340A, pb_ioe_scom_pb_fp01_cfg); - write_scom(0x501340B, pb_ioe_scom_pb_fp23_cfg); - write_scom(0x501340C, pb_ioe_scom_pb_fp45_cfg); - write_scom(0x5013410, pb_ioe_scom_pb_elink_data_01_cfg_reg); - write_scom(0x5013411, pb_ioe_scom_pb_elink_data_23_cfg_reg); - write_scom(0x5013412, pb_ioe_scom_pb_elink_data_45_cfg_reg); - write_scom(0x5013423, pb_ioe_scom_pb_misc_cfg); - write_scom(0x5013424, pb_ioe_scom_pb_trace_cfg); + write_scom(PB_ELE_PB_FRAMER_PARSER_01_CFG, pb_ioe_scom_pb_fp01_cfg); + write_scom(PB_ELE_PB_FRAMER_PARSER_23_CFG, pb_ioe_scom_pb_fp23_cfg); + write_scom(PB_ELE_PB_FRAMER_PARSER_45_CFG, pb_ioe_scom_pb_fp45_cfg); + write_scom(PB_ELE_PB_DATA_BUFF_01_CFG, pb_ioe_scom_pb_elink_data_01_cfg_reg); + write_scom(PB_ELE_PB_DATA_BUFF_23_CFG, pb_ioe_scom_pb_elink_data_23_cfg_reg); + write_scom(PB_ELE_PB_DATA_BUFF_45_CFG, pb_ioe_scom_pb_elink_data_45_cfg_reg); + write_scom(PB_ELE_MISC_CFG, pb_ioe_scom_pb_misc_cfg); + write_scom(PB_ELE_LINK_TRACE_CFG, pb_ioe_scom_pb_trace_cfg); } void main(void) From 93369644cdeb4a480da4534a0aed0c9572fa69d6 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Tue, 16 Feb 2021 15:10:23 +0100 Subject: [PATCH 65/90] move scom registers definitions --- src/cpu/power/scom_init.c | 0 src/include/cpu/power/scom.h | 12 +- src/include/cpu/power/scom_registers.h | 51 +++++ src/mainboard/raptor-cs/talos-2/romstage.c | 235 +++++++-------------- 4 files changed, 138 insertions(+), 160 deletions(-) create mode 100644 src/cpu/power/scom_init.c create mode 100644 src/include/cpu/power/scom_registers.h diff --git a/src/cpu/power/scom_init.c b/src/cpu/power/scom_init.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index a839f84c619..036357cf0ca 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -120,17 +120,17 @@ void write_scom_indirect(uint64_t reg_address, uint64_t data); static inline void write_scom(uint64_t addr, uint64_t data) { - if (addr & XSCOM_ADDR_IND_FLAG) - write_scom_indirect(addr, data); - else + // if (addr & XSCOM_ADDR_IND_FLAG) + // write_scom_indirect(addr, data); + // else write_scom_direct(addr, data); } static inline uint64_t read_scom(uint64_t addr) { - if (addr & XSCOM_ADDR_IND_FLAG) - return read_scom_indirect(addr); - else + // if (addr & XSCOM_ADDR_IND_FLAG) + // return read_scom_indirect(addr); + // else return read_scom_direct(addr); } diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h new file mode 100644 index 00000000000..0a51100ca6a --- /dev/null +++ b/src/include/cpu/power/scom_registers.h @@ -0,0 +1,51 @@ +typedef enum +{ + // Power Bus PB West Mode Configuration Register + PB_WEST_MODE_CFG = 0x501180A, + // Power Bus PB CENT Mode Register + PB_CENT_MODE_CFG = 0x5011C0A, + // Power Bus PB CENT GP command RATE DP0 Register + PB_CENT_GP_COMMAND_RATE_DP0 = 0x5011C26, + // Power Bus PB CENT GP command RATE DP1 Register + PB_CENT_GP_COMMAND_RATE_DP1 = 0x5011C27, + // Power Bus PB CENT RGP command RATE DP0 Register + PB_CENT_RGP_COMMAND_RATE_DP0 = 0x5011C28, + // Power Bus PB CENT RGP command RATE DP1 Register + PB_CENT_RGP_COMMAND_RATE_DP1 = 0x5011C29, + // Power Bus PB CENT SP command RATE DP0 Register + PB_CENT_SP_COMMAND_RATE_DP0 = 0x5011C2A, + // Power Bus PB CENT SP command RATE DP1 Register + PB_CENT_SP_COMMAND_RATE_DP1 = 0x5011C2B, + // Power Bus PB East Mode Configuration Register + PB_EAST_MODE_CFG = 0x501200A, + // Power bus Electrical Framer/Parser 01 configuration register + PB_ELE_PB_FRAMER_PARSER_01_CFG = 0x501340A, + // Power Bus Electrical Framer/Parser 23 Configuration Register + PB_ELE_PB_FRAMER_PARSER_23_CFG = 0x501340B, + // Power Bus Electrical Framer/Parser 45 Configuration Register + PB_ELE_PB_FRAMER_PARSER_45_CFG = 0x501340C, + // Power Bus Electrical Link Data Buffer 01 Configuration Register + PB_ELE_PB_DATA_BUFF_01_CFG = 0x5013410, + // Power Bus Electrical Link Data Buffer 23 Configuration Register + PB_ELE_PB_DATA_BUFF_23_CFG = 0x5013411, + // Power Bus Electrical Link Data Buffer 45 Configuration Register + PB_ELE_PB_DATA_BUFF_45_CFG = 0x5013412, + // Power Bus Electrical Miscellaneous Configuration Register + PB_ELE_MISC_CFG = 0x5013423, + // Power Bus Electrical Link Trace Configuration Register + PB_ELE_LINK_TRACE_CFG = 0x5013424, + PU_PB_IOE_FIR_ACTION0_REG = 0x5013406, + PU_PB_IOE_FIR_ACTION1_REG = 0x5013407, + XBUS_LL0_IOEL_FIR_ACTION0_REG = 0x6011806, + XBUS_LL0_IOEL_FIR_ACTION1_REG = 0x6011807, + XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG = 0x6011803, + PB_ELE_CONFIG_REG = 0x601180A, + PB_ELE_REPLAY_TRESHOLD_REG = 0x6011818, + PB_ELE_ECC_TRESHOLD_REG = 0x6011819, + // ELL Configuration Register + ELL_CFG_REG = 0x601180A, + // ELL Replay Threshold Register + ELL_REPLAY_TRESHOLD_REG = 0x6011818, + // ELL SL ECC Threshold Register + ELL_SL_ECC_TRESHOLD_REG = 0x6011819, +} scom_reg_t diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 10f8f61e8f0..167ecf46c2f 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -4,6 +4,7 @@ #include #include +#include #define X0_ENABLED (true) #define X1_ENABLED (true) @@ -25,45 +26,9 @@ #define CHIP_IS_GROUP (0x02) #define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) // default value -// Power Bus PB West Mode Configuration Register -#define PB_WEST_MODE_CFG (0x501180A) -// Power Bus PB CENT Mode Register -#define PB_CENT_MODE_CFG (0x5011C0A) -// Power Bus PB CENT GP command RATE DP0 Register -#define PB_CENT_GP_COMMAND_RATE_DP0 (0x5011C26) -// Power Bus PB CENT GP command RATE DP1 Register -#define PB_CENT_GP_COMMAND_RATE_DP1 (0x5011C27) -// Power Bus PB CENT RGP command RATE DP0 Register -#define PB_CENT_RGP_COMMAND_RATE_DP0 (0x5011C28) -// Power Bus PB CENT RGP command RATE DP1 Register -#define PB_CENT_RGP_COMMAND_RATE_DP1 (0x5011C29) -// Power Bus PB CENT SP command RATE DP0 Register -#define PB_CENT_SP_COMMAND_RATE_DP0 (0x5011C2A) -// Power Bus PB CENT SP command RATE DP1 Register -#define PB_CENT_SP_COMMAND_RATE_DP1 (0x5011C2B) -// Power Bus PB East Mode Configuration Register -#define PB_EAST_MODE_CFG (0x501200A) -// Power bus Electrical Framer/Parser 01 configuration register -#define PB_ELE_PB_FRAMER_PARSER_01_CFG (0x501340A) -// Power Bus Electrical Framer/Parser 23 Configuration Register -#define PB_ELE_PB_FRAMER_PARSER_23_CFG (0x501340B) -// Power Bus Electrical Framer/Parser 45 Configuration Register -#define PB_ELE_PB_FRAMER_PARSER_45_CFG (0x501340C) -// Power Bus Electrical Link Data Buffer 01 Configuration Register -#define PB_ELE_PB_DATA_BUFF_01_CFG (0x5013410) -// Power Bus Electrical Link Data Buffer 23 Configuration Register -#define PB_ELE_PB_DATA_BUFF_23_CFG (0x5013411) -// Power Bus Electrical Link Data Buffer 45 Configuration Register -#define PB_ELE_PB_DATA_BUFF_45_CFG (0x5013412) -// Power Bus Electrical Miscellaneous Configuration Register -#define PB_ELE_MISC_CFG (0x5013423) -// Power Bus Electrical Link Trace Configuration Register -#define PB_ELE_LINK_TRACE_CFG (0x5013424) - #define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) #define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) -#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) -#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) + #define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) #define P9_FBC_UTILS_MAX_ELECTRICAL_LINKS (3) #define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) @@ -71,19 +36,9 @@ #define FBC_IOE_TL_FIR_MASK_X2_NF (0x000300C0C0000220ULL) #define PU_PB_IOE_FIR_MASK_REG (0x5013403) -uint64_t xbusChiplets[] = {0x06}; -#define ARRAY_LENGTH(a) (sizeof(a)/sizeof(*a)) - #define FBC_IOE_DL_FIR_ACTION0 (0) #define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) #define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) -#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) -#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) -#define XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG (0x6011803) - -#define PB_ELE_CONFIG_REG (0x601180A) -#define PB_ELE_REPLAY_TRESHOLD_REG (0x6011818) -#define PB_ELE_ECC_TRESHOLD_REG (0x6011819) #define BOTH (0x0) #define EVEN_ONLY (0x1) @@ -91,11 +46,14 @@ uint64_t xbusChiplets[] = {0x06}; #define NONE (0x3) #define ATTR_LINK_TRAIN BOTH +// this is probably wrong +#define PROC_CHIPLET (0x10) + void p9_fbc_ioe_tl_scom(void); void istep89(void); void p9_fbc_no_hp_scom(void); void tl_fir(void); -void p9_fbc_ioe_dl_scom(uint64_t TGT0, uint64_t &TGT1); +void p9_fbc_ioe_dl_scom(uint64_t TGT0); void istep89(void) { @@ -103,34 +61,18 @@ void istep89(void) p9_fbc_no_hp_scom(); p9_fbc_ioe_tl_scom(); - // setup IOE (XBUS FBC IO) DL SCOMs - for(size_t xbusChipletIndex = 0; xbusChipletIndex < ARRAY_LENGTH(xbusChiplets); ++xbusChipletIndex) - { - p9_fbc_ioe_dl_scom(xbusChiplets[xbusChipletIndex], i_target); - write_scom_for_chiplet(xbusChipletIndex, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); - write_scom_for_chiplet(xbusChipletIndex, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); - write_scom_for_chiplet(xbusChipletIndex, XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); - } - - // set FBC optics config mode attribute - l_obus_chiplets = i_target.getChildren(); - - for l_iter in l_obus_chiplets: - { - uint8_t l_unit_pos; - l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[l_iter]; - l_fbc_optics_cfg_mode[l_unit_pos] = fapi2::ATTR_OPTICS_CONFIG_MODE[l_iter]; - } - fapi2::ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE[i_target] = l_fbc_optics_cfg_mode; + p9_fbc_ioe_dl_scom(XB_CHIPLET_ID); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); printk(BIOS_EMERG, "ending istep 8.9\n"); } -void p9_fbc_ioe_dl_scom(uint64_t TGT0, uint64_t TGT1) -{ - // REGISTERS read - uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, 0x601180A); // ELL Configuration Register - uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, 0x6011818); // ELL Replay Threshold Register - uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, 0x6011819); // ELL SL ECC Threshold Register +void p9_fbc_ioe_dl_scom(uint64_t TGT0) +{ + uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, ELL_CFG_REG); + uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, ELL_REPLAY_TRESHOLD_REG); + uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, ELL_SL_ECC_TRESHOLD_REG); if (ATTR_LINK_TRAIN == BOTH) { pb_ioe_ll0_ioel_config |= 0x8000000000000000; @@ -141,61 +83,46 @@ void p9_fbc_ioe_dl_scom(uint64_t TGT0, uint64_t TGT1) } pb_ioe_ll0_ioel_config &= 0xFFEFFFFFFFFFFFFF; pb_ioe_ll0_ioel_config |= 0x280F000F00000000; - pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x0070000000000000; pb_ioe_ll0_ioel_replay_threshold &= 0x0FFFFFFFFFFFFFFF; pb_ioe_ll0_ioel_replay_threshold |= 0x6FE0000000000000; - pb_ioe_ll0_ioel_sl_ecc_threshold &= 0x7FFFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F00000000000000; - // REGISTERS write - TGT0[0x601180A] = pb_ioe_ll0_ioel_config; - TGT0[0x6011818] = pb_ioe_ll0_ioel_replay_threshold; - TGT0[0x6011819] = pb_ioe_ll0_ioel_sl_ecc_threshold; + pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F70000000000000; + + write_scom_for_chiplet(TGT0, ELL_CFG_REG, pb_ioe_ll0_ioel_config); + write_scom_for_chiplet(TGT0, ELL_REPLAY_TRESHOLD_REG, pb_ioe_ll0_ioel_replay_threshold); + write_scom_for_chiplet(TGT0, ELL_SL_ECC_TRESHOLD_REG, pb_ioe_ll0_ioel_sl_ecc_threshold); } void tl_fir(void) { - write_scom(PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); - write_scom(PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); uint64_t l_fir_mask = FBC_IOE_TL_FIR_MASK; - if (len(l_xbusChiplets) == 0) - { - // no valid links, mask - // l_fir_mask.flush<1>(); - l_fir_mask = 0xFFFFFFFFFFFFFFFF; - } - else - { - bool l_x_functional[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = - { - false, - false, - false - }; - uint64_t l_x_non_functional_mask[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = - { - FBC_IOE_TL_FIR_MASK_X0_NF, - FBC_IOE_TL_FIR_MASK_X1_NF, - FBC_IOE_TL_FIR_MASK_X2_NF - }; - for l_iter in l_xbusChiplets: - { - uint8_t l_unit_pos; - l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[l_iter]; - l_x_functional[l_unit_pos] = true; - } - - for(unsigned int ll = 0; ll < P9_FBC_UTILS_MAX_ELECTRICAL_LINKS; ++ll) - { - if (!l_x_functional[ll]) - { - l_fir_mask |= l_x_non_functional_mask[ll]; - } - } - // shoudn't this happen for no xbus chiplets too? - write_scom(PU_PB_IOE_FIR_MASK_REG, l_fir_mask); - } + l_fir_mask |= FBC_IOE_TL_FIR_MASK_X0_NF; + // bool l_x_functional[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = + // { + // false, + // false, + // false + // }; + // uint64_t l_x_non_functional_mask[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = + // { + // FBC_IOE_TL_FIR_MASK_X0_NF, + // FBC_IOE_TL_FIR_MASK_X1_NF, + // FBC_IOE_TL_FIR_MASK_X2_NF + // }; + // uint8_t l_unit_pos; + // l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[XB_CHIPLET_ID]; + // l_x_functional[l_unit_pos] = true; + // for(unsigned int ll = 0; ll < P9_FBC_UTILS_MAX_ELECTRICAL_LINKS; ++ll) + // { + // if (!l_x_functional[ll]) + // { + // l_fir_mask |= l_x_non_functional_mask[ll]; + // } + // } + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_MASK_REG, l_fir_mask); } void p9_fbc_no_hp_scom(void) @@ -203,15 +130,15 @@ void p9_fbc_no_hp_scom(void) uint64_t is_flat_8 = false; // REGISTERS read - uint64_t pb_com_pb_west_mode = read_scom(PB_WEST_MODE_CFG); - uint64_t pb_com_pb_cent_mode = read_scom(PB_CENT_MODE_CFG); - uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom(PB_CENT_GP_COMMAND_RATE_DP0); - uint64_t pb_com_pb_cent_gp_cmd_rate_dp1 = read_scom(PB_CENT_GP_COMMAND_RATE_DP1); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP0); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP1); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom(PB_CENT_SP_COMMAND_RATE_DP0); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom(PB_CENT_SP_COMMAND_RATE_DP1); - uint64_t pb_com_pb_east_mode = read_scom(PB_EAST_MODE_CFG); + uint64_t pb_com_pb_west_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG); + uint64_t pb_com_pb_cent_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG); + uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0); + uint64_t pb_com_pb_cent_gp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1); + uint64_t pb_com_pb_east_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG); if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) @@ -304,27 +231,27 @@ void p9_fbc_no_hp_scom(void) pb_com_pb_east_mode |= 0x00000002a0000000; // REGISTERS write - write_scom(PB_WEST_MODE_CFG, pb_com_pb_west_mode); - write_scom(PB_CENT_MODE_CFG, pb_com_pb_cent_mode); - write_scom(PB_CENT_GP_COMMAND_RATE_DP0, pb_com_pb_cent_gp_cmd_rate_dp0); - write_scom(PB_CENT_GP_COMMAND_RATE_DP1, pb_com_pb_cent_gp_cmd_rate_dp1); - write_scom(PB_CENT_RGP_COMMAND_RATE_DP0, pb_com_pb_cent_rgp_cmd_rate_dp0); - write_scom(PB_CENT_RGP_COMMAND_RATE_DP1, pb_com_pb_cent_rgp_cmd_rate_dp1); - write_scom(PB_CENT_SP_COMMAND_RATE_DP0, pb_com_pb_cent_sp_cmd_rate_dp0); - write_scom(PB_CENT_SP_COMMAND_RATE_DP1, pb_com_pb_cent_sp_cmd_rate_dp1); - write_scom(PB_EAST_MODE_CFG, pb_com_pb_east_mode); + write_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG, pb_com_pb_west_mode); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG, pb_com_pb_cent_mode); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0, pb_com_pb_cent_gp_cmd_rate_dp0); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1, pb_com_pb_cent_gp_cmd_rate_dp1); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0, pb_com_pb_cent_rgp_cmd_rate_dp0); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1, pb_com_pb_cent_rgp_cmd_rate_dp1); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0, pb_com_pb_cent_sp_cmd_rate_dp0); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1, pb_com_pb_cent_sp_cmd_rate_dp1); + write_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG, pb_com_pb_east_mode); } void p9_fbc_ioe_tl_scom(void) { - uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom(PB_ELE_PB_FRAMER_PARSER_01_CFG); - uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom(PB_ELE_PB_FRAMER_PARSER_23_CFG); - uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom(PB_ELE_PB_FRAMER_PARSER_45_CFG); - uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom(PB_ELE_PB_DATA_BUFF_01_CFG); - uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom(PB_ELE_PB_DATA_BUFF_23_CFG); - uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom(PB_ELE_PB_DATA_BUFF_45_CFG); - uint64_t pb_ioe_scom_pb_misc_cfg = read_scom(PB_ELE_MISC_CFG); - uint64_t pb_ioe_scom_pb_trace_cfg = read_scom(PB_ELE_LINK_TRACE_CFG); + uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG); + uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG); + uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG); + uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG); + uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG); + uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG); + uint64_t pb_ioe_scom_pb_misc_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG); + uint64_t pb_ioe_scom_pb_trace_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG); if(X0_ENABLED) { @@ -364,7 +291,7 @@ void p9_fbc_ioe_tl_scom(void) } // if (X2_ENABLED && DD2X_PARTS) // { - // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) + // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / )) // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) // } // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) @@ -494,14 +421,14 @@ void p9_fbc_ioe_tl_scom(void) } // REGISTERS write - write_scom(PB_ELE_PB_FRAMER_PARSER_01_CFG, pb_ioe_scom_pb_fp01_cfg); - write_scom(PB_ELE_PB_FRAMER_PARSER_23_CFG, pb_ioe_scom_pb_fp23_cfg); - write_scom(PB_ELE_PB_FRAMER_PARSER_45_CFG, pb_ioe_scom_pb_fp45_cfg); - write_scom(PB_ELE_PB_DATA_BUFF_01_CFG, pb_ioe_scom_pb_elink_data_01_cfg_reg); - write_scom(PB_ELE_PB_DATA_BUFF_23_CFG, pb_ioe_scom_pb_elink_data_23_cfg_reg); - write_scom(PB_ELE_PB_DATA_BUFF_45_CFG, pb_ioe_scom_pb_elink_data_45_cfg_reg); - write_scom(PB_ELE_MISC_CFG, pb_ioe_scom_pb_misc_cfg); - write_scom(PB_ELE_LINK_TRACE_CFG, pb_ioe_scom_pb_trace_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG, pb_ioe_scom_pb_fp01_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG, pb_ioe_scom_pb_fp23_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG, pb_ioe_scom_pb_fp45_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG, pb_ioe_scom_pb_elink_data_01_cfg_reg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG, pb_ioe_scom_pb_elink_data_23_cfg_reg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG, pb_ioe_scom_pb_elink_data_45_cfg_reg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG, pb_ioe_scom_pb_misc_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG, pb_ioe_scom_pb_trace_cfg); } void main(void) From ff2f7178431cfeff15d0e160339906a706594f78 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Wed, 17 Feb 2021 14:54:14 +0100 Subject: [PATCH 66/90] start implementation of istep 8.10 --- src/include/cpu/power/scom_registers.h | 73 +- src/mainboard/raptor-cs/talos-2/istep810.c | 3065 ++++++++++++++++++++ src/mainboard/raptor-cs/talos-2/romstage.c | 14 +- 3 files changed, 3098 insertions(+), 54 deletions(-) create mode 100644 src/mainboard/raptor-cs/talos-2/istep810.c diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index 0a51100ca6a..2d8a74b79bd 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -1,51 +1,30 @@ typedef enum { - // Power Bus PB West Mode Configuration Register - PB_WEST_MODE_CFG = 0x501180A, - // Power Bus PB CENT Mode Register - PB_CENT_MODE_CFG = 0x5011C0A, - // Power Bus PB CENT GP command RATE DP0 Register - PB_CENT_GP_COMMAND_RATE_DP0 = 0x5011C26, - // Power Bus PB CENT GP command RATE DP1 Register - PB_CENT_GP_COMMAND_RATE_DP1 = 0x5011C27, - // Power Bus PB CENT RGP command RATE DP0 Register - PB_CENT_RGP_COMMAND_RATE_DP0 = 0x5011C28, - // Power Bus PB CENT RGP command RATE DP1 Register - PB_CENT_RGP_COMMAND_RATE_DP1 = 0x5011C29, - // Power Bus PB CENT SP command RATE DP0 Register - PB_CENT_SP_COMMAND_RATE_DP0 = 0x5011C2A, - // Power Bus PB CENT SP command RATE DP1 Register - PB_CENT_SP_COMMAND_RATE_DP1 = 0x5011C2B, - // Power Bus PB East Mode Configuration Register - PB_EAST_MODE_CFG = 0x501200A, - // Power bus Electrical Framer/Parser 01 configuration register - PB_ELE_PB_FRAMER_PARSER_01_CFG = 0x501340A, - // Power Bus Electrical Framer/Parser 23 Configuration Register - PB_ELE_PB_FRAMER_PARSER_23_CFG = 0x501340B, - // Power Bus Electrical Framer/Parser 45 Configuration Register - PB_ELE_PB_FRAMER_PARSER_45_CFG = 0x501340C, - // Power Bus Electrical Link Data Buffer 01 Configuration Register - PB_ELE_PB_DATA_BUFF_01_CFG = 0x5013410, - // Power Bus Electrical Link Data Buffer 23 Configuration Register - PB_ELE_PB_DATA_BUFF_23_CFG = 0x5013411, - // Power Bus Electrical Link Data Buffer 45 Configuration Register - PB_ELE_PB_DATA_BUFF_45_CFG = 0x5013412, - // Power Bus Electrical Miscellaneous Configuration Register - PB_ELE_MISC_CFG = 0x5013423, - // Power Bus Electrical Link Trace Configuration Register - PB_ELE_LINK_TRACE_CFG = 0x5013424, - PU_PB_IOE_FIR_ACTION0_REG = 0x5013406, - PU_PB_IOE_FIR_ACTION1_REG = 0x5013407, + PB_WEST_MODE_CFG = 0x501180A, // Power Bus PB West Mode Configuration Register + PB_CENT_MODE_CFG = 0x5011C0A, // Power Bus PB CENT Mode Register + PB_CENT_GP_COMMAND_RATE_DP0 = 0x5011C26, // Power Bus PB CENT GP command RATE DP0 Register + PB_CENT_GP_COMMAND_RATE_DP1 = 0x5011C27, // Power Bus PB CENT GP command RATE DP1 Register + PB_CENT_RGP_COMMAND_RATE_DP0 = 0x5011C28, // Power Bus PB CENT RGP command RATE DP0 Register + PB_CENT_RGP_COMMAND_RATE_DP1 = 0x5011C29, // Power Bus PB CENT RGP command RATE DP1 Register + PB_CENT_SP_COMMAND_RATE_DP0 = 0x5011C2A, // Power Bus PB CENT SP command RATE DP0 Register + PB_CENT_SP_COMMAND_RATE_DP1 = 0x5011C2B, // Power Bus PB CENT SP command RATE DP1 Register + PB_EAST_MODE_CFG = 0x501200A, // Power Bus PB East Mode Configuration Register + PU_PB_IOE_FIR_ACTION0_REG = 0x5013406, + PU_PB_IOE_FIR_ACTION1_REG = 0x5013407, + PB_ELE_PB_FRAMER_PARSER_01_CFG =0x501340A, // Power bus Electrical Framer/Parser 01 configuration register + PB_ELE_PB_FRAMER_PARSER_23_CFG =0x501340B, // Power Bus Electrical Framer/Parser 23 Configuration Register + PB_ELE_PB_FRAMER_PARSER_45_CFG =0x501340C, // Power Bus Electrical Framer/Parser 45 Configuration Register + PB_ELE_PB_DATA_BUFF_01_CFG = 0x5013410, // Power Bus Electrical Link Data Buffer 01 Configuration Register + PB_ELE_PB_DATA_BUFF_23_CFG = 0x5013411, // Power Bus Electrical Link Data Buffer 23 Configuration Register + PB_ELE_PB_DATA_BUFF_45_CFG = 0x5013412, // Power Bus Electrical Link Data Buffer 45 Configuration Register + PB_ELE_MISC_CFG = 0x5013423, // Power Bus Electrical Miscellaneous Configuration Register + PB_ELE_LINK_TRACE_CFG = 0x5013424, // Power Bus Electrical Link Trace Configuration Register + XBUS_LL0_IOEL_FIR_MASK_REG = 0x6011803, XBUS_LL0_IOEL_FIR_ACTION0_REG = 0x6011806, XBUS_LL0_IOEL_FIR_ACTION1_REG = 0x6011807, - XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG = 0x6011803, - PB_ELE_CONFIG_REG = 0x601180A, - PB_ELE_REPLAY_TRESHOLD_REG = 0x6011818, - PB_ELE_ECC_TRESHOLD_REG = 0x6011819, - // ELL Configuration Register - ELL_CFG_REG = 0x601180A, - // ELL Replay Threshold Register - ELL_REPLAY_TRESHOLD_REG = 0x6011818, - // ELL SL ECC Threshold Register - ELL_SL_ECC_TRESHOLD_REG = 0x6011819, -} scom_reg_t + PB_ELL_CFG_REG = 0x601180A, // ELL Configuration Register + PB_ELL_REPLAY_TRESHOLD_REG = 0x6011818, // ELL Replay Threshold Register + PB_ELL_SL_ECC_TRESHOLD_REG = 0x6011819, // ELL SL ECC Threshold Register + XBUS_FIR_ACTION0_REG = 0x06010C06, + XBUS_FIR_ACTION1_REG = 0x06010C07, +} scom_reg_t; diff --git a/src/mainboard/raptor-cs/talos-2/istep810.c b/src/mainboard/raptor-cs/talos-2/istep810.c new file mode 100644 index 00000000000..edd9dd5fefa --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/istep810.c @@ -0,0 +1,3065 @@ +#include +#include + +#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) +#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) +#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) +#define XBUS_FIR_MASK_REG (0x06010C0) + +// void *call_proc_xbus_scominit(void *io_pArgs) +// { +// EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; +// // Note: +// // i_noDuplicate parameter must be set to true because +// // one call to p9_io_xbus_scominit will handle both +// // X0 <--> X1 +// // X1 <--> X0 +// // both the xbus and the connected target are used to issue SCOMs +// EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections(l_XbusConnections, TYPE_XBUS, true); +// for l_XbusConnection in l_XbusConnections: +// { +// // XBUS_GROUP_COUNT = 2 +// for group in range(0, XBUS_GROUP_COUNT): +// { +// p9_io_xbus_scominit(l_XbusConnection.first, l_XbusConnection.second, group); +// } +// } +// } + +// fapi2::ReturnCode p9_io_xbus_scominit( +// const fapi2::Target &i_target, +// const fapi2::Target &i_connected_target, +// const uint8_t group) +// { +// const uint8_t LANE_00 = 0; +// fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS; +// // get system target +// const fapi2::Target l_system_target; +// // get proc chip to pass for EC level checks in procedure +// fapi2::Target l_proc = i_target.getParent(); +// // assert IO reset to power-up bus endpoint logic +// // read-modify-write, set single reset bit (HW auto-clears) +// // on writeback +// EDIP_RX_IORESET[i_target, group, LANE_00] = 1; +// EDIP_RX_IORESET[i_connected_target, group, LANE_00] = 1; +// wait_us(50, false); +// EDIP_TX_IORESET[i_target, group, LANE_00] = 1; +// EDIP_TX_IORESET[i_connected_target, group, LANE_00] = 1; +// wait_us(50, false); +// // Set rx master/slave attribute prior to calling the scominit procedures. +// // The scominit procedure will reference the attribute to set the register field. +// set_rx_master_mode(i_target, i_connected_target); +// // Set Msb Swap based upon attribute data. +// set_msb_swap(i_target, group); +// set_msb_swap(i_connected_target, group); +// switch (group) +// { +// case ENUM_ATTR_XBUS_GROUP_0: +// p9_xbus_g0_scom(i_target, l_system_target, l_proc); +// p9_xbus_g0_scom(i_connected_target, l_system_target, l_proc); +// break; +// case ENUM_ATTR_XBUS_GROUP_1: +// p9_xbus_g1_scom(i_target, l_system_target, l_proc); +// p9_xbus_g1_scom(i_connected_target, l_system_target, l_proc); +// break; +// } + +// fapi2::buffer l_scom_data; +// l_scom_data = l_proc[PU_PB_CENT_SM0_PB_CENT_FIR_REG]; +// if(!l_scom_data.getBit<13>()) +// { + +// i_target[XBUS_FIR_ACTION0_REG] = XBUS_PHY_FIR_ACTION0; +// i_target[XBUS_FIR_ACTION1_REG] = XBUS_PHY_FIR_ACTION1; +// i_target[XBUS_FIR_MASK_REG] = XBUS_PHY_FIR_MASK; +// } +// } + +// void set_msb_swap(/*const Target*/uint64_t i_tgt, const uint8_t i_grp) +// { +// const uint8_t lane0 = 0; +// uint8_t tx_msb_swap = 0x0; +// uint8_t field_data = 0x0; + +// // Retrieve msb swap attribute +// tx_msb_swap = ATTR_EI_BUS_TX_MSBSWAP[i_tgt]; + +// if(i_grp == ENUM_ATTR_XBUS_GROUP_0 && (tx_msb_swap & ENUM_ATTR_EI_BUS_TX_MSBSWAP_GROUP_0_SWAP) +// || i_grp == ENUM_ATTR_XBUS_GROUP_1 && (tx_msb_swap & ENUM_ATTR_EI_BUS_TX_MSBSWAP_GROUP_1_SWAP)) +// { +// field_data = 1; +// } +// EDIP_TX_MSBSWAP[i_tgt, i_grp, lane0] = field_data; +// } + +// fapi2::ReturnCode set_rx_master_mode( +// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_target, +// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_ctarget ) +// { +// uint8_t l_primary_group_id = 0; +// uint8_t l_primary_chip_id = 0; +// uint32_t l_primary_id = 0; +// uint8_t l_primary_attr = 0; +// uint8_t l_connected_group_id = 0; +// uint8_t l_connected_chip_id = 0; +// uint32_t l_connected_id = 0; +// uint8_t l_connected_attr = 0; + +// p9_get_proc_fabric_group_id(i_target, l_primary_group_id); +// p9_get_proc_fabric_group_id(i_ctarget, l_connected_group_id); + +// p9_get_proc_fabric_chip_id(i_target, l_primary_chip_id); +// p9_get_proc_fabric_chip_id(i_ctarget, l_connected_chip_id); + +// l_primary_id = ((uint32_t)l_primary_group_id << 8) + (uint32_t)l_primary_chip_id; +// l_connected_id = ((uint32_t)l_connected_group_id << 8) + (uint32_t)l_connected_chip_id; + +// if(l_primary_id < l_connected_id) { +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; +// } +// else { +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; +// } +// } + +// fapi2::ReturnCode p9_get_proc_fabric_group_id( +// const fapi2::Target& i_target, uint8_t& o_group_id) +// { +// fapi2::Target l_proc = i_target.getParent(); +// // Retrieve node attribute +// o_group_id = fapi2::ATTR_PROC_FABRIC_GROUP_ID[l_proc]; +// } + +// fapi2::ReturnCode p9_get_proc_fabric_chip_id( +// const fapi2::Target& i_target, uint8_t& o_chip_id) +// { +// fapi2::Target l_proc = i_target.getParent(); +// // Retrieve pos ID attribute +// o_chip_id = fapi2::ATTR_PROC_FABRIC_CHIP_ID[l_proc]; +// } + +// default value +#define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) + +void p9_xbus_g0_scom( + /*const fapi2::Target &*/ uint64_t TGT0, + /*const fapi2::Target &*/ uint64_t TGT1, + /*const fapi2::Target &*/ uint64_t TGT2) +{ + uint64_t l_scom_buffer; + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000006010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000106010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000206010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000306010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000406010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000506010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000606010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000706010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000806010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000906010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000A06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000B06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000C06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000D06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000E06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000000F06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000000F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000001006010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000001006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000001106010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; + write_scom(0x8000001106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080006010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080106010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080206010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080306010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080406010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080506010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080606010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080706010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080806010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080906010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080A06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080B06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080C06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080D06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080E06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000080F06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000080F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000081006010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000081006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000081106010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8000081106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000280F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000280F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000281006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000281006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000281106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000281106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300906010C3F, l_scom_buffer); + + l_scom_buffer = read_scom(0x8000300A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000300F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000300F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000301006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000301006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000301106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000301106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C00F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C00F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C01006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C01006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C01106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C01106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200706010C3F, l_scom_buffer); + + l_scom_buffer = read_scom(0x8002200806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002200F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002200F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002201006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002201006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002201106010C3F); + l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON + write_scom(0x8002201106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00006010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1000; + write_scom(0x8002C00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00106010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFFF03E; + write_scom(0x8002C00106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00206010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07BC; + write_scom(0x8002C00206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00306010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07C7; + write_scom(0x8002C00306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00406010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF03EF; + write_scom(0x8002C00406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00506010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; + write_scom(0x8002C00506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00606010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1800; + write_scom(0x8002C00606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00706010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF9C00; + write_scom(0x8002C00706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00806010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1000; + write_scom(0x8002C00806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00906010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF9C00; + write_scom(0x8002C00906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00A06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1800; + write_scom(0x8002C00A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00B06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; + write_scom(0x8002C00B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00C06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF03EF; + write_scom(0x8002C00C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00D06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07C7; + write_scom(0x8002C00D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00E06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07BC; + write_scom(0x8002C00E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C00F06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFFF03E; + write_scom(0x8002C00F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C01006010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1000; + write_scom(0x8002C01006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80006010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004200; + write_scom(0x8002C80006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80106010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000003E00; + write_scom(0x8002C80106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80206010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + write_scom(0x8002C80206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80306010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000006000; + write_scom(0x8002C80306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80406010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C80406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80506010C3F); + // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C80506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80606010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C80606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80706010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C80706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80806010C3F); + // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004200; + write_scom(0x8002C80806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80906010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C80906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80A06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C80A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80B06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C80B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80C06010C3F); + // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C80C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80D06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000006000; + write_scom(0x8002C80D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80E06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + write_scom(0x8002C80E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C80F06010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000003E00; + write_scom(0x8002C80F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C81006010C3F); + // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004200; + write_scom(0x8002C81006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004040F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004040F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004041006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004041006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0006010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0106010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0206010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0306010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0406010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0506010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0606010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0706010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0806010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0906010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0A06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0B06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0C06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0D06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0E06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C0F06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C0F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C1006010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C1006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C0106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0206010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001E; + write_scom(0x80043C0206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0306010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001F; + write_scom(0x80043C0306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0406010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000000F; + write_scom(0x80043C0406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0506010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000007C; + write_scom(0x80043C0506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0606010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000C63; + write_scom(0x80043C0606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0706010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000E73; + write_scom(0x80043C0706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C0806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0906010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000E73; + write_scom(0x80043C0906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0A06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000C63; + write_scom(0x80043C0A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0B06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000007C; + write_scom(0x80043C0B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0C06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000000F; + write_scom(0x80043C0C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0D06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001F; + write_scom(0x80043C0D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0E06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001E; + write_scom(0x80043C0E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C0F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C0F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C1006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C1006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440006010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8004440006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440106010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000F800; + write_scom(0x8004440106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440206010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000F600; + write_scom(0x8004440206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440306010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004440306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440406010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004440406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440506010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000002000; + write_scom(0x8004440506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440606010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004440606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440706010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004440706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440806010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8004440806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440906010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000009C00; + write_scom(0x8004440906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440A06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004440A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440B06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004440B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440C06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004440C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440D06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004440D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440E06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004440E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004440F06010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000F800; + write_scom(0x8004440F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004441006010C3F); + // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8004441006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_SPARE_MODE_PG + l_scom_buffer = read_scom(0x8008000006010C3F); + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8008000006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_ID1_PG + l_scom_buffer = read_scom(0x8008080006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF03FF; + write_scom(0x8008080006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE1_EO_PG + l_scom_buffer = read_scom(0x8008100006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF + write_scom(0x8008100006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE5_EO_PG + l_scom_buffer = read_scom(0x8008300006010C3F); + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + l_scom_buffer &= 0xffffffffffffe0ff; + l_scom_buffer |= 0x0000000000001500; + write_scom(0x8008300006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE7_EO_PG + l_scom_buffer = read_scom(0x8008400006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFFF0; + l_scom_buffer |= 0x000000000000000A; + write_scom(0x8008400006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG + l_scom_buffer = read_scom(0x8008C00006010C3F); + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON + l_scom_buffer &= 0xFFFFFFFFFFFF3E07; + l_scom_buffer |= 0x00000000000010F8; + write_scom(0x8008C00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE29_EO_PG + l_scom_buffer = read_scom(0x8008D00006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000001044; + write_scom(0x8008D00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE27_EO_PG + l_scom_buffer = read_scom(0x8009700006010C3F); + l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON + write_scom(0x8009700006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_ID2_PG + l_scom_buffer = read_scom(0x8009800006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF8080; + l_scom_buffer |= 0x0000000000000010; + write_scom(0x8009800006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE1_E_PG + l_scom_buffer = read_scom(0x8009900006010C3F); + if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) { + l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER + } + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED + l_scom_buffer |= 0x0000000000000060; + write_scom(0x8009900006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE2_E_PG + l_scom_buffer = read_scom(0x8009980006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF07FF; + l_scom_buffer |= 0x0000000000000800; + write_scom(0x8009980006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE3_E_PG + l_scom_buffer = read_scom(0x8009A00006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; + l_scom_buffer |= 0x000000000000B000; + write_scom(0x8009A00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE5_E_PG + l_scom_buffer = read_scom(0x8009B00006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; + l_scom_buffer |= 0x0000000000001000; + write_scom(0x8009B00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE6_E_PG + l_scom_buffer = read_scom(0x8009B80006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + l_scom_buffer |= 0x0000000000002244; + write_scom(0x8009B80006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE8_E_PG + l_scom_buffer = read_scom(0x8009C80006010C3F); + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 + l_scom_buffer &= 0xffffffffffff0018; + l_scom_buffer |= 0x0000000000001ea5; + write_scom(0x8009C80006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE9_E_PG + l_scom_buffer = read_scom(0x8009D00006010C3F); + // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 + l_scom_buffer &= 0xffffffffffff001f; + l_scom_buffer |= 0x0000000000003fa0; + write_scom(0x8009D00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE11_E_PG + l_scom_buffer = read_scom(0x8009E00006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + write_scom(0x8009E00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE12_E_PG + l_scom_buffer = read_scom(0x8009E80006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + l_scom_buffer |= 0x0000000000007F00; + write_scom(0x8009E80006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_GLBSM_SPARE_MODE_PG + l_scom_buffer = read_scom(0x800A800006010C3F); + // l_IOF1_RX_RX0_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + // l_IOF1_RX_RX0_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON + l_scom_buffer |= 0x10000010000000; + write_scom(0x800A800006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_GLBSM_CNTL3_EO_PG + l_scom_buffer = read_scom(0x800AE80006010C3F); + l_scom_buffer.insert<56, 2, 62, uint64_t>(0x02); + write_scom(0x800AE80006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_GLBSM_MODE1_EO_PG + l_scom_buffer = read_scom(0x800AF80006010C3F); + l_scom_buffer.insert<48, 4, 60, uint64_t>(0x0C); + l_scom_buffer.insert<52, 4, 60, uint64_t>(0x0C); + write_scom(0x800AF80006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_DATASM_SPARE_MODE_PG + l_scom_buffer = read_scom(0x800B800006010C3F); + l_scom_buffer.insert<60, 1, 63, uint64_t>(0x0); // l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + write_scom(0x800B800006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_SPARE_MODE_PG + l_scom_buffer = read_scom(0x800C040006010C3F); + l_scom_buffer.insert<56, 2, 62, uint64_t>(0); + write_scom(0x800C040006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_ID1_PG + l_scom_buffer = read_scom(0x800C0C0006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF03FF; + write_scom(0x800C0C0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTL_MODE1_EO_PG + l_scom_buffer = read_scom(0x800C140006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON + l_scom_buffer.insert<53, 5, 59, uint64_t>(0b00001); + write_scom(0x800C140006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTL_MODE2_EO_PG + l_scom_buffer = read_scom(0x800C1C0006010C3F); + l_scom_buffer.insert<56, 7, 57, uint64_t>(0x11); + write_scom(0x800C1C0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTL_CNTLG1_EO_PG + l_scom_buffer = read_scom(0x800C240006010C3F); + l_scom_buffer.insert<48, 2, 62, uint64_t>(0x0); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S + write_scom(0x800C240006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_ID2_PG + l_scom_buffer = read_scom(0x800C840006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF8080; + l_scom_buffer |= 0x0000000000000010; + write_scom(0x800C840006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTL_MODE1_E_PG + l_scom_buffer = read_scom(0x800C8C0006010C3F); + l_scom_buffer.insert<55, 3, 61, uint64_t>(0x5); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + l_scom_buffer.insert<58, 2, 62, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + write_scom(0x800C8C0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTL_MODE2_E_PG + l_scom_buffer = read_scom(0x800CEC0006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + write_scom(0x800CEC0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTL_MODE3_E_PG + l_scom_buffer = read_scom(0x800CF40006010C3F); + l_scom_buffer.insert<48, 8, 56, uint64_t>(0x71111); + write_scom(0x800CF40006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX0_TX_CTLSM_MODE1_EO_PG + l_scom_buffer = read_scom(0x800D2C0006010C3F); + l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX0_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON + write_scom(0x800D2C0006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX_IMPCAL_P_4X_PB + l_scom_buffer = read_scom(0x800F1C0006010C3F); + l_scom_buffer.insert<48, 5, 59, uint64_t>(0x70); + write_scom(0x800F1C0006010C3F, l_scom_buffer); +} + +fapi2::ReturnCode p9_xbus_g1_scom( + const fapi2::Target &TGT0, + const fapi2::Target &TGT1, + const fapi2::Target &TGT2) +{ + l_chip_id = fapi2::ATTR_NAME[TGT2]; + l_chip_ec = fapi2::ATTR_EC[TGT2]; + l_TGT1_ATTR_IS_SIMULATION = fapi2::ATTR_IS_SIMULATION[TGT1]; + l_TGT0_ATTR_IO_XBUS_MASTER_MODE = fapi2::ATTR_IO_XBUS_MASTER_MODE[TGT0]; + fapi2::buffer l_scom_buffer; + + // P9A_XBUS_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002006010C3F); + //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002106010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002206010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002306010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002406010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002506010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002606010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002706010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002806010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002906010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002A06010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002B06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002C06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002D06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002E06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000002F06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000002F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000003006010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000003006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + l_scom_buffer = read_scom(0x8000003106010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + l_scom_buffer &= 0xfffffffffffff8ff; + write_scom(0x8000003106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + write_scom(0x8000082706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082806010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082906010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082A06010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082B06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082C06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082D06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082E06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000082F06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000082F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000083006010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; + write_scom(0x8000083006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL + l_scom_buffer = read_scom(0x8000083106010C3F); + l_scom_buffer.insert<54, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON + write_scom(0x8000083106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000282F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000282F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000283006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000283006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL + l_scom_buffer = read_scom(0x8000283106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0003; + write_scom(0x8000283106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000302F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000302F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000303006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000303006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL + l_scom_buffer = read_scom(0x8000303106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF007F; + l_scom_buffer |= 0x0000000000006380; + write_scom(0x8000303106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C02F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C02F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C03006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C03006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL + l_scom_buffer = read_scom(0x8000C03106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0007; + write_scom(0x8000C03106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002202F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002202F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002203006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + write_scom(0x8002203006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL + l_scom_buffer = read_scom(0x8002203106010C3F); + l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON + write_scom(0x8002203106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02006010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1000; + write_scom(0x8002C02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02106010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFFF03E; + write_scom(0x8002C02106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02206010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07BC; + write_scom(0x8002C02206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02306010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07C7; + write_scom(0x8002C02306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02406010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF03EF; + write_scom(0x8002C02406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02506010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; + write_scom(0x8002C02506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02606010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1800; + write_scom(0x8002C02606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02706010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF9C00; + write_scom(0x8002C02706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02806010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1000; + write_scom(0x8002C02806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02906010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF9C00; + write_scom(0x8002C02906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02A06010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1800; + write_scom(0x8002C02A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02B06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; + write_scom(0x8002C02B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02C06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF03EF; + write_scom(0x8002C02C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02D06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07C7; + write_scom(0x8002C02D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C02E06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF07BC; + write_scom(0x8002C02E06010C3F, l_scom_buffer); + + l_scom_buffer = read_scom(0x8002C02F06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFFF03E; + write_scom(0x8002C02F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x8002C03006010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0xFFFFFFFFFFFF1000; + write_scom(0x8002C03006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82006010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF + l_scom_buffer |= 0x0000000000004200 + write_scom(0x8002C82006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82106010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000003E00; + write_scom(0x8002C82106010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82206010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF + write_scom(0x8002C82206010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82306010C3F); + // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000006000; + write_scom(0x8002C82306010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82406010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C82406010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82506010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C82506010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82606010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C82606010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82706010C3F); + // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C82706010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82806010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF + l_scom_buffer |= 0x0000000000004200 + write_scom(0x8002C82806010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82906010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C82906010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82A06010C3F); + // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000300; + write_scom(0x8002C82A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82B06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C82B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82C06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8002C82C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82D06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000006000; + write_scom(0x8002C82D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82E06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF + write_scom(0x8002C82E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C82F06010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000003E00; + write_scom(0x8002C82F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8002C83006010C3F); + // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF + l_scom_buffer |= 0x0000000000004200 + write_scom(0x8002C83006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042206010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042206010C3F, l_scom_buffer); + + l_scom_buffer = read_scom(0x8004042306010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042406010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042506010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042606010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042706010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042906010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042A06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042B06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042C06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042D06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042E06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004042F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004042F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE1_PL + l_scom_buffer = read_scom(0x8004043006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + write_scom(0x8004043006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2006010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2106010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2106010C3F, l_scom_buffer); + + l_scom_buffer = read_scom(0x80040C2206010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2306010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2406010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2506010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2606010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2706010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2806010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2906010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2A06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2B06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2C06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2D06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2E06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C2F06010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C2F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE2_PL + l_scom_buffer = read_scom(0x80040C3006010C3F); + l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + write_scom(0x80040C3006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2106010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C2106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2206010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001E; + write_scom(0x80043C2206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2306010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001F; + write_scom(0x80043C2306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2406010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000000F; + write_scom(0x80043C2406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2506010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000007C; + write_scom(0x80043C2506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2606010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000C63; + write_scom(0x80043C2606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2706010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000E73; + write_scom(0x80043C2706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2806010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C2806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2906010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000E73; + write_scom(0x80043C2906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2A06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000000C63; + write_scom(0x80043C2A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2B06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000007C; + write_scom(0x80043C2B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2C06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000000F; + write_scom(0x80043C2C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2D06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001F; + write_scom(0x80043C2D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2E06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x000000000000001E; + write_scom(0x80043C2E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C2F06010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C2F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL + l_scom_buffer = read_scom(0x80043C3006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 + write_scom(0x80043C3006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442006010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8004442006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442106010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000F800; + write_scom(0x8004442106010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442206010C3F); + l_scom_buffer.insert<48, 7, 57, uint64_t>(0x7b); // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + write_scom(0x8004442206010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442306010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004442306010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442406010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004442406010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442506010C3F); + l_scom_buffer.insert<48, 7, 57, uint64_t>(0x10); // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + write_scom(0x8004442506010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442606010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004442606010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442706010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004442706010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442806010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8004442806010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442906010C3F); + l_scom_buffer.insert<48, 7, 57, uint64_t>(0x4e); // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + write_scom(0x8004442906010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442A06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004442A06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442B06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004442B06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442C06010C3F); + l_scom_buffer.insert<48, 7, 57, uint64_t>(0x5e); // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + write_scom(0x8004442C06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442D06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000001800; + write_scom(0x8004442D06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442E06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000BC00; + write_scom(0x8004442E06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004442F06010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000F800; + write_scom(0x8004442F06010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL + l_scom_buffer = read_scom(0x8004443006010C3F); + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000000200; + write_scom(0x8004443006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_SPARE_MODE_PG + l_scom_buffer = read_scom(0x8008002006010C3F); + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON + l_scom_buffer |= 0x0000000000004000; + write_scom(0x8008002006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_ID1_PG + l_scom_buffer = read_scom(0x8008082006010C3F); + l_scom_buffer.insert<48, 6, 58, uint64_t>(1); + write_scom(0x8008082006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE1_EO_PG + l_scom_buffer = read_scom(0x8008102006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF + write_scom(0x8008102006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE5_EO_PG + l_scom_buffer = read_scom(0x8008302006010C3F); + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + l_scom_buffer &= 0xffffffffffffe0ff; + l_scom_buffer |= 0x0000000000001500; + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + write_scom(0x8008302006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE7_EO_PG + l_scom_buffer = read_scom(0x8008402006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFFF0; + l_scom_buffer |= 0x000000000000000A; + write_scom(0x8008402006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG + l_scom_buffer = read_scom(0x8008C00006010C3F); + l_scom_buffer.insert<48, 2, 62, uint64_t>(0b01); + write_scom(0x8008C00006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG + l_scom_buffer = read_scom(0x8008C02006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFFFEFF; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + l_scom_buffer.insert<57, 2, 62, uint64_t>(0x3); + l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + l_scom_buffer.insert<60, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON + l_scom_buffer.insert<56, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON + write_scom(0x8008C02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG + l_scom_buffer = read_scom(0x8008D02006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0000; + l_scom_buffer |= 0x0000000000001044; + write_scom(0x8008D02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG + l_scom_buffer = read_scom(0x8009702006010C3F); + l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON + write_scom(0x8009702006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_ID2_PG + l_scom_buffer = read_scom(0x8009802006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF8080; + l_scom_buffer |= 0x0000000000000010; + write_scom(0x8009802006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG + l_scom_buffer = read_scom(0x8009902006010C3F); + if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) { + l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER + } + l_scom_buffer.insert<58, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + l_scom_buffer.insert<57, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED + write_scom(0x8009902006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG + l_scom_buffer = read_scom(0x8009982006010C3F); + l_scom_buffer.insert<48, 5, 59, uint64_t>(0x01); + write_scom(0x8009982006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG + l_scom_buffer = read_scom(0x8009A02006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; + l_scom_buffer |= 0x000000000000B000; + write_scom(0x8009A02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG + l_scom_buffer = read_scom(0x8009B02006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; + l_scom_buffer |= 0x0000000000001000; + write_scom(0x8009B02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG + l_scom_buffer = read_scom(0x8009B82006010C3F); + l_scom_buffer &= 0xffffffffffff0003; + l_scom_buffer |= 0x0000000000002244; + write_scom(0x8009B82006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG + l_scom_buffer = read_scom(0x8009C82006010C3F); + l_scom_buffer.insert<48, 7, 57, uint64_t>(0x1111); + l_scom_buffer.insert<55, 4, 60, uint64_t>(0x5); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 + l_scom_buffer.insert<61, 3, 61, uint64_t>(0x05); + write_scom(0x8009C82006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG + l_scom_buffer = read_scom(0x8009D02006010C3F); + l_scom_buffer.insert<48, 7, 57, uint64_t>(0x7111); + l_scom_buffer.insert<55, 4, 60, uint64_t>(0x5); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 + write_scom(0x8009D02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE11_E_PG + l_scom_buffer = read_scom(0x8009E02006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + write_scom(0x8009E02006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG + l_scom_buffer = read_scom(0x8009E82006010C3F); + l_scom_buffer.insert<48, 8, 56, uint64_t>(0x71111); + write_scom(0x8009E82006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG + l_scom_buffer = read_scom(0x800A802006010C3F); + l_scom_buffer.insert<56, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + l_scom_buffer.insert<50, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON + write_scom(0x800A802006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG + l_scom_buffer = read_scom(0x800AE82006010C3F); + l_scom_buffer.insert<56, 2, 62, uint64_t>(0x02); + write_scom(0x800AE82006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG + l_scom_buffer = read_scom(0x800AF82006010C3F); + l_scom_buffer.insert<48, 4, 60, uint64_t>(0x0C); + l_scom_buffer.insert<52, 4, 60, uint64_t>(0x0C); + write_scom(0x800AF82006010C3F, l_scom_buffer); + + // P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG + l_scom_buffer = read_scom(0x800B802006010C3F); + l_scom_buffer.insert<60, 1, 63, uint64_t>(0x0); // l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + write_scom(0x800B802006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_SPARE_MODE_PG + l_scom_buffer = read_scom(0x800C042006010C3F); + l_scom_buffer.insert<56, 2, 62, uint64_t>(0); + write_scom(0x800C042006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_ID1_PG + l_scom_buffer = read_scom(0x800C0C2006010C3F); + l_scom_buffer.insert<48, 6, 58, uint64_t>(1); + write_scom(0x800C0C2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG + l_scom_buffer = read_scom(0x800C142006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON + l_scom_buffer.insert<53, 5, 59, uint64_t>(0b00001); + write_scom(0x800C142006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG + l_scom_buffer = read_scom(0x800C1C2006010C3F); + l_scom_buffer.insert<56, 7, 57, uint64_t>(0x11); + write_scom(0x800C1C2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG + l_scom_buffer = read_scom(0x800C242006010C3F); + l_scom_buffer.insert<48, 2, 62, uint64_t>(0x0); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S + write_scom(0x800C242006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_ID2_PG + l_scom_buffer = read_scom(0x800C842006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF8080; + l_scom_buffer |= 0x0000000000000010; + write_scom(0x800C842006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG + l_scom_buffer = read_scom(0x800C8C2006010C3F); + l_scom_buffer.insert<55, 3, 61, uint64_t>(0x5); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + l_scom_buffer.insert<58, 2, 62, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + write_scom(0x800C8C2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG + l_scom_buffer = read_scom(0x800CEC2006010C3F); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + write_scom(0x800CEC2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG + l_scom_buffer = read_scom(0x800CF42006010C3F); + l_scom_buffer.insert<48, 8, 56, uint64_t>(0x71111); + write_scom(0x800CF42006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG + l_scom_buffer = read_scom(0x800D2C2006010C3F); + l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON + write_scom(0x800D2C2006010C3F, l_scom_buffer); + + // P9A_XBUS_0_TX_IMPCAL_P_4X_PB + l_scom_buffer = read_scom(0x800F1C0006010C3F); + l_scom_buffer.insert<48, 5, 59, uint64_t>(0x70); + write_scom(0x800F1C0006010C3F, l_scom_buffer); +} diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 167ecf46c2f..1ff78c45ed2 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -64,15 +64,15 @@ void istep89(void) p9_fbc_ioe_dl_scom(XB_CHIPLET_ID); write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); printk(BIOS_EMERG, "ending istep 8.9\n"); } void p9_fbc_ioe_dl_scom(uint64_t TGT0) { - uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, ELL_CFG_REG); - uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, ELL_REPLAY_TRESHOLD_REG); - uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, ELL_SL_ECC_TRESHOLD_REG); + uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, PB_ELL_CFG_REG); + uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG); + uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG); if (ATTR_LINK_TRAIN == BOTH) { pb_ioe_ll0_ioel_config |= 0x8000000000000000; @@ -88,9 +88,9 @@ void p9_fbc_ioe_dl_scom(uint64_t TGT0) pb_ioe_ll0_ioel_sl_ecc_threshold &= 0x7FFFFFFFFFFFFFFF; pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F70000000000000; - write_scom_for_chiplet(TGT0, ELL_CFG_REG, pb_ioe_ll0_ioel_config); - write_scom_for_chiplet(TGT0, ELL_REPLAY_TRESHOLD_REG, pb_ioe_ll0_ioel_replay_threshold); - write_scom_for_chiplet(TGT0, ELL_SL_ECC_TRESHOLD_REG, pb_ioe_ll0_ioel_sl_ecc_threshold); + write_scom_for_chiplet(TGT0, PB_ELL_CFG_REG, pb_ioe_ll0_ioel_config); + write_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG, pb_ioe_ll0_ioel_replay_threshold); + write_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG, pb_ioe_ll0_ioel_sl_ecc_threshold); } void tl_fir(void) From 7b0365c40848ddde2806c04c3be5d1278ab89d6b Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 18 Feb 2021 12:55:30 +0100 Subject: [PATCH 67/90] cpu/power9: fix directory structure and timer build fault Signed-off-by: Krystian Hebel --- src/cpu/Makefile.inc | 2 +- src/cpu/{power => }/power9/Kconfig | 1 - src/cpu/{power => }/power9/Makefile.inc | 0 src/cpu/{power => }/power9/power9.c | 0 src/cpu/{power => }/power9/scom.c | 0 src/mainboard/raptor-cs/talos-2/devicetree.cb | 2 +- 6 files changed, 2 insertions(+), 3 deletions(-) rename src/cpu/{power => }/power9/Kconfig (86%) rename src/cpu/{power => }/power9/Makefile.inc (100%) rename src/cpu/{power => }/power9/power9.c (100%) rename src/cpu/{power => }/power9/scom.c (100%) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 3a61b3eeb9d..93d2d27e01e 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -7,7 +7,7 @@ subdirs-y += intel subdirs-y += ti subdirs-$(CONFIG_ARCH_X86) += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 -subdirs-$(CONFIG_CPU_POWER9) += power/power9 +subdirs-$(CONFIG_CPU_POWER9) += power9 $(eval $(call create_class_compiler,cpu_microcode,x86_32)) ################################################################################ diff --git a/src/cpu/power/power9/Kconfig b/src/cpu/power9/Kconfig similarity index 86% rename from src/cpu/power/power9/Kconfig rename to src/cpu/power9/Kconfig index 6eaa5027c9f..c3a628cc343 100644 --- a/src/cpu/power/power9/Kconfig +++ b/src/cpu/power9/Kconfig @@ -6,4 +6,3 @@ config CPU_POWER9 select ARCH_VERSTAGE_PPC64 select ARCH_ROMSTAGE_PPC64 select ARCH_RAMSTAGE_PPC64 - select NO_MONOTONIC_TIMER diff --git a/src/cpu/power/power9/Makefile.inc b/src/cpu/power9/Makefile.inc similarity index 100% rename from src/cpu/power/power9/Makefile.inc rename to src/cpu/power9/Makefile.inc diff --git a/src/cpu/power/power9/power9.c b/src/cpu/power9/power9.c similarity index 100% rename from src/cpu/power/power9/power9.c rename to src/cpu/power9/power9.c diff --git a/src/cpu/power/power9/scom.c b/src/cpu/power9/scom.c similarity index 100% rename from src/cpu/power/power9/scom.c rename to src/cpu/power9/scom.c diff --git a/src/mainboard/raptor-cs/talos-2/devicetree.cb b/src/mainboard/raptor-cs/talos-2/devicetree.cb index 1a090890d58..7ea6247070e 100644 --- a/src/mainboard/raptor-cs/talos-2/devicetree.cb +++ b/src/mainboard/raptor-cs/talos-2/devicetree.cb @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -chip cpu/power/power9 +chip cpu/power9 device cpu_cluster 0 on end end From 7595dc1cfdc979d169c41e9720469e8d40b900c7 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Thu, 18 Feb 2021 14:24:18 +0100 Subject: [PATCH 68/90] add istep 8.10 --- src/include/cpu/power/isteps.h | 58 +++ src/include/cpu/power/scom.h | 12 +- src/include/cpu/power/scom_registers.h | 57 ++- src/mainboard/raptor-cs/talos-2/Makefile.inc | 3 + src/mainboard/raptor-cs/talos-2/istep810.c | 291 +++++++------ src/mainboard/raptor-cs/talos-2/istep89.c | 345 +++++++++++++++ src/mainboard/raptor-cs/talos-2/romstage.c | 430 +------------------ src/soc/ibm/power9/romstage.c | 2 + 8 files changed, 604 insertions(+), 594 deletions(-) create mode 100644 src/include/cpu/power/isteps.h create mode 100644 src/mainboard/raptor-cs/talos-2/istep89.c diff --git a/src/include/cpu/power/isteps.h b/src/include/cpu/power/isteps.h new file mode 100644 index 00000000000..9951a4b626e --- /dev/null +++ b/src/include/cpu/power/isteps.h @@ -0,0 +1,58 @@ +#include + +#define X0_ENABLED (true) +#define X1_ENABLED (true) +#define X2_ENABLED (true) +#define X0_IS_PAIRED (true) +#define X1_IS_PAIRED (true) +#define X2_IS_PAIRED (true) +#define DD2X_PARTS (true) +#define OPTICS_IS_A_BUS (true) +#define ATTR_PROC_FABRIC_A_LINKS_CNFG (0) +#define ATTR_PROC_FABRIC_X_LINKS_CNFG (0) + +#define EPS_TYPE_LE (0x01), +#define EPS_TYPE_HE (0x02), +#define EPS_TYPE_HE_F8 (0x03) +#define ATTR_PROC_EPS_TABLE_TYPE (EPS_TYPE_LE) // default value + +#define CHIP_IS_NODE (0x01) +#define CHIP_IS_GROUP (0x02) +#define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) // default value + +#define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) +#define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) + +#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) +#define P9_FBC_UTILS_MAX_ELECTRICAL_LINKS (3) +#define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) +#define FBC_IOE_TL_FIR_MASK_X1_NF (0x0018030300000440ULL) +#define FBC_IOE_TL_FIR_MASK_X2_NF (0x000300C0C0000220ULL) +#define PU_PB_IOE_FIR_MASK_REG (0x5013403) + +#define FBC_IOE_DL_FIR_ACTION0 (0) +#define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) +#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) + +#define BOTH (0x0) +#define EVEN_ONLY (0x1) +#define ODD_ONLY (0x2) +#define NONE (0x3) +#define ATTR_LINK_TRAIN BOTH + +#define PROC_CHIPLET (0x10) // this is probably wrong +#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) +#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) +#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) +#define XBUS_FIR_MASK_REG (0x06010C0) +#define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) // default value + +void istep810(void); +void p9_xbus_g1_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); +void p9_xbus_g0_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); + +void p9_fbc_ioe_tl_scom(void); +void istep89(void); +void p9_fbc_no_hp_scom(void); +void tl_fir(void); +void p9_fbc_ioe_dl_scom(uint64_t TGT0); diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index 036357cf0ca..a839f84c619 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -120,17 +120,17 @@ void write_scom_indirect(uint64_t reg_address, uint64_t data); static inline void write_scom(uint64_t addr, uint64_t data) { - // if (addr & XSCOM_ADDR_IND_FLAG) - // write_scom_indirect(addr, data); - // else + if (addr & XSCOM_ADDR_IND_FLAG) + write_scom_indirect(addr, data); + else write_scom_direct(addr, data); } static inline uint64_t read_scom(uint64_t addr) { - // if (addr & XSCOM_ADDR_IND_FLAG) - // return read_scom_indirect(addr); - // else + if (addr & XSCOM_ADDR_IND_FLAG) + return read_scom_indirect(addr); + else return read_scom_direct(addr); } diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index 2d8a74b79bd..56148f64796 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -1,30 +1,27 @@ -typedef enum -{ - PB_WEST_MODE_CFG = 0x501180A, // Power Bus PB West Mode Configuration Register - PB_CENT_MODE_CFG = 0x5011C0A, // Power Bus PB CENT Mode Register - PB_CENT_GP_COMMAND_RATE_DP0 = 0x5011C26, // Power Bus PB CENT GP command RATE DP0 Register - PB_CENT_GP_COMMAND_RATE_DP1 = 0x5011C27, // Power Bus PB CENT GP command RATE DP1 Register - PB_CENT_RGP_COMMAND_RATE_DP0 = 0x5011C28, // Power Bus PB CENT RGP command RATE DP0 Register - PB_CENT_RGP_COMMAND_RATE_DP1 = 0x5011C29, // Power Bus PB CENT RGP command RATE DP1 Register - PB_CENT_SP_COMMAND_RATE_DP0 = 0x5011C2A, // Power Bus PB CENT SP command RATE DP0 Register - PB_CENT_SP_COMMAND_RATE_DP1 = 0x5011C2B, // Power Bus PB CENT SP command RATE DP1 Register - PB_EAST_MODE_CFG = 0x501200A, // Power Bus PB East Mode Configuration Register - PU_PB_IOE_FIR_ACTION0_REG = 0x5013406, - PU_PB_IOE_FIR_ACTION1_REG = 0x5013407, - PB_ELE_PB_FRAMER_PARSER_01_CFG =0x501340A, // Power bus Electrical Framer/Parser 01 configuration register - PB_ELE_PB_FRAMER_PARSER_23_CFG =0x501340B, // Power Bus Electrical Framer/Parser 23 Configuration Register - PB_ELE_PB_FRAMER_PARSER_45_CFG =0x501340C, // Power Bus Electrical Framer/Parser 45 Configuration Register - PB_ELE_PB_DATA_BUFF_01_CFG = 0x5013410, // Power Bus Electrical Link Data Buffer 01 Configuration Register - PB_ELE_PB_DATA_BUFF_23_CFG = 0x5013411, // Power Bus Electrical Link Data Buffer 23 Configuration Register - PB_ELE_PB_DATA_BUFF_45_CFG = 0x5013412, // Power Bus Electrical Link Data Buffer 45 Configuration Register - PB_ELE_MISC_CFG = 0x5013423, // Power Bus Electrical Miscellaneous Configuration Register - PB_ELE_LINK_TRACE_CFG = 0x5013424, // Power Bus Electrical Link Trace Configuration Register - XBUS_LL0_IOEL_FIR_MASK_REG = 0x6011803, - XBUS_LL0_IOEL_FIR_ACTION0_REG = 0x6011806, - XBUS_LL0_IOEL_FIR_ACTION1_REG = 0x6011807, - PB_ELL_CFG_REG = 0x601180A, // ELL Configuration Register - PB_ELL_REPLAY_TRESHOLD_REG = 0x6011818, // ELL Replay Threshold Register - PB_ELL_SL_ECC_TRESHOLD_REG = 0x6011819, // ELL SL ECC Threshold Register - XBUS_FIR_ACTION0_REG = 0x06010C06, - XBUS_FIR_ACTION1_REG = 0x06010C07, -} scom_reg_t; +#define PB_WEST_MODE_CFG_REG (0x501180A) // Power Bus PB West Mode Configuration Register +#define PB_CENT_MODE_CFG_REG (0x5011C0A) // Power Bus PB CENT Mode Register +#define PB_CENT_GP_COMMAND_RATE_DP0_REG (0x5011C26) // Power Bus PB CENT GP command RATE DP0 Register +#define PB_CENT_GP_COMMAND_RATE_DP1_REG (0x5011C27) // Power Bus PB CENT GP command RATE DP1 Register +#define PB_CENT_RGP_COMMAND_RATE_DP0_REG (0x5011C28) // Power Bus PB CENT RGP command RATE DP0 Register +#define PB_CENT_RGP_COMMAND_RATE_DP1_REG (0x5011C29) // Power Bus PB CENT RGP command RATE DP1 Register +#define PB_CENT_SP_COMMAND_RATE_DP0_REG (0x5011C2A) // Power Bus PB CENT SP command RATE DP0 Register +#define PB_CENT_SP_COMMAND_RATE_DP1_REG (0x5011C2B) // Power Bus PB CENT SP command RATE DP1 Register +#define PB_EAST_MODE_CFG_REG (0x501200A) // Power Bus PB East Mode Configuration Register +#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) +#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) +#define PB_ELE_PB_FRAMER_PARSER_01_CFG_REG (0x501340A) // Power bus Electrical Framer/Parser 01 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_23_CFG_REG (0x501340B) // Power Bus Electrical Framer/Parser 23 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_45_CFG_REG (0x501340C) // Power Bus Electrical Framer/Parser 45 Configuration Register +#define PB_ELE_PB_DATA_BUFF_01_CFG_REG (0x5013410) // Power Bus Electrical Link Data Buffer 01 Configuration Register +#define PB_ELE_PB_DATA_BUFF_23_CFG_REG (0x5013411) // Power Bus Electrical Link Data Buffer 23 Configuration Register +#define PB_ELE_PB_DATA_BUFF_45_CFG_REG (0x5013412) // Power Bus Electrical Link Data Buffer 45 Configuration Register +#define PB_ELE_MISC_CFG_REG (0x5013423) // Power Bus Electrical Miscellaneous Configuration Register +#define PB_ELE_LINK_TRACE_CFG_REG (0x5013424) // Power Bus Electrical Link Trace Configuration Register +#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) +#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) +#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) +#define PB_ELL_CFG_REG (0x601180A) // Power Bus ELL Configuration Register +#define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) // Power Bus ELL Replay Threshold Register +#define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) // Power Bus ELL SL ECC Threshold Register +#define XBUS_FIR_ACTION0_REG (0x6010C06) +#define XBUS_FIR_ACTION1_REG (0x6010C07) diff --git a/src/mainboard/raptor-cs/talos-2/Makefile.inc b/src/mainboard/raptor-cs/talos-2/Makefile.inc index 3e69e6226a4..1c90c15f486 100644 --- a/src/mainboard/raptor-cs/talos-2/Makefile.inc +++ b/src/mainboard/raptor-cs/talos-2/Makefile.inc @@ -3,3 +3,6 @@ bootblock-y += bootblock.c romstage-y += cbmem.c romstage-y += romstage.c +romstage-y += istep89.c +romstage-y += istep810.c +romstage-y += ../../../cpu/power/power9/scom.c diff --git a/src/mainboard/raptor-cs/talos-2/istep810.c b/src/mainboard/raptor-cs/talos-2/istep810.c index edd9dd5fefa..f24c5f547de 100644 --- a/src/mainboard/raptor-cs/talos-2/istep810.c +++ b/src/mainboard/raptor-cs/talos-2/istep810.c @@ -1,10 +1,9 @@ -#include +#include +#include +#include +#include #include - -#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) -#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) -#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) -#define XBUS_FIR_MASK_REG (0x06010C0) +#include // void *call_proc_xbus_scominit(void *io_pArgs) // { @@ -26,7 +25,7 @@ // } // } -// fapi2::ReturnCode p9_io_xbus_scominit( +// void p9_io_xbus_scominit( // const fapi2::Target &i_target, // const fapi2::Target &i_connected_target, // const uint8_t group) @@ -92,57 +91,6 @@ // EDIP_TX_MSBSWAP[i_tgt, i_grp, lane0] = field_data; // } -// fapi2::ReturnCode set_rx_master_mode( -// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_target, -// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_ctarget ) -// { -// uint8_t l_primary_group_id = 0; -// uint8_t l_primary_chip_id = 0; -// uint32_t l_primary_id = 0; -// uint8_t l_primary_attr = 0; -// uint8_t l_connected_group_id = 0; -// uint8_t l_connected_chip_id = 0; -// uint32_t l_connected_id = 0; -// uint8_t l_connected_attr = 0; - -// p9_get_proc_fabric_group_id(i_target, l_primary_group_id); -// p9_get_proc_fabric_group_id(i_ctarget, l_connected_group_id); - -// p9_get_proc_fabric_chip_id(i_target, l_primary_chip_id); -// p9_get_proc_fabric_chip_id(i_ctarget, l_connected_chip_id); - -// l_primary_id = ((uint32_t)l_primary_group_id << 8) + (uint32_t)l_primary_chip_id; -// l_connected_id = ((uint32_t)l_connected_group_id << 8) + (uint32_t)l_connected_chip_id; - -// if(l_primary_id < l_connected_id) { -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; -// } -// else { -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; -// } -// } - -// fapi2::ReturnCode p9_get_proc_fabric_group_id( -// const fapi2::Target& i_target, uint8_t& o_group_id) -// { -// fapi2::Target l_proc = i_target.getParent(); -// // Retrieve node attribute -// o_group_id = fapi2::ATTR_PROC_FABRIC_GROUP_ID[l_proc]; -// } - -// fapi2::ReturnCode p9_get_proc_fabric_chip_id( -// const fapi2::Target& i_target, uint8_t& o_chip_id) -// { -// fapi2::Target l_proc = i_target.getParent(); -// // Retrieve pos ID attribute -// o_chip_id = fapi2::ATTR_PROC_FABRIC_CHIP_ID[l_proc]; -// } - -// default value -#define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) - void p9_xbus_g0_scom( /*const fapi2::Target &*/ uint64_t TGT0, /*const fapi2::Target &*/ uint64_t TGT1, @@ -1537,23 +1485,24 @@ void p9_xbus_g0_scom( // P9A_XBUS_0_RX0_RX_GLBSM_CNTL3_EO_PG l_scom_buffer = read_scom(0x800AE80006010C3F); - l_scom_buffer.insert<56, 2, 62, uint64_t>(0x02); + l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; + l_scom_buffer |= 0x0000000000000020; write_scom(0x800AE80006010C3F, l_scom_buffer); // P9A_XBUS_0_RX0_RX_GLBSM_MODE1_EO_PG l_scom_buffer = read_scom(0x800AF80006010C3F); - l_scom_buffer.insert<48, 4, 60, uint64_t>(0x0C); - l_scom_buffer.insert<52, 4, 60, uint64_t>(0x0C); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + l_scom_buffer |= 0x000000000000CC00; write_scom(0x800AF80006010C3F, l_scom_buffer); // P9A_XBUS_0_RX0_RX_DATASM_SPARE_MODE_PG l_scom_buffer = read_scom(0x800B800006010C3F); - l_scom_buffer.insert<60, 1, 63, uint64_t>(0x0); // l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFFF7; // l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF write_scom(0x800B800006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_SPARE_MODE_PG l_scom_buffer = read_scom(0x800C040006010C3F); - l_scom_buffer.insert<56, 2, 62, uint64_t>(0); + l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; write_scom(0x800C040006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_ID1_PG @@ -1563,19 +1512,21 @@ void p9_xbus_g0_scom( // P9A_XBUS_0_TX0_TX_CTL_MODE1_EO_PG l_scom_buffer = read_scom(0x800C140006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF - l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON - l_scom_buffer.insert<53, 5, 59, uint64_t>(0b00001); + // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON + l_scom_buffer &= 0xFFFFFFFFFFFF783F; + l_scom_buffer |= 0x0000000000000050; write_scom(0x800C140006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_CTL_MODE2_EO_PG l_scom_buffer = read_scom(0x800C1C0006010C3F); - l_scom_buffer.insert<56, 7, 57, uint64_t>(0x11); + l_scom_buffer &= 0xFFFFFFFFFFFFFF01; + l_scom_buffer |= 0x0000000000000022; write_scom(0x800C1C0006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_CTL_CNTLG1_EO_PG l_scom_buffer = read_scom(0x800C240006010C3F); - l_scom_buffer.insert<48, 2, 62, uint64_t>(0x0); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S + l_scom_buffer &= 0xFFFFFFFFFFFF3FFF; // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S write_scom(0x800C240006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_ID2_PG @@ -1586,8 +1537,10 @@ void p9_xbus_g0_scom( // P9A_XBUS_0_TX0_TX_CTL_MODE1_E_PG l_scom_buffer = read_scom(0x800C8C0006010C3F); - l_scom_buffer.insert<55, 3, 61, uint64_t>(0x5); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 - l_scom_buffer.insert<58, 2, 62, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + l_scom_buffer &= 0xfffffffffffffe0f; + l_scom_buffer |= 0x0000000000000150; write_scom(0x800C8C0006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_CTL_MODE2_E_PG @@ -1597,30 +1550,28 @@ void p9_xbus_g0_scom( // P9A_XBUS_0_TX0_TX_CTL_MODE3_E_PG l_scom_buffer = read_scom(0x800CF40006010C3F); - l_scom_buffer.insert<48, 8, 56, uint64_t>(0x71111); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + l_scom_buffer |= 0x0000000000007F00; write_scom(0x800CF40006010C3F, l_scom_buffer); // P9A_XBUS_0_TX0_TX_CTLSM_MODE1_EO_PG l_scom_buffer = read_scom(0x800D2C0006010C3F); - l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX0_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON + l_scom_buffer |= 0x0000000000000010; // l_IOF1_TX_WRAP_TX0_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON write_scom(0x800D2C0006010C3F, l_scom_buffer); // P9A_XBUS_0_TX_IMPCAL_P_4X_PB l_scom_buffer = read_scom(0x800F1C0006010C3F); - l_scom_buffer.insert<48, 5, 59, uint64_t>(0x70); + l_scom_buffer &= 0xFFFFFFFFFFFF07FF; + l_scom_buffer |= 0x0000000000007000; write_scom(0x800F1C0006010C3F, l_scom_buffer); } -fapi2::ReturnCode p9_xbus_g1_scom( - const fapi2::Target &TGT0, - const fapi2::Target &TGT1, - const fapi2::Target &TGT2) +void p9_xbus_g1_scom( + /* const fapi2::Target*/ uint64_t TGT0, + /* const fapi2::Target*/ uint64_t TGT1, + /* const fapi2::Target*/ uint64_t TGT2) { - l_chip_id = fapi2::ATTR_NAME[TGT2]; - l_chip_ec = fapi2::ATTR_EC[TGT2]; - l_TGT1_ATTR_IS_SIMULATION = fapi2::ATTR_IS_SIMULATION[TGT1]; - l_TGT0_ATTR_IO_XBUS_MASTER_MODE = fapi2::ATTR_IO_XBUS_MASTER_MODE[TGT0]; - fapi2::buffer l_scom_buffer; + uint64_t l_scom_buffer; // P9A_XBUS_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL l_scom_buffer = read_scom(0x8000002006010C3F); @@ -1862,7 +1813,7 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL l_scom_buffer = read_scom(0x8000083106010C3F); - l_scom_buffer.insert<54, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON + l_scom_buffer |= 0x0000000000000200; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON write_scom(0x8000083106010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL @@ -2364,8 +2315,8 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8002C82006010C3F); // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF - l_scom_buffer |= 0x0000000000004200 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004200; write_scom(0x8002C82006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL @@ -2378,7 +2329,7 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8002C82206010C3F); // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; write_scom(0x8002C82206010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL @@ -2419,8 +2370,8 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8002C82806010C3F); // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF - l_scom_buffer |= 0x0000000000004200 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004200; write_scom(0x8002C82806010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL @@ -2461,7 +2412,7 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8002C82E06010C3F); // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; write_scom(0x8002C82E06010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL @@ -2474,8 +2425,8 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8002C83006010C3F); // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF - l_scom_buffer |= 0x0000000000004200 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000004200; write_scom(0x8002C83006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE1_PL @@ -2771,7 +2722,9 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8004442206010C3F); - l_scom_buffer.insert<48, 7, 57, uint64_t>(0x7b); // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF0100; + l_scom_buffer |= 0x000000000000F600; write_scom(0x8004442206010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL @@ -2790,7 +2743,9 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8004442506010C3F); - l_scom_buffer.insert<48, 7, 57, uint64_t>(0x10); // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000002000; write_scom(0x8004442506010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL @@ -2816,7 +2771,9 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8004442906010C3F); - l_scom_buffer.insert<48, 7, 57, uint64_t>(0x4e); // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x0000000000009C00; write_scom(0x8004442906010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL @@ -2835,7 +2792,9 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL l_scom_buffer = read_scom(0x8004442C06010C3F); - l_scom_buffer.insert<48, 7, 57, uint64_t>(0x5e); // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 + l_scom_buffer &= 0xFFFFFFFFFFFF01FF; + l_scom_buffer |= 0x000000000000bc00; write_scom(0x8004442C06010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL @@ -2874,7 +2833,8 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RX_ID1_PG l_scom_buffer = read_scom(0x8008082006010C3F); - l_scom_buffer.insert<48, 6, 58, uint64_t>(1); + l_scom_buffer &= 0xffffffffffff03ff; + l_scom_buffer |= 0x0000000000000400; write_scom(0x8008082006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE1_EO_PG @@ -2898,16 +2858,18 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG l_scom_buffer = read_scom(0x8008C00006010C3F); - l_scom_buffer.insert<48, 2, 62, uint64_t>(0b01); + l_scom_buffer &= 0xFFFFFFFFFFFF3FFF; + l_scom_buffer |= 0x0000000000004000; write_scom(0x8008C00006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG l_scom_buffer = read_scom(0x8008C02006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFEFF; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF - l_scom_buffer.insert<57, 2, 62, uint64_t>(0x3); - l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON - l_scom_buffer.insert<60, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON - l_scom_buffer.insert<56, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON + l_scom_buffer &= 0xFFFFFFFFFFFFFEFF; + l_scom_buffer |= 0x00000000000000F8; write_scom(0x8008C02006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG @@ -2932,13 +2894,15 @@ fapi2::ReturnCode p9_xbus_g1_scom( if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) { l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER } - l_scom_buffer.insert<58, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON - l_scom_buffer.insert<57, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED + l_scom_buffer |= 0x0000000000000060; write_scom(0x8009902006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG l_scom_buffer = read_scom(0x8009982006010C3F); - l_scom_buffer.insert<48, 5, 59, uint64_t>(0x01); + l_scom_buffer &= 0xFFFFFFFFFFFF07FF; + l_scom_buffer |= 0x0000000000000800; write_scom(0x8009982006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG @@ -2955,21 +2919,22 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG l_scom_buffer = read_scom(0x8009B82006010C3F); - l_scom_buffer &= 0xffffffffffff0003; + l_scom_buffer &= 0xFFFFFFFFFFFF0003; l_scom_buffer |= 0x0000000000002244; write_scom(0x8009B82006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG l_scom_buffer = read_scom(0x8009C82006010C3F); - l_scom_buffer.insert<48, 7, 57, uint64_t>(0x1111); - l_scom_buffer.insert<55, 4, 60, uint64_t>(0x5); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 - l_scom_buffer.insert<61, 3, 61, uint64_t>(0x05); + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 + l_scom_buffer &= 0xFFFFFFFFFFFF0018; + l_scom_buffer |= 0x0000000000001EA5; write_scom(0x8009C82006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG l_scom_buffer = read_scom(0x8009D02006010C3F); - l_scom_buffer.insert<48, 7, 57, uint64_t>(0x7111); - l_scom_buffer.insert<55, 4, 60, uint64_t>(0x5); // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 + // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 + l_scom_buffer &= 0x7fffffffffff800; + l_scom_buffer |= 0x0000000000003f5; write_scom(0x8009D02006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_CTL_MODE11_E_PG @@ -2979,56 +2944,63 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG l_scom_buffer = read_scom(0x8009E82006010C3F); - l_scom_buffer.insert<48, 8, 56, uint64_t>(0x71111); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + l_scom_buffer |= 0x0000000000007F00; write_scom(0x8009E82006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG l_scom_buffer = read_scom(0x800A802006010C3F); - l_scom_buffer.insert<56, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER - l_scom_buffer.insert<50, 1, 63, uint64_t>(0x1); // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON + // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON + l_scom_buffer |= 0x0000000000002080; write_scom(0x800A802006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG l_scom_buffer = read_scom(0x800AE82006010C3F); - l_scom_buffer.insert<56, 2, 62, uint64_t>(0x02); + l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; + l_scom_buffer |= 0x0000000000000080; write_scom(0x800AE82006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG l_scom_buffer = read_scom(0x800AF82006010C3F); - l_scom_buffer.insert<48, 4, 60, uint64_t>(0x0C); - l_scom_buffer.insert<52, 4, 60, uint64_t>(0x0C); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + l_scom_buffer |= 0x000000000000CC00; write_scom(0x800AF82006010C3F, l_scom_buffer); // P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG l_scom_buffer = read_scom(0x800B802006010C3F); - l_scom_buffer.insert<60, 1, 63, uint64_t>(0x0); // l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + // l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF + l_scom_buffer &= 0xFFFFFFFFFFFFFFF7; write_scom(0x800B802006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_SPARE_MODE_PG l_scom_buffer = read_scom(0x800C042006010C3F); - l_scom_buffer.insert<56, 2, 62, uint64_t>(0); + l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; write_scom(0x800C042006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_ID1_PG l_scom_buffer = read_scom(0x800C0C2006010C3F); - l_scom_buffer.insert<48, 6, 58, uint64_t>(1); + l_scom_buffer &= 0xFFFFFFFFFFFF03FF; + l_scom_buffer |= 0x0000000000000400; write_scom(0x800C0C2006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG l_scom_buffer = read_scom(0x800C142006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF - l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON - l_scom_buffer.insert<53, 5, 59, uint64_t>(0b00001); + // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON + l_scom_buffer &= 0xFFFFFFFFFFFF783F; + l_scom_buffer |= 0x0000000000000050; write_scom(0x800C142006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG l_scom_buffer = read_scom(0x800C1C2006010C3F); - l_scom_buffer.insert<56, 7, 57, uint64_t>(0x11); + l_scom_buffer &= 0xFFFFFFFFFFFFFF01; + l_scom_buffer |= 0x0000000000000F22; write_scom(0x800C1C2006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG l_scom_buffer = read_scom(0x800C242006010C3F); - l_scom_buffer.insert<48, 2, 62, uint64_t>(0x0); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S + l_scom_buffer &= 0xFFFFFFFFFFFF3FFF; // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S write_scom(0x800C242006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_ID2_PG @@ -3039,8 +3011,10 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG l_scom_buffer = read_scom(0x800C8C2006010C3F); - l_scom_buffer.insert<55, 3, 61, uint64_t>(0x5); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 - l_scom_buffer.insert<58, 2, 62, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 + l_scom_buffer &= 0xfffffffffffffe0f; + l_scom_buffer |= 0x0000000000000150; write_scom(0x800C8C2006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG @@ -3050,16 +3024,73 @@ fapi2::ReturnCode p9_xbus_g1_scom( // P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG l_scom_buffer = read_scom(0x800CF42006010C3F); - l_scom_buffer.insert<48, 8, 56, uint64_t>(0x71111); + l_scom_buffer &= 0xFFFFFFFFFFFF00FF; + l_scom_buffer |= 0x0000000000007F00; write_scom(0x800CF42006010C3F, l_scom_buffer); // P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG l_scom_buffer = read_scom(0x800D2C2006010C3F); - l_scom_buffer.insert<59, 1, 63, uint64_t>(0x1); // l_IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON + l_scom_buffer |= 0x0000000000000010; // l_IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON write_scom(0x800D2C2006010C3F, l_scom_buffer); // P9A_XBUS_0_TX_IMPCAL_P_4X_PB l_scom_buffer = read_scom(0x800F1C0006010C3F); - l_scom_buffer.insert<48, 5, 59, uint64_t>(0x70); + l_scom_buffer &= 0xFFFFFFFFFFFF07FF; + l_scom_buffer |= 0x0000000000007000; write_scom(0x800F1C0006010C3F, l_scom_buffer); } + +void istep810(void) +{ + printk(BIOS_EMERG, "starting istep 8.10\n"); + printk(BIOS_EMERG, "ending istep 8.10\n"); + return; +} + +// fapi2::ReturnCode set_rx_master_mode( +// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_target, +// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_ctarget ) +// { +// uint8_t l_primary_group_id = 0; +// uint8_t l_primary_chip_id = 0; +// uint32_t l_primary_id = 0; +// uint8_t l_primary_attr = 0; +// uint8_t l_connected_group_id = 0; +// uint8_t l_connected_chip_id = 0; +// uint32_t l_connected_id = 0; +// uint8_t l_connected_attr = 0; + +// p9_get_proc_fabric_group_id(i_target, l_primary_group_id); +// p9_get_proc_fabric_group_id(i_ctarget, l_connected_group_id); + +// p9_get_proc_fabric_chip_id(i_target, l_primary_chip_id); +// p9_get_proc_fabric_chip_id(i_ctarget, l_connected_chip_id); + +// l_primary_id = ((uint32_t)l_primary_group_id << 8) + (uint32_t)l_primary_chip_id; +// l_connected_id = ((uint32_t)l_connected_group_id << 8) + (uint32_t)l_connected_chip_id; + +// if(l_primary_id < l_connected_id) { +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; +// } +// else { +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; +// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; +// } +// } + +// fapi2::ReturnCode p9_get_proc_fabric_group_id( +// const fapi2::Target& i_target, uint8_t& o_group_id) +// { +// fapi2::Target l_proc = i_target.getParent(); +// // Retrieve node attribute +// o_group_id = fapi2::ATTR_PROC_FABRIC_GROUP_ID[l_proc]; +// } + +// fapi2::ReturnCode p9_get_proc_fabric_chip_id( +// const fapi2::Target& i_target, uint8_t& o_chip_id) +// { +// fapi2::Target l_proc = i_target.getParent(); +// // Retrieve pos ID attribute +// o_chip_id = fapi2::ATTR_PROC_FABRIC_CHIP_ID[l_proc]; +// } diff --git a/src/mainboard/raptor-cs/talos-2/istep89.c b/src/mainboard/raptor-cs/talos-2/istep89.c new file mode 100644 index 00000000000..7b0e3396215 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/istep89.c @@ -0,0 +1,345 @@ +#include +#include +#include +#include + +void istep89(void) +{ + printk(BIOS_EMERG, "starting istep 8.9\n"); + p9_fbc_no_hp_scom(); + p9_fbc_ioe_tl_scom(); + + p9_fbc_ioe_dl_scom(XB_CHIPLET_ID); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); + printk(BIOS_EMERG, "ending istep 8.9\n"); +} + +void p9_fbc_ioe_dl_scom(uint64_t TGT0) +{ + uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, PB_ELL_CFG_REG); + uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG); + uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG); + if (ATTR_LINK_TRAIN == BOTH) + { + pb_ioe_ll0_ioel_config |= 0x8000000000000000; + } + else + { + pb_ioe_ll0_ioel_config &= 0x7FFFFFFFFFFFFFFF; + } + pb_ioe_ll0_ioel_config &= 0xFFEFFFFFFFFFFFFF; + pb_ioe_ll0_ioel_config |= 0x280F000F00000000; + pb_ioe_ll0_ioel_replay_threshold &= 0x0FFFFFFFFFFFFFFF; + pb_ioe_ll0_ioel_replay_threshold |= 0x6FE0000000000000; + pb_ioe_ll0_ioel_sl_ecc_threshold &= 0x7FFFFFFFFFFFFFFF; + pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F70000000000000; + + write_scom_for_chiplet(TGT0, PB_ELL_CFG_REG, pb_ioe_ll0_ioel_config); + write_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG, pb_ioe_ll0_ioel_replay_threshold); + write_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG, pb_ioe_ll0_ioel_sl_ecc_threshold); +} + +void tl_fir(void) +{ + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); + uint64_t l_fir_mask = FBC_IOE_TL_FIR_MASK; + + l_fir_mask |= FBC_IOE_TL_FIR_MASK_X0_NF; + // bool l_x_functional[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = + // { + // false, + // false, + // false + // }; + // uint64_t l_x_non_functional_mask[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = + // { + // FBC_IOE_TL_FIR_MASK_X0_NF, + // FBC_IOE_TL_FIR_MASK_X1_NF, + // FBC_IOE_TL_FIR_MASK_X2_NF + // }; + // uint8_t l_unit_pos; + // l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[XB_CHIPLET_ID]; + // l_x_functional[l_unit_pos] = true; + // for(unsigned int ll = 0; ll < P9_FBC_UTILS_MAX_ELECTRICAL_LINKS; ++ll) + // { + // if (!l_x_functional[ll]) + // { + // l_fir_mask |= l_x_non_functional_mask[ll]; + // } + // } + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_MASK_REG, l_fir_mask); +} + +void p9_fbc_no_hp_scom(void) +{ + uint64_t is_flat_8 = false; + + // REGISTERS read + uint64_t pb_com_pb_west_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG); + uint64_t pb_com_pb_cent_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG); + uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG); + uint64_t pb_com_pb_cent_gp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1_REG); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0_REG); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1_REG); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0_REG); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1_REG); + uint64_t pb_com_pb_east_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG_REG); + + if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP + || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) + { + pb_com_pb_cent_gp_cmd_rate_dp0 = 0; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP + && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) + { + pb_com_pb_cent_gp_cmd_rate_dp0 = 0x030406171C243448; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0x040508191F283A50; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) + { + pb_com_pb_cent_gp_cmd_rate_dp0 = 0x0304062832405C80; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0x0405082F3B4C6D98; + } + + if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406080A0C1218; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508080A0C1218; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x030406080A0C1218; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x030406080A0C1218; + } + else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 3) + || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304060D10141D28; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405080D10141D28; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x05070A0D10141D28; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x05070A0D10141D28; + } + else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && is_flat_8) + || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3)) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406171C243448; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508191F283A50; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x080C12171C243448; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A0D14191F283A50; + } + else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) + { + pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304062832405C80; + pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405082F3B4C6D98; + pb_com_pb_cent_sp_cmd_rate_dp0 = 0x08141F2832405C80; + pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A18252F3B4C6D98; + } + + if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0 && ATTR_PROC_FABRIC_A_LINKS_CNFG == 0) + { + pb_com_pb_east_mode |= 0x0300000000000000; + } + else + { + pb_com_pb_east_mode &= 0xF1FFFFFFFFFFFFFF; + } + if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && is_flat_8) + { + pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_west_mode |= 0x00003E8000000000; + pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_cent_mode |= 0x00003E8000000000; + pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_east_mode |= 0x00003E8000000000; + } + else + { + pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_west_mode |= 0x0000FAFC00000000; + pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_cent_mode |= 0x00007EFC00000000; + pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_east_mode |= 0x000007EFC0000000; + } + + pb_com_pb_west_mode &= 0xFFFFFFFC0FFFFFFF; + pb_com_pb_west_mode |= 0x00000002a0000000; + pb_com_pb_cent_mode &= 0xFFFFFFFC0FFFFFFF; + pb_com_pb_cent_mode |= 0x00000002a0000000; + pb_com_pb_east_mode &= 0xFFFFFFFC0FFFFFFF; + pb_com_pb_east_mode |= 0x00000002a0000000; + + // REGISTERS write + write_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG, pb_com_pb_west_mode); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG, pb_com_pb_cent_mode); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_gp_cmd_rate_dp0); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1_REG, pb_com_pb_cent_gp_cmd_rate_dp1); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_rgp_cmd_rate_dp0); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1_REG, pb_com_pb_cent_rgp_cmd_rate_dp1); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_sp_cmd_rate_dp0); + write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1_REG, pb_com_pb_cent_sp_cmd_rate_dp1); + write_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG_REG, pb_com_pb_east_mode); +} + +void p9_fbc_ioe_tl_scom(void) +{ + uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG_REG); + uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG_REG); + uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG_REG); + uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG_REG); + uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG_REG); + uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG_REG); + uint64_t pb_ioe_scom_pb_misc_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG_REG); + uint64_t pb_ioe_scom_pb_trace_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG_REG); + + if(X0_ENABLED) + { + pb_ioe_scom_pb_fp01_cfg &= 0xfff004fffff007bf; + pb_ioe_scom_pb_fp01_cfg |= 0x0002010000020000; + } + else + { + pb_ioe_scom_pb_fp01_cfg |= 0x84000000840; + } + + if(X0_ENABLED && DD2X_PARTS) + { + pb_ioe_scom_pb_fp01_cfg &= 0xF00FFFFFF00FFFFF; + pb_ioe_scom_pb_fp01_cfg |= 0x00C0000000C00000; + } + + if(X2_ENABLED) + { + pb_ioe_scom_pb_fp45_cfg &= 0xfff004bffff007bf; + pb_ioe_scom_pb_fp45_cfg |= 0x0002010000020000; + } + else + { + pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; + } + + if (X2_ENABLED && DD2X_PARTS) + { + pb_ioe_scom_pb_fp45_cfg &= 0xF00FFFFFF00FFFFF; + pb_ioe_scom_pb_fp45_cfg |= 0x00C0000000C00000; + } + + if (X0_ENABLED && OPTICS_IS_A_BUS) + { + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFFFFFF07FFFFFFFF; + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001000000000; + } + else if(X0_ENABLED) + { + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001F00000000; + } + + if (X0_ENABLED) + { + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF; + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x4000000040000000; + + pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFF8080FFFF8080FF; + pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x003C3C00003C3C00; + + pb_ioe_scom_pb_trace_cfg &= 0x0000FFFFFFFFFFFF; + pb_ioe_scom_pb_trace_cfg |= 0x4141000000000000; + } + else if (X1_ENABLED) + { + pb_ioe_scom_pb_trace_cfg &= 0xFFFF0000FFFFFFFF; + pb_ioe_scom_pb_trace_cfg |= 0x0000414100000000; + } + else if (X2_ENABLED) + { + pb_ioe_scom_pb_trace_cfg &= 0xFFFFFFFF0000FFFF; + pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000; + } + + if (X1_ENABLED && DD2X_PARTS) + { + pb_ioe_scom_pb_fp23_cfg &= 0xF00FFFFFF00FFFFF; + pb_ioe_scom_pb_fp23_cfg |= 0x00C0000000C00000; + } + + if(X1_ENABLED) + { + pb_ioe_scom_pb_fp23_cfg &= 0xfff004bffff007bf; + pb_ioe_scom_pb_fp23_cfg |= 0x0002010000020000; + if (OPTICS_IS_A_BUS) + { + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x0100000000000000; + } + else + { + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x01F0000000000000; + } + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0x808080FF808080FF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x403C3C00403C3C00; + } + else + { + pb_ioe_scom_pb_fp23_cfg |= 0x0000084000000840; + } + + if(X2_ENABLED) + { + if (OPTICS_IS_A_BUS) + { + pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0xFFFFFF07FFFFFFFF; + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x0000008000000000; + } + else + { + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x000000F800000000; + } + pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0x808080FF808080FF; + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x403C3C00403C3C00; + } + + if(X0_IS_PAIRED) + { + pb_ioe_scom_pb_misc_cfg |= 0x8000000000000000; + } + else + { + pb_ioe_scom_pb_misc_cfg &= 0x7FFFFFFFFFFFFFFF; + } + if(X1_IS_PAIRED) + { + pb_ioe_scom_pb_misc_cfg |= 0x4000000000000000; + } + else + { + pb_ioe_scom_pb_misc_cfg &= 0xBFFFFFFFFFFFFFFF; + } + if(X2_IS_PAIRED) + { + pb_ioe_scom_pb_misc_cfg |= 0x2000000000000000; + } + else + { + pb_ioe_scom_pb_misc_cfg &= 0xDFFFFFFFFFFFFFFF; + } + + // REGISTERS write + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG_REG, pb_ioe_scom_pb_trace_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG_REG, pb_ioe_scom_pb_misc_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG_REG, pb_ioe_scom_pb_elink_data_01_cfg_reg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG_REG, pb_ioe_scom_pb_elink_data_23_cfg_reg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG_REG, pb_ioe_scom_pb_elink_data_45_cfg_reg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG_REG, pb_ioe_scom_pb_fp01_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG_REG, pb_ioe_scom_pb_fp23_cfg); + write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG_REG, pb_ioe_scom_pb_fp45_cfg); +} diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 1ff78c45ed2..70a95051dd0 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -1,439 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include -#include - -#define X0_ENABLED (true) -#define X1_ENABLED (true) -#define X2_ENABLED (true) -#define X0_IS_PAIRED (true) -#define X1_IS_PAIRED (true) -#define X2_IS_PAIRED (true) -#define DD2X_PARTS (true) -#define OPTICS_IS_A_BUS (true) -#define ATTR_PROC_FABRIC_A_LINKS_CNFG (0) -#define ATTR_PROC_FABRIC_X_LINKS_CNFG (0) - -#define EPS_TYPE_LE (0x01), -#define EPS_TYPE_HE (0x02), -#define EPS_TYPE_HE_F8 (0x03) -#define ATTR_PROC_EPS_TABLE_TYPE (EPS_TYPE_LE) // default value - -#define CHIP_IS_NODE (0x01) -#define CHIP_IS_GROUP (0x02) -#define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) // default value - -#define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) -#define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) - -#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) -#define P9_FBC_UTILS_MAX_ELECTRICAL_LINKS (3) -#define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) -#define FBC_IOE_TL_FIR_MASK_X1_NF (0x0018030300000440ULL) -#define FBC_IOE_TL_FIR_MASK_X2_NF (0x000300C0C0000220ULL) -#define PU_PB_IOE_FIR_MASK_REG (0x5013403) - -#define FBC_IOE_DL_FIR_ACTION0 (0) -#define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) -#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) - -#define BOTH (0x0) -#define EVEN_ONLY (0x1) -#define ODD_ONLY (0x2) -#define NONE (0x3) -#define ATTR_LINK_TRAIN BOTH - -// this is probably wrong -#define PROC_CHIPLET (0x10) - -void p9_fbc_ioe_tl_scom(void); -void istep89(void); -void p9_fbc_no_hp_scom(void); -void tl_fir(void); -void p9_fbc_ioe_dl_scom(uint64_t TGT0); - -void istep89(void) -{ - printk(BIOS_EMERG, "starting istep 8.9\n"); - p9_fbc_no_hp_scom(); - p9_fbc_ioe_tl_scom(); - - p9_fbc_ioe_dl_scom(XB_CHIPLET_ID); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); - printk(BIOS_EMERG, "ending istep 8.9\n"); -} - -void p9_fbc_ioe_dl_scom(uint64_t TGT0) -{ - uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, PB_ELL_CFG_REG); - uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG); - uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG); - if (ATTR_LINK_TRAIN == BOTH) - { - pb_ioe_ll0_ioel_config |= 0x8000000000000000; - } - else - { - pb_ioe_ll0_ioel_config &= 0x7FFFFFFFFFFFFFFF; - } - pb_ioe_ll0_ioel_config &= 0xFFEFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_config |= 0x280F000F00000000; - pb_ioe_ll0_ioel_replay_threshold &= 0x0FFFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_replay_threshold |= 0x6FE0000000000000; - pb_ioe_ll0_ioel_sl_ecc_threshold &= 0x7FFFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F70000000000000; - - write_scom_for_chiplet(TGT0, PB_ELL_CFG_REG, pb_ioe_ll0_ioel_config); - write_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG, pb_ioe_ll0_ioel_replay_threshold); - write_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG, pb_ioe_ll0_ioel_sl_ecc_threshold); -} - -void tl_fir(void) -{ - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); - uint64_t l_fir_mask = FBC_IOE_TL_FIR_MASK; - - l_fir_mask |= FBC_IOE_TL_FIR_MASK_X0_NF; - // bool l_x_functional[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = - // { - // false, - // false, - // false - // }; - // uint64_t l_x_non_functional_mask[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = - // { - // FBC_IOE_TL_FIR_MASK_X0_NF, - // FBC_IOE_TL_FIR_MASK_X1_NF, - // FBC_IOE_TL_FIR_MASK_X2_NF - // }; - // uint8_t l_unit_pos; - // l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[XB_CHIPLET_ID]; - // l_x_functional[l_unit_pos] = true; - // for(unsigned int ll = 0; ll < P9_FBC_UTILS_MAX_ELECTRICAL_LINKS; ++ll) - // { - // if (!l_x_functional[ll]) - // { - // l_fir_mask |= l_x_non_functional_mask[ll]; - // } - // } - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_MASK_REG, l_fir_mask); -} - -void p9_fbc_no_hp_scom(void) -{ - uint64_t is_flat_8 = false; - - // REGISTERS read - uint64_t pb_com_pb_west_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG); - uint64_t pb_com_pb_cent_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG); - uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0); - uint64_t pb_com_pb_cent_gp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1); - uint64_t pb_com_pb_east_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG); - - if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP - || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) - { - pb_com_pb_cent_gp_cmd_rate_dp0 = 0; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP - && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) - { - pb_com_pb_cent_gp_cmd_rate_dp0 = 0x030406171C243448; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0x040508191F283A50; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) - { - pb_com_pb_cent_gp_cmd_rate_dp0 = 0x0304062832405C80; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0x0405082F3B4C6D98; - } - - if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406080A0C1218; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508080A0C1218; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x030406080A0C1218; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x030406080A0C1218; - } - else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 3) - || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304060D10141D28; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405080D10141D28; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x05070A0D10141D28; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x05070A0D10141D28; - } - else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && is_flat_8) - || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3)) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406171C243448; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508191F283A50; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x080C12171C243448; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A0D14191F283A50; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304062832405C80; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405082F3B4C6D98; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x08141F2832405C80; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A18252F3B4C6D98; - } - - if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0 && ATTR_PROC_FABRIC_A_LINKS_CNFG == 0) - { - pb_com_pb_east_mode |= 0x0300000000000000; - } - else - { - pb_com_pb_east_mode &= 0xF1FFFFFFFFFFFFFF; - } - if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && is_flat_8) - { - pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_west_mode |= 0x00003E8000000000; - pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_cent_mode |= 0x00003E8000000000; - pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_east_mode |= 0x00003E8000000000; - } - else - { - pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_west_mode |= 0x0000FAFC00000000; - pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_cent_mode |= 0x00007EFC00000000; - pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_east_mode |= 0x000007EFC0000000; - } - - pb_com_pb_west_mode &= 0xFFFFFFFC0FFFFFFF; - pb_com_pb_west_mode |= 0x00000002a0000000; - pb_com_pb_cent_mode &= 0xFFFFFFFC0FFFFFFF; - pb_com_pb_cent_mode |= 0x00000002a0000000; - pb_com_pb_east_mode &= 0xFFFFFFFC0FFFFFFF; - pb_com_pb_east_mode |= 0x00000002a0000000; - - // REGISTERS write - write_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG, pb_com_pb_west_mode); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG, pb_com_pb_cent_mode); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0, pb_com_pb_cent_gp_cmd_rate_dp0); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1, pb_com_pb_cent_gp_cmd_rate_dp1); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0, pb_com_pb_cent_rgp_cmd_rate_dp0); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1, pb_com_pb_cent_rgp_cmd_rate_dp1); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0, pb_com_pb_cent_sp_cmd_rate_dp0); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1, pb_com_pb_cent_sp_cmd_rate_dp1); - write_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG, pb_com_pb_east_mode); -} - -void p9_fbc_ioe_tl_scom(void) -{ - uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG); - uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG); - uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG); - uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG); - uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG); - uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG); - uint64_t pb_ioe_scom_pb_misc_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG); - uint64_t pb_ioe_scom_pb_trace_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG); - - if(X0_ENABLED) - { - pb_ioe_scom_pb_fp01_cfg &= 0xfff004fffff007bf; - pb_ioe_scom_pb_fp01_cfg |= 0x0002010000020000; - } - else - { - pb_ioe_scom_pb_fp01_cfg |= 0x84000000840; - } - - // if(X0_ENABLED && DD2X_PARTS) - // { - // PB_IOE_SCOM_PB_FP01_CFG.insert<4, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) - // PB_IOE_SCOM_PB_FP01_CFG.insert<36, 8, 56, uint64_t>(0x15 - (l_def_DD2_LO_LIMIT_N / l_def_DD2_LO_LIMIT_D)) - // } - // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) - // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && DD1_LO_LIMIT_P)) - // { - // PB_IOE_SCOM_PB_FP01_CFG.insert<4, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - // PB_IOE_SCOM_PB_FP01_CFG.insert<36, 8, 56, uint64_t>(0x1A - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - // } - // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && !DD1_LO_LIMIT_P) - // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R > DD1_LO_LIMIT_H)) - // { - // PB_IOE_SCOM_PB_FP01_CFG.insert<4, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - // PB_IOE_SCOM_PB_FP01_CFG.insert<36, 8, 56, uint64_t>(0x19 - (l_def_DD1_LO_LIMIT_N / l_def_DD1_LO_LIMIT_D)) - // } - if(X2_ENABLED) - { - pb_ioe_scom_pb_fp45_cfg &= 0xfff004bffff007bf; - pb_ioe_scom_pb_fp45_cfg |= 0x0002010000020000; - } - else - { - pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; - } - // if (X2_ENABLED && DD2X_PARTS) - // { - // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / )) - // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x15 - (l_def_dd2_lo_limit_n / l_def_dd2_lo_limit_d)) - // } - // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) - // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && DD1_LO_LIMIT_P)) - // { - // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) - // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) - // } - // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && !DD1_LO_LIMIT_P) - // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R > DD1_LO_LIMIT_H)) - // { - // pb_ioe_scom_pb_fp45_cfg.insert<4, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) - // pb_ioe_scom_pb_fp45_cfg.insert<36, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)) - // } - - if (X0_ENABLED && OPTICS_IS_A_BUS) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFFFFFF07FFFFFFFF; - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001000000000; - } - else if(X0_ENABLED) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001F00000000; - } - - if (X0_ENABLED) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF; - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x4000000040000000; - - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFF8080FFFF8080FF; - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x003C3C00003C3C00; - - pb_ioe_scom_pb_trace_cfg &= 0x0000FFFFFFFFFFFF; - pb_ioe_scom_pb_trace_cfg |= 0x4141000000000000; - } - else if (X1_ENABLED) - { - pb_ioe_scom_pb_trace_cfg &= 0xFFFF0000FFFFFFFF; - pb_ioe_scom_pb_trace_cfg |= 0x0000414100000000; - } - else if (X2_ENABLED) - { - pb_ioe_scom_pb_trace_cfg &= 0xFFFFFFFF0000FFFF; - pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000; - } - - // if (X1_ENABLED && DD2X_PARTS) - // { - // PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x15 - (DD2_LO_LIMIT_N / DD2_LO_LIMIT_D)); - // PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x15 - (DD2_LO_LIMIT_N / DD2_LO_LIMIT_D)); - // } - // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R < DD1_LO_LIMIT_H) - // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && DD1_LO_LIMIT_P)) - // { - // PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); - // PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x1A - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); - // } - // else if ((X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R == DD1_LO_LIMIT_H && !DD1_LO_LIMIT_P) - // || (X0_ENABLED && DD1_PARTS && DD1_LO_LIMIT_R > DD1_LO_LIMIT_H)) - // { - // PB_IOE_SCOM_PB_FP23_CFG.insert<4, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); - // PB_IOE_SCOM_PB_FP23_CFG.insert<36, 8, 56, uint64_t>(0x19 - (DD1_LO_LIMIT_N / DD1_LO_LIMIT_D)); - // } - - - if(X1_ENABLED) - { - pb_ioe_scom_pb_fp23_cfg &= 0xfff004bffff007bf; - pb_ioe_scom_pb_fp23_cfg |= 0x0002010000020000; - if (OPTICS_IS_A_BUS) - { - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x0100000000000000; - } - else - { - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x01F0000000000000; - } - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0x808080FF808080FF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x403C3C00403C3C00; - } - else - { - pb_ioe_scom_pb_fp23_cfg |= 0x0000084000000840; - } - - if(X2_ENABLED) - { - if (OPTICS_IS_A_BUS) - { - pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0xFFFFFF07FFFFFFFF; - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x0000008000000000; - } - else - { - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x000000F800000000; - } - pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0x808080FF808080FF; - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x403C3C00403C3C00; - } - - if(X0_IS_PAIRED) - { - pb_ioe_scom_pb_misc_cfg |= 0x8000000000000000; - } - else - { - pb_ioe_scom_pb_misc_cfg &= 0x7FFFFFFFFFFFFFFF; - } - if(X1_IS_PAIRED) - { - pb_ioe_scom_pb_misc_cfg |= 0x4000000000000000; - } - else - { - pb_ioe_scom_pb_misc_cfg &= 0xBFFFFFFFFFFFFFFF; - } - if(X2_IS_PAIRED) - { - pb_ioe_scom_pb_misc_cfg |= 0x2000000000000000; - } - else - { - pb_ioe_scom_pb_misc_cfg &= 0xDFFFFFFFFFFFFFFF; - } - - // REGISTERS write - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG, pb_ioe_scom_pb_fp01_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG, pb_ioe_scom_pb_fp23_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG, pb_ioe_scom_pb_fp45_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG, pb_ioe_scom_pb_elink_data_01_cfg_reg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG, pb_ioe_scom_pb_elink_data_23_cfg_reg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG, pb_ioe_scom_pb_elink_data_45_cfg_reg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG, pb_ioe_scom_pb_misc_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG, pb_ioe_scom_pb_trace_cfg); -} - void main(void) { console_init(); istep89(); + istep810(); run_ramstage(); } diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c index 91074b20125..1d2c71bdca7 100644 --- a/src/soc/ibm/power9/romstage.c +++ b/src/soc/ibm/power9/romstage.c @@ -2,6 +2,8 @@ #include + asmlinkage void car_stage_entry(void) { + printk(BIOS_EMERG, "hello from SoC!\n"); } From f4b873378b8809f10d0815bf144ad09315e328b9 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Thu, 18 Feb 2021 14:28:45 +0100 Subject: [PATCH 69/90] fix indentation --- src/mainboard/raptor-cs/talos-2/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 70a95051dd0..09fb642f5fe 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -6,8 +6,8 @@ void main(void) { - console_init(); - istep89(); + console_init(); + istep89(); istep810(); - run_ramstage(); + run_ramstage(); } From 2b1baa0145ebcaeb3ee9388921950277b3252aee Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 19 Feb 2021 14:49:10 +0100 Subject: [PATCH 70/90] move isteps 8.9, 8.10 to soc subdir --- src/include/cpu/power/isteps.h | 18 ++--- src/mainboard/raptor-cs/talos-2/Makefile.inc | 3 - src/mainboard/raptor-cs/talos-2/romstage.c | 5 +- src/soc/ibm/power9/Makefile.inc | 7 +- src/soc/ibm/power9/bootblock.c | 2 + .../ibm/power9/istep_8_10.c} | 3 +- .../istep89.c => soc/ibm/power9/istep_8_9.c} | 70 +++++++------------ src/soc/ibm/power9/romstage.c | 13 +++- 8 files changed, 58 insertions(+), 63 deletions(-) rename src/{mainboard/raptor-cs/talos-2/istep810.c => soc/ibm/power9/istep_8_10.c} (99%) rename src/{mainboard/raptor-cs/talos-2/istep89.c => soc/ibm/power9/istep_8_9.c} (93%) diff --git a/src/include/cpu/power/isteps.h b/src/include/cpu/power/isteps.h index 9951a4b626e..2b0bfa444a3 100644 --- a/src/include/cpu/power/isteps.h +++ b/src/include/cpu/power/isteps.h @@ -34,10 +34,10 @@ #define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) #define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) -#define BOTH (0x0) -#define EVEN_ONLY (0x1) -#define ODD_ONLY (0x2) -#define NONE (0x3) +#define BOTH (0x0) +#define EVEN_ONLY (0x1) +#define ODD_ONLY (0x2) +#define NONE (0x3) #define ATTR_LINK_TRAIN BOTH #define PROC_CHIPLET (0x10) // this is probably wrong @@ -47,12 +47,12 @@ #define XBUS_FIR_MASK_REG (0x06010C0) #define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) // default value -void istep810(void); -void p9_xbus_g1_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); -void p9_xbus_g0_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); - void p9_fbc_ioe_tl_scom(void); -void istep89(void); +void istep_8_9(void); void p9_fbc_no_hp_scom(void); void tl_fir(void); void p9_fbc_ioe_dl_scom(uint64_t TGT0); + +void istep_8_10(void); +void p9_xbus_g1_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); +void p9_xbus_g0_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); diff --git a/src/mainboard/raptor-cs/talos-2/Makefile.inc b/src/mainboard/raptor-cs/talos-2/Makefile.inc index 1c90c15f486..3e69e6226a4 100644 --- a/src/mainboard/raptor-cs/talos-2/Makefile.inc +++ b/src/mainboard/raptor-cs/talos-2/Makefile.inc @@ -3,6 +3,3 @@ bootblock-y += bootblock.c romstage-y += cbmem.c romstage-y += romstage.c -romstage-y += istep89.c -romstage-y += istep810.c -romstage-y += ../../../cpu/power/power9/scom.c diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 09fb642f5fe..333aed5e245 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -4,10 +4,11 @@ #include #include +void scom_init(void); + void main(void) { console_init(); - istep89(); - istep810(); + scom_init(); run_ramstage(); } diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index 14ee650584f..8bbf9e6f2ee 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -1,12 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CPU_IBM_POWER9),y) +# ifeq ($(CPU_IBM_POWER9),y) bootblock-y += bootblock.c postcar-y += exit_car.S romstage-y += romstage.c +romstage-y += istep_8_9.c +romstage-y += istep_8_10.c +romstage-y += ../../../cpu/power/power9/scom.c ramstage-y += chip.c ramstage-y += timer.c -endif +# endif diff --git a/src/soc/ibm/power9/bootblock.c b/src/soc/ibm/power9/bootblock.c index 54e7e5d3747..bb4a9480a1f 100644 --- a/src/soc/ibm/power9/bootblock.c +++ b/src/soc/ibm/power9/bootblock.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +void bootblock_soc_early_init(void); + void bootblock_soc_early_init(void) { } diff --git a/src/mainboard/raptor-cs/talos-2/istep810.c b/src/soc/ibm/power9/istep_8_10.c similarity index 99% rename from src/mainboard/raptor-cs/talos-2/istep810.c rename to src/soc/ibm/power9/istep_8_10.c index f24c5f547de..49ca50a05fe 100644 --- a/src/mainboard/raptor-cs/talos-2/istep810.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -3040,9 +3040,10 @@ void p9_xbus_g1_scom( write_scom(0x800F1C0006010C3F, l_scom_buffer); } -void istep810(void) +void istep_8_10(void) { printk(BIOS_EMERG, "starting istep 8.10\n"); + read_scom(0x800F1C0006010C3F); printk(BIOS_EMERG, "ending istep 8.10\n"); return; } diff --git a/src/mainboard/raptor-cs/talos-2/istep89.c b/src/soc/ibm/power9/istep_8_9.c similarity index 93% rename from src/mainboard/raptor-cs/talos-2/istep89.c rename to src/soc/ibm/power9/istep_8_9.c index 7b0e3396215..8e12de40245 100644 --- a/src/mainboard/raptor-cs/talos-2/istep89.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -3,7 +3,7 @@ #include #include -void istep89(void) +void istep_8_9(void) { printk(BIOS_EMERG, "starting istep 8.9\n"); p9_fbc_no_hp_scom(); @@ -45,32 +45,8 @@ void tl_fir(void) { write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); - uint64_t l_fir_mask = FBC_IOE_TL_FIR_MASK; - - l_fir_mask |= FBC_IOE_TL_FIR_MASK_X0_NF; - // bool l_x_functional[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = - // { - // false, - // false, - // false - // }; - // uint64_t l_x_non_functional_mask[P9_FBC_UTILS_MAX_ELECTRICAL_LINKS] = - // { - // FBC_IOE_TL_FIR_MASK_X0_NF, - // FBC_IOE_TL_FIR_MASK_X1_NF, - // FBC_IOE_TL_FIR_MASK_X2_NF - // }; - // uint8_t l_unit_pos; - // l_unit_pos = fapi2::ATTR_CHIP_UNIT_POS[XB_CHIPLET_ID]; - // l_x_functional[l_unit_pos] = true; - // for(unsigned int ll = 0; ll < P9_FBC_UTILS_MAX_ELECTRICAL_LINKS; ++ll) - // { - // if (!l_x_functional[ll]) - // { - // l_fir_mask |= l_x_non_functional_mask[ll]; - // } - // } - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_MASK_REG, l_fir_mask); + // not sure about this one, maybe X1 or X2 mask? + write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_MASK_REG, FBC_IOE_TL_FIR_MASK | FBC_IOE_TL_FIR_MASK_X0_NF); } void p9_fbc_no_hp_scom(void) @@ -213,25 +189,10 @@ void p9_fbc_ioe_tl_scom(void) if(X0_ENABLED && DD2X_PARTS) { + // not sure about this one pb_ioe_scom_pb_fp01_cfg &= 0xF00FFFFFF00FFFFF; - pb_ioe_scom_pb_fp01_cfg |= 0x00C0000000C00000; + pb_ioe_scom_pb_fp01_cfg |= 0x00D0000000D00000; } - - if(X2_ENABLED) - { - pb_ioe_scom_pb_fp45_cfg &= 0xfff004bffff007bf; - pb_ioe_scom_pb_fp45_cfg |= 0x0002010000020000; - } - else - { - pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; - } - - if (X2_ENABLED && DD2X_PARTS) - { - pb_ioe_scom_pb_fp45_cfg &= 0xF00FFFFFF00FFFFF; - pb_ioe_scom_pb_fp45_cfg |= 0x00C0000000C00000; - } if (X0_ENABLED && OPTICS_IS_A_BUS) { @@ -265,10 +226,12 @@ void p9_fbc_ioe_tl_scom(void) pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000; } + if (X1_ENABLED && DD2X_PARTS) { + // not sure about this one pb_ioe_scom_pb_fp23_cfg &= 0xF00FFFFFF00FFFFF; - pb_ioe_scom_pb_fp23_cfg |= 0x00C0000000C00000; + pb_ioe_scom_pb_fp23_cfg |= 0x00D0000000D00000; } if(X1_ENABLED) @@ -292,6 +255,23 @@ void p9_fbc_ioe_tl_scom(void) { pb_ioe_scom_pb_fp23_cfg |= 0x0000084000000840; } + + if(X2_ENABLED) + { + pb_ioe_scom_pb_fp45_cfg &= 0xfff004bffff007bf; + pb_ioe_scom_pb_fp45_cfg |= 0x0002010000020000; + } + else + { + pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; + } + + if (X2_ENABLED && DD2X_PARTS) + { + // not sure about this one + pb_ioe_scom_pb_fp45_cfg &= 0xF00FFFFFF00FFFFF; + pb_ioe_scom_pb_fp45_cfg |= 0x00D0000000D00000; + } if(X2_ENABLED) { diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c index 1d2c71bdca7..195b94d9873 100644 --- a/src/soc/ibm/power9/romstage.c +++ b/src/soc/ibm/power9/romstage.c @@ -1,9 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include +asmlinkage void scom_init(void); +asmlinkage void car_stage_entry(void); + +asmlinkage void scom_init(void) +{ + istep_8_9(); + istep_8_10(); + printk(BIOS_EMERG, "Hello from SoC/scom_init()!\n"); +} + asmlinkage void car_stage_entry(void) { - printk(BIOS_EMERG, "hello from SoC!\n"); } From ab696413a0feede98d5c7bc3e2568944685ea854 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 19 Feb 2021 14:57:55 +0100 Subject: [PATCH 71/90] src/soc/ibm/power9/istep_8_10.c: Change testet indirect scom reg --- src/soc/ibm/power9/istep_8_10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 49ca50a05fe..b78bca01e25 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -3043,7 +3043,7 @@ void p9_xbus_g1_scom( void istep_8_10(void) { printk(BIOS_EMERG, "starting istep 8.10\n"); - read_scom(0x800F1C0006010C3F); + read_scom(0x8000C8000701103Full); printk(BIOS_EMERG, "ending istep 8.10\n"); return; } From 62568e6d419de37408bb90da0df0eefa015732a5 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 22 Feb 2021 14:59:21 +0100 Subject: [PATCH 72/90] rc/include/cpu/power/scom.h: create functions for scom rmw --- src/include/cpu/power/istep_8_10.h | 6 + .../cpu/power/{isteps.h => istep_8_9.h} | 18 +- src/include/cpu/power/scom.h | 16 + src/include/cpu/power/scom_registers.h | 1 + src/soc/ibm/power9/istep_8_10.c | 3609 +++-------------- src/soc/ibm/power9/istep_8_9.c | 5 +- 6 files changed, 569 insertions(+), 3086 deletions(-) create mode 100644 src/include/cpu/power/istep_8_10.h rename src/include/cpu/power/{isteps.h => istep_8_9.h} (78%) diff --git a/src/include/cpu/power/istep_8_10.h b/src/include/cpu/power/istep_8_10.h new file mode 100644 index 00000000000..7cb72143911 --- /dev/null +++ b/src/include/cpu/power/istep_8_10.h @@ -0,0 +1,6 @@ +// default value +#define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) + +void istep_8_10(void); +void p9_xbus_g0_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); +void p9_xbus_g1_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); diff --git a/src/include/cpu/power/isteps.h b/src/include/cpu/power/istep_8_9.h similarity index 78% rename from src/include/cpu/power/isteps.h rename to src/include/cpu/power/istep_8_9.h index 2b0bfa444a3..4c946df24bf 100644 --- a/src/include/cpu/power/isteps.h +++ b/src/include/cpu/power/istep_8_9.h @@ -14,11 +14,13 @@ #define EPS_TYPE_LE (0x01), #define EPS_TYPE_HE (0x02), #define EPS_TYPE_HE_F8 (0x03) -#define ATTR_PROC_EPS_TABLE_TYPE (EPS_TYPE_LE) // default value +// default value +#define ATTR_PROC_EPS_TABLE_TYPE (EPS_TYPE_LE) #define CHIP_IS_NODE (0x01) #define CHIP_IS_GROUP (0x02) -#define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) // default value +// default value +#define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) #define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) #define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) @@ -40,19 +42,15 @@ #define NONE (0x3) #define ATTR_LINK_TRAIN BOTH -#define PROC_CHIPLET (0x10) // this is probably wrong +// this is probably wrong +#define PROC_CHIPLET (0x10) #define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) #define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) #define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) #define XBUS_FIR_MASK_REG (0x06010C0) -#define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) // default value -void p9_fbc_ioe_tl_scom(void); void istep_8_9(void); +void p9_fbc_ioe_dl_scom(uint64_t TGT0); +void p9_fbc_ioe_tl_scom(void); void p9_fbc_no_hp_scom(void); void tl_fir(void); -void p9_fbc_ioe_dl_scom(uint64_t TGT0); - -void istep_8_10(void); -void p9_xbus_g1_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); -void p9_xbus_g0_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index a839f84c619..d58467b8b06 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -148,5 +148,21 @@ static inline uint64_t read_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr return read_scom(addr); } +static inline void scom_and_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t and, uint64_t or) +{ + uint64_t data = read_scom_for_chiplet(chiplet, addr); + write_scom_for_chiplet(chiplet, addr, (data & and) | or); +} + +static inline void scom_and_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t and) +{ + scom_and_or_for_chiplet(chiplet, addr, and, 0); +} + +static inline void scom_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t or) +{ + scom_and_or_for_chiplet(chiplet, addr, ~0, or); +} + #endif /* __ASSEMBLER__ */ #endif /* CPU_PPC64_SCOM_H */ diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index 56148f64796..819e032e98b 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -1,4 +1,5 @@ #define PB_WEST_MODE_CFG_REG (0x501180A) // Power Bus PB West Mode Configuration Register +#define PB_CENT_SM0_PB_CENT_FIR_REG (0x5011C00) // Power Bus PB CENT FIR Register #define PB_CENT_MODE_CFG_REG (0x5011C0A) // Power Bus PB CENT Mode Register #define PB_CENT_GP_COMMAND_RATE_DP0_REG (0x5011C26) // Power Bus PB CENT GP command RATE DP0 Register #define PB_CENT_GP_COMMAND_RATE_DP1_REG (0x5011C27) // Power Bus PB CENT GP command RATE DP1 Register diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index b78bca01e25..150ec71d9c1 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -1,3097 +1,562 @@ #include -#include +#include #include #include #include #include -// void *call_proc_xbus_scominit(void *io_pArgs) -// { -// EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; -// // Note: -// // i_noDuplicate parameter must be set to true because -// // one call to p9_io_xbus_scominit will handle both -// // X0 <--> X1 -// // X1 <--> X0 -// // both the xbus and the connected target are used to issue SCOMs -// EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections(l_XbusConnections, TYPE_XBUS, true); -// for l_XbusConnection in l_XbusConnections: -// { -// // XBUS_GROUP_COUNT = 2 -// for group in range(0, XBUS_GROUP_COUNT): -// { -// p9_io_xbus_scominit(l_XbusConnection.first, l_XbusConnection.second, group); -// } -// } -// } - -// void p9_io_xbus_scominit( -// const fapi2::Target &i_target, -// const fapi2::Target &i_connected_target, -// const uint8_t group) -// { -// const uint8_t LANE_00 = 0; -// fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS; -// // get system target -// const fapi2::Target l_system_target; -// // get proc chip to pass for EC level checks in procedure -// fapi2::Target l_proc = i_target.getParent(); -// // assert IO reset to power-up bus endpoint logic -// // read-modify-write, set single reset bit (HW auto-clears) -// // on writeback -// EDIP_RX_IORESET[i_target, group, LANE_00] = 1; -// EDIP_RX_IORESET[i_connected_target, group, LANE_00] = 1; -// wait_us(50, false); -// EDIP_TX_IORESET[i_target, group, LANE_00] = 1; -// EDIP_TX_IORESET[i_connected_target, group, LANE_00] = 1; -// wait_us(50, false); -// // Set rx master/slave attribute prior to calling the scominit procedures. -// // The scominit procedure will reference the attribute to set the register field. -// set_rx_master_mode(i_target, i_connected_target); -// // Set Msb Swap based upon attribute data. -// set_msb_swap(i_target, group); -// set_msb_swap(i_connected_target, group); -// switch (group) -// { -// case ENUM_ATTR_XBUS_GROUP_0: -// p9_xbus_g0_scom(i_target, l_system_target, l_proc); -// p9_xbus_g0_scom(i_connected_target, l_system_target, l_proc); -// break; -// case ENUM_ATTR_XBUS_GROUP_1: -// p9_xbus_g1_scom(i_target, l_system_target, l_proc); -// p9_xbus_g1_scom(i_connected_target, l_system_target, l_proc); -// break; -// } - -// fapi2::buffer l_scom_data; -// l_scom_data = l_proc[PU_PB_CENT_SM0_PB_CENT_FIR_REG]; -// if(!l_scom_data.getBit<13>()) -// { - -// i_target[XBUS_FIR_ACTION0_REG] = XBUS_PHY_FIR_ACTION0; -// i_target[XBUS_FIR_ACTION1_REG] = XBUS_PHY_FIR_ACTION1; -// i_target[XBUS_FIR_MASK_REG] = XBUS_PHY_FIR_MASK; -// } -// } - -// void set_msb_swap(/*const Target*/uint64_t i_tgt, const uint8_t i_grp) -// { -// const uint8_t lane0 = 0; -// uint8_t tx_msb_swap = 0x0; -// uint8_t field_data = 0x0; - -// // Retrieve msb swap attribute -// tx_msb_swap = ATTR_EI_BUS_TX_MSBSWAP[i_tgt]; - -// if(i_grp == ENUM_ATTR_XBUS_GROUP_0 && (tx_msb_swap & ENUM_ATTR_EI_BUS_TX_MSBSWAP_GROUP_0_SWAP) -// || i_grp == ENUM_ATTR_XBUS_GROUP_1 && (tx_msb_swap & ENUM_ATTR_EI_BUS_TX_MSBSWAP_GROUP_1_SWAP)) -// { -// field_data = 1; -// } -// EDIP_TX_MSBSWAP[i_tgt, i_grp, lane0] = field_data; -// } - -void p9_xbus_g0_scom( - /*const fapi2::Target &*/ uint64_t TGT0, - /*const fapi2::Target &*/ uint64_t TGT1, - /*const fapi2::Target &*/ uint64_t TGT2) +void *call_proc_xbus_scominit(void *io_pArgs) { - uint64_t l_scom_buffer; - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000006010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000106010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000206010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000306010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000406010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000506010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000606010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000706010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000806010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000906010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000A06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000B06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000C06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000D06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000E06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000000F06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000000F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000001006010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000001006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000001106010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFF8FF; - write_scom(0x8000001106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080006010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080106010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080206010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080306010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080406010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080506010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080606010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080706010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080806010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080906010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080A06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080B06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080C06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080D06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080E06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000080F06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000080F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000081006010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000081006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000081106010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8000081106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000280F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000280F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000281006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000281006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000281106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000281106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300906010C3F, l_scom_buffer); - - l_scom_buffer = read_scom(0x8000300A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000300F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000300F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000301006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000301006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000301106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000301106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C00F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C00F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C01006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C01006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C01106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C01106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200706010C3F, l_scom_buffer); - - l_scom_buffer = read_scom(0x8002200806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002200F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002200F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002201006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002201006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002201106010C3F); - l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON - write_scom(0x8002201106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00006010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1000; - write_scom(0x8002C00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00106010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFFF03E; - write_scom(0x8002C00106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00206010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07BC; - write_scom(0x8002C00206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00306010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07C7; - write_scom(0x8002C00306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00406010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF03EF; - write_scom(0x8002C00406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00506010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; - write_scom(0x8002C00506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00606010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1800; - write_scom(0x8002C00606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00706010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF9C00; - write_scom(0x8002C00706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00806010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1000; - write_scom(0x8002C00806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00906010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF9C00; - write_scom(0x8002C00906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00A06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1800; - write_scom(0x8002C00A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00B06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; - write_scom(0x8002C00B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00C06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF03EF; - write_scom(0x8002C00C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00D06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07C7; - write_scom(0x8002C00D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00E06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07BC; - write_scom(0x8002C00E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C00F06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFFF03E; - write_scom(0x8002C00F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C01006010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1000; - write_scom(0x8002C01006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80006010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004200; - write_scom(0x8002C80006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80106010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000003E00; - write_scom(0x8002C80106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80206010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - write_scom(0x8002C80206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80306010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000006000; - write_scom(0x8002C80306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80406010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C80406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80506010C3F); - // l_IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C80506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80606010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C80606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80706010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C80706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80806010C3F); - // l_IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004200; - write_scom(0x8002C80806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80906010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C80906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80A06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C80A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80B06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C80B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80C06010C3F); - // l_IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C80C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80D06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000006000; - write_scom(0x8002C80D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80E06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - write_scom(0x8002C80E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C80F06010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000003E00; - write_scom(0x8002C80F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C81006010C3F); - // l_IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004200; - write_scom(0x8002C81006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004040F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004040F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004041006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004041006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0006010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0106010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0206010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0306010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0406010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0506010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0606010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0706010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0806010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0906010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0A06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0B06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0C06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0D06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0E06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C0F06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C0F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C1006010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C1006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C0106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0206010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001E; - write_scom(0x80043C0206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0306010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001F; - write_scom(0x80043C0306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0406010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000000F; - write_scom(0x80043C0406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0506010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000007C; - write_scom(0x80043C0506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0606010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000C63; - write_scom(0x80043C0606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0706010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000E73; - write_scom(0x80043C0706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C0806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0906010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000E73; - write_scom(0x80043C0906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0A06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000C63; - write_scom(0x80043C0A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0B06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000007C; - write_scom(0x80043C0B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0C06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000000F; - write_scom(0x80043C0C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0D06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001F; - write_scom(0x80043C0D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0E06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001E; - write_scom(0x80043C0E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C0F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C0F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C1006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C1006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440006010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8004440006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440106010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000F800; - write_scom(0x8004440106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440206010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000F600; - write_scom(0x8004440206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440306010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004440306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440406010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004440406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440506010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000002000; - write_scom(0x8004440506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440606010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004440606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440706010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004440706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440806010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8004440806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440906010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000009C00; - write_scom(0x8004440906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440A06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004440A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440B06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004440B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440C06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004440C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440D06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004440D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440E06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004440E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004440F06010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000F800; - write_scom(0x8004440F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004441006010C3F); - // l_IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8004441006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_SPARE_MODE_PG - l_scom_buffer = read_scom(0x8008000006010C3F); - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8008000006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_ID1_PG - l_scom_buffer = read_scom(0x8008080006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF03FF; - write_scom(0x8008080006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE1_EO_PG - l_scom_buffer = read_scom(0x8008100006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF - write_scom(0x8008100006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE5_EO_PG - l_scom_buffer = read_scom(0x8008300006010C3F); - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 - l_scom_buffer &= 0xffffffffffffe0ff; - l_scom_buffer |= 0x0000000000001500; - write_scom(0x8008300006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE7_EO_PG - l_scom_buffer = read_scom(0x8008400006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFFF0; - l_scom_buffer |= 0x000000000000000A; - write_scom(0x8008400006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG - l_scom_buffer = read_scom(0x8008C00006010C3F); - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON - l_scom_buffer &= 0xFFFFFFFFFFFF3E07; - l_scom_buffer |= 0x00000000000010F8; - write_scom(0x8008C00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE29_EO_PG - l_scom_buffer = read_scom(0x8008D00006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000001044; - write_scom(0x8008D00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE27_EO_PG - l_scom_buffer = read_scom(0x8009700006010C3F); - l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON - write_scom(0x8009700006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_ID2_PG - l_scom_buffer = read_scom(0x8009800006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF8080; - l_scom_buffer |= 0x0000000000000010; - write_scom(0x8009800006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE1_E_PG - l_scom_buffer = read_scom(0x8009900006010C3F); - if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) { - l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER + EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; + EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections(l_XbusConnections, TYPE_XBUS, true); + for l_XbusConnection in l_XbusConnections: + { + p9_io_xbus_scominit(l_XbusConnection.first, l_XbusConnection.second, 0); + p9_io_xbus_scominit(l_XbusConnection.first, l_XbusConnection.second, 1); } - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED - l_scom_buffer |= 0x0000000000000060; - write_scom(0x8009900006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE2_E_PG - l_scom_buffer = read_scom(0x8009980006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF07FF; - l_scom_buffer |= 0x0000000000000800; - write_scom(0x8009980006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE3_E_PG - l_scom_buffer = read_scom(0x8009A00006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; - l_scom_buffer |= 0x000000000000B000; - write_scom(0x8009A00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE5_E_PG - l_scom_buffer = read_scom(0x8009B00006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; - l_scom_buffer |= 0x0000000000001000; - write_scom(0x8009B00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE6_E_PG - l_scom_buffer = read_scom(0x8009B80006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - l_scom_buffer |= 0x0000000000002244; - write_scom(0x8009B80006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE8_E_PG - l_scom_buffer = read_scom(0x8009C80006010C3F); - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 - l_scom_buffer &= 0xffffffffffff0018; - l_scom_buffer |= 0x0000000000001ea5; - write_scom(0x8009C80006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE9_E_PG - l_scom_buffer = read_scom(0x8009D00006010C3F); - // l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 - l_scom_buffer &= 0xffffffffffff001f; - l_scom_buffer |= 0x0000000000003fa0; - write_scom(0x8009D00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE11_E_PG - l_scom_buffer = read_scom(0x8009E00006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - write_scom(0x8009E00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE12_E_PG - l_scom_buffer = read_scom(0x8009E80006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - l_scom_buffer |= 0x0000000000007F00; - write_scom(0x8009E80006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_GLBSM_SPARE_MODE_PG - l_scom_buffer = read_scom(0x800A800006010C3F); - // l_IOF1_RX_RX0_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER - // l_IOF1_RX_RX0_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON - l_scom_buffer |= 0x10000010000000; - write_scom(0x800A800006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_GLBSM_CNTL3_EO_PG - l_scom_buffer = read_scom(0x800AE80006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; - l_scom_buffer |= 0x0000000000000020; - write_scom(0x800AE80006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_GLBSM_MODE1_EO_PG - l_scom_buffer = read_scom(0x800AF80006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - l_scom_buffer |= 0x000000000000CC00; - write_scom(0x800AF80006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_DATASM_SPARE_MODE_PG - l_scom_buffer = read_scom(0x800B800006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFFF7; // l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF - write_scom(0x800B800006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_SPARE_MODE_PG - l_scom_buffer = read_scom(0x800C040006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; - write_scom(0x800C040006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_ID1_PG - l_scom_buffer = read_scom(0x800C0C0006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF03FF; - write_scom(0x800C0C0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTL_MODE1_EO_PG - l_scom_buffer = read_scom(0x800C140006010C3F); - // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF - // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON - l_scom_buffer &= 0xFFFFFFFFFFFF783F; - l_scom_buffer |= 0x0000000000000050; - write_scom(0x800C140006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTL_MODE2_EO_PG - l_scom_buffer = read_scom(0x800C1C0006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFF01; - l_scom_buffer |= 0x0000000000000022; - write_scom(0x800C1C0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTL_CNTLG1_EO_PG - l_scom_buffer = read_scom(0x800C240006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF3FFF; // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S - write_scom(0x800C240006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_ID2_PG - l_scom_buffer = read_scom(0x800C840006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF8080; - l_scom_buffer |= 0x0000000000000010; - write_scom(0x800C840006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTL_MODE1_E_PG - l_scom_buffer = read_scom(0x800C8C0006010C3F); - // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 - // l_IOF1_TX_WRAP_TX0_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 - l_scom_buffer &= 0xfffffffffffffe0f; - l_scom_buffer |= 0x0000000000000150; - write_scom(0x800C8C0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTL_MODE2_E_PG - l_scom_buffer = read_scom(0x800CEC0006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - write_scom(0x800CEC0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTL_MODE3_E_PG - l_scom_buffer = read_scom(0x800CF40006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - l_scom_buffer |= 0x0000000000007F00; - write_scom(0x800CF40006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX0_TX_CTLSM_MODE1_EO_PG - l_scom_buffer = read_scom(0x800D2C0006010C3F); - l_scom_buffer |= 0x0000000000000010; // l_IOF1_TX_WRAP_TX0_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON - write_scom(0x800D2C0006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX_IMPCAL_P_4X_PB - l_scom_buffer = read_scom(0x800F1C0006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF07FF; - l_scom_buffer |= 0x0000000000007000; - write_scom(0x800F1C0006010C3F, l_scom_buffer); } -void p9_xbus_g1_scom( - /* const fapi2::Target*/ uint64_t TGT0, - /* const fapi2::Target*/ uint64_t TGT1, - /* const fapi2::Target*/ uint64_t TGT2) +void p9_io_xbus_scominit( + chiplet_id_t i_target, + chiplet_id_t i_connected_target, + const uint8_t group) { + chiplet_id_t l_proc = i_target.getParent(); + const uint8_t LANE_00 = 0; uint64_t l_scom_buffer; - // P9A_XBUS_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002006010C3F); - //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002106010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002206010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002306010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002406010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002506010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002606010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002706010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002806010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002906010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002A06010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002B06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002C06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002D06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002E06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000002F06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000002F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000003006010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF; - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF; - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000003006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - l_scom_buffer = read_scom(0x8000003106010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - l_scom_buffer &= 0xfffffffffffff8ff; - write_scom(0x8000003106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - write_scom(0x8000082706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082806010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082906010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082A06010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082B06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082C06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082D06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082E06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000082F06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000082F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000083006010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFDFF; - write_scom(0x8000083006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL - l_scom_buffer = read_scom(0x8000083106010C3F); - l_scom_buffer |= 0x0000000000000200; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON - write_scom(0x8000083106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000282F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000282F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000283006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000283006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL - l_scom_buffer = read_scom(0x8000283106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - write_scom(0x8000283106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000302F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000302F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000303006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000303006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL - l_scom_buffer = read_scom(0x8000303106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF007F; - l_scom_buffer |= 0x0000000000006380; - write_scom(0x8000303106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C02F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C02F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C03006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C03006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL - l_scom_buffer = read_scom(0x8000C03106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0007; - write_scom(0x8000C03106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002202F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002202F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002203006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - write_scom(0x8002203006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL - l_scom_buffer = read_scom(0x8002203106010C3F); - l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON - write_scom(0x8002203106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02006010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1000; - write_scom(0x8002C02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02106010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFFF03E; - write_scom(0x8002C02106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02206010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07BC; - write_scom(0x8002C02206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02306010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07C7; - write_scom(0x8002C02306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02406010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF03EF; - write_scom(0x8002C02406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02506010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; - write_scom(0x8002C02506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02606010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1800; - write_scom(0x8002C02606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02706010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF9C00; - write_scom(0x8002C02706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02806010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1000; - write_scom(0x8002C02806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02906010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF9C00; - write_scom(0x8002C02906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02A06010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1800; - write_scom(0x8002C02A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02B06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1F0F; - write_scom(0x8002C02B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02C06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF03EF; - write_scom(0x8002C02C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02D06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07C7; - write_scom(0x8002C02D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C02E06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF07BC; - write_scom(0x8002C02E06010C3F, l_scom_buffer); - - l_scom_buffer = read_scom(0x8002C02F06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFFF03E; - write_scom(0x8002C02F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x8002C03006010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0xFFFFFFFFFFFF1000; - write_scom(0x8002C03006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82006010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004200; - write_scom(0x8002C82006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82106010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000003E00; - write_scom(0x8002C82106010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82206010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - write_scom(0x8002C82206010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82306010C3F); - // l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000006000; - write_scom(0x8002C82306010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82406010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C82406010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82506010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C82506010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82606010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C82606010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82706010C3F); - // l_IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C82706010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82806010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004200; - write_scom(0x8002C82806010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82906010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C82906010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82A06010C3F); - // l_IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000300; - write_scom(0x8002C82A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82B06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C82B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82C06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8002C82C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82D06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000006000; - write_scom(0x8002C82D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82E06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - write_scom(0x8002C82E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C82F06010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000003E00; - write_scom(0x8002C82F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8002C83006010C3F); - // l_IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000004200; - write_scom(0x8002C83006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042206010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042206010C3F, l_scom_buffer); - - l_scom_buffer = read_scom(0x8004042306010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042406010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042506010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042606010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042706010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042906010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042A06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042B06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042C06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042D06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042E06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004042F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004042F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE1_PL - l_scom_buffer = read_scom(0x8004043006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - write_scom(0x8004043006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2006010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2106010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2106010C3F, l_scom_buffer); - - l_scom_buffer = read_scom(0x80040C2206010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2306010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2406010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2506010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2606010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2706010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2806010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2906010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2A06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2B06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2C06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2D06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2E06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C2F06010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C2F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE2_PL - l_scom_buffer = read_scom(0x80040C3006010C3F); - l_scom_buffer |= 0x0000000000000002; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - write_scom(0x80040C3006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C2006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2106010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C2106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2206010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001E; - write_scom(0x80043C2206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2306010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001F; - write_scom(0x80043C2306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2406010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000000F; - write_scom(0x80043C2406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2506010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000007C; - write_scom(0x80043C2506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2606010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000C63; - write_scom(0x80043C2606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2706010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000E73; - write_scom(0x80043C2706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2806010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C2806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2906010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000E73; - write_scom(0x80043C2906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2A06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000000C63; - write_scom(0x80043C2A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2B06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000007C; - write_scom(0x80043C2B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2C06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000000F; - write_scom(0x80043C2C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2D06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001F; - write_scom(0x80043C2D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2E06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x000000000000001E; - write_scom(0x80043C2E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C2F06010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C2F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL - l_scom_buffer = read_scom(0x80043C3006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - write_scom(0x80043C3006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442006010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8004442006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442106010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000F800; - write_scom(0x8004442106010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442206010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF0100; - l_scom_buffer |= 0x000000000000F600; - write_scom(0x8004442206010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442306010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004442306010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442406010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004442406010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442506010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000002000; - write_scom(0x8004442506010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442606010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004442606010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442706010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004442706010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442806010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8004442806010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442906010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000009C00; - write_scom(0x8004442906010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442A06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004442A06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442B06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004442B06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442C06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000bc00; - write_scom(0x8004442C06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442D06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000001800; - write_scom(0x8004442D06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442E06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000BC00; - write_scom(0x8004442E06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004442F06010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x000000000000F800; - write_scom(0x8004442F06010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL - l_scom_buffer = read_scom(0x8004443006010C3F); - // l_IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - l_scom_buffer &= 0xFFFFFFFFFFFF01FF; - l_scom_buffer |= 0x0000000000000200; - write_scom(0x8004443006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_SPARE_MODE_PG - l_scom_buffer = read_scom(0x8008002006010C3F); - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8008002006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_ID1_PG - l_scom_buffer = read_scom(0x8008082006010C3F); - l_scom_buffer &= 0xffffffffffff03ff; - l_scom_buffer |= 0x0000000000000400; - write_scom(0x8008082006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE1_EO_PG - l_scom_buffer = read_scom(0x8008102006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF7FFF; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF - write_scom(0x8008102006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE5_EO_PG - l_scom_buffer = read_scom(0x8008302006010C3F); - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 - l_scom_buffer &= 0xffffffffffffe0ff; - l_scom_buffer |= 0x0000000000001500; - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 - write_scom(0x8008302006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE7_EO_PG - l_scom_buffer = read_scom(0x8008402006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFFF0; - l_scom_buffer |= 0x000000000000000A; - write_scom(0x8008402006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG - l_scom_buffer = read_scom(0x8008C00006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF3FFF; - l_scom_buffer |= 0x0000000000004000; - write_scom(0x8008C00006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG - l_scom_buffer = read_scom(0x8008C02006010C3F); - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON - l_scom_buffer &= 0xFFFFFFFFFFFFFEFF; - l_scom_buffer |= 0x00000000000000F8; - write_scom(0x8008C02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG - l_scom_buffer = read_scom(0x8008D02006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0000; - l_scom_buffer |= 0x0000000000001044; - write_scom(0x8008D02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG - l_scom_buffer = read_scom(0x8009702006010C3F); - l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON - write_scom(0x8009702006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_ID2_PG - l_scom_buffer = read_scom(0x8009802006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF8080; - l_scom_buffer |= 0x0000000000000010; - write_scom(0x8009802006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG - l_scom_buffer = read_scom(0x8009902006010C3F); - if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) { - l_scom_buffer |= 0x0000000000008000; // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER + scom_or_for_chiplet(i_target, 0x8009F8000000003F, 0x800); + scom_or_for_chiplet(i_connected_target, 0x8009F8000000003F, 0x800); + wait_us(50, false); + scom_or_for_chiplet(i_target, 0x800C9C000000003F, 0x8000); + scom_or_for_chiplet(i_connected_target, 0x800C9C000000003F, 0x8000); + wait_us(50, false); + + if(0 == group) + { + p9_xbus_g0_scom(i_target); + p9_xbus_g0_scom(i_connected_target); + } + else if(1 == group) + { + p9_xbus_g1_scom(i_target); + p9_xbus_g1_scom(i_connected_target); } - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED - l_scom_buffer |= 0x0000000000000060; - write_scom(0x8009902006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG - l_scom_buffer = read_scom(0x8009982006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF07FF; - l_scom_buffer |= 0x0000000000000800; - write_scom(0x8009982006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG - l_scom_buffer = read_scom(0x8009A02006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; - l_scom_buffer |= 0x000000000000B000; - write_scom(0x8009A02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG - l_scom_buffer = read_scom(0x8009B02006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0FFF; - l_scom_buffer |= 0x0000000000001000; - write_scom(0x8009B02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG - l_scom_buffer = read_scom(0x8009B82006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF0003; - l_scom_buffer |= 0x0000000000002244; - write_scom(0x8009B82006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG - l_scom_buffer = read_scom(0x8009C82006010C3F); - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 - l_scom_buffer &= 0xFFFFFFFFFFFF0018; - l_scom_buffer |= 0x0000000000001EA5; - write_scom(0x8009C82006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG - l_scom_buffer = read_scom(0x8009D02006010C3F); - // l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 - l_scom_buffer &= 0x7fffffffffff800; - l_scom_buffer |= 0x0000000000003f5; - write_scom(0x8009D02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE11_E_PG - l_scom_buffer = read_scom(0x8009E02006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - write_scom(0x8009E02006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG - l_scom_buffer = read_scom(0x8009E82006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - l_scom_buffer |= 0x0000000000007F00; - write_scom(0x8009E82006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG - l_scom_buffer = read_scom(0x800A802006010C3F); - // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER - // l_IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON - l_scom_buffer |= 0x0000000000002080; - write_scom(0x800A802006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG - l_scom_buffer = read_scom(0x800AE82006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; - l_scom_buffer |= 0x0000000000000080; - write_scom(0x800AE82006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG - l_scom_buffer = read_scom(0x800AF82006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - l_scom_buffer |= 0x000000000000CC00; - write_scom(0x800AF82006010C3F, l_scom_buffer); - - // P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG - l_scom_buffer = read_scom(0x800B802006010C3F); - // l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF - l_scom_buffer &= 0xFFFFFFFFFFFFFFF7; - write_scom(0x800B802006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_SPARE_MODE_PG - l_scom_buffer = read_scom(0x800C042006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFF3F; - write_scom(0x800C042006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_ID1_PG - l_scom_buffer = read_scom(0x800C0C2006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF03FF; - l_scom_buffer |= 0x0000000000000400; - write_scom(0x800C0C2006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG - l_scom_buffer = read_scom(0x800C142006010C3F); - // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF - // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON - l_scom_buffer &= 0xFFFFFFFFFFFF783F; - l_scom_buffer |= 0x0000000000000050; - write_scom(0x800C142006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG - l_scom_buffer = read_scom(0x800C1C2006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFFFF01; - l_scom_buffer |= 0x0000000000000F22; - write_scom(0x800C1C2006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG - l_scom_buffer = read_scom(0x800C242006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF3FFF; // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S - write_scom(0x800C242006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_ID2_PG - l_scom_buffer = read_scom(0x800C842006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF8080; - l_scom_buffer |= 0x0000000000000010; - write_scom(0x800C842006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG - l_scom_buffer = read_scom(0x800C8C2006010C3F); - // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 - // l_IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 - l_scom_buffer &= 0xfffffffffffffe0f; - l_scom_buffer |= 0x0000000000000150; - write_scom(0x800C8C2006010C3F, l_scom_buffer); - - // P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG - l_scom_buffer = read_scom(0x800CEC2006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - write_scom(0x800CEC2006010C3F, l_scom_buffer); - // P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG - l_scom_buffer = read_scom(0x800CF42006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF00FF; - l_scom_buffer |= 0x0000000000007F00; - write_scom(0x800CF42006010C3F, l_scom_buffer); + if(!(read_scom_for_chiplet(l_proc, PB_CENT_SM0_PB_CENT_FIR_REG) & 0x4000000000000)) + { + write_scom_for_chiplet(i_target, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); + write_scom_for_chiplet(i_target, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); + write_scom_for_chiplet(i_target, XBUS_FIR_MASK_REG, XBUS_PHY_FIR_MASK); + } +} - // P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG - l_scom_buffer = read_scom(0x800D2C2006010C3F); - l_scom_buffer |= 0x0000000000000010; // l_IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON - write_scom(0x800D2C2006010C3F, l_scom_buffer); +void p9_xbus_g0_scom(chiplet_id_t TGT0) +{ + scom_and_for_chiplet(TGT0, 0x8000000006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000206010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000306010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000406010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000506010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000606010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000706010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000806010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000906010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000A06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000B06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000C06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000D06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000E06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000000F06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000001006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000001106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(TGT0, 0x8000080006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080106010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080206010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080306010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080406010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080506010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080606010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080706010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080806010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080906010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080A06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080B06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080C06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080D06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080E06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000080F06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000081006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_or_for_chiplet(TGT0, 0x8000081106010C3F, 0x200); + scom_and_for_chiplet(TGT0, 0x8000280006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280206010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280306010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280406010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280506010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280606010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280706010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280806010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280906010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280A06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280B06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280C06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280D06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280E06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000280F06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000281006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000281106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_or_for_chiplet(TGT0, 0x8000300006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000300F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000301006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000301106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_for_chiplet(TGT0, 0x8000C00006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00206010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00306010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00406010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00506010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00606010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00706010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00806010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00906010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00A06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00B06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00C06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00D06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00E06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C00F06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C01006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C01106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8002200006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002200F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002201006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(TGT0, 0x8002201106010C3F, 0x8000); + scom_and_or_for_chiplet(TGT0, 0x8002C00006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8002C00106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(TGT0, 0x8002C00206010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); + scom_and_or_for_chiplet(TGT0, 0x8002C00306010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); + scom_and_or_for_chiplet(TGT0, 0x8002C00406010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); + scom_and_or_for_chiplet(TGT0, 0x8002C00506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(TGT0, 0x8002C00606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8002C00706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(TGT0, 0x8002C00806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8002C00906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(TGT0, 0x8002C00A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8002C00B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(TGT0, 0x8002C00C06010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); + scom_and_or_for_chiplet(TGT0, 0x8002C00D06010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); + scom_and_or_for_chiplet(TGT0, 0x8002C00E06010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); + scom_and_or_for_chiplet(TGT0, 0x8002C00F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(TGT0, 0x8002C01006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8002C80006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(TGT0, 0x8002C80106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_for_chiplet(TGT0, 0x8002C80206010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(TGT0, 0x8002C80306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_or_for_chiplet(TGT0, 0x8002C80406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C80506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C80606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C80706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C80806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(TGT0, 0x8002C80906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C80A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C80B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C80C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C80D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_for_chiplet(TGT0, 0x8002C80E06010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(TGT0, 0x8002C80F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_or_for_chiplet(TGT0, 0x8002C81006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_for_chiplet(TGT0, 0x8004040006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004040F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004041006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(TGT0, 0x80040C0006010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0106010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0206010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0306010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0406010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0506010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0606010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0706010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0806010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0906010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0A06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0B06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0C06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0D06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0E06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C0F06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C1006010C3F, 0x2); + scom_and_for_chiplet(TGT0, 0x80043C0006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(TGT0, 0x80043C0106010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(TGT0, 0x80043C0206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_or_for_chiplet(TGT0, 0x80043C0306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(TGT0, 0x80043C0406010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(TGT0, 0x80043C0506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(TGT0, 0x80043C0606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(TGT0, 0x80043C0706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_for_chiplet(TGT0, 0x80043C0806010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(TGT0, 0x80043C0906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_or_for_chiplet(TGT0, 0x80043C0A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(TGT0, 0x80043C0B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(TGT0, 0x80043C0C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(TGT0, 0x80043C0D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(TGT0, 0x80043C0E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_for_chiplet(TGT0, 0x80043C0F06010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(TGT0, 0x80043C1006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(TGT0, 0x8004440006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(TGT0, 0x8004440106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(TGT0, 0x8004440206010C3F, 0xFFFFFFFFFFFF01FF, 0xF600); + scom_and_or_for_chiplet(TGT0, 0x8004440306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004440406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004440506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); + scom_and_or_for_chiplet(TGT0, 0x8004440606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004440706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004440806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(TGT0, 0x8004440906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); + scom_and_or_for_chiplet(TGT0, 0x8004440A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004440B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004440C06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004440D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004440E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004440F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(TGT0, 0x8004441006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_or_for_chiplet(TGT0, 0x8008000006010C3F, 0x4000); + scom_and_for_chiplet(TGT0, 0x8008080006010C3F, 0xFFFFFFFFFFFF03FF); + scom_and_for_chiplet(TGT0, 0x8008100006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_or_for_chiplet(TGT0, 0x8008300006010C3F, 0xffffffffffffe0ff, 0x1500); + scom_and_or_for_chiplet(TGT0, 0x8008400006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); + scom_and_or_for_chiplet(TGT0, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3E07, 0x10F8); + scom_and_or_for_chiplet(TGT0, 0x8008D00006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); + scom_or_for_chiplet(TGT0, 0x8009700006010C3F, 0x8000); + scom_and_or_for_chiplet(TGT0, 0x8009800006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) + scom_or_for_chiplet(TGT0, 0x8009900006010C3F, 0x8060); + else + scom_or_for_chiplet(TGT0, 0x8009900006010C3F, 0x60); + scom_and_or_for_chiplet(TGT0, 0x8009980006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); + scom_and_or_for_chiplet(TGT0, 0x8009A00006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); + scom_and_or_for_chiplet(TGT0, 0x8009B00006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8009B80006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); + scom_and_or_for_chiplet(TGT0, 0x8009C80006010C3F, 0xffffffffffff0018, 0x1ea5); + scom_and_or_for_chiplet(TGT0, 0x8009D00006010C3F, 0xffffffffffff001f, 0x3fa0); + scom_and_for_chiplet(TGT0, 0x8009E00006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(TGT0, 0x8009E80006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(TGT0, 0x800A800006010C3F, 0x10000010000000); + scom_and_or_for_chiplet(TGT0, 0x800AE80006010C3F, 0xFFFFFFFFFFFFFF3F, 0x20); + scom_and_or_for_chiplet(TGT0, 0x800AF80006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); + scom_and_for_chiplet(TGT0, 0x800B800006010C3F, 0xFFFFFFFFFFFFFFF7); + scom_and_for_chiplet(TGT0, 0x800C040006010C3F, 0xFFFFFFFFFFFFFF3F); + scom_and_for_chiplet(TGT0, 0x800C0C0006010C3F, 0xFFFFFFFFFFFF03FF); + scom_and_or_for_chiplet(TGT0, 0x800C140006010C3F, 0xFFFFFFFFFFFF783F, 0x50); + scom_and_or_for_chiplet(TGT0, 0x800C1C0006010C3F, 0xFFFFFFFFFFFFFF01, 0x22); + scom_and_for_chiplet(TGT0, 0x800C240006010C3F, 0xFFFFFFFFFFFF3FFF); + scom_and_or_for_chiplet(TGT0, 0x800C840006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_and_or_for_chiplet(TGT0, 0x800C8C0006010C3F, 0xfffffffffffffe0f, 0x150); + scom_and_for_chiplet(TGT0, 0x800CEC0006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(TGT0, 0x800CF40006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(TGT0, 0x800D2C0006010C3F, 0x10); + scom_and_or_for_chiplet(TGT0, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); +} - // P9A_XBUS_0_TX_IMPCAL_P_4X_PB - l_scom_buffer = read_scom(0x800F1C0006010C3F); - l_scom_buffer &= 0xFFFFFFFFFFFF07FF; - l_scom_buffer |= 0x0000000000007000; - write_scom(0x800F1C0006010C3F, l_scom_buffer); +void p9_xbus_g1_scom(chiplet_id_t TGT0) +{ + uint64_t l_scom_buffer; + scom_and_for_chiplet(TGT0, 0x8000002006010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002106010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002206010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002306010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002406010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002506010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002606010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002706010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002806010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002906010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002A06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002B06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002C06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002D06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002E06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000002F06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000003006010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000003106010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(TGT0, 0x8000082006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082106010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082206010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082306010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082406010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082506010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082606010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082706010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082806010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082906010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082A06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082B06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082C06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082D06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082E06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000082F06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(TGT0, 0x8000083006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_or_for_chiplet(TGT0, 0x8000083106010C3F, 0x200); + scom_and_for_chiplet(TGT0, 0x8000282006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282206010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282306010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282406010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282506010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282606010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282706010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282806010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282906010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282A06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282B06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282C06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282D06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282E06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000282F06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000283006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(TGT0, 0x8000283106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_or_for_chiplet(TGT0, 0x8000302006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000302F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000303006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(TGT0, 0x8000303106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_for_chiplet(TGT0, 0x8000C02006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02206010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02306010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02406010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02506010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02606010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02706010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02806010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02906010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02A06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02B06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02C06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02D06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02E06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C02F06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C03006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8000C03106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(TGT0, 0x8002202006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002202F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8002203006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(TGT0, 0x8002203106010C3F, 0x8000); + scom_and_or_for_chiplet(TGT0, 0x8002C02006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8002C02106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(TGT0, 0x8002C02206010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); + scom_and_or_for_chiplet(TGT0, 0x8002C02306010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); + scom_and_or_for_chiplet(TGT0, 0x8002C02406010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); + scom_and_or_for_chiplet(TGT0, 0x8002C02506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(TGT0, 0x8002C02606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8002C02706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(TGT0, 0x8002C02806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8002C02906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(TGT0, 0x8002C02A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8002C02B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(TGT0, 0x8002C02C06010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); + scom_and_or_for_chiplet(TGT0, 0x8002C02D06010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); + scom_and_or_for_chiplet(TGT0, 0x8002C02E06010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); + scom_and_or_for_chiplet(TGT0, 0x8002C02F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(TGT0, 0x8002C03006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8002C82006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(TGT0, 0x8002C82106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_for_chiplet(TGT0, 0x8002C82206010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(TGT0, 0x8002C82306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_or_for_chiplet(TGT0, 0x8002C82406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C82506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C82606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C82706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C82806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(TGT0, 0x8002C82906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C82A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(TGT0, 0x8002C82B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C82C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8002C82D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_for_chiplet(TGT0, 0x8002C82E06010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(TGT0, 0x8002C82F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_or_for_chiplet(TGT0, 0x8002C83006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_for_chiplet(TGT0, 0x8004042006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004042F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(TGT0, 0x8004043006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(TGT0, 0x80040C2006010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2106010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2206010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2306010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2406010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2506010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2606010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2706010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2806010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2906010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2A06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2B06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2C06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2D06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2E06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C2F06010C3F, 0x2); + scom_or_for_chiplet(TGT0, 0x80040C3006010C3F, 0x2); + scom_and_for_chiplet(TGT0, 0x80043C2006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(TGT0, 0x80043C2106010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(TGT0, 0x80043C2206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_or_for_chiplet(TGT0, 0x80043C2306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(TGT0, 0x80043C2406010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(TGT0, 0x80043C2506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(TGT0, 0x80043C2606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(TGT0, 0x80043C2706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_for_chiplet(TGT0, 0x80043C2806010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(TGT0, 0x80043C2906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_or_for_chiplet(TGT0, 0x80043C2A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(TGT0, 0x80043C2B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(TGT0, 0x80043C2C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(TGT0, 0x80043C2D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(TGT0, 0x80043C2E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_for_chiplet(TGT0, 0x80043C2F06010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(TGT0, 0x80043C3006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(TGT0, 0x8004442006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(TGT0, 0x8004442106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(TGT0, 0x8004442206010C3F, 0xFFFFFFFFFFFF0100, 0xF600); + scom_and_or_for_chiplet(TGT0, 0x8004442306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004442406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004442506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); + scom_and_or_for_chiplet(TGT0, 0x8004442606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004442706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004442806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(TGT0, 0x8004442906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); + scom_and_or_for_chiplet(TGT0, 0x8004442A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004442B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004442C06010C3F, 0xFFFFFFFFFFFF01FF, 0xbc00); + scom_and_or_for_chiplet(TGT0, 0x8004442D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(TGT0, 0x8004442E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(TGT0, 0x8004442F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(TGT0, 0x8004443006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_or_for_chiplet(TGT0, 0x8008002006010C3F, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8008082006010C3F, 0xffffffffffff03ff, 0x400); + scom_and_for_chiplet(TGT0, 0x8008102006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_or_for_chiplet(TGT0, 0x8008302006010C3F, 0xffffffffffffe0ff, 0x1500); + scom_and_or_for_chiplet(TGT0, 0x8008402006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); + scom_and_or_for_chiplet(TGT0, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3FFF, 0x4000); + scom_and_or_for_chiplet(TGT0, 0x8008C02006010C3F, 0xFFFFFFFFFFFFFEFF, 0xF8); + scom_and_or_for_chiplet(TGT0, 0x8008D02006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); + scom_or_for_chiplet(TGT0, 0x8009702006010C3F, 0x8000); + scom_and_or_for_chiplet(TGT0, 0x8009802006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) + scom_or_for_chiplet(TGT0, 0x8009902006010C3F, 0x8060); + else + scom_or_for_chiplet(TGT0, 0x8009902006010C3F, 0x60); + scom_and_or_for_chiplet(TGT0, 0x8009982006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); + scom_and_or_for_chiplet(TGT0, 0x8009A02006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); + scom_and_or_for_chiplet(TGT0, 0x8009B02006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); + scom_and_or_for_chiplet(TGT0, 0x8009B82006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); + scom_and_or_for_chiplet(TGT0, 0x8009C82006010C3F, 0xFFFFFFFFFFFF0018, 0x1EA5); + scom_and_or_for_chiplet(TGT0, 0x8009D02006010C3F, 0x7fffffffffff800, 0x3f5); + scom_and_for_chiplet(TGT0, 0x8009E02006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(TGT0, 0x8009E82006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(TGT0, 0x800A802006010C3F, 0x2080); + scom_and_or_for_chiplet(TGT0, 0x800AE82006010C3F, 0xFFFFFFFFFFFFFF3F, 0x80); + scom_and_or_for_chiplet(TGT0, 0x800AF82006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); + scom_and_for_chiplet(TGT0, 0x800B802006010C3F, 0xFFFFFFFFFFFFFFF7); + scom_and_for_chiplet(TGT0, 0x800C042006010C3F, 0xFFFFFFFFFFFFFF3F); + scom_and_or_for_chiplet(TGT0, 0x800C0C2006010C3F, 0xFFFFFFFFFFFF03FF, 0x400); + scom_and_or_for_chiplet(TGT0, 0x800C142006010C3F, 0xFFFFFFFFFFFF783F, 0x50); + scom_and_or_for_chiplet(TGT0, 0x800C1C2006010C3F, 0xFFFFFFFFFFFFFF01, 0xF22); + scom_and_for_chiplet(TGT0, 0x800C242006010C3F, 0xFFFFFFFFFFFF3FFF); + scom_and_or_for_chiplet(TGT0, 0x800C842006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_and_or_for_chiplet(TGT0, 0x800C8C2006010C3F, 0xfffffffffffffe0f, 0x150); + scom_and_for_chiplet(TGT0, 0x800CEC2006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(TGT0, 0x800CF42006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(TGT0, 0x800D2C2006010C3F, 0x10); + scom_and_or_for_chiplet(TGT0, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); } void istep_8_10(void) { printk(BIOS_EMERG, "starting istep 8.10\n"); - read_scom(0x8000C8000701103Full); + read_scom_for_chiplet(TGT0, 0x8000C8000701103Full); printk(BIOS_EMERG, "ending istep 8.10\n"); return; } - -// fapi2::ReturnCode set_rx_master_mode( -// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_target, -// const fapi2::Target< fapi2::TARGET_TYPE_XBUS >& i_ctarget ) -// { -// uint8_t l_primary_group_id = 0; -// uint8_t l_primary_chip_id = 0; -// uint32_t l_primary_id = 0; -// uint8_t l_primary_attr = 0; -// uint8_t l_connected_group_id = 0; -// uint8_t l_connected_chip_id = 0; -// uint32_t l_connected_id = 0; -// uint8_t l_connected_attr = 0; - -// p9_get_proc_fabric_group_id(i_target, l_primary_group_id); -// p9_get_proc_fabric_group_id(i_ctarget, l_connected_group_id); - -// p9_get_proc_fabric_chip_id(i_target, l_primary_chip_id); -// p9_get_proc_fabric_chip_id(i_ctarget, l_connected_chip_id); - -// l_primary_id = ((uint32_t)l_primary_group_id << 8) + (uint32_t)l_primary_chip_id; -// l_connected_id = ((uint32_t)l_connected_group_id << 8) + (uint32_t)l_connected_chip_id; - -// if(l_primary_id < l_connected_id) { -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; -// } -// else { -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_target] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_FALSE; -// fapi2::ATTR_IO_XBUS_MASTER_MODE[i_ctarget] = fapi2::ENUM_ATTR_IO_XBUS_MASTER_MODE_TRUE; -// } -// } - -// fapi2::ReturnCode p9_get_proc_fabric_group_id( -// const fapi2::Target& i_target, uint8_t& o_group_id) -// { -// fapi2::Target l_proc = i_target.getParent(); -// // Retrieve node attribute -// o_group_id = fapi2::ATTR_PROC_FABRIC_GROUP_ID[l_proc]; -// } - -// fapi2::ReturnCode p9_get_proc_fabric_chip_id( -// const fapi2::Target& i_target, uint8_t& o_chip_id) -// { -// fapi2::Target l_proc = i_target.getParent(); -// // Retrieve pos ID attribute -// o_chip_id = fapi2::ATTR_PROC_FABRIC_CHIP_ID[l_proc]; -// } diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c index 8e12de40245..b9fda2f1d0a 100644 --- a/src/soc/ibm/power9/istep_8_9.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -1,5 +1,5 @@ #include -#include +#include #include #include @@ -53,7 +53,6 @@ void p9_fbc_no_hp_scom(void) { uint64_t is_flat_8 = false; - // REGISTERS read uint64_t pb_com_pb_west_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG); uint64_t pb_com_pb_cent_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG); uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG); @@ -154,7 +153,6 @@ void p9_fbc_no_hp_scom(void) pb_com_pb_east_mode &= 0xFFFFFFFC0FFFFFFF; pb_com_pb_east_mode |= 0x00000002a0000000; - // REGISTERS write write_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG, pb_com_pb_west_mode); write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG, pb_com_pb_cent_mode); write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_gp_cmd_rate_dp0); @@ -313,7 +311,6 @@ void p9_fbc_ioe_tl_scom(void) pb_ioe_scom_pb_misc_cfg &= 0xDFFFFFFFFFFFFFFF; } - // REGISTERS write write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG_REG, pb_ioe_scom_pb_trace_cfg); write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG_REG, pb_ioe_scom_pb_misc_cfg); write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG_REG, pb_ioe_scom_pb_elink_data_01_cfg_reg); From a965f572682c5127e47c13e1307900217e42261e Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 18 Feb 2021 12:55:30 +0100 Subject: [PATCH 73/90] cpu/power9: fix directory structure and timer build fault Signed-off-by: Krystian Hebel --- src/cpu/Makefile.inc | 2 +- src/cpu/{power => }/power9/Kconfig | 1 - src/cpu/{power => }/power9/Makefile.inc | 0 src/cpu/{power => }/power9/power9.c | 0 src/cpu/{power => }/power9/scom.c | 0 src/mainboard/raptor-cs/talos-2/Kconfig | 1 + src/mainboard/raptor-cs/talos-2/devicetree.cb | 2 +- src/soc/ibm/power9/Makefile.inc | 4 ++-- 8 files changed, 5 insertions(+), 5 deletions(-) rename src/cpu/{power => }/power9/Kconfig (86%) rename src/cpu/{power => }/power9/Makefile.inc (100%) rename src/cpu/{power => }/power9/power9.c (100%) rename src/cpu/{power => }/power9/scom.c (100%) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 3a61b3eeb9d..93d2d27e01e 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -7,7 +7,7 @@ subdirs-y += intel subdirs-y += ti subdirs-$(CONFIG_ARCH_X86) += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 -subdirs-$(CONFIG_CPU_POWER9) += power/power9 +subdirs-$(CONFIG_CPU_POWER9) += power9 $(eval $(call create_class_compiler,cpu_microcode,x86_32)) ################################################################################ diff --git a/src/cpu/power/power9/Kconfig b/src/cpu/power9/Kconfig similarity index 86% rename from src/cpu/power/power9/Kconfig rename to src/cpu/power9/Kconfig index 6eaa5027c9f..c3a628cc343 100644 --- a/src/cpu/power/power9/Kconfig +++ b/src/cpu/power9/Kconfig @@ -6,4 +6,3 @@ config CPU_POWER9 select ARCH_VERSTAGE_PPC64 select ARCH_ROMSTAGE_PPC64 select ARCH_RAMSTAGE_PPC64 - select NO_MONOTONIC_TIMER diff --git a/src/cpu/power/power9/Makefile.inc b/src/cpu/power9/Makefile.inc similarity index 100% rename from src/cpu/power/power9/Makefile.inc rename to src/cpu/power9/Makefile.inc diff --git a/src/cpu/power/power9/power9.c b/src/cpu/power9/power9.c similarity index 100% rename from src/cpu/power/power9/power9.c rename to src/cpu/power9/power9.c diff --git a/src/cpu/power/power9/scom.c b/src/cpu/power9/scom.c similarity index 100% rename from src/cpu/power/power9/scom.c rename to src/cpu/power9/scom.c diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig index e827bf964f5..b399f8403ca 100644 --- a/src/mainboard/raptor-cs/talos-2/Kconfig +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -5,6 +5,7 @@ if BOARD_RAPTOR_CS_TALOS_2 config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_POWER9 + select CPU_IBM_POWER9 select BOARD_ROMSIZE_KB_16384 select ARCH_BOOTBLOCK_PPC64 select ARCH_VERSTAGE_PPC64 diff --git a/src/mainboard/raptor-cs/talos-2/devicetree.cb b/src/mainboard/raptor-cs/talos-2/devicetree.cb index 1a090890d58..7ea6247070e 100644 --- a/src/mainboard/raptor-cs/talos-2/devicetree.cb +++ b/src/mainboard/raptor-cs/talos-2/devicetree.cb @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -chip cpu/power/power9 +chip cpu/power9 device cpu_cluster 0 on end end diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index 8bbf9e6f2ee..26f45c2cbb9 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -# ifeq ($(CPU_IBM_POWER9),y) +ifeq ($(CPU_IBM_POWER9),y) bootblock-y += bootblock.c postcar-y += exit_car.S @@ -12,4 +12,4 @@ romstage-y += ../../../cpu/power/power9/scom.c ramstage-y += chip.c ramstage-y += timer.c -# endif +endif From c28043c3126b9eec98f38656e58a0bc74a1ca00e Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Tue, 23 Feb 2021 13:38:17 +0100 Subject: [PATCH 74/90] src/include/cpu/power/istep_8_9.c: remove attributes found in hosboot config files --- src/include/cpu/power/istep_8_10.h | 14 +- src/include/cpu/power/istep_8_9.h | 29 +- src/include/cpu/power/scom_registers.h | 3 + src/mainboard/raptor-cs/talos-2/Makefile.inc | 2 + src/mainboard/raptor-cs/talos-2/romstage.c | 8 +- src/soc/ibm/power9/istep_8_10.c | 1034 +++++++++--------- src/soc/ibm/power9/istep_8_9.c | 121 +- src/soc/ibm/power9/romstage.c | 12 - 8 files changed, 553 insertions(+), 670 deletions(-) diff --git a/src/include/cpu/power/istep_8_10.h b/src/include/cpu/power/istep_8_10.h index 7cb72143911..e111ecae1bf 100644 --- a/src/include/cpu/power/istep_8_10.h +++ b/src/include/cpu/power/istep_8_10.h @@ -1,6 +1,12 @@ -// default value -#define l_TGT0_ATTR_IO_XBUS_MASTER_MODE (0) +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) +#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) +#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) void istep_8_10(void); -void p9_xbus_g0_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); -void p9_xbus_g1_scom(uint64_t TGT0, uint64_t TGT1, uint64_t TGT2); +void p9_io_xbus_scominit(const uint8_t); +void p9_xbus_g0_scom(chiplet_id_t); +void p9_xbus_g1_scom(chiplet_id_t); diff --git a/src/include/cpu/power/istep_8_9.h b/src/include/cpu/power/istep_8_9.h index 4c946df24bf..048604b0e07 100644 --- a/src/include/cpu/power/istep_8_9.h +++ b/src/include/cpu/power/istep_8_9.h @@ -1,27 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include +// not sure about them #define X0_ENABLED (true) #define X1_ENABLED (true) #define X2_ENABLED (true) + +// not sure about them #define X0_IS_PAIRED (true) #define X1_IS_PAIRED (true) #define X2_IS_PAIRED (true) -#define DD2X_PARTS (true) -#define OPTICS_IS_A_BUS (true) + +// set in c++ code please verify #define ATTR_PROC_FABRIC_A_LINKS_CNFG (0) +// set in c++ code please verify #define ATTR_PROC_FABRIC_X_LINKS_CNFG (0) -#define EPS_TYPE_LE (0x01), -#define EPS_TYPE_HE (0x02), -#define EPS_TYPE_HE_F8 (0x03) -// default value -#define ATTR_PROC_EPS_TABLE_TYPE (EPS_TYPE_LE) - -#define CHIP_IS_NODE (0x01) -#define CHIP_IS_GROUP (0x02) -// default value -#define ATTR_PROC_FABRIC_PUMP_MODE (CHIP_IS_NODE) - #define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) #define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) @@ -36,18 +31,16 @@ #define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) #define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) +// set in c++ code please verify #define BOTH (0x0) #define EVEN_ONLY (0x1) #define ODD_ONLY (0x2) #define NONE (0x3) -#define ATTR_LINK_TRAIN BOTH +// for sure can be NONE, but maybe should be smth else? +#define ATTR_LINK_TRAIN NONE // this is probably wrong #define PROC_CHIPLET (0x10) -#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) -#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) -#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) -#define XBUS_FIR_MASK_REG (0x06010C0) void istep_8_9(void); void p9_fbc_ioe_dl_scom(uint64_t TGT0); diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index 819e032e98b..ee9cf8999d4 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #define PB_WEST_MODE_CFG_REG (0x501180A) // Power Bus PB West Mode Configuration Register #define PB_CENT_SM0_PB_CENT_FIR_REG (0x5011C00) // Power Bus PB CENT FIR Register #define PB_CENT_MODE_CFG_REG (0x5011C0A) // Power Bus PB CENT Mode Register @@ -26,3 +28,4 @@ #define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) // Power Bus ELL SL ECC Threshold Register #define XBUS_FIR_ACTION0_REG (0x6010C06) #define XBUS_FIR_ACTION1_REG (0x6010C07) +#define XBUS_FIR_MASK_REG (0x6010C03) diff --git a/src/mainboard/raptor-cs/talos-2/Makefile.inc b/src/mainboard/raptor-cs/talos-2/Makefile.inc index 3e69e6226a4..299c73ec609 100644 --- a/src/mainboard/raptor-cs/talos-2/Makefile.inc +++ b/src/mainboard/raptor-cs/talos-2/Makefile.inc @@ -3,3 +3,5 @@ bootblock-y += bootblock.c romstage-y += cbmem.c romstage-y += romstage.c +romstage-y += ../../../soc/ibm/power9/istep_8_9.c +romstage-y += ../../../soc/ibm/power9/istep_8_10.c diff --git a/src/mainboard/raptor-cs/talos-2/romstage.c b/src/mainboard/raptor-cs/talos-2/romstage.c index 333aed5e245..47f77ee9b31 100644 --- a/src/mainboard/raptor-cs/talos-2/romstage.c +++ b/src/mainboard/raptor-cs/talos-2/romstage.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include +#include #include -void scom_init(void); - void main(void) { console_init(); - scom_init(); + istep_8_9(); + istep_8_10(); run_ramstage(); } diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 150ec71d9c1..4972ff33592 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include #include #include @@ -5,558 +7,534 @@ #include #include -void *call_proc_xbus_scominit(void *io_pArgs) -{ - EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; - EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections(l_XbusConnections, TYPE_XBUS, true); - for l_XbusConnection in l_XbusConnections: - { - p9_io_xbus_scominit(l_XbusConnection.first, l_XbusConnection.second, 0); - p9_io_xbus_scominit(l_XbusConnection.first, l_XbusConnection.second, 1); - } -} -void p9_io_xbus_scominit( - chiplet_id_t i_target, - chiplet_id_t i_connected_target, - const uint8_t group) +void p9_io_xbus_scominit(const uint8_t group) { - chiplet_id_t l_proc = i_target.getParent(); - const uint8_t LANE_00 = 0; - uint64_t l_scom_buffer; + // chiplet_id_t l_proc = XB_CHIPLET_ID.getParent(); + // uint64_t l_scom_buffer; - scom_or_for_chiplet(i_target, 0x8009F8000000003F, 0x800); - scom_or_for_chiplet(i_connected_target, 0x8009F8000000003F, 0x800); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009F8000000003F, 0x800); wait_us(50, false); - scom_or_for_chiplet(i_target, 0x800C9C000000003F, 0x8000); - scom_or_for_chiplet(i_connected_target, 0x800C9C000000003F, 0x8000); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800C9C000000003F, 0x8000); wait_us(50, false); if(0 == group) { - p9_xbus_g0_scom(i_target); - p9_xbus_g0_scom(i_connected_target); + p9_xbus_g0_scom(XB_CHIPLET_ID); } else if(1 == group) { - p9_xbus_g1_scom(i_target); - p9_xbus_g1_scom(i_connected_target); + p9_xbus_g1_scom(XB_CHIPLET_ID); } - if(!(read_scom_for_chiplet(l_proc, PB_CENT_SM0_PB_CENT_FIR_REG) & 0x4000000000000)) - { - write_scom_for_chiplet(i_target, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); - write_scom_for_chiplet(i_target, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); - write_scom_for_chiplet(i_target, XBUS_FIR_MASK_REG, XBUS_PHY_FIR_MASK); - } + // if(!(read_scom_for_chiplet(l_proc, PB_CENT_SM0_PB_CENT_FIR_REG) & 0x4000000000000)) + // { + // write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); + // write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); + // write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_MASK_REG, XBUS_PHY_FIR_MASK); + // } } -void p9_xbus_g0_scom(chiplet_id_t TGT0) +void p9_xbus_g0_scom(chiplet_id_t chiplet) { - scom_and_for_chiplet(TGT0, 0x8000000006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000206010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000306010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000406010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000506010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000606010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000706010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000806010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000906010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000A06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000B06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000C06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000D06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000E06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000000F06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000001006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000001106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(TGT0, 0x8000080006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080106010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080206010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080306010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080406010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080506010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080606010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080706010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080806010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080906010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080A06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080B06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080C06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080D06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080E06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000080F06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000081006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_or_for_chiplet(TGT0, 0x8000081106010C3F, 0x200); - scom_and_for_chiplet(TGT0, 0x8000280006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280206010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280306010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280406010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280506010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280606010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280706010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280806010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280906010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280A06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280B06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280C06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280D06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280E06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000280F06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000281006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000281106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_or_for_chiplet(TGT0, 0x8000300006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000300F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000301006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000301106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_for_chiplet(TGT0, 0x8000C00006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00206010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00306010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00406010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00506010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00606010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00706010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00806010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00906010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00A06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00B06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00C06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00D06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00E06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C00F06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C01006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C01106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8002200006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002200F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002201006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(TGT0, 0x8002201106010C3F, 0x8000); - scom_and_or_for_chiplet(TGT0, 0x8002C00006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8002C00106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(TGT0, 0x8002C00206010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); - scom_and_or_for_chiplet(TGT0, 0x8002C00306010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); - scom_and_or_for_chiplet(TGT0, 0x8002C00406010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); - scom_and_or_for_chiplet(TGT0, 0x8002C00506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(TGT0, 0x8002C00606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8002C00706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(TGT0, 0x8002C00806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8002C00906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(TGT0, 0x8002C00A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8002C00B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(TGT0, 0x8002C00C06010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); - scom_and_or_for_chiplet(TGT0, 0x8002C00D06010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); - scom_and_or_for_chiplet(TGT0, 0x8002C00E06010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); - scom_and_or_for_chiplet(TGT0, 0x8002C00F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(TGT0, 0x8002C01006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8002C80006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(TGT0, 0x8002C80106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_for_chiplet(TGT0, 0x8002C80206010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(TGT0, 0x8002C80306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_or_for_chiplet(TGT0, 0x8002C80406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C80506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C80606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C80706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C80806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(TGT0, 0x8002C80906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C80A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C80B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C80C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C80D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_for_chiplet(TGT0, 0x8002C80E06010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(TGT0, 0x8002C80F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_or_for_chiplet(TGT0, 0x8002C81006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_for_chiplet(TGT0, 0x8004040006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004040F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004041006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(TGT0, 0x80040C0006010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0106010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0206010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0306010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0406010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0506010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0606010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0706010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0806010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0906010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0A06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0B06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0C06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0D06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0E06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C0F06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C1006010C3F, 0x2); - scom_and_for_chiplet(TGT0, 0x80043C0006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(TGT0, 0x80043C0106010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(TGT0, 0x80043C0206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_or_for_chiplet(TGT0, 0x80043C0306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(TGT0, 0x80043C0406010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(TGT0, 0x80043C0506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(TGT0, 0x80043C0606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(TGT0, 0x80043C0706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_for_chiplet(TGT0, 0x80043C0806010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(TGT0, 0x80043C0906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_or_for_chiplet(TGT0, 0x80043C0A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(TGT0, 0x80043C0B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(TGT0, 0x80043C0C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(TGT0, 0x80043C0D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(TGT0, 0x80043C0E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_for_chiplet(TGT0, 0x80043C0F06010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(TGT0, 0x80043C1006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(TGT0, 0x8004440006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(TGT0, 0x8004440106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(TGT0, 0x8004440206010C3F, 0xFFFFFFFFFFFF01FF, 0xF600); - scom_and_or_for_chiplet(TGT0, 0x8004440306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004440406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004440506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); - scom_and_or_for_chiplet(TGT0, 0x8004440606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004440706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004440806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(TGT0, 0x8004440906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); - scom_and_or_for_chiplet(TGT0, 0x8004440A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004440B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004440C06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004440D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004440E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004440F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(TGT0, 0x8004441006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_or_for_chiplet(TGT0, 0x8008000006010C3F, 0x4000); - scom_and_for_chiplet(TGT0, 0x8008080006010C3F, 0xFFFFFFFFFFFF03FF); - scom_and_for_chiplet(TGT0, 0x8008100006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_or_for_chiplet(TGT0, 0x8008300006010C3F, 0xffffffffffffe0ff, 0x1500); - scom_and_or_for_chiplet(TGT0, 0x8008400006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); - scom_and_or_for_chiplet(TGT0, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3E07, 0x10F8); - scom_and_or_for_chiplet(TGT0, 0x8008D00006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); - scom_or_for_chiplet(TGT0, 0x8009700006010C3F, 0x8000); - scom_and_or_for_chiplet(TGT0, 0x8009800006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) - scom_or_for_chiplet(TGT0, 0x8009900006010C3F, 0x8060); - else - scom_or_for_chiplet(TGT0, 0x8009900006010C3F, 0x60); - scom_and_or_for_chiplet(TGT0, 0x8009980006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); - scom_and_or_for_chiplet(TGT0, 0x8009A00006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); - scom_and_or_for_chiplet(TGT0, 0x8009B00006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8009B80006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); - scom_and_or_for_chiplet(TGT0, 0x8009C80006010C3F, 0xffffffffffff0018, 0x1ea5); - scom_and_or_for_chiplet(TGT0, 0x8009D00006010C3F, 0xffffffffffff001f, 0x3fa0); - scom_and_for_chiplet(TGT0, 0x8009E00006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(TGT0, 0x8009E80006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(TGT0, 0x800A800006010C3F, 0x10000010000000); - scom_and_or_for_chiplet(TGT0, 0x800AE80006010C3F, 0xFFFFFFFFFFFFFF3F, 0x20); - scom_and_or_for_chiplet(TGT0, 0x800AF80006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); - scom_and_for_chiplet(TGT0, 0x800B800006010C3F, 0xFFFFFFFFFFFFFFF7); - scom_and_for_chiplet(TGT0, 0x800C040006010C3F, 0xFFFFFFFFFFFFFF3F); - scom_and_for_chiplet(TGT0, 0x800C0C0006010C3F, 0xFFFFFFFFFFFF03FF); - scom_and_or_for_chiplet(TGT0, 0x800C140006010C3F, 0xFFFFFFFFFFFF783F, 0x50); - scom_and_or_for_chiplet(TGT0, 0x800C1C0006010C3F, 0xFFFFFFFFFFFFFF01, 0x22); - scom_and_for_chiplet(TGT0, 0x800C240006010C3F, 0xFFFFFFFFFFFF3FFF); - scom_and_or_for_chiplet(TGT0, 0x800C840006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_and_or_for_chiplet(TGT0, 0x800C8C0006010C3F, 0xfffffffffffffe0f, 0x150); - scom_and_for_chiplet(TGT0, 0x800CEC0006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(TGT0, 0x800CF40006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(TGT0, 0x800D2C0006010C3F, 0x10); - scom_and_or_for_chiplet(TGT0, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); + scom_and_for_chiplet(chiplet, 0x8000000006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000206010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000306010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000406010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000506010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000606010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000706010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000806010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000906010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000A06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000B06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000C06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000D06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000E06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000000F06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000001006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000001106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(chiplet, 0x8000080006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080106010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080206010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080306010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080406010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080506010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080606010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080706010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080806010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080906010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080A06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080B06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080C06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080D06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080E06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000080F06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000081006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_or_for_chiplet(chiplet, 0x8000081106010C3F, 0x200); + scom_and_for_chiplet(chiplet, 0x8000280006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280206010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280306010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280406010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280506010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280606010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280706010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280806010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280906010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280A06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280B06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280C06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280D06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280E06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000280F06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000281006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000281106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_or_for_chiplet(chiplet, 0x8000300006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000300F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000301006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000301106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_for_chiplet(chiplet, 0x8000C00006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00206010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00306010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00406010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00506010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00606010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00706010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00806010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00906010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00A06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00B06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00C06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00D06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00E06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C00F06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C01006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C01106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8002200006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002200F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002201006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(chiplet, 0x8002201106010C3F, 0x8000); + scom_and_or_for_chiplet(chiplet, 0x8002C00006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8002C00106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(chiplet, 0x8002C00206010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); + scom_and_or_for_chiplet(chiplet, 0x8002C00306010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); + scom_and_or_for_chiplet(chiplet, 0x8002C00406010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); + scom_and_or_for_chiplet(chiplet, 0x8002C00506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(chiplet, 0x8002C00606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8002C00706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(chiplet, 0x8002C00806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8002C00906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(chiplet, 0x8002C00A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8002C00B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(chiplet, 0x8002C00C06010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); + scom_and_or_for_chiplet(chiplet, 0x8002C00D06010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); + scom_and_or_for_chiplet(chiplet, 0x8002C00E06010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); + scom_and_or_for_chiplet(chiplet, 0x8002C00F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(chiplet, 0x8002C01006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8002C80006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(chiplet, 0x8002C80106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_for_chiplet(chiplet, 0x8002C80206010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(chiplet, 0x8002C80306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_or_for_chiplet(chiplet, 0x8002C80406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C80506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C80606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C80706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C80806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(chiplet, 0x8002C80906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C80A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C80B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C80C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C80D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_for_chiplet(chiplet, 0x8002C80E06010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(chiplet, 0x8002C80F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_or_for_chiplet(chiplet, 0x8002C81006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_for_chiplet(chiplet, 0x8004040006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004040F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004041006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(chiplet, 0x80040C0006010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0106010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0206010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0306010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0406010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0506010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0606010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0706010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0806010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0906010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0A06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0B06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0C06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0D06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0E06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C0F06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C1006010C3F, 0x2); + scom_and_for_chiplet(chiplet, 0x80043C0006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(chiplet, 0x80043C0106010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(chiplet, 0x80043C0206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_or_for_chiplet(chiplet, 0x80043C0306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(chiplet, 0x80043C0406010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(chiplet, 0x80043C0506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(chiplet, 0x80043C0606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(chiplet, 0x80043C0706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_for_chiplet(chiplet, 0x80043C0806010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(chiplet, 0x80043C0906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_or_for_chiplet(chiplet, 0x80043C0A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(chiplet, 0x80043C0B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(chiplet, 0x80043C0C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(chiplet, 0x80043C0D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(chiplet, 0x80043C0E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_for_chiplet(chiplet, 0x80043C0F06010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(chiplet, 0x80043C1006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(chiplet, 0x8004440006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(chiplet, 0x8004440106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(chiplet, 0x8004440206010C3F, 0xFFFFFFFFFFFF01FF, 0xF600); + scom_and_or_for_chiplet(chiplet, 0x8004440306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004440406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004440506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); + scom_and_or_for_chiplet(chiplet, 0x8004440606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004440706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004440806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(chiplet, 0x8004440906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); + scom_and_or_for_chiplet(chiplet, 0x8004440A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004440B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004440C06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004440D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004440E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004440F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(chiplet, 0x8004441006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_or_for_chiplet(chiplet, 0x8008000006010C3F, 0x4000); + scom_and_for_chiplet(chiplet, 0x8008080006010C3F, 0xFFFFFFFFFFFF03FF); + scom_and_for_chiplet(chiplet, 0x8008100006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_or_for_chiplet(chiplet, 0x8008300006010C3F, 0xffffffffffffe0ff, 0x1500); + scom_and_or_for_chiplet(chiplet, 0x8008400006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); + scom_and_or_for_chiplet(chiplet, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3E07, 0x10F8); + scom_and_or_for_chiplet(chiplet, 0x8008D00006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); + scom_or_for_chiplet(chiplet, 0x8009700006010C3F, 0x8000); + scom_and_or_for_chiplet(chiplet, 0x8009800006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_or_for_chiplet(chiplet, 0x8009900006010C3F, 0x60); + scom_and_or_for_chiplet(chiplet, 0x8009980006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); + scom_and_or_for_chiplet(chiplet, 0x8009A00006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); + scom_and_or_for_chiplet(chiplet, 0x8009B00006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8009B80006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); + scom_and_or_for_chiplet(chiplet, 0x8009C80006010C3F, 0xffffffffffff0018, 0x1ea5); + scom_and_or_for_chiplet(chiplet, 0x8009D00006010C3F, 0xffffffffffff001f, 0x3fa0); + scom_and_for_chiplet(chiplet, 0x8009E00006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(chiplet, 0x8009E80006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(chiplet, 0x800A800006010C3F, 0x10000010000000); + scom_and_or_for_chiplet(chiplet, 0x800AE80006010C3F, 0xFFFFFFFFFFFFFF3F, 0x20); + scom_and_or_for_chiplet(chiplet, 0x800AF80006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); + scom_and_for_chiplet(chiplet, 0x800B800006010C3F, 0xFFFFFFFFFFFFFFF7); + scom_and_for_chiplet(chiplet, 0x800C040006010C3F, 0xFFFFFFFFFFFFFF3F); + scom_and_for_chiplet(chiplet, 0x800C0C0006010C3F, 0xFFFFFFFFFFFF03FF); + scom_and_or_for_chiplet(chiplet, 0x800C140006010C3F, 0xFFFFFFFFFFFF783F, 0x50); + scom_and_or_for_chiplet(chiplet, 0x800C1C0006010C3F, 0xFFFFFFFFFFFFFF01, 0x22); + scom_and_for_chiplet(chiplet, 0x800C240006010C3F, 0xFFFFFFFFFFFF3FFF); + scom_and_or_for_chiplet(chiplet, 0x800C840006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_and_or_for_chiplet(chiplet, 0x800C8C0006010C3F, 0xfffffffffffffe0f, 0x150); + scom_and_for_chiplet(chiplet, 0x800CEC0006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(chiplet, 0x800CF40006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(chiplet, 0x800D2C0006010C3F, 0x10); + scom_and_or_for_chiplet(chiplet, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); } -void p9_xbus_g1_scom(chiplet_id_t TGT0) +void p9_xbus_g1_scom(chiplet_id_t chiplet) { - uint64_t l_scom_buffer; - scom_and_for_chiplet(TGT0, 0x8000002006010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002106010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002206010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002306010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002406010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002506010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002606010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002706010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002806010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002906010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002A06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002B06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002C06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002D06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002E06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000002F06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000003006010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000003106010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(TGT0, 0x8000082006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082106010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082206010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082306010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082406010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082506010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082606010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082706010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082806010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082906010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082A06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082B06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082C06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082D06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082E06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000082F06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(TGT0, 0x8000083006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_or_for_chiplet(TGT0, 0x8000083106010C3F, 0x200); - scom_and_for_chiplet(TGT0, 0x8000282006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282206010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282306010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282406010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282506010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282606010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282706010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282806010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282906010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282A06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282B06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282C06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282D06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282E06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000282F06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000283006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(TGT0, 0x8000283106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_or_for_chiplet(TGT0, 0x8000302006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000302F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000303006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(TGT0, 0x8000303106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_for_chiplet(TGT0, 0x8000C02006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02206010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02306010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02406010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02506010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02606010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02706010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02806010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02906010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02A06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02B06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02C06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02D06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02E06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C02F06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C03006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8000C03106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(TGT0, 0x8002202006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002202F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8002203006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(TGT0, 0x8002203106010C3F, 0x8000); - scom_and_or_for_chiplet(TGT0, 0x8002C02006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8002C02106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(TGT0, 0x8002C02206010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); - scom_and_or_for_chiplet(TGT0, 0x8002C02306010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); - scom_and_or_for_chiplet(TGT0, 0x8002C02406010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); - scom_and_or_for_chiplet(TGT0, 0x8002C02506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(TGT0, 0x8002C02606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8002C02706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(TGT0, 0x8002C02806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8002C02906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(TGT0, 0x8002C02A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8002C02B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(TGT0, 0x8002C02C06010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); - scom_and_or_for_chiplet(TGT0, 0x8002C02D06010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); - scom_and_or_for_chiplet(TGT0, 0x8002C02E06010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); - scom_and_or_for_chiplet(TGT0, 0x8002C02F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(TGT0, 0x8002C03006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8002C82006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(TGT0, 0x8002C82106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_for_chiplet(TGT0, 0x8002C82206010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(TGT0, 0x8002C82306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_or_for_chiplet(TGT0, 0x8002C82406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C82506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C82606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C82706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C82806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(TGT0, 0x8002C82906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C82A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(TGT0, 0x8002C82B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C82C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8002C82D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_for_chiplet(TGT0, 0x8002C82E06010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(TGT0, 0x8002C82F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_or_for_chiplet(TGT0, 0x8002C83006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_for_chiplet(TGT0, 0x8004042006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004042F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(TGT0, 0x8004043006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(TGT0, 0x80040C2006010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2106010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2206010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2306010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2406010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2506010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2606010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2706010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2806010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2906010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2A06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2B06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2C06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2D06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2E06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C2F06010C3F, 0x2); - scom_or_for_chiplet(TGT0, 0x80040C3006010C3F, 0x2); - scom_and_for_chiplet(TGT0, 0x80043C2006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(TGT0, 0x80043C2106010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(TGT0, 0x80043C2206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_or_for_chiplet(TGT0, 0x80043C2306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(TGT0, 0x80043C2406010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(TGT0, 0x80043C2506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(TGT0, 0x80043C2606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(TGT0, 0x80043C2706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_for_chiplet(TGT0, 0x80043C2806010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(TGT0, 0x80043C2906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_or_for_chiplet(TGT0, 0x80043C2A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(TGT0, 0x80043C2B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(TGT0, 0x80043C2C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(TGT0, 0x80043C2D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(TGT0, 0x80043C2E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_for_chiplet(TGT0, 0x80043C2F06010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(TGT0, 0x80043C3006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(TGT0, 0x8004442006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(TGT0, 0x8004442106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(TGT0, 0x8004442206010C3F, 0xFFFFFFFFFFFF0100, 0xF600); - scom_and_or_for_chiplet(TGT0, 0x8004442306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004442406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004442506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); - scom_and_or_for_chiplet(TGT0, 0x8004442606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004442706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004442806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(TGT0, 0x8004442906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); - scom_and_or_for_chiplet(TGT0, 0x8004442A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004442B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004442C06010C3F, 0xFFFFFFFFFFFF01FF, 0xbc00); - scom_and_or_for_chiplet(TGT0, 0x8004442D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(TGT0, 0x8004442E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(TGT0, 0x8004442F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(TGT0, 0x8004443006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_or_for_chiplet(TGT0, 0x8008002006010C3F, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8008082006010C3F, 0xffffffffffff03ff, 0x400); - scom_and_for_chiplet(TGT0, 0x8008102006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_or_for_chiplet(TGT0, 0x8008302006010C3F, 0xffffffffffffe0ff, 0x1500); - scom_and_or_for_chiplet(TGT0, 0x8008402006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); - scom_and_or_for_chiplet(TGT0, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3FFF, 0x4000); - scom_and_or_for_chiplet(TGT0, 0x8008C02006010C3F, 0xFFFFFFFFFFFFFEFF, 0xF8); - scom_and_or_for_chiplet(TGT0, 0x8008D02006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); - scom_or_for_chiplet(TGT0, 0x8009702006010C3F, 0x8000); - scom_and_or_for_chiplet(TGT0, 0x8009802006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - if(l_TGT0_ATTR_IO_XBUS_MASTER_MODE) - scom_or_for_chiplet(TGT0, 0x8009902006010C3F, 0x8060); - else - scom_or_for_chiplet(TGT0, 0x8009902006010C3F, 0x60); - scom_and_or_for_chiplet(TGT0, 0x8009982006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); - scom_and_or_for_chiplet(TGT0, 0x8009A02006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); - scom_and_or_for_chiplet(TGT0, 0x8009B02006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); - scom_and_or_for_chiplet(TGT0, 0x8009B82006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); - scom_and_or_for_chiplet(TGT0, 0x8009C82006010C3F, 0xFFFFFFFFFFFF0018, 0x1EA5); - scom_and_or_for_chiplet(TGT0, 0x8009D02006010C3F, 0x7fffffffffff800, 0x3f5); - scom_and_for_chiplet(TGT0, 0x8009E02006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(TGT0, 0x8009E82006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(TGT0, 0x800A802006010C3F, 0x2080); - scom_and_or_for_chiplet(TGT0, 0x800AE82006010C3F, 0xFFFFFFFFFFFFFF3F, 0x80); - scom_and_or_for_chiplet(TGT0, 0x800AF82006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); - scom_and_for_chiplet(TGT0, 0x800B802006010C3F, 0xFFFFFFFFFFFFFFF7); - scom_and_for_chiplet(TGT0, 0x800C042006010C3F, 0xFFFFFFFFFFFFFF3F); - scom_and_or_for_chiplet(TGT0, 0x800C0C2006010C3F, 0xFFFFFFFFFFFF03FF, 0x400); - scom_and_or_for_chiplet(TGT0, 0x800C142006010C3F, 0xFFFFFFFFFFFF783F, 0x50); - scom_and_or_for_chiplet(TGT0, 0x800C1C2006010C3F, 0xFFFFFFFFFFFFFF01, 0xF22); - scom_and_for_chiplet(TGT0, 0x800C242006010C3F, 0xFFFFFFFFFFFF3FFF); - scom_and_or_for_chiplet(TGT0, 0x800C842006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_and_or_for_chiplet(TGT0, 0x800C8C2006010C3F, 0xfffffffffffffe0f, 0x150); - scom_and_for_chiplet(TGT0, 0x800CEC2006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(TGT0, 0x800CF42006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(TGT0, 0x800D2C2006010C3F, 0x10); - scom_and_or_for_chiplet(TGT0, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); + scom_and_for_chiplet(chiplet, 0x8000002006010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002106010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002206010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002306010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002406010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002506010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002606010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002706010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002806010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002906010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002A06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002B06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002C06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002D06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002E06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000002F06010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000003006010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000003106010C3F, 0xfffffffffffff8ff); + scom_and_for_chiplet(chiplet, 0x8000082006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082106010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082206010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082306010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082406010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082506010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082606010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082706010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082806010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082906010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082A06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082B06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082C06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082D06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082E06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000082F06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(chiplet, 0x8000083006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_or_for_chiplet(chiplet, 0x8000083106010C3F, 0x200); + scom_and_for_chiplet(chiplet, 0x8000282006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282206010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282306010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282406010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282506010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282606010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282706010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282806010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282906010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282A06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282B06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282C06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282D06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282E06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000282F06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000283006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(chiplet, 0x8000283106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_or_for_chiplet(chiplet, 0x8000302006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000302F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000303006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(chiplet, 0x8000303106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_for_chiplet(chiplet, 0x8000C02006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02206010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02306010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02406010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02506010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02606010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02706010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02806010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02906010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02A06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02B06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02C06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02D06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02E06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C02F06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C03006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8000C03106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(chiplet, 0x8002202006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002202F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8002203006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(chiplet, 0x8002203106010C3F, 0x8000); + scom_and_or_for_chiplet(chiplet, 0x8002C02006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8002C02106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(chiplet, 0x8002C02206010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); + scom_and_or_for_chiplet(chiplet, 0x8002C02306010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); + scom_and_or_for_chiplet(chiplet, 0x8002C02406010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); + scom_and_or_for_chiplet(chiplet, 0x8002C02506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(chiplet, 0x8002C02606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8002C02706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(chiplet, 0x8002C02806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8002C02906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(chiplet, 0x8002C02A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8002C02B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(chiplet, 0x8002C02C06010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); + scom_and_or_for_chiplet(chiplet, 0x8002C02D06010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); + scom_and_or_for_chiplet(chiplet, 0x8002C02E06010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); + scom_and_or_for_chiplet(chiplet, 0x8002C02F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(chiplet, 0x8002C03006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8002C82006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(chiplet, 0x8002C82106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_for_chiplet(chiplet, 0x8002C82206010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(chiplet, 0x8002C82306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_or_for_chiplet(chiplet, 0x8002C82406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C82506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C82606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C82706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C82806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(chiplet, 0x8002C82906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C82A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(chiplet, 0x8002C82B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C82C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8002C82D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_for_chiplet(chiplet, 0x8002C82E06010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(chiplet, 0x8002C82F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_or_for_chiplet(chiplet, 0x8002C83006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_for_chiplet(chiplet, 0x8004042006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004042F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(chiplet, 0x8004043006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(chiplet, 0x80040C2006010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2106010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2206010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2306010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2406010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2506010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2606010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2706010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2806010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2906010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2A06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2B06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2C06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2D06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2E06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C2F06010C3F, 0x2); + scom_or_for_chiplet(chiplet, 0x80040C3006010C3F, 0x2); + scom_and_for_chiplet(chiplet, 0x80043C2006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(chiplet, 0x80043C2106010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(chiplet, 0x80043C2206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_or_for_chiplet(chiplet, 0x80043C2306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(chiplet, 0x80043C2406010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(chiplet, 0x80043C2506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(chiplet, 0x80043C2606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(chiplet, 0x80043C2706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_for_chiplet(chiplet, 0x80043C2806010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(chiplet, 0x80043C2906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_or_for_chiplet(chiplet, 0x80043C2A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(chiplet, 0x80043C2B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(chiplet, 0x80043C2C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(chiplet, 0x80043C2D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(chiplet, 0x80043C2E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_for_chiplet(chiplet, 0x80043C2F06010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(chiplet, 0x80043C3006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(chiplet, 0x8004442006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(chiplet, 0x8004442106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(chiplet, 0x8004442206010C3F, 0xFFFFFFFFFFFF0100, 0xF600); + scom_and_or_for_chiplet(chiplet, 0x8004442306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004442406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004442506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); + scom_and_or_for_chiplet(chiplet, 0x8004442606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004442706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004442806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(chiplet, 0x8004442906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); + scom_and_or_for_chiplet(chiplet, 0x8004442A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004442B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004442C06010C3F, 0xFFFFFFFFFFFF01FF, 0xbc00); + scom_and_or_for_chiplet(chiplet, 0x8004442D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(chiplet, 0x8004442E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(chiplet, 0x8004442F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(chiplet, 0x8004443006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_or_for_chiplet(chiplet, 0x8008002006010C3F, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8008082006010C3F, 0xffffffffffff03ff, 0x400); + scom_and_for_chiplet(chiplet, 0x8008102006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_or_for_chiplet(chiplet, 0x8008302006010C3F, 0xffffffffffffe0ff, 0x1500); + scom_and_or_for_chiplet(chiplet, 0x8008402006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); + scom_and_or_for_chiplet(chiplet, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3FFF, 0x4000); + scom_and_or_for_chiplet(chiplet, 0x8008C02006010C3F, 0xFFFFFFFFFFFFFEFF, 0xF8); + scom_and_or_for_chiplet(chiplet, 0x8008D02006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); + scom_or_for_chiplet(chiplet, 0x8009702006010C3F, 0x8000); + scom_and_or_for_chiplet(chiplet, 0x8009802006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_or_for_chiplet(chiplet, 0x8009902006010C3F, 0x60); + scom_and_or_for_chiplet(chiplet, 0x8009982006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); + scom_and_or_for_chiplet(chiplet, 0x8009A02006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); + scom_and_or_for_chiplet(chiplet, 0x8009B02006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); + scom_and_or_for_chiplet(chiplet, 0x8009B82006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); + scom_and_or_for_chiplet(chiplet, 0x8009C82006010C3F, 0xFFFFFFFFFFFF0018, 0x1EA5); + scom_and_or_for_chiplet(chiplet, 0x8009D02006010C3F, 0x7fffffffffff800, 0x3f5); + scom_and_for_chiplet(chiplet, 0x8009E02006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(chiplet, 0x8009E82006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(chiplet, 0x800A802006010C3F, 0x2080); + scom_and_or_for_chiplet(chiplet, 0x800AE82006010C3F, 0xFFFFFFFFFFFFFF3F, 0x80); + scom_and_or_for_chiplet(chiplet, 0x800AF82006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); + scom_and_for_chiplet(chiplet, 0x800B802006010C3F, 0xFFFFFFFFFFFFFFF7); + scom_and_for_chiplet(chiplet, 0x800C042006010C3F, 0xFFFFFFFFFFFFFF3F); + scom_and_or_for_chiplet(chiplet, 0x800C0C2006010C3F, 0xFFFFFFFFFFFF03FF, 0x400); + scom_and_or_for_chiplet(chiplet, 0x800C142006010C3F, 0xFFFFFFFFFFFF783F, 0x50); + scom_and_or_for_chiplet(chiplet, 0x800C1C2006010C3F, 0xFFFFFFFFFFFFFF01, 0xF22); + scom_and_for_chiplet(chiplet, 0x800C242006010C3F, 0xFFFFFFFFFFFF3FFF); + scom_and_or_for_chiplet(chiplet, 0x800C842006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_and_or_for_chiplet(chiplet, 0x800C8C2006010C3F, 0xfffffffffffffe0f, 0x150); + scom_and_for_chiplet(chiplet, 0x800CEC2006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(chiplet, 0x800CF42006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(chiplet, 0x800D2C2006010C3F, 0x10); + scom_and_or_for_chiplet(chiplet, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); } void istep_8_10(void) { printk(BIOS_EMERG, "starting istep 8.10\n"); - read_scom_for_chiplet(TGT0, 0x8000C8000701103Full); + p9_io_xbus_scominit(0); + p9_io_xbus_scominit(1); printk(BIOS_EMERG, "ending istep 8.10\n"); return; } diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c index b9fda2f1d0a..885bfbf2ee8 100644 --- a/src/soc/ibm/power9/istep_8_9.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include #include #include @@ -51,8 +53,6 @@ void tl_fir(void) void p9_fbc_no_hp_scom(void) { - uint64_t is_flat_8 = false; - uint64_t pb_com_pb_west_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG); uint64_t pb_com_pb_cent_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG); uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG); @@ -63,61 +63,30 @@ void p9_fbc_no_hp_scom(void) uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1_REG); uint64_t pb_com_pb_east_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG_REG); - if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP - || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) - { - pb_com_pb_cent_gp_cmd_rate_dp0 = 0; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP - && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) - { - pb_com_pb_cent_gp_cmd_rate_dp0 = 0x030406171C243448; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0x040508191F283A50; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) - { - pb_com_pb_cent_gp_cmd_rate_dp0 = 0x0304062832405C80; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0x0405082F3B4C6D98; - } + pb_com_pb_cent_gp_cmd_rate_dp0 = 0; + pb_com_pb_cent_gp_cmd_rate_dp1 = 0; - if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0) + if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0) { pb_com_pb_cent_rgp_cmd_rate_dp0 = 0; pb_com_pb_cent_rgp_cmd_rate_dp1 = 0; pb_com_pb_cent_sp_cmd_rate_dp0 = 0; pb_com_pb_cent_sp_cmd_rate_dp1 = 0; } - else if (ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) + else if (ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) { pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406080A0C1218; pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508080A0C1218; pb_com_pb_cent_sp_cmd_rate_dp0 = 0x030406080A0C1218; pb_com_pb_cent_sp_cmd_rate_dp1 = 0x030406080A0C1218; } - else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 3) - || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG == 0)) + else if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 3) { pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304060D10141D28; pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405080D10141D28; pb_com_pb_cent_sp_cmd_rate_dp0 = 0x05070A0D10141D28; pb_com_pb_cent_sp_cmd_rate_dp1 = 0x05070A0D10141D28; } - else if ((ATTR_PROC_FABRIC_PUMP_MODE == CHIP_IS_GROUP && is_flat_8) - || (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3)) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406171C243448; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508191F283A50; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x080C12171C243448; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A0D14191F283A50; - } - else if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && ATTR_PROC_FABRIC_X_LINKS_CNFG > 2) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304062832405C80; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405082F3B4C6D98; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x08141F2832405C80; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x0A18252F3B4C6D98; - } if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0 && ATTR_PROC_FABRIC_A_LINKS_CNFG == 0) { @@ -127,24 +96,12 @@ void p9_fbc_no_hp_scom(void) { pb_com_pb_east_mode &= 0xF1FFFFFFFFFFFFFF; } - if (ATTR_PROC_FABRIC_PUMP_MODE != CHIP_IS_GROUP && is_flat_8) - { - pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_west_mode |= 0x00003E8000000000; - pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_cent_mode |= 0x00003E8000000000; - pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_east_mode |= 0x00003E8000000000; - } - else - { - pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_west_mode |= 0x0000FAFC00000000; - pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_cent_mode |= 0x00007EFC00000000; - pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_east_mode |= 0x000007EFC0000000; - } + pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_west_mode |= 0x0000FAFC00000000; + pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_cent_mode |= 0x00007EFC00000000; + pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; + pb_com_pb_east_mode |= 0x000007EFC0000000; pb_com_pb_west_mode &= 0xFFFFFFFC0FFFFFFF; pb_com_pb_west_mode |= 0x00000002a0000000; @@ -185,19 +142,7 @@ void p9_fbc_ioe_tl_scom(void) pb_ioe_scom_pb_fp01_cfg |= 0x84000000840; } - if(X0_ENABLED && DD2X_PARTS) - { - // not sure about this one - pb_ioe_scom_pb_fp01_cfg &= 0xF00FFFFFF00FFFFF; - pb_ioe_scom_pb_fp01_cfg |= 0x00D0000000D00000; - } - - if (X0_ENABLED && OPTICS_IS_A_BUS) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFFFFFF07FFFFFFFF; - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001000000000; - } - else if(X0_ENABLED) + if(X0_ENABLED) { pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001F00000000; } @@ -224,28 +169,12 @@ void p9_fbc_ioe_tl_scom(void) pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000; } - - if (X1_ENABLED && DD2X_PARTS) - { - // not sure about this one - pb_ioe_scom_pb_fp23_cfg &= 0xF00FFFFFF00FFFFF; - pb_ioe_scom_pb_fp23_cfg |= 0x00D0000000D00000; - } - if(X1_ENABLED) { pb_ioe_scom_pb_fp23_cfg &= 0xfff004bffff007bf; pb_ioe_scom_pb_fp23_cfg |= 0x0002010000020000; - if (OPTICS_IS_A_BUS) - { - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x0100000000000000; - } - else - { - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x01F0000000000000; - } + pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; + pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x01F0000000000000; pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0x808080FF808080FF; pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x403C3C00403C3C00; } @@ -264,26 +193,10 @@ void p9_fbc_ioe_tl_scom(void) pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; } - if (X2_ENABLED && DD2X_PARTS) - { - // not sure about this one - pb_ioe_scom_pb_fp45_cfg &= 0xF00FFFFFF00FFFFF; - pb_ioe_scom_pb_fp45_cfg |= 0x00D0000000D00000; - } - if(X2_ENABLED) { - if (OPTICS_IS_A_BUS) - { - pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0xFFFFFF07FFFFFFFF; - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x0000008000000000; - } - else - { - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x000000F800000000; - } pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0x808080FF808080FF; - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x403C3C00403C3C00; + pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x403C3CF8403C3C00; } if(X0_IS_PAIRED) diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c index 195b94d9873..2a5936f162b 100644 --- a/src/soc/ibm/power9/romstage.c +++ b/src/soc/ibm/power9/romstage.c @@ -1,20 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include -asmlinkage void scom_init(void); -asmlinkage void car_stage_entry(void); - -asmlinkage void scom_init(void) -{ - istep_8_9(); - istep_8_10(); - printk(BIOS_EMERG, "Hello from SoC/scom_init()!\n"); -} - - asmlinkage void car_stage_entry(void) { } From b94ea9ba40dbf4131c36fc2de8b59be0d76b2114 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Tue, 23 Feb 2021 14:50:52 +0100 Subject: [PATCH 75/90] scom_registers.h, step_8_10.c: fix formatting --- src/include/cpu/power/scom_registers.h | 2 +- src/soc/ibm/power9/istep_8_10.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index ee9cf8999d4..d6d048a2e1a 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -26,6 +26,6 @@ #define PB_ELL_CFG_REG (0x601180A) // Power Bus ELL Configuration Register #define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) // Power Bus ELL Replay Threshold Register #define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) // Power Bus ELL SL ECC Threshold Register +#define XBUS_FIR_MASK_REG (0x6010C03) #define XBUS_FIR_ACTION0_REG (0x6010C06) #define XBUS_FIR_ACTION1_REG (0x6010C07) -#define XBUS_FIR_MASK_REG (0x6010C03) diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 4972ff33592..a5f12fc4297 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -535,6 +535,6 @@ void istep_8_10(void) printk(BIOS_EMERG, "starting istep 8.10\n"); p9_io_xbus_scominit(0); p9_io_xbus_scominit(1); - printk(BIOS_EMERG, "ending istep 8.10\n"); + printk(BIOS_EMERG, "ending istep 8.10\n"); return; } From dfb7d062054f86d5310c74ce57f7d9b910cddad5 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Wed, 24 Feb 2021 14:00:55 +0100 Subject: [PATCH 76/90] src/include/cpu/power/istep_8_9.c: remove attributes with values set in hostboot cpp code --- src/include/cpu/power/istep_8_10.h | 4 +- src/include/cpu/power/istep_8_9.h | 39 +- src/include/cpu/power/scom_registers.h | 59 +- src/soc/ibm/power9/istep_8_10.c | 1015 ++++++++++++------------ src/soc/ibm/power9/istep_8_9.c | 255 ++---- 5 files changed, 589 insertions(+), 783 deletions(-) diff --git a/src/include/cpu/power/istep_8_10.h b/src/include/cpu/power/istep_8_10.h index e111ecae1bf..8319050ed15 100644 --- a/src/include/cpu/power/istep_8_10.h +++ b/src/include/cpu/power/istep_8_10.h @@ -8,5 +8,5 @@ void istep_8_10(void); void p9_io_xbus_scominit(const uint8_t); -void p9_xbus_g0_scom(chiplet_id_t); -void p9_xbus_g1_scom(chiplet_id_t); +void p9_xbus_g0_scom(void); +void p9_xbus_g1_scom(void); diff --git a/src/include/cpu/power/istep_8_9.h b/src/include/cpu/power/istep_8_9.h index 048604b0e07..6d57392e53e 100644 --- a/src/include/cpu/power/istep_8_9.h +++ b/src/include/cpu/power/istep_8_9.h @@ -2,48 +2,21 @@ #include -// not sure about them -#define X0_ENABLED (true) -#define X1_ENABLED (true) -#define X2_ENABLED (true) - -// not sure about them -#define X0_IS_PAIRED (true) -#define X1_IS_PAIRED (true) -#define X2_IS_PAIRED (true) - -// set in c++ code please verify -#define ATTR_PROC_FABRIC_A_LINKS_CNFG (0) -// set in c++ code please verify -#define ATTR_PROC_FABRIC_X_LINKS_CNFG (0) +#define ATTR_PROC_FABRIC_X_LINKS_CNFG (1) #define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) #define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) -#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) -#define P9_FBC_UTILS_MAX_ELECTRICAL_LINKS (3) +#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) #define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) -#define FBC_IOE_TL_FIR_MASK_X1_NF (0x0018030300000440ULL) -#define FBC_IOE_TL_FIR_MASK_X2_NF (0x000300C0C0000220ULL) -#define PU_PB_IOE_FIR_MASK_REG (0x5013403) #define FBC_IOE_DL_FIR_ACTION0 (0) #define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) -#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) - -// set in c++ code please verify -#define BOTH (0x0) -#define EVEN_ONLY (0x1) -#define ODD_ONLY (0x2) -#define NONE (0x3) -// for sure can be NONE, but maybe should be smth else? -#define ATTR_LINK_TRAIN NONE - -// this is probably wrong -#define PROC_CHIPLET (0x10) +#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) void istep_8_9(void); -void p9_fbc_ioe_dl_scom(uint64_t TGT0); +void p9_fbc_ioe_dl_scom(void); void p9_fbc_ioe_tl_scom(void); void p9_fbc_no_hp_scom(void); -void tl_fir(void); +void ioe_tl_fir(void); +void ioel_fir(void); diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index d6d048a2e1a..ab403617bdb 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -1,31 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define PB_WEST_MODE_CFG_REG (0x501180A) // Power Bus PB West Mode Configuration Register -#define PB_CENT_SM0_PB_CENT_FIR_REG (0x5011C00) // Power Bus PB CENT FIR Register -#define PB_CENT_MODE_CFG_REG (0x5011C0A) // Power Bus PB CENT Mode Register -#define PB_CENT_GP_COMMAND_RATE_DP0_REG (0x5011C26) // Power Bus PB CENT GP command RATE DP0 Register -#define PB_CENT_GP_COMMAND_RATE_DP1_REG (0x5011C27) // Power Bus PB CENT GP command RATE DP1 Register -#define PB_CENT_RGP_COMMAND_RATE_DP0_REG (0x5011C28) // Power Bus PB CENT RGP command RATE DP0 Register -#define PB_CENT_RGP_COMMAND_RATE_DP1_REG (0x5011C29) // Power Bus PB CENT RGP command RATE DP1 Register -#define PB_CENT_SP_COMMAND_RATE_DP0_REG (0x5011C2A) // Power Bus PB CENT SP command RATE DP0 Register -#define PB_CENT_SP_COMMAND_RATE_DP1_REG (0x5011C2B) // Power Bus PB CENT SP command RATE DP1 Register -#define PB_EAST_MODE_CFG_REG (0x501200A) // Power Bus PB East Mode Configuration Register -#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) -#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) -#define PB_ELE_PB_FRAMER_PARSER_01_CFG_REG (0x501340A) // Power bus Electrical Framer/Parser 01 Configuration Register -#define PB_ELE_PB_FRAMER_PARSER_23_CFG_REG (0x501340B) // Power Bus Electrical Framer/Parser 23 Configuration Register -#define PB_ELE_PB_FRAMER_PARSER_45_CFG_REG (0x501340C) // Power Bus Electrical Framer/Parser 45 Configuration Register -#define PB_ELE_PB_DATA_BUFF_01_CFG_REG (0x5013410) // Power Bus Electrical Link Data Buffer 01 Configuration Register -#define PB_ELE_PB_DATA_BUFF_23_CFG_REG (0x5013411) // Power Bus Electrical Link Data Buffer 23 Configuration Register -#define PB_ELE_PB_DATA_BUFF_45_CFG_REG (0x5013412) // Power Bus Electrical Link Data Buffer 45 Configuration Register -#define PB_ELE_MISC_CFG_REG (0x5013423) // Power Bus Electrical Miscellaneous Configuration Register -#define PB_ELE_LINK_TRACE_CFG_REG (0x5013424) // Power Bus Electrical Link Trace Configuration Register -#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) -#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) -#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) -#define PB_ELL_CFG_REG (0x601180A) // Power Bus ELL Configuration Register -#define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) // Power Bus ELL Replay Threshold Register -#define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) // Power Bus ELL SL ECC Threshold Register -#define XBUS_FIR_MASK_REG (0x6010C03) -#define XBUS_FIR_ACTION0_REG (0x6010C06) -#define XBUS_FIR_ACTION1_REG (0x6010C07) +#define PB_WEST_MODE_CFG_REG (0x501180A) // Power Bus PB West Mode Configuration Register +#define PB_CENT_SM0_PB_CENT_FIR_REG (0x5011C00) // Power Bus PB CENT FIR Register +#define PB_CENT_MODE_CFG_REG (0x5011C0A) // Power Bus PB CENT Mode Register +#define PB_CENT_GP_COMMAND_RATE_DP0_REG (0x5011C26) // Power Bus PB CENT GP command RATE DP0 Register +#define PB_CENT_GP_COMMAND_RATE_DP1_REG (0x5011C27) // Power Bus PB CENT GP command RATE DP1 Register +#define PB_CENT_RGP_COMMAND_RATE_DP0_REG (0x5011C28) // Power Bus PB CENT RGP command RATE DP0 Register +#define PB_CENT_RGP_COMMAND_RATE_DP1_REG (0x5011C29) // Power Bus PB CENT RGP command RATE DP1 Register +#define PB_CENT_SP_COMMAND_RATE_DP0_REG (0x5011C2A) // Power Bus PB CENT SP command RATE DP0 Register +#define PB_CENT_SP_COMMAND_RATE_DP1_REG (0x5011C2B) // Power Bus PB CENT SP command RATE DP1 Register +#define PB_EAST_MODE_CFG_REG (0x501200A) // Power Bus PB East Mode Configuration Register +#define PU_PB_IOE_FIR_MASK_REG (0x5013403) +#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) +#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) +#define PB_ELE_PB_FRAMER_PARSER_01_CFG_REG (0x501340A) // Power bus Electrical Framer/Parser 01 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_23_CFG_REG (0x501340B) // Power Bus Electrical Framer/Parser 23 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_45_CFG_REG (0x501340C) // Power Bus Electrical Framer/Parser 45 Configuration Register +#define PB_ELE_PB_DATA_BUFF_01_CFG_REG (0x5013410) // Power Bus Electrical Link Data Buffer 01 Configuration Register +#define PB_ELE_PB_DATA_BUFF_23_CFG_REG (0x5013411) // Power Bus Electrical Link Data Buffer 23 Configuration Register +#define PB_ELE_PB_DATA_BUFF_45_CFG_REG (0x5013412) // Power Bus Electrical Link Data Buffer 45 Configuration Register +#define PB_ELE_MISC_CFG_REG (0x5013423) // Power Bus Electrical Miscellaneous Configuration Register +#define PB_ELE_LINK_TRACE_CFG_REG (0x5013424) // Power Bus Electrical Link Trace Configuration Register +#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) +#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) +#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) +#define PB_ELL_CFG_REG (0x601180A) // Power Bus ELL Configuration Register +#define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) // Power Bus ELL Replay Threshold Register +#define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) // Power Bus ELL SL ECC Threshold Register +#define XBUS_FIR_MASK_REG (0x6010C03) +#define XBUS_FIR_ACTION0_REG (0x6010C06) +#define XBUS_FIR_ACTION1_REG (0x6010C07) diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index a5f12fc4297..328a77412a4 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -7,12 +7,18 @@ #include #include +void istep_8_10(void) +{ + printk(BIOS_EMERG, "starting istep 8.10\n"); + report_istep(8, 10); + // p9_io_xbus_scominit(0); + // p9_io_xbus_scominit(1); + printk(BIOS_EMERG, "ending istep 8.10\n"); + return; +} void p9_io_xbus_scominit(const uint8_t group) { - // chiplet_id_t l_proc = XB_CHIPLET_ID.getParent(); - // uint64_t l_scom_buffer; - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009F8000000003F, 0x800); wait_us(50, false); scom_or_for_chiplet(XB_CHIPLET_ID, 0x800C9C000000003F, 0x8000); @@ -20,521 +26,512 @@ void p9_io_xbus_scominit(const uint8_t group) if(0 == group) { - p9_xbus_g0_scom(XB_CHIPLET_ID); + p9_xbus_g0_scom(); } else if(1 == group) { - p9_xbus_g1_scom(XB_CHIPLET_ID); + p9_xbus_g1_scom(); } - // if(!(read_scom_for_chiplet(l_proc, PB_CENT_SM0_PB_CENT_FIR_REG) & 0x4000000000000)) - // { - // write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); - // write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); - // write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_MASK_REG, XBUS_PHY_FIR_MASK); - // } -} - -void p9_xbus_g0_scom(chiplet_id_t chiplet) -{ - scom_and_for_chiplet(chiplet, 0x8000000006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000206010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000306010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000406010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000506010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000606010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000706010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000806010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000906010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000A06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000B06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000C06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000D06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000E06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000000F06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000001006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000001106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(chiplet, 0x8000080006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080106010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080206010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080306010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080406010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080506010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080606010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080706010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080806010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080906010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080A06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080B06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080C06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080D06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080E06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000080F06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000081006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_or_for_chiplet(chiplet, 0x8000081106010C3F, 0x200); - scom_and_for_chiplet(chiplet, 0x8000280006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280206010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280306010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280406010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280506010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280606010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280706010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280806010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280906010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280A06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280B06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280C06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280D06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280E06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000280F06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000281006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000281106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_or_for_chiplet(chiplet, 0x8000300006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000300F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000301006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000301106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_for_chiplet(chiplet, 0x8000C00006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00206010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00306010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00406010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00506010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00606010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00706010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00806010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00906010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00A06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00B06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00C06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00D06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00E06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C00F06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C01006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C01106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8002200006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002200F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002201006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(chiplet, 0x8002201106010C3F, 0x8000); - scom_and_or_for_chiplet(chiplet, 0x8002C00006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8002C00106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(chiplet, 0x8002C00206010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); - scom_and_or_for_chiplet(chiplet, 0x8002C00306010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); - scom_and_or_for_chiplet(chiplet, 0x8002C00406010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); - scom_and_or_for_chiplet(chiplet, 0x8002C00506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(chiplet, 0x8002C00606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8002C00706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(chiplet, 0x8002C00806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8002C00906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(chiplet, 0x8002C00A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8002C00B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(chiplet, 0x8002C00C06010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); - scom_and_or_for_chiplet(chiplet, 0x8002C00D06010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); - scom_and_or_for_chiplet(chiplet, 0x8002C00E06010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); - scom_and_or_for_chiplet(chiplet, 0x8002C00F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(chiplet, 0x8002C01006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8002C80006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(chiplet, 0x8002C80106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_for_chiplet(chiplet, 0x8002C80206010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(chiplet, 0x8002C80306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_or_for_chiplet(chiplet, 0x8002C80406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C80506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C80606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C80706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C80806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(chiplet, 0x8002C80906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C80A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C80B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C80C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C80D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_for_chiplet(chiplet, 0x8002C80E06010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(chiplet, 0x8002C80F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_or_for_chiplet(chiplet, 0x8002C81006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_for_chiplet(chiplet, 0x8004040006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004040F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004041006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(chiplet, 0x80040C0006010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0106010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0206010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0306010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0406010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0506010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0606010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0706010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0806010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0906010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0A06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0B06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0C06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0D06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0E06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C0F06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C1006010C3F, 0x2); - scom_and_for_chiplet(chiplet, 0x80043C0006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(chiplet, 0x80043C0106010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(chiplet, 0x80043C0206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_or_for_chiplet(chiplet, 0x80043C0306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(chiplet, 0x80043C0406010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(chiplet, 0x80043C0506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(chiplet, 0x80043C0606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(chiplet, 0x80043C0706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_for_chiplet(chiplet, 0x80043C0806010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(chiplet, 0x80043C0906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_or_for_chiplet(chiplet, 0x80043C0A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(chiplet, 0x80043C0B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(chiplet, 0x80043C0C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(chiplet, 0x80043C0D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(chiplet, 0x80043C0E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_for_chiplet(chiplet, 0x80043C0F06010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(chiplet, 0x80043C1006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(chiplet, 0x8004440006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(chiplet, 0x8004440106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(chiplet, 0x8004440206010C3F, 0xFFFFFFFFFFFF01FF, 0xF600); - scom_and_or_for_chiplet(chiplet, 0x8004440306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004440406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004440506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); - scom_and_or_for_chiplet(chiplet, 0x8004440606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004440706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004440806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(chiplet, 0x8004440906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); - scom_and_or_for_chiplet(chiplet, 0x8004440A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004440B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004440C06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004440D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004440E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004440F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(chiplet, 0x8004441006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_or_for_chiplet(chiplet, 0x8008000006010C3F, 0x4000); - scom_and_for_chiplet(chiplet, 0x8008080006010C3F, 0xFFFFFFFFFFFF03FF); - scom_and_for_chiplet(chiplet, 0x8008100006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_or_for_chiplet(chiplet, 0x8008300006010C3F, 0xffffffffffffe0ff, 0x1500); - scom_and_or_for_chiplet(chiplet, 0x8008400006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); - scom_and_or_for_chiplet(chiplet, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3E07, 0x10F8); - scom_and_or_for_chiplet(chiplet, 0x8008D00006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); - scom_or_for_chiplet(chiplet, 0x8009700006010C3F, 0x8000); - scom_and_or_for_chiplet(chiplet, 0x8009800006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_or_for_chiplet(chiplet, 0x8009900006010C3F, 0x60); - scom_and_or_for_chiplet(chiplet, 0x8009980006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); - scom_and_or_for_chiplet(chiplet, 0x8009A00006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); - scom_and_or_for_chiplet(chiplet, 0x8009B00006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8009B80006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); - scom_and_or_for_chiplet(chiplet, 0x8009C80006010C3F, 0xffffffffffff0018, 0x1ea5); - scom_and_or_for_chiplet(chiplet, 0x8009D00006010C3F, 0xffffffffffff001f, 0x3fa0); - scom_and_for_chiplet(chiplet, 0x8009E00006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(chiplet, 0x8009E80006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(chiplet, 0x800A800006010C3F, 0x10000010000000); - scom_and_or_for_chiplet(chiplet, 0x800AE80006010C3F, 0xFFFFFFFFFFFFFF3F, 0x20); - scom_and_or_for_chiplet(chiplet, 0x800AF80006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); - scom_and_for_chiplet(chiplet, 0x800B800006010C3F, 0xFFFFFFFFFFFFFFF7); - scom_and_for_chiplet(chiplet, 0x800C040006010C3F, 0xFFFFFFFFFFFFFF3F); - scom_and_for_chiplet(chiplet, 0x800C0C0006010C3F, 0xFFFFFFFFFFFF03FF); - scom_and_or_for_chiplet(chiplet, 0x800C140006010C3F, 0xFFFFFFFFFFFF783F, 0x50); - scom_and_or_for_chiplet(chiplet, 0x800C1C0006010C3F, 0xFFFFFFFFFFFFFF01, 0x22); - scom_and_for_chiplet(chiplet, 0x800C240006010C3F, 0xFFFFFFFFFFFF3FFF); - scom_and_or_for_chiplet(chiplet, 0x800C840006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_and_or_for_chiplet(chiplet, 0x800C8C0006010C3F, 0xfffffffffffffe0f, 0x150); - scom_and_for_chiplet(chiplet, 0x800CEC0006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(chiplet, 0x800CF40006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(chiplet, 0x800D2C0006010C3F, 0x10); - scom_and_or_for_chiplet(chiplet, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); + if(!(read_scom(PB_CENT_SM0_PB_CENT_FIR_REG) & 0x4000000000000)) + { + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_MASK_REG, XBUS_PHY_FIR_MASK); + } } -void p9_xbus_g1_scom(chiplet_id_t chiplet) +void p9_xbus_g0_scom() { - scom_and_for_chiplet(chiplet, 0x8000002006010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002106010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002206010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002306010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002406010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002506010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002606010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002706010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002806010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002906010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002A06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002B06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002C06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002D06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002E06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000002F06010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000003006010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000003106010C3F, 0xfffffffffffff8ff); - scom_and_for_chiplet(chiplet, 0x8000082006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082106010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082206010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082306010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082406010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082506010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082606010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082706010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082806010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082906010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082A06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082B06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082C06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082D06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082E06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000082F06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(chiplet, 0x8000083006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_or_for_chiplet(chiplet, 0x8000083106010C3F, 0x200); - scom_and_for_chiplet(chiplet, 0x8000282006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282206010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282306010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282406010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282506010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282606010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282706010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282806010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282906010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282A06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282B06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282C06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282D06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282E06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000282F06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000283006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(chiplet, 0x8000283106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_or_for_chiplet(chiplet, 0x8000302006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000302F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000303006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(chiplet, 0x8000303106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_for_chiplet(chiplet, 0x8000C02006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02206010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02306010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02406010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02506010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02606010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02706010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02806010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02906010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02A06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02B06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02C06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02D06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02E06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C02F06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C03006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8000C03106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(chiplet, 0x8002202006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002202F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8002203006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(chiplet, 0x8002203106010C3F, 0x8000); - scom_and_or_for_chiplet(chiplet, 0x8002C02006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8002C02106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(chiplet, 0x8002C02206010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); - scom_and_or_for_chiplet(chiplet, 0x8002C02306010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); - scom_and_or_for_chiplet(chiplet, 0x8002C02406010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); - scom_and_or_for_chiplet(chiplet, 0x8002C02506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(chiplet, 0x8002C02606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8002C02706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(chiplet, 0x8002C02806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8002C02906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(chiplet, 0x8002C02A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8002C02B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(chiplet, 0x8002C02C06010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); - scom_and_or_for_chiplet(chiplet, 0x8002C02D06010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); - scom_and_or_for_chiplet(chiplet, 0x8002C02E06010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); - scom_and_or_for_chiplet(chiplet, 0x8002C02F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(chiplet, 0x8002C03006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8002C82006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(chiplet, 0x8002C82106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_for_chiplet(chiplet, 0x8002C82206010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(chiplet, 0x8002C82306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_or_for_chiplet(chiplet, 0x8002C82406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C82506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C82606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C82706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C82806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(chiplet, 0x8002C82906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C82A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(chiplet, 0x8002C82B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C82C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8002C82D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_for_chiplet(chiplet, 0x8002C82E06010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(chiplet, 0x8002C82F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_or_for_chiplet(chiplet, 0x8002C83006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_for_chiplet(chiplet, 0x8004042006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004042F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(chiplet, 0x8004043006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(chiplet, 0x80040C2006010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2106010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2206010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2306010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2406010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2506010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2606010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2706010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2806010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2906010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2A06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2B06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2C06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2D06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2E06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C2F06010C3F, 0x2); - scom_or_for_chiplet(chiplet, 0x80040C3006010C3F, 0x2); - scom_and_for_chiplet(chiplet, 0x80043C2006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(chiplet, 0x80043C2106010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(chiplet, 0x80043C2206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_or_for_chiplet(chiplet, 0x80043C2306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(chiplet, 0x80043C2406010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(chiplet, 0x80043C2506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(chiplet, 0x80043C2606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(chiplet, 0x80043C2706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_for_chiplet(chiplet, 0x80043C2806010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(chiplet, 0x80043C2906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_or_for_chiplet(chiplet, 0x80043C2A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(chiplet, 0x80043C2B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(chiplet, 0x80043C2C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(chiplet, 0x80043C2D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(chiplet, 0x80043C2E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_for_chiplet(chiplet, 0x80043C2F06010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(chiplet, 0x80043C3006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(chiplet, 0x8004442006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(chiplet, 0x8004442106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(chiplet, 0x8004442206010C3F, 0xFFFFFFFFFFFF0100, 0xF600); - scom_and_or_for_chiplet(chiplet, 0x8004442306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004442406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004442506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); - scom_and_or_for_chiplet(chiplet, 0x8004442606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004442706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004442806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(chiplet, 0x8004442906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); - scom_and_or_for_chiplet(chiplet, 0x8004442A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004442B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004442C06010C3F, 0xFFFFFFFFFFFF01FF, 0xbc00); - scom_and_or_for_chiplet(chiplet, 0x8004442D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(chiplet, 0x8004442E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(chiplet, 0x8004442F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(chiplet, 0x8004443006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_or_for_chiplet(chiplet, 0x8008002006010C3F, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8008082006010C3F, 0xffffffffffff03ff, 0x400); - scom_and_for_chiplet(chiplet, 0x8008102006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_or_for_chiplet(chiplet, 0x8008302006010C3F, 0xffffffffffffe0ff, 0x1500); - scom_and_or_for_chiplet(chiplet, 0x8008402006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); - scom_and_or_for_chiplet(chiplet, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3FFF, 0x4000); - scom_and_or_for_chiplet(chiplet, 0x8008C02006010C3F, 0xFFFFFFFFFFFFFEFF, 0xF8); - scom_and_or_for_chiplet(chiplet, 0x8008D02006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); - scom_or_for_chiplet(chiplet, 0x8009702006010C3F, 0x8000); - scom_and_or_for_chiplet(chiplet, 0x8009802006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_or_for_chiplet(chiplet, 0x8009902006010C3F, 0x60); - scom_and_or_for_chiplet(chiplet, 0x8009982006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); - scom_and_or_for_chiplet(chiplet, 0x8009A02006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); - scom_and_or_for_chiplet(chiplet, 0x8009B02006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); - scom_and_or_for_chiplet(chiplet, 0x8009B82006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); - scom_and_or_for_chiplet(chiplet, 0x8009C82006010C3F, 0xFFFFFFFFFFFF0018, 0x1EA5); - scom_and_or_for_chiplet(chiplet, 0x8009D02006010C3F, 0x7fffffffffff800, 0x3f5); - scom_and_for_chiplet(chiplet, 0x8009E02006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(chiplet, 0x8009E82006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(chiplet, 0x800A802006010C3F, 0x2080); - scom_and_or_for_chiplet(chiplet, 0x800AE82006010C3F, 0xFFFFFFFFFFFFFF3F, 0x80); - scom_and_or_for_chiplet(chiplet, 0x800AF82006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); - scom_and_for_chiplet(chiplet, 0x800B802006010C3F, 0xFFFFFFFFFFFFFFF7); - scom_and_for_chiplet(chiplet, 0x800C042006010C3F, 0xFFFFFFFFFFFFFF3F); - scom_and_or_for_chiplet(chiplet, 0x800C0C2006010C3F, 0xFFFFFFFFFFFF03FF, 0x400); - scom_and_or_for_chiplet(chiplet, 0x800C142006010C3F, 0xFFFFFFFFFFFF783F, 0x50); - scom_and_or_for_chiplet(chiplet, 0x800C1C2006010C3F, 0xFFFFFFFFFFFFFF01, 0xF22); - scom_and_for_chiplet(chiplet, 0x800C242006010C3F, 0xFFFFFFFFFFFF3FFF); - scom_and_or_for_chiplet(chiplet, 0x800C842006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_and_or_for_chiplet(chiplet, 0x800C8C2006010C3F, 0xfffffffffffffe0f, 0x150); - scom_and_for_chiplet(chiplet, 0x800CEC2006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(chiplet, 0x800CF42006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(chiplet, 0x800D2C2006010C3F, 0x10); - scom_and_or_for_chiplet(chiplet, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000206010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000306010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000406010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000506010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000606010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000706010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000806010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000906010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000A06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000B06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000C06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000D06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000E06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000F06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080106010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080206010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080306010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080406010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080506010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080606010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080706010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080806010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080906010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080A06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080B06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080C06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080D06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080E06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080F06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000081006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, 0x200); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280206010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280306010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280406010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280506010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280606010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280706010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280806010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280906010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280A06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280B06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280C06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280D06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280E06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280F06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00206010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00306010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00406010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00506010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00606010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00706010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00806010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00906010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00A06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00B06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00C06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00D06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00E06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00F06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002201006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002201106010C3F, 0x8000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00206010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00306010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00406010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00C06010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00D06010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00E06010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C01006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80206010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80E06010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C81006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004041006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0006010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0106010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0206010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0306010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0406010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0506010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0606010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0706010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0806010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0906010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0A06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0B06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0C06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0D06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0E06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0F06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C1006010C3F, 0x2); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0106010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0406010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0806010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0F06010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C1006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440206010C3F, 0xFFFFFFFFFFFF01FF, 0xF600); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440C06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004441006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008000006010C3F, 0x4000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008080006010C3F, 0xFFFFFFFFFFFF03FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008100006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008300006010C3F, 0xffffffffffffe0ff, 0x1500); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008400006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3E07, 0x10F8); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D00006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009700006010C3F, 0x8000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009800006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009900006010C3F, 0x60); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009980006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A00006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B00006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B80006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C80006010C3F, 0xffffffffffff0018, 0x1ea5); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D00006010C3F, 0xffffffffffff001f, 0x3fa0); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E00006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E80006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A800006010C3F, 0x10000010000000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE80006010C3F, 0xFFFFFFFFFFFFFF3F, 0x20); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF80006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B800006010C3F, 0xFFFFFFFFFFFFFFF7); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C040006010C3F, 0xFFFFFFFFFFFFFF3F); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C0C0006010C3F, 0xFFFFFFFFFFFF03FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C140006010C3F, 0xFFFFFFFFFFFF783F, 0x50); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C0006010C3F, 0xFFFFFFFFFFFFFF01, 0x22); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C240006010C3F, 0xFFFFFFFFFFFF3FFF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C840006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C0006010C3F, 0xfffffffffffffe0f, 0x150); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC0006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF40006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C0006010C3F, 0x10); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); } -void istep_8_10(void) +void p9_xbus_g1_scom() { - printk(BIOS_EMERG, "starting istep 8.10\n"); - p9_io_xbus_scominit(0); - p9_io_xbus_scominit(1); - printk(BIOS_EMERG, "ending istep 8.10\n"); - return; + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002206010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002306010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002406010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002506010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002606010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002706010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002806010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002906010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002A06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002B06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002C06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002D06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002E06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002F06010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003006010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003106010C3F, 0xFFFFFFFFFFFFF8FF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082106010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082206010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082306010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082406010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082506010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082606010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082706010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082806010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082906010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082A06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082B06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082C06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082D06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082E06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082F06010C3F, 0xFFFFFFFFFFFFFDFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000083006010C3F, 0xFFFFFFFFFFFFFDFF); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000083106010C3F, 0x200); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282206010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282306010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282406010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282506010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282606010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282706010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282806010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282906010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282A06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282B06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282C06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282D06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282E06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282F06010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283006010C3F, 0xFFFFFFFFFFFF0003); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283106010C3F, 0xFFFFFFFFFFFF0003); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02206010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02306010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02406010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02506010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02606010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02706010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02806010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02906010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02A06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02B06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02C06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02D06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02E06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02F06010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03006010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03106010C3F, 0xFFFFFFFFFFFF0007); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002203006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002203106010C3F, 0x8000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02206010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02306010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02406010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02C06010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02D06010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02E06010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C03006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82206010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82E06010C3F, 0xFFFFFFFFFFFF01FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042106010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042206010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042306010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042406010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042506010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042606010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042706010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042806010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042906010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042A06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042B06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042C06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042D06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042E06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042F06010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004043006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2006010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2106010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2206010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2306010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2406010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2506010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2606010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2706010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2806010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2906010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2A06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2B06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2C06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2D06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2E06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2F06010C3F, 0x2); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C3006010C3F, 0x2); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2106010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2406010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2806010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2F06010C3F, 0xFFFFFFFFFFFF0000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C3006010C3F, 0xFFFFFFFFFFFF0000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442206010C3F, 0xFFFFFFFFFFFF0100, 0xF600); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442C06010C3F, 0xFFFFFFFFFFFF01FF, 0xbc00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004443006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008002006010C3F, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008082006010C3F, 0xffffffffffff03ff, 0x400); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008102006010C3F, 0xFFFFFFFFFFFF7FFF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008302006010C3F, 0xffffffffffffe0ff, 0x1500); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008402006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3FFF, 0x4000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C02006010C3F, 0xFFFFFFFFFFFFFEFF, 0xF8); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D02006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009702006010C3F, 0x8000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009802006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009902006010C3F, 0x60); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009982006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A02006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B02006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B82006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C82006010C3F, 0xFFFFFFFFFFFF0018, 0x1EA5); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D02006010C3F, 0x7fffffffffff800, 0x3f5); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E02006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E82006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A802006010C3F, 0x2080); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE82006010C3F, 0xFFFFFFFFFFFFFF3F, 0x80); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF82006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B802006010C3F, 0xFFFFFFFFFFFFFFF7); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C042006010C3F, 0xFFFFFFFFFFFFFF3F); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C0C2006010C3F, 0xFFFFFFFFFFFF03FF, 0x400); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C142006010C3F, 0xFFFFFFFFFFFF783F, 0x50); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C2006010C3F, 0xFFFFFFFFFFFFFF01, 0xF22); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C242006010C3F, 0xFFFFFFFFFFFF3FFF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C842006010C3F, 0xFFFFFFFFFFFF8080, 0x10); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C2006010C3F, 0xfffffffffffffe0f, 0x150); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC2006010C3F, 0xFFFFFFFFFFFF00FF); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF42006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C2006010C3F, 0x10); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); } diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c index 885bfbf2ee8..864286e5ad9 100644 --- a/src/soc/ibm/power9/istep_8_9.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -7,229 +7,64 @@ void istep_8_9(void) { - printk(BIOS_EMERG, "starting istep 8.9\n"); - p9_fbc_no_hp_scom(); + printk(BIOS_EMERG, "starting istep 8.9\n"); + report_istep(8, 9); + p9_fbc_no_hp_scom(); p9_fbc_ioe_tl_scom(); - - p9_fbc_ioe_dl_scom(XB_CHIPLET_ID); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); - write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); - printk(BIOS_EMERG, "ending istep 8.9\n"); + ioe_tl_fir(); + p9_fbc_ioe_dl_scom(); + ioel_fir(); + printk(BIOS_EMERG, "ending istep 8.9\n"); } -void p9_fbc_ioe_dl_scom(uint64_t TGT0) -{ - uint64_t pb_ioe_ll0_ioel_config = read_scom_for_chiplet(TGT0, PB_ELL_CFG_REG); - uint64_t pb_ioe_ll0_ioel_replay_threshold = read_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG); - uint64_t pb_ioe_ll0_ioel_sl_ecc_threshold = read_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG); - if (ATTR_LINK_TRAIN == BOTH) - { - pb_ioe_ll0_ioel_config |= 0x8000000000000000; - } - else - { - pb_ioe_ll0_ioel_config &= 0x7FFFFFFFFFFFFFFF; - } - pb_ioe_ll0_ioel_config &= 0xFFEFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_config |= 0x280F000F00000000; - pb_ioe_ll0_ioel_replay_threshold &= 0x0FFFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_replay_threshold |= 0x6FE0000000000000; - pb_ioe_ll0_ioel_sl_ecc_threshold &= 0x7FFFFFFFFFFFFFFF; - pb_ioe_ll0_ioel_sl_ecc_threshold |= 0x7F70000000000000; +void p9_fbc_ioe_dl_scom(void) +{ + scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_CFG_REG, 0x7FEFFFFFFFFFFFFF, 0x280F000F00000000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_REPLAY_TRESHOLD_REG, 0xFFFFFFFFFFFFFFF, 0x6FE0000000000000); + scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_SL_ECC_TRESHOLD_REG, 0x7FFFFFFFFFFFFFFF, 0x7F70000000000000); +} - write_scom_for_chiplet(TGT0, PB_ELL_CFG_REG, pb_ioe_ll0_ioel_config); - write_scom_for_chiplet(TGT0, PB_ELL_REPLAY_TRESHOLD_REG, pb_ioe_ll0_ioel_replay_threshold); - write_scom_for_chiplet(TGT0, PB_ELL_SL_ECC_TRESHOLD_REG, pb_ioe_ll0_ioel_sl_ecc_threshold); +void ioe_tl_fir(void) +{ + write_scom(PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); + write_scom(PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); + write_scom(PU_PB_IOE_FIR_MASK_REG, FBC_IOE_TL_FIR_MASK | FBC_IOE_TL_FIR_MASK_X0_NF); } -void tl_fir(void) +void ioel_fir(void) { - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); - // not sure about this one, maybe X1 or X2 mask? - write_scom_for_chiplet(PROC_CHIPLET, PU_PB_IOE_FIR_MASK_REG, FBC_IOE_TL_FIR_MASK | FBC_IOE_TL_FIR_MASK_X0_NF); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); + write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); } void p9_fbc_no_hp_scom(void) { - uint64_t pb_com_pb_west_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG); - uint64_t pb_com_pb_cent_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG); - uint64_t pb_com_pb_cent_gp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG); - uint64_t pb_com_pb_cent_gp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1_REG); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0_REG); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1_REG); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0_REG); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1_REG); - uint64_t pb_com_pb_east_mode = read_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG_REG); - - pb_com_pb_cent_gp_cmd_rate_dp0 = 0; - pb_com_pb_cent_gp_cmd_rate_dp1 = 0; - - if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0; - } - else if (ATTR_PROC_FABRIC_X_LINKS_CNFG > 0 && ATTR_PROC_FABRIC_X_LINKS_CNFG < 3) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x030406080A0C1218; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x040508080A0C1218; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x030406080A0C1218; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x030406080A0C1218; - } - else if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 3) - { - pb_com_pb_cent_rgp_cmd_rate_dp0 = 0x0304060D10141D28; - pb_com_pb_cent_rgp_cmd_rate_dp1 = 0x0405080D10141D28; - pb_com_pb_cent_sp_cmd_rate_dp0 = 0x05070A0D10141D28; - pb_com_pb_cent_sp_cmd_rate_dp1 = 0x05070A0D10141D28; - } - - if (ATTR_PROC_FABRIC_X_LINKS_CNFG == 0 && ATTR_PROC_FABRIC_A_LINKS_CNFG == 0) - { - pb_com_pb_east_mode |= 0x0300000000000000; - } - else - { - pb_com_pb_east_mode &= 0xF1FFFFFFFFFFFFFF; - } - pb_com_pb_west_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_west_mode |= 0x0000FAFC00000000; - pb_com_pb_cent_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_cent_mode |= 0x00007EFC00000000; - pb_com_pb_east_mode &= 0xFFFF0003FFFFFFFF; - pb_com_pb_east_mode |= 0x000007EFC0000000; - - pb_com_pb_west_mode &= 0xFFFFFFFC0FFFFFFF; - pb_com_pb_west_mode |= 0x00000002a0000000; - pb_com_pb_cent_mode &= 0xFFFFFFFC0FFFFFFF; - pb_com_pb_cent_mode |= 0x00000002a0000000; - pb_com_pb_east_mode &= 0xFFFFFFFC0FFFFFFF; - pb_com_pb_east_mode |= 0x00000002a0000000; - - write_scom_for_chiplet(PROC_CHIPLET, PB_WEST_MODE_CFG_REG, pb_com_pb_west_mode); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_MODE_CFG_REG, pb_com_pb_cent_mode); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_gp_cmd_rate_dp0); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_GP_COMMAND_RATE_DP1_REG, pb_com_pb_cent_gp_cmd_rate_dp1); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_rgp_cmd_rate_dp0); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_RGP_COMMAND_RATE_DP1_REG, pb_com_pb_cent_rgp_cmd_rate_dp1); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP0_REG, pb_com_pb_cent_sp_cmd_rate_dp0); - write_scom_for_chiplet(PROC_CHIPLET, PB_CENT_SP_COMMAND_RATE_DP1_REG, pb_com_pb_cent_sp_cmd_rate_dp1); - write_scom_for_chiplet(PROC_CHIPLET, PB_EAST_MODE_CFG_REG, pb_com_pb_east_mode); + uint64_t pb_com_pb_cent_mode = read_scom(PB_CENT_MODE_CFG_REG); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP0_REG); + uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP1_REG); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom(PB_CENT_SP_COMMAND_RATE_DP0_REG); + uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom(PB_CENT_SP_COMMAND_RATE_DP1_REG); + uint64_t pb_com_pb_east_mode = read_scom(PB_EAST_MODE_CFG_REG); + uint64_t pb_com_pb_west_mode = read_scom(PB_WEST_MODE_CFG_REG); + + scom_and_or(PB_WEST_MODE_CFG_REG, 0xFFFF00000FFFFFFF, 0xFAFEA0000000); + scom_and_or(PB_CENT_MODE_CFG_REG, 0xFFFF00000FFFFFFF, 0x7EFEA0000000); + write_scom(PB_CENT_GP_COMMAND_RATE_DP0_REG, 0); + write_scom(PB_CENT_GP_COMMAND_RATE_DP1_REG, 0); + write_scom(PB_CENT_RGP_COMMAND_RATE_DP0_REG, 0x30406080A0C1218); + write_scom(PB_CENT_RGP_COMMAND_RATE_DP1_REG, 0x40508080A0C1218); + write_scom(PB_CENT_SP_COMMAND_RATE_DP0_REG, 0x30406080A0C1218); + write_scom(PB_CENT_SP_COMMAND_RATE_DP1_REG, 0x30406080A0C1218); + scom_and_or(PB_EAST_MODE_CFG_REG, 0xF1FF00000FFFFFFF, 0x7EFE0000000); } void p9_fbc_ioe_tl_scom(void) { - uint64_t pb_ioe_scom_pb_elink_data_01_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG_REG); - uint64_t pb_ioe_scom_pb_elink_data_23_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG_REG); - uint64_t pb_ioe_scom_pb_elink_data_45_cfg_reg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG_REG); - uint64_t pb_ioe_scom_pb_fp01_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG_REG); - uint64_t pb_ioe_scom_pb_fp23_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG_REG); - uint64_t pb_ioe_scom_pb_fp45_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG_REG); - uint64_t pb_ioe_scom_pb_misc_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG_REG); - uint64_t pb_ioe_scom_pb_trace_cfg = read_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG_REG); - - if(X0_ENABLED) - { - pb_ioe_scom_pb_fp01_cfg &= 0xfff004fffff007bf; - pb_ioe_scom_pb_fp01_cfg |= 0x0002010000020000; - } - else - { - pb_ioe_scom_pb_fp01_cfg |= 0x84000000840; - } - - if(X0_ENABLED) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x0000001F00000000; - } - - if (X0_ENABLED) - { - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0x80FFFFFF80FFFFFF; - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x4000000040000000; - - pb_ioe_scom_pb_elink_data_01_cfg_reg &= 0xFF8080FFFF8080FF; - pb_ioe_scom_pb_elink_data_01_cfg_reg |= 0x003C3C00003C3C00; - - pb_ioe_scom_pb_trace_cfg &= 0x0000FFFFFFFFFFFF; - pb_ioe_scom_pb_trace_cfg |= 0x4141000000000000; - } - else if (X1_ENABLED) - { - pb_ioe_scom_pb_trace_cfg &= 0xFFFF0000FFFFFFFF; - pb_ioe_scom_pb_trace_cfg |= 0x0000414100000000; - } - else if (X2_ENABLED) - { - pb_ioe_scom_pb_trace_cfg &= 0xFFFFFFFF0000FFFF; - pb_ioe_scom_pb_trace_cfg |= 0x0000000041410000; - } - - if(X1_ENABLED) - { - pb_ioe_scom_pb_fp23_cfg &= 0xfff004bffff007bf; - pb_ioe_scom_pb_fp23_cfg |= 0x0002010000020000; - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0xFE0FFFFFFFFFFFFF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x01F0000000000000; - pb_ioe_scom_pb_elink_data_23_cfg_reg &= 0x808080FF808080FF; - pb_ioe_scom_pb_elink_data_23_cfg_reg |= 0x403C3C00403C3C00; - } - else - { - pb_ioe_scom_pb_fp23_cfg |= 0x0000084000000840; - } - - if(X2_ENABLED) - { - pb_ioe_scom_pb_fp45_cfg &= 0xfff004bffff007bf; - pb_ioe_scom_pb_fp45_cfg |= 0x0002010000020000; - } - else - { - pb_ioe_scom_pb_fp45_cfg |= 0x84000000840; - } - - if(X2_ENABLED) - { - pb_ioe_scom_pb_elink_data_45_cfg_reg &= 0x808080FF808080FF; - pb_ioe_scom_pb_elink_data_45_cfg_reg |= 0x403C3CF8403C3C00; - } - - if(X0_IS_PAIRED) - { - pb_ioe_scom_pb_misc_cfg |= 0x8000000000000000; - } - else - { - pb_ioe_scom_pb_misc_cfg &= 0x7FFFFFFFFFFFFFFF; - } - if(X1_IS_PAIRED) - { - pb_ioe_scom_pb_misc_cfg |= 0x4000000000000000; - } - else - { - pb_ioe_scom_pb_misc_cfg &= 0xBFFFFFFFFFFFFFFF; - } - if(X2_IS_PAIRED) - { - pb_ioe_scom_pb_misc_cfg |= 0x2000000000000000; - } - else - { - pb_ioe_scom_pb_misc_cfg &= 0xDFFFFFFFFFFFFFFF; - } - - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_LINK_TRACE_CFG_REG, pb_ioe_scom_pb_trace_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_MISC_CFG_REG, pb_ioe_scom_pb_misc_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_01_CFG_REG, pb_ioe_scom_pb_elink_data_01_cfg_reg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_23_CFG_REG, pb_ioe_scom_pb_elink_data_23_cfg_reg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_DATA_BUFF_45_CFG_REG, pb_ioe_scom_pb_elink_data_45_cfg_reg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_01_CFG_REG, pb_ioe_scom_pb_fp01_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_23_CFG_REG, pb_ioe_scom_pb_fp23_cfg); - write_scom_for_chiplet(PROC_CHIPLET, PB_ELE_PB_FRAMER_PARSER_45_CFG_REG, pb_ioe_scom_pb_fp45_cfg); + scom_and_or(PB_ELE_PB_FRAMER_PARSER_01_CFG_REG, 0xfff004fffff007bf, 0x2010000020000); + scom_and_or(PB_ELE_PB_DATA_BUFF_01_CFG_REG, 0x808080FF808080FF, 0x403C3C1F403C3C00); + scom_and_or(PB_ELE_LINK_TRACE_CFG_REG, 0xFFFFFFFFFFFF, 0x4141000000000000); + scom_or(PB_ELE_PB_FRAMER_PARSER_23_CFG_REG, 0x84000000840); + scom_or(PB_ELE_PB_FRAMER_PARSER_45_CFG_REG, 0x84000000840); + scom_and_or(PB_ELE_MISC_CFG_REG, 0x9FFFFFFFFFFFFFFF, 0x8000000000000000); } From 19ba2879f1f27c1413e14a3b302c1155a9989767 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 23 Feb 2021 16:59:39 +0100 Subject: [PATCH 77/90] include/cpu/power/scom.h: add RMW variants without a chiplet ID Signed-off-by: Krystian Hebel --- src/include/cpu/power/scom.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index d58467b8b06..fd1f41aacb7 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -134,6 +134,22 @@ static inline uint64_t read_scom(uint64_t addr) return read_scom_direct(addr); } +static inline void scom_and_or(uint64_t addr, uint64_t and, uint64_t or) +{ + uint64_t data = read_scom(addr); + write_scom(addr, (data & and) | or); +} + +static inline void scom_and(uint64_t addr, uint64_t and) +{ + scom_and_or(addr, and, 0); +} + +static inline void scom_or(uint64_t addr, uint64_t or) +{ + scom_and_or(addr, ~0, or); +} + static inline void write_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t data) { addr &= ~PPC_BITMASK(34,39); From 1c40160b043d137a10df5f4c4f0210f2bab06cd4 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Thu, 25 Feb 2021 17:06:17 +0100 Subject: [PATCH 78/90] cpu/power9/scom.c: reset SCOM after an error Signed-off-by: Krystian Hebel --- src/cpu/power9/scom.c | 15 +++++++++++ src/include/cpu/power/scom.h | 52 +++++++++++++++++++++++++++--------- src/include/cpu/power/spr.h | 6 +++++ 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/src/cpu/power9/scom.c b/src/cpu/power9/scom.c index 76269b5d3c0..f0052dc4dbf 100644 --- a/src/cpu/power9/scom.c +++ b/src/cpu/power9/scom.c @@ -157,3 +157,18 @@ uint64_t read_scom_indirect(uint64_t reg_address) return data & XSCOM_DATA_IND_DATA; } + +/* This function should be rarely called, don't make it inlined */ +void reset_scom_engine(void) +{ + /* + * With cross-CPU SCOM accesses, first register should be cleared on the + * executing CPU, the other two on target CPU. In that case it may be + * necessary to do the remote writes in assembly directly to skip checking + * HMER and possibly end in a loop. + */ + write_scom_direct(0x00090018, 0); + write_scom_direct(0x00090012, 0); + write_scom_direct(0x00090013, 0); + eieio(); +} diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index a839f84c619..9aa55958aa5 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -33,6 +33,7 @@ #ifndef __ASSEMBLER__ #include #include +#include // TODO: these are probably specific to POWER9 typedef enum @@ -85,26 +86,53 @@ typedef enum EC23_CHIPLET_ID = 0x37 ///< Core23 chiplet (Quad5, EX11, C1) } chiplet_id_t; +void reset_scom_engine(void); + static uint64_t read_scom_direct(uint64_t reg_address) { uint64_t val; - asm volatile( - "ldcix %0, %1, %2": - "=r"(val): - "b"(0x800603FC00000000), - "r"(reg_address << 3)); - eieio(); + uint64_t hmer; + do { + clear_hmer(); + eieio(); + asm volatile( + "ldcix %0, %1, %2": + "=r"(val): + "b"(0x800603FC00000000), + "r"(reg_address << 3)); + eieio(); + hmer = read_hmer(); + } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); + + if (hmer & SPR_HMER_XSCOM_STATUS) { + reset_scom_engine(); + /* + * All F's are returned in case of error, but code polls for a set bit + * after changes that can make such error appear (e.g. clock settings). + * Return 0 so caller won't have to test for all F's in that case. + */ + return 0; + } return val; } static void write_scom_direct(uint64_t reg_address, uint64_t data) { - asm volatile( - "stdcix %0, %1, %2":: - "r"(data), - "b"(0x800603FC00000000), - "r"(reg_address << 3)); - eieio(); + uint64_t hmer; + do { + clear_hmer(); + eieio(); + asm volatile( + "stdcix %0, %1, %2":: + "r"(data), + "b"(0x800603FC00000000), + "r"(reg_address << 3)); + eieio(); + hmer = read_hmer(); + } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); + + if (hmer & SPR_HMER_XSCOM_STATUS) + reset_scom_engine(); } /* diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h index 59c089d8ef9..b0f4e340397 100644 --- a/src/include/cpu/power/spr.h +++ b/src/include/cpu/power/spr.h @@ -19,6 +19,7 @@ #define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) #define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) #define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) +#define SPR_HMER_XSCOM_OCCUPIED PPC_BIT(23) #ifndef __ASSEMBLER__ #include @@ -30,6 +31,11 @@ static inline uint64_t read_hmer(void) return val; } +static inline void clear_hmer(void) +{ + asm volatile("mtspr %0, %1" :: "i"(SPR_HMER), "r"(0) : "memory"); +} + static inline uint64_t read_msr(void) { uint64_t val; From abd3717035007ad6de7a09fac999a104bfd73bfa Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 26 Feb 2021 12:28:39 +0100 Subject: [PATCH 79/90] cpu/power9/scom: fixes after review Signed-off-by: Krystian Hebel --- src/arch/ppc64/include/arch/io.h | 1 + src/cpu/power9/scom.c | 16 ++++++++++------ src/include/cpu/power/scom.h | 4 ++-- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 132a5ce353d..0462047a322 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -9,6 +9,7 @@ #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 #define LPCHC_IO_SPACE 0xD0010000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) +#define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x8006030000000000 /* Enforce In-order Execution of I/O */ static inline void eieio(void) diff --git a/src/cpu/power9/scom.c b/src/cpu/power9/scom.c index f0052dc4dbf..493d3193bac 100644 --- a/src/cpu/power9/scom.c +++ b/src/cpu/power9/scom.c @@ -4,13 +4,17 @@ #include // HMER #include -#define XSCOM_DATA_IND_READ PPC_BIT(0) +#define XSCOM_DATA_IND_READ PPC_BIT(0) #define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) -#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) -#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) #define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63) #define XSCOM_IND_MAX_RETRIES 10 +#define XSCOM_RCVED_STAT_REG 0x00090018 +#define XSCOM_LOG_REG 0x00090012 +#define XSCOM_ERR_REG 0x00090013 + /* * WARNING: * Indirect access uses the same approach as Hostboot, yet all our tests so far @@ -167,8 +171,8 @@ void reset_scom_engine(void) * necessary to do the remote writes in assembly directly to skip checking * HMER and possibly end in a loop. */ - write_scom_direct(0x00090018, 0); - write_scom_direct(0x00090012, 0); - write_scom_direct(0x00090013, 0); + write_scom_direct(XSCOM_RCVED_STAT_REG, 0); + write_scom_direct(XSCOM_LOG_REG, 0); + write_scom_direct(XSCOM_ERR_REG, 0); eieio(); } diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index 9aa55958aa5..df2100e6bc0 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -98,7 +98,7 @@ static uint64_t read_scom_direct(uint64_t reg_address) asm volatile( "ldcix %0, %1, %2": "=r"(val): - "b"(0x800603FC00000000), + "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), "r"(reg_address << 3)); eieio(); hmer = read_hmer(); @@ -125,7 +125,7 @@ static void write_scom_direct(uint64_t reg_address, uint64_t data) asm volatile( "stdcix %0, %1, %2":: "r"(data), - "b"(0x800603FC00000000), + "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), "r"(reg_address << 3)); eieio(); hmer = read_hmer(); From fc0a7b49f3d596ed14c186862beb6d2b69710db3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 26 Feb 2021 12:58:43 +0100 Subject: [PATCH 80/90] cpu/power9: fix tabulations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: Ic61ec002a70a90cf1f567487c32a32150083507a --- src/cpu/power9/scom.c | 18 +++++++++--------- src/include/cpu/power/spr.h | 32 ++++++++++++++++---------------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/cpu/power9/scom.c b/src/cpu/power9/scom.c index 493d3193bac..113d047d303 100644 --- a/src/cpu/power9/scom.c +++ b/src/cpu/power9/scom.c @@ -4,16 +4,16 @@ #include // HMER #include -#define XSCOM_DATA_IND_READ PPC_BIT(0) -#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) -#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) -#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) -#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63) -#define XSCOM_IND_MAX_RETRIES 10 +#define XSCOM_DATA_IND_READ PPC_BIT(0) +#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63) +#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63) +#define XSCOM_IND_MAX_RETRIES 10 -#define XSCOM_RCVED_STAT_REG 0x00090018 -#define XSCOM_LOG_REG 0x00090012 -#define XSCOM_ERR_REG 0x00090013 +#define XSCOM_RCVED_STAT_REG 0x00090018 +#define XSCOM_LOG_REG 0x00090012 +#define XSCOM_ERR_REG 0x00090013 /* * WARNING: diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h index b0f4e340397..97a3399e911 100644 --- a/src/include/cpu/power/spr.h +++ b/src/include/cpu/power/spr.h @@ -3,23 +3,23 @@ #include // PPC_BIT() -#define SPR_HMER 0x150 +#define SPR_HMER 0x150 /* Bits in HMER/HMEER */ -#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) -#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) -#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) -#define SPR_HMER_TFAC_ERROR PPC_BIT(4) -#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) -#define SPR_HMER_XSCOM_FAIL PPC_BIT(8) -#define SPR_HMER_XSCOM_DONE PPC_BIT(9) -#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) -#define SPR_HMER_WARN_RISE PPC_BIT(14) -#define SPR_HMER_WARN_FALL PPC_BIT(15) -#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) -#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) -#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) -#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) -#define SPR_HMER_XSCOM_OCCUPIED PPC_BIT(23) +#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) +#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) +#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) +#define SPR_HMER_TFAC_ERROR PPC_BIT(4) +#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) +#define SPR_HMER_XSCOM_FAIL PPC_BIT(8) +#define SPR_HMER_XSCOM_DONE PPC_BIT(9) +#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) +#define SPR_HMER_WARN_RISE PPC_BIT(14) +#define SPR_HMER_WARN_FALL PPC_BIT(15) +#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) +#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) +#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) +#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21,23) +#define SPR_HMER_XSCOM_OCCUPIED PPC_BIT(23) #ifndef __ASSEMBLER__ #include From 33ea2bac7ea2a0f4556a287d6d35cbad3f0154c0 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 1 Mar 2021 11:41:20 +0100 Subject: [PATCH 81/90] src/soc/ibm/power9: review fixes --- src/soc/ibm/power9/Makefile.inc | 1 - src/soc/ibm/power9/istep_8_9.c | 8 -------- src/soc/ibm/power9/romstage.c | 1 - 3 files changed, 10 deletions(-) diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index 26f45c2cbb9..eaabab43919 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -7,7 +7,6 @@ postcar-y += exit_car.S romstage-y += romstage.c romstage-y += istep_8_9.c romstage-y += istep_8_10.c -romstage-y += ../../../cpu/power/power9/scom.c ramstage-y += chip.c ramstage-y += timer.c diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c index 864286e5ad9..0f4c58dee81 100644 --- a/src/soc/ibm/power9/istep_8_9.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -40,14 +40,6 @@ void ioel_fir(void) void p9_fbc_no_hp_scom(void) { - uint64_t pb_com_pb_cent_mode = read_scom(PB_CENT_MODE_CFG_REG); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp0 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP0_REG); - uint64_t pb_com_pb_cent_rgp_cmd_rate_dp1 = read_scom(PB_CENT_RGP_COMMAND_RATE_DP1_REG); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp0 = read_scom(PB_CENT_SP_COMMAND_RATE_DP0_REG); - uint64_t pb_com_pb_cent_sp_cmd_rate_dp1 = read_scom(PB_CENT_SP_COMMAND_RATE_DP1_REG); - uint64_t pb_com_pb_east_mode = read_scom(PB_EAST_MODE_CFG_REG); - uint64_t pb_com_pb_west_mode = read_scom(PB_WEST_MODE_CFG_REG); - scom_and_or(PB_WEST_MODE_CFG_REG, 0xFFFF00000FFFFFFF, 0xFAFEA0000000); scom_and_or(PB_CENT_MODE_CFG_REG, 0xFFFF00000FFFFFFF, 0x7EFEA0000000); write_scom(PB_CENT_GP_COMMAND_RATE_DP0_REG, 0); diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c index 2a5936f162b..91074b20125 100644 --- a/src/soc/ibm/power9/romstage.c +++ b/src/soc/ibm/power9/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include asmlinkage void car_stage_entry(void) From 620ec8bc3c188a07f2d0f6c5c217dcd6a599a1de Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 1 Mar 2021 14:58:09 +0100 Subject: [PATCH 82/90] src/soc/ibm/power9/istep_8_10.c: Change mask values to PPC_BITMASK() and PPC_BIT() --- src/mainboard/raptor-cs/talos-2/Makefile.inc | 2 - src/soc/ibm/power9/istep_8_10.c | 981 ++++++++++--------- 2 files changed, 491 insertions(+), 492 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/Makefile.inc b/src/mainboard/raptor-cs/talos-2/Makefile.inc index 299c73ec609..3e69e6226a4 100644 --- a/src/mainboard/raptor-cs/talos-2/Makefile.inc +++ b/src/mainboard/raptor-cs/talos-2/Makefile.inc @@ -3,5 +3,3 @@ bootblock-y += bootblock.c romstage-y += cbmem.c romstage-y += romstage.c -romstage-y += ../../../soc/ibm/power9/istep_8_9.c -romstage-y += ../../../soc/ibm/power9/istep_8_10.c diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 328a77412a4..80d440eb9ad 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,9 +20,9 @@ void istep_8_10(void) void p9_io_xbus_scominit(const uint8_t group) { - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009F8000000003F, 0x800); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009F8000000003F, PPC_BIT(52)); wait_us(50, false); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800C9C000000003F, 0x8000); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800C9C000000003F, PPC_BIT(48)); wait_us(50, false); if(0 == group) @@ -33,7 +34,7 @@ void p9_io_xbus_scominit(const uint8_t group) p9_xbus_g1_scom(); } - if(!(read_scom(PB_CENT_SM0_PB_CENT_FIR_REG) & 0x4000000000000)) + if(!(read_scom(PB_CENT_SM0_PB_CENT_FIR_REG) & PPC_BIT(13))) { write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION0_REG, XBUS_PHY_FIR_ACTION0); write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_FIR_ACTION1_REG, XBUS_PHY_FIR_ACTION1); @@ -43,495 +44,495 @@ void p9_io_xbus_scominit(const uint8_t group) void p9_xbus_g0_scom() { - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000206010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000306010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000406010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000506010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000606010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000706010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000806010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000906010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000A06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000B06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000C06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000D06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000E06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000F06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080106010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080206010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080306010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080406010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080506010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080606010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080706010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080806010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080906010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080A06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080B06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080C06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080D06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080E06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080F06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000081006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, 0x200); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280206010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280306010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280406010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280506010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280606010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280706010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280806010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280906010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280A06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280B06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280C06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280D06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280E06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280F06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00206010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00306010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00406010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00506010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00606010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00706010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00806010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00906010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00A06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00B06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00C06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00D06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00E06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00F06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002201006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002201106010C3F, 0x8000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00206010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00306010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00406010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00C06010C3F, 0xFFFFFFFFFFFF0000, 0x3EF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00D06010C3F, 0xFFFFFFFFFFFF0000, 0x7C7); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00E06010C3F, 0xFFFFFFFFFFFF0000, 0x7BC); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C01006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80206010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80E06010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C81006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004041006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0006010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0106010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0206010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0306010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0406010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0506010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0606010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0706010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0806010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0906010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0A06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0B06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0C06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0D06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0E06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0F06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C1006010C3F, 0x2); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0106010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0406010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0806010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0F06010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C1006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440206010C3F, 0xFFFFFFFFFFFF01FF, 0xF600); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440C06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004441006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008000006010C3F, 0x4000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008080006010C3F, 0xFFFFFFFFFFFF03FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008100006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008300006010C3F, 0xffffffffffffe0ff, 0x1500); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008400006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3E07, 0x10F8); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D00006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009700006010C3F, 0x8000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009800006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009900006010C3F, 0x60); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009980006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A00006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B00006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B80006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C80006010C3F, 0xffffffffffff0018, 0x1ea5); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D00006010C3F, 0xffffffffffff001f, 0x3fa0); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E00006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E80006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A800006010C3F, 0x10000010000000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE80006010C3F, 0xFFFFFFFFFFFFFF3F, 0x20); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF80006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B800006010C3F, 0xFFFFFFFFFFFFFFF7); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C040006010C3F, 0xFFFFFFFFFFFFFF3F); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C0C0006010C3F, 0xFFFFFFFFFFFF03FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C140006010C3F, 0xFFFFFFFFFFFF783F, 0x50); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C0006010C3F, 0xFFFFFFFFFFFFFF01, 0x22); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C240006010C3F, 0xFFFFFFFFFFFF3FFF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C840006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C0006010C3F, 0xfffffffffffffe0f, 0x150); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC0006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF40006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C0006010C3F, 0x10); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000006010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000106010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000206010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000306010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000406010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000506010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000606010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000706010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000806010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000906010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000A06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000B06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000C06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000D06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000E06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000F06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001006010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001106010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080006010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080106010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080206010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080306010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080406010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080506010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080606010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080706010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080806010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080906010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080A06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080B06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080C06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080D06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080E06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080F06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000081006010C3F, ~PPC_BIT(54)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280006010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280106010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280206010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280306010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280406010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280506010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280606010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280706010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280806010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280906010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280A06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280B06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280C06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280D06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280E06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280F06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281006010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281106010C3F, ~PPC_BITMASK(44, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300206010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300306010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300406010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300506010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300606010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300706010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300806010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300906010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300A06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300B06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300C06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300D06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300E06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300F06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00006010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00106010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00206010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00306010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00406010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00506010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00606010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00706010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00806010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00906010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00A06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00B06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00C06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00D06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00E06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00F06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01006010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01106010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200006010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200106010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200206010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200306010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200406010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200506010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200606010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200706010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200806010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200906010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200A06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200B06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200C06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200D06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200E06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200F06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002201006010C3F, ~PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002201106010C3F, PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00106010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00706010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00806010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00906010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00F06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C01006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80206010C3F, ~PPC_BITMASK(48, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80706010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80906010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80E06010C3F, ~PPC_BITMASK(48, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C81006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040006010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040106010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040206010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040306010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040406010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040506010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040606010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040706010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040806010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040906010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040A06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040B06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040C06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040D06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040E06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040F06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004041006010C3F, ~PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0006010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0106010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0206010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0306010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0406010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0506010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0606010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0706010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0806010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0906010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0A06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0B06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0C06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0D06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0E06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0F06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C1006010C3F, PPC_BIT(62)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0006010C3F, ~PPC_BITMASK(48, 63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0106010C3F, ~PPC_BITMASK(48, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0706010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0806010C3F, ~PPC_BITMASK(48, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0906010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0F06010C3F, ~PPC_BITMASK(48, 63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C1006010C3F, ~PPC_BITMASK(48, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440206010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(50)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440706010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440906010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440E06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004441006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008000006010C3F, PPC_BIT(49)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008080006010C3F, ~PPC_BITMASK(48, 53)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008100006010C3F, ~PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008300006010C3F, ~PPC_BITMASK(51, 55), PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008400006010C3F, ~PPC_BITMASK(60, 63), PPC_BIT(62) | PPC_BIT(60)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, ~PPC_BITMASK(55, 60), PPC_BIT(51) | PPC_BITMASK(56, 60)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D00006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009700006010C3F, PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009800006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009900006010C3F, PPC_BITMASK(57, 58)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009980006010C3F, ~PPC_BITMASK(48, 52), PPC_BIT(52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A00006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(48) | PPC_BITMASK(50, 51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B00006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B80006010C3F, ~PPC_BITMASK(44, 56), PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C80006010C3F, ~(PPC_BITMASK(48, 58) | PPC_BITMASK(61, 63)), PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D00006010C3F, ~PPC_BITMASK(48, 58), PPC_BITMASK(50, 56) | PPC_BIT(58)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E00006010C3F, ~PPC_BITMASK(48, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E80006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A800006010C3F, PPC_BIT(11) | PPC_BIT(35)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE80006010C3F, ~PPC_BITMASK(56, 57), PPC_BIT(58)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF80006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B800006010C3F, ~PPC_BIT(60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C040006010C3F, ~PPC_BITMASK(56, 57)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C0C0006010C3F, ~PPC_BITMASK(48, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C140006010C3F, ~(PPC_BITMASK(53, 57) | PPC_BIT(48)), PPC_BIT(57) | PPC_BIT(59)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C0006010C3F, ~PPC_BITMASK(56, 62), PPC_BIT(58) | PPC_BIT(62)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C240006010C3F, ~PPC_BITMASK(48, 49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C840006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C0006010C3F, ~PPC_BITMASK(55, 59), PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC0006010C3F, ~PPC_BITMASK(48, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF40006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C0006010C3F, PPC_BIT(59)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, ~PPC_BITMASK(48, 52), PPC_BITMASK(49, 51)); } void p9_xbus_g1_scom() { - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002206010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002306010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002406010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002506010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002606010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002706010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002806010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002906010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002A06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002B06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002C06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002D06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002E06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002F06010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003006010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003106010C3F, 0xFFFFFFFFFFFFF8FF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082106010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082206010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082306010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082406010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082506010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082606010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082706010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082806010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082906010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082A06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082B06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082C06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082D06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082E06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082F06010C3F, 0xFFFFFFFFFFFFFDFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000083006010C3F, 0xFFFFFFFFFFFFFDFF); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000083106010C3F, 0x200); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282206010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282306010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282406010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282506010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282606010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282706010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282806010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282906010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282A06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282B06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282C06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282D06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282E06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282F06010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283006010C3F, 0xFFFFFFFFFFFF0003); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283106010C3F, 0xFFFFFFFFFFFF0003); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302206010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302306010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302406010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302506010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302606010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302706010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302806010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302906010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302A06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302B06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302C06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302D06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302E06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302F06010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303006010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303106010C3F, 0xFFFFFFFFFFFF007F, 0x6380); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02206010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02306010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02406010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02506010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02606010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02706010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02806010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02906010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02A06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02B06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02C06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02D06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02E06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02F06010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03006010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03106010C3F, 0xFFFFFFFFFFFF0007); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002203006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002203106010C3F, 0x8000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02106010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02206010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02306010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02406010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02506010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02606010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02706010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02806010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02906010C3F, 0xFFFFFFFFFFFF0000, 0x9C00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02A06010C3F, 0xFFFFFFFFFFFF0000, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02B06010C3F, 0xFFFFFFFFFFFF0000, 0x1F0F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02C06010C3F, 0xFFFFFFFFFFFF0000, 0x03EF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02D06010C3F, 0xFFFFFFFFFFFF0000, 0x07C7); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02E06010C3F, 0xFFFFFFFFFFFF0000, 0x07BC); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02F06010C3F, 0xFFFFFFFFFFFF0000, 0xF03E); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C03006010C3F, 0xFFFFFFFFFFFF0000, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82106010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82206010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82306010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82406010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82506010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82606010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82706010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82806010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82906010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82A06010C3F, 0xFFFFFFFFFFFF01FF, 0x300); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82B06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82C06010C3F, 0xFFFFFFFFFFFF01FF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82D06010C3F, 0xFFFFFFFFFFFF01FF, 0x6000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82E06010C3F, 0xFFFFFFFFFFFF01FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82F06010C3F, 0xFFFFFFFFFFFF01FF, 0x3E00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, 0xFFFFFFFFFFFF01FF, 0x4200); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042106010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042206010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042306010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042406010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042506010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042606010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042706010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042806010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042906010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042A06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042B06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042C06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042D06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042E06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042F06010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004043006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2006010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2106010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2206010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2306010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2406010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2506010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2606010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2706010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2806010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2906010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2A06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2B06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2C06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2D06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2E06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2F06010C3F, 0x2); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C3006010C3F, 0x2); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2106010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2206010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2306010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2406010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2506010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2606010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2706010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2806010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2906010C3F, 0xFFFFFFFFFFFF0000, 0xE73); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2A06010C3F, 0xFFFFFFFFFFFF0000, 0xC63); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2B06010C3F, 0xFFFFFFFFFFFF0000, 0x7C); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2C06010C3F, 0xFFFFFFFFFFFF0000, 0xF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2D06010C3F, 0xFFFFFFFFFFFF0000, 0x1F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2E06010C3F, 0xFFFFFFFFFFFF0000, 0x1E); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2F06010C3F, 0xFFFFFFFFFFFF0000); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C3006010C3F, 0xFFFFFFFFFFFF0000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442106010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442206010C3F, 0xFFFFFFFFFFFF0100, 0xF600); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442306010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442406010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442506010C3F, 0xFFFFFFFFFFFF01FF, 0x2000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442606010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442706010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442806010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442906010C3F, 0xFFFFFFFFFFFF01FF, 0x9C00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442A06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442B06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442C06010C3F, 0xFFFFFFFFFFFF01FF, 0xbc00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442D06010C3F, 0xFFFFFFFFFFFF01FF, 0x1800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442E06010C3F, 0xFFFFFFFFFFFF01FF, 0xBC00); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442F06010C3F, 0xFFFFFFFFFFFF01FF, 0xF800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004443006010C3F, 0xFFFFFFFFFFFF01FF, 0x200); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008002006010C3F, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008082006010C3F, 0xffffffffffff03ff, 0x400); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008102006010C3F, 0xFFFFFFFFFFFF7FFF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008302006010C3F, 0xffffffffffffe0ff, 0x1500); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008402006010C3F, 0xFFFFFFFFFFFFFFF0, 0xA); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, 0xFFFFFFFFFFFF3FFF, 0x4000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C02006010C3F, 0xFFFFFFFFFFFFFEFF, 0xF8); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D02006010C3F, 0xFFFFFFFFFFFF0000, 0x1044); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009702006010C3F, 0x8000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009802006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009902006010C3F, 0x60); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009982006010C3F, 0xFFFFFFFFFFFF07FF, 0x800); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A02006010C3F, 0xFFFFFFFFFFFF0FFF, 0xB000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B02006010C3F, 0xFFFFFFFFFFFF0FFF, 0x1000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B82006010C3F, 0xFFFFFFFFFFFF0003, 0x2244); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C82006010C3F, 0xFFFFFFFFFFFF0018, 0x1EA5); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D02006010C3F, 0x7fffffffffff800, 0x3f5); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E02006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E82006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A802006010C3F, 0x2080); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE82006010C3F, 0xFFFFFFFFFFFFFF3F, 0x80); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF82006010C3F, 0xFFFFFFFFFFFF00FF, 0xCC00); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B802006010C3F, 0xFFFFFFFFFFFFFFF7); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C042006010C3F, 0xFFFFFFFFFFFFFF3F); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C0C2006010C3F, 0xFFFFFFFFFFFF03FF, 0x400); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C142006010C3F, 0xFFFFFFFFFFFF783F, 0x50); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C2006010C3F, 0xFFFFFFFFFFFFFF01, 0xF22); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C242006010C3F, 0xFFFFFFFFFFFF3FFF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C842006010C3F, 0xFFFFFFFFFFFF8080, 0x10); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C2006010C3F, 0xfffffffffffffe0f, 0x150); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC2006010C3F, 0xFFFFFFFFFFFF00FF); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF42006010C3F, 0xFFFFFFFFFFFF00FF, 0x7F00); - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C2006010C3F, 0x10); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, 0xFFFFFFFFFFFF07FF, 0x7000); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002006010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002106010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002206010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002306010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002406010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002506010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002606010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002706010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002806010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002906010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002A06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002B06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002C06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002D06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002E06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002F06010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003006010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003106010C3F, ~PPC_BITMASK(53, 55)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082006010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082106010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082206010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082306010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082406010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082506010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082606010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082706010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082806010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082906010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082A06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082B06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082C06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082D06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082E06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082F06010C3F, ~PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000083006010C3F, ~PPC_BIT(54)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000083106010C3F, PPC_BIT(54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282006010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282106010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282206010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282306010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282406010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282506010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282606010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282706010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282806010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282906010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282A06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282B06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282C06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282D06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282E06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282F06010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283006010C3F, ~PPC_BITMASK(44, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283106010C3F, ~PPC_BITMASK(44, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302206010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302306010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302406010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302506010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302606010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302706010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302806010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302906010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302A06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302B06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302C06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302D06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302E06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302F06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02006010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02106010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02206010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02306010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02406010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02506010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02606010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02706010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02806010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02906010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02A06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02B06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02C06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02D06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02E06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02F06010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03006010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03106010C3F, ~PPC_BITMASK(48, 60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202106010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202206010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202306010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202406010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202506010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202606010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202706010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202806010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202906010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202A06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202B06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202C06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202D06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202E06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202F06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002203006010C3F, ~PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002203106010C3F, PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02106010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(49, 52) | PPC_BITMASK(58, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 57) | PPC_BITMASK(61, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02706010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02806010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02906010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 57) | PPC_BITMASK(61, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(49, 52) | PPC_BITMASK(58, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02F06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C03006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82206010C3F, ~PPC_BITMASK(48, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82706010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82906010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82E06010C3F, ~PPC_BITMASK(48, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042006010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042106010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042206010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042306010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042406010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042506010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042606010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042706010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042806010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042906010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042A06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042B06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042C06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042D06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042E06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042F06010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004043006010C3F, ~PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2006010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2106010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2206010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2306010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2406010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2506010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2606010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2706010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2806010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2906010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2A06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2B06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2C06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2D06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2E06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2F06010C3F, PPC_BIT(62)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C3006010C3F, PPC_BIT(62)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2006010C3F, ~PPC_BITMASK(48, 63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2106010C3F, ~PPC_BITMASK(48, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2706010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2806010C3F, ~PPC_BITMASK(48, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2906010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2F06010C3F, ~PPC_BITMASK(48, 63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C3006010C3F, ~PPC_BITMASK(48, 63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442206010C3F, ~(PPC_BITMASK(48, 51) | PPC_BITMASK(56, 63)), PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(42)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442706010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442906010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442E06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004443006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008002006010C3F, PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008082006010C3F, ~PPC_BITMASK(48, 53), PPC_BIT(53)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008102006010C3F, ~PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008302006010C3F, ~PPC_BITMASK(51, 55), PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008402006010C3F, ~PPC_BITMASK(60, 63), PPC_BIT(62) | PPC_BIT(60)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, ~PPC_BITMASK(48, 49), PPC_BIT(49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C02006010C3F, ~PPC_BIT(55), PPC_BITMASK(56, 60)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009702006010C3F, PPC_BIT(48)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009802006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009902006010C3F, PPC_BITMASK(57, 58)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009982006010C3F, ~PPC_BITMASK(48, 52), PPC_BIT(52)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A02006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(48) | PPC_BITMASK(50, 51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B02006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(51)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B82006010C3F, ~PPC_BITMASK(44, 56), PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C82006010C3F, PPC_BITMASK(48, 55) | PPC_BITMASK(61, 63), PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D02006010C3F, ~PPC_BITMASK(53, 63), PPC_BITMASK(54, 59) | PPC_BIT(61) | PPC_BIT(63)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E02006010C3F, ~PPC_BITMASK(48, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E82006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A802006010C3F, PPC_BIT(50) | PPC_BIT(56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE82006010C3F, ~PPC_BITMASK(56, 57), PPC_BIT(56)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF82006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B802006010C3F, ~PPC_BIT(60)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C042006010C3F, ~PPC_BITMASK(56, 57)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C0C2006010C3F, ~PPC_BITMASK(48, 53), PPC_BIT(53)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C142006010C3F, ~(PPC_BIT(48) | PPC_BITMASK(53, 57)), PPC_BIT(57) | PPC_BIT(59)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C2006010C3F, ~PPC_BITMASK(56, 62), PPC_BITMASK(52, 55) | PPC_BIT(58) | PPC_BIT(62)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C242006010C3F, ~PPC_BITMASK(48, 49)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C842006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C2006010C3F, ~PPC_BITMASK(55, 59), PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC2006010C3F, ~PPC_BITMASK(48, 55)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF42006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C2006010C3F, PPC_BIT(59)); + scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, ~PPC_BITMASK(48, 52), PPC_BITMASK(49, 51)); } From f5b3c7490f997e602581af3b7a12f4421ac000d7 Mon Sep 17 00:00:00 2001 From: IgorBagnucki <69140743+IgorBagnucki@users.noreply.github.com> Date: Mon, 1 Mar 2021 15:00:03 +0100 Subject: [PATCH 83/90] src/cpu/power/scom_init.c: Delete empty file --- src/cpu/power/scom_init.c | 0 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 src/cpu/power/scom_init.c diff --git a/src/cpu/power/scom_init.c b/src/cpu/power/scom_init.c deleted file mode 100644 index e69de29bb2d..00000000000 From 9c8521c1958567b8d429875a73acfd4fa026d995 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Tue, 2 Mar 2021 11:16:19 +0100 Subject: [PATCH 84/90] src/soc/ibm/power9/istep_8_9.c: Describe register fields --- src/include/cpu/power/scom_registers.h | 12 +- src/soc/ibm/power9/istep_8_10.c | 911 +++++++++++++++++++++++++ src/soc/ibm/power9/istep_8_9.c | 209 +++++- 3 files changed, 1117 insertions(+), 15 deletions(-) diff --git a/src/include/cpu/power/scom_registers.h b/src/include/cpu/power/scom_registers.h index ab403617bdb..2aedfccab3e 100644 --- a/src/include/cpu/power/scom_registers.h +++ b/src/include/cpu/power/scom_registers.h @@ -10,9 +10,9 @@ #define PB_CENT_SP_COMMAND_RATE_DP0_REG (0x5011C2A) // Power Bus PB CENT SP command RATE DP0 Register #define PB_CENT_SP_COMMAND_RATE_DP1_REG (0x5011C2B) // Power Bus PB CENT SP command RATE DP1 Register #define PB_EAST_MODE_CFG_REG (0x501200A) // Power Bus PB East Mode Configuration Register -#define PU_PB_IOE_FIR_MASK_REG (0x5013403) -#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) -#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) +#define PU_PB_IOE_FIR_MASK_REG (0x5013403) // Power Bus PBEN IOX Domain FIR0 Mask Register +#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) // Power Bus PBEN IOX Domain FIR Action 0 Register +#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) // Power Bus PBEN IOX Domain FIR Action 1 Register #define PB_ELE_PB_FRAMER_PARSER_01_CFG_REG (0x501340A) // Power bus Electrical Framer/Parser 01 Configuration Register #define PB_ELE_PB_FRAMER_PARSER_23_CFG_REG (0x501340B) // Power Bus Electrical Framer/Parser 23 Configuration Register #define PB_ELE_PB_FRAMER_PARSER_45_CFG_REG (0x501340C) // Power Bus Electrical Framer/Parser 45 Configuration Register @@ -21,9 +21,9 @@ #define PB_ELE_PB_DATA_BUFF_45_CFG_REG (0x5013412) // Power Bus Electrical Link Data Buffer 45 Configuration Register #define PB_ELE_MISC_CFG_REG (0x5013423) // Power Bus Electrical Miscellaneous Configuration Register #define PB_ELE_LINK_TRACE_CFG_REG (0x5013424) // Power Bus Electrical Link Trace Configuration Register -#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) -#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) -#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) +#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) // ELL FIR Mask Register +#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) // ELL FIR Action 0 Register +#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) // ELL FIR Action 1 Register #define PB_ELL_CFG_REG (0x601180A) // Power Bus ELL Configuration Register #define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) // Power Bus ELL Replay Threshold Register #define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) // Power Bus ELL SL ECC Threshold Register diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 80d440eb9ad..d9d03c0b63e 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -44,495 +44,1406 @@ void p9_io_xbus_scominit(const uint8_t group) void p9_xbus_g0_scom() { + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000006010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000106010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000206010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000306010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000406010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000506010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000606010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000706010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000806010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000906010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000A06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000B06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000C06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000D06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000E06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000F06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001006010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001106010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080006010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080106010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080206010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080306010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080406010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080506010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080606010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080706010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080806010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080906010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080A06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080B06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080C06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080D06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080E06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080F06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000081006010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, PPC_BIT(54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280006010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280106010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280206010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280306010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280406010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280506010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280606010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280706010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280806010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280906010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280A06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280B06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280C06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280D06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280E06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280F06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281006010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281106010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300206010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300306010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300406010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300506010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300606010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300706010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300806010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300906010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300A06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300B06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300C06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300D06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300E06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300F06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00006010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00106010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00206010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00306010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00406010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00506010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00606010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00706010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00806010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00906010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00A06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00B06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00C06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00D06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00E06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00F06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01006010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01106010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200106010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200206010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200306010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200406010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200506010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200606010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200706010C3F, ~PPC_BIT(48)); + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200806010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200906010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200A06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200B06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200C06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200D06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200E06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200F06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002201006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002201106010C3F, PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00106010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00706010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00806010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00906010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00F06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C01006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80206010C3F, ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80706010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80906010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80E06010C3F, ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C81006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040106010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040206010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040306010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040406010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040506010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040606010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040706010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040806010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040906010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040A06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040B06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040C06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040D06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040E06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040F06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004041006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0006010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0106010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0206010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0306010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0406010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0506010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0606010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0706010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0806010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0906010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0A06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0B06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0C06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0D06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0E06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0F06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C1006010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0006010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0106010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0706010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0806010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0906010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0F06010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C1006010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440206010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(50)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440706010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440906010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440E06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004441006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RX_SPARE_MODE_PG + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008000006010C3F, PPC_BIT(49)); + // register P9A_XBUS_0_RX0_RX_ID1_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008080006010C3F, ~PPC_BITMASK(48, 53)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE1_EO_PG + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008100006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE5_EO_PG + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008300006010C3F, ~PPC_BITMASK(51, 55), PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE7_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008400006010C3F, ~PPC_BITMASK(60, 63), PPC_BIT(62) | PPC_BIT(60)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, ~PPC_BITMASK(55, 60), PPC_BIT(51) | PPC_BITMASK(56, 60)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_OFF + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D00006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009700006010C3F, PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009800006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + // P9A_XBUS_0_RX1_RX_ID2_PG scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009900006010C3F, PPC_BITMASK(57, 58)); + // P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009980006010C3F, ~PPC_BITMASK(48, 52), PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A00006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(48) | PPC_BITMASK(50, 51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B00006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B80006010C3F, ~PPC_BITMASK(44, 56), PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C80006010C3F, ~(PPC_BITMASK(48, 58) | PPC_BITMASK(61, 63)), PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D00006010C3F, ~PPC_BITMASK(48, 58), PPC_BITMASK(50, 56) | PPC_BIT(58)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E00006010C3F, ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E80006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A800006010C3F, PPC_BIT(11) | PPC_BIT(35)); + // register P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE80006010C3F, ~PPC_BITMASK(56, 57), PPC_BIT(58)); + // register P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF80006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + // register P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B800006010C3F, ~PPC_BIT(60)); + // register P9A_XBUS_0_TX1_TX_SPARE_MODE_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C040006010C3F, ~PPC_BITMASK(56, 57)); + // register P9A_XBUS_0_TX1_TX_ID1_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C0C0006010C3F, ~PPC_BITMASK(48, 53)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C140006010C3F, ~(PPC_BITMASK(53, 57) | PPC_BIT(48)), PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C0006010C3F, ~PPC_BITMASK(56, 62), PPC_BIT(58) | PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C240006010C3F, ~PPC_BITMASK(48, 49)); + // register P9A_XBUS_0_TX1_TX_ID2_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C840006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C0006010C3F, ~PPC_BITMASK(55, 59), PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC0006010C3F, ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF40006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C0006010C3F, PPC_BIT(59)); + // register P9A_XBUS_0_TX_IMPCAL_P_4X_PB scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, ~PPC_BITMASK(48, 52), PPC_BITMASK(49, 51)); } void p9_xbus_g1_scom() { + // register P9A_XBUS_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002006010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002106010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002206010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002306010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002406010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002506010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002606010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002706010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002806010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002906010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002A06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002B06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002C06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002D06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002E06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002F06010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003006010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003106010C3F, ~PPC_BITMASK(53, 55)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082006010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082106010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082206010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082306010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082406010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082506010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082606010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082706010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082806010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082906010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082A06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082B06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082C06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082D06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082E06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082F06010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000083006010C3F, ~PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000083106010C3F, PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282006010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282106010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282206010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282306010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282406010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282506010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282606010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282706010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282806010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282906010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282A06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282B06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282C06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282D06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282E06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282F06010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283006010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283106010C3F, ~PPC_BITMASK(44, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302206010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302306010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302406010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302506010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302606010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302706010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302806010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302906010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302A06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302B06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302C06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302D06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302E06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302F06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_ scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02006010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02106010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_ scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02206010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02306010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_P scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02406010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02506010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02606010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02706010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02806010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02906010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02A06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02B06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02C06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02D06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02E06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02F06010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03006010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03106010C3F, ~PPC_BITMASK(48, 60)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202106010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202206010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202306010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202406010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202506010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202606010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202706010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202806010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202906010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202A06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202B06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202C06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202D06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202E06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202F06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002203006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002203106010C3F, PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02106010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(49, 52) | PPC_BITMASK(58, 61)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 57) | PPC_BITMASK(61, 63)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02706010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02806010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02906010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 57) | PPC_BITMASK(61, 63)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(49, 52) | PPC_BITMASK(58, 61)); + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02F06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C03006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82206010C3F, ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82706010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82906010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C82E06010C3F, ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL + // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042106010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042206010C3F, ~PPC_BIT(48)); + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042306010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042406010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042506010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042606010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042706010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042806010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042906010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042A06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042B06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042C06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042D06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042E06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042F06010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004043006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2006010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2106010C3F, PPC_BIT(62)); + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2206010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2306010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2406010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2506010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2606010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2706010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2806010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2906010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2A06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2B06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2C06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2D06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2E06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2F06010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C3006010C3F, PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2006010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2106010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2706010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2806010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2906010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C2E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2F06010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C3006010C3F, ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442206010C3F, ~(PPC_BITMASK(48, 51) | PPC_BITMASK(56, 63)), PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(42)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442706010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442906010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(51, 53)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442E06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL + // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004443006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + // register P9A_XBUS_0_RX1_RX_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008002006010C3F, PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RX_ID1_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008082006010C3F, ~PPC_BITMASK(48, 53), PPC_BIT(53)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE1_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008102006010C3F, ~PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE5_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008302006010C3F, ~PPC_BITMASK(51, 55), PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE7_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008402006010C3F, ~PPC_BITMASK(60, 63), PPC_BIT(62) | PPC_BIT(60)); + // register P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, ~PPC_BITMASK(48, 49), PPC_BIT(49)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C02006010C3F, ~PPC_BIT(55), PPC_BITMASK(56, 60)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009702006010C3F, PPC_BIT(48)); + // register P9A_XBUS_0_RX1_RX_ID2_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009802006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009902006010C3F, PPC_BITMASK(57, 58)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009982006010C3F, ~PPC_BITMASK(48, 52), PPC_BIT(52)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A02006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(48) | PPC_BITMASK(50, 51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B02006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(51)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B82006010C3F, ~PPC_BITMASK(44, 56), PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C82006010C3F, PPC_BITMASK(48, 55) | PPC_BITMASK(61, 63), PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG + // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D02006010C3F, ~PPC_BITMASK(53, 63), PPC_BITMASK(54, 59) | PPC_BIT(61) | PPC_BIT(63)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE11_E_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E02006010C3F, ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E82006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER + // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A802006010C3F, PPC_BIT(50) | PPC_BIT(56)); + // register P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE82006010C3F, ~PPC_BITMASK(56, 57), PPC_BIT(56)); + // register P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF82006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + // register P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG + // IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B802006010C3F, ~PPC_BIT(60)); + // register P9A_XBUS_0_TX1_TX_SPARE_MODE_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C042006010C3F, ~PPC_BITMASK(56, 57)); + // register P9A_XBUS_0_TX1_TX_ID1_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C0C2006010C3F, ~PPC_BITMASK(48, 53), PPC_BIT(53)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C142006010C3F, ~(PPC_BIT(48) | PPC_BITMASK(53, 57)), PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C2006010C3F, ~PPC_BITMASK(56, 62), PPC_BITMASK(52, 55) | PPC_BIT(58) | PPC_BIT(62)); + // register P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C242006010C3F, ~PPC_BITMASK(48, 49)); + // register P9A_XBUS_0_TX1_TX_ID2_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C842006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 + // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C2006010C3F, ~PPC_BITMASK(55, 59), PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC2006010C3F, ~PPC_BITMASK(48, 55)); + // register P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF42006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + // register P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG + // IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C2006010C3F, PPC_BIT(59)); + // register P9A_XBUS_0_TX_IMPCAL_P_4X_PB scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, ~PPC_BITMASK(48, 52), PPC_BITMASK(49, 51)); } diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c index 0f4c58dee81..0a4e165959d 100644 --- a/src/soc/ibm/power9/istep_8_9.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,44 +20,234 @@ void istep_8_9(void) void p9_fbc_ioe_dl_scom(void) { - scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_CFG_REG, 0x7FEFFFFFFFFFFFFF, 0x280F000F00000000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_REPLAY_TRESHOLD_REG, 0xFFFFFFFFFFFFFFF, 0x6FE0000000000000); - scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_SL_ECC_TRESHOLD_REG, 0x7FFFFFFFFFFFFFFF, 0x7F70000000000000); + // PB_ELL_CFG_REG + // [0] CONFIG_LINK_PAIR: When 1, the two links operate as a pair. + // When 0, only one link is used or they are independent. + // [2] CONFIG_CRC_LANE_ID: When 1, use lane IDs from CRC for lane sparing. + // [4] CONFIG_SL_UE_CRC_ERR: When 1, UEs on the SL ECC cause the packet + // to be treated as a CRC error. + // [8:11] CONFIG_UNUSED1: Spare bits. + // [12:15] CONFIG_PACKET_DELAY_LIMIT: This field indicates the number + // of cycles of delay of frame data that are required for the + // packet to be considered delayed or replayed. (0 is 16 cycles.) + // [27:27] CONFIG_AUTO_TDM_BW_DIFF: Bandwidth difference + // for auto-entry TMD mode. + scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_CFG_REG, ~(PPC_BIT(0) | PPC_BIT(11)), PPC_BIT(2) | PPC_BIT(4) | PPC_BITMASK(12, 15) | PPC_BITMASK(24, 27)); + // PB_ELL_REPLAY_TRESHOLD_REG + // [0:3] THRESH_REPLAY_TB_SEL: Replay threshold timebase select. + // [4:7] THRESH_REPLAY_TAP_SEL: Replay threshold tap select. + // [8:10] THRESH_REPLAY_ENABLE: Replay threshold error enable. + scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_REPLAY_TRESHOLD_REG, ~PPC_BITMASK(0, 3), PPC_BITMASK(1, 2) | PPC_BITMASK(4, 10)); + // PB_ELL_SL_ECC_TRESHOLD_REG + // [0:3] THRESH_SL_ECC_TB_SEL: SL ECC threshold timebase select. + // [4:7] THRESH_SL_ECC_TAP_SEL: SL ECC threshold tap select. + // [8:9] THRESH_SL_ECC_ENABLE: SL ECC threshold error enable. + // [10:25] THRESH_SL_ECC_UNUSED1: Spare bits. + scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_SL_ECC_TRESHOLD_REG, ~PPC_BIT(0), PPC_BITMASK(1, 7) | PPC_BITMASK(9, 11)); } void ioe_tl_fir(void) { + // PB_IOE_FIR_ACTION0: Processor bus IOE domain action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) Checkstop. + // (0,1) Recoverable Error to Service Processor. + // (1,0) Special Attention to Service Processor. + // (1,1) Invalid. write_scom(PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0); + // PB_IOE_FIR_ACTION1: Processor bus FIR LSB of action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) Checkstop. + // (0,1) Recoverable Error to Service Processor. + // (1,0) Special Attention to Service Processor. + // (1,1) Invalid. write_scom(PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1); + // PU_PB_IOE_FIR_MASK_REG: Power Bus PBEN IOX Domain FIR0 Mask Register + // [0:5] FMR[0:5]_TRAINED_MASK fmr[0:5] trained. + // [6:7] RSV[6:7]_MASK rsv[6:7] mask. + // [8] DOB01_UE_MASK: dob01 ue mask. + // [9] DOB01_CE_MASK: dob01 ce mask. + // [10] DOB01_SUE_MASK: dob01 sue mask. + // [11] DOB23_UE_MASK: dob23 ue mask. + // [12] DOB23_CE_MASK: dob23 ce mask. + // [13] DOB23_SUE_MASK: dob23 sue mask. + // [14] DOB45_UE_MASK: dob45 ue mask. + // [15] DOB45_CE_MASK: dob45 ce mask. + // [16] DOB45_SUE_MASK: dob45 sue mask. + // [17:19] RSV17_MASK: rsv[17:19] mask. + // [20:25] FRAMER[0:5]_ATTN_MASK: framer[0:5] attn mask. + // [26:27] RSV[26:27]_MASK: rsv[26:27] mask. + // [28:33] PARSER[0:5]_ATTN_MASK: parser[0:5] attn mask. + // [34:35] RSV[34:35]_MASK: rsv[34:35] mask. + // [36:37] MB[0:1]_SPATTN_MASK: mb[0:1] spattn mask. + // [38:39] MB[10:11]_SPATTN_MASK: mb[10:11] spattn mask. + // [40:41] MB[20:21]_SPATTN_MASK: mb[20:21] spattn mask. + // [42:43] MB[30:31]_SPATTN_MASK: mb[30:31] spattn mask. + // [44:45] MB[40:41]_SPATTN_MASK: mb[40:41] spattn mask. + // [46:47] MB[50:51]_SPATTN_MASK: mb[50:51] spattn mask. + // [48:51] Reserved. + // [52] DOB01_ERR_MASK: data outbound switch internal error mask - links 01. + // [53] DOB23_ERR_MASK: data outbound switch internal error mask - links 23. + // [54] DOB45_ERR_MASK: data outbound switch internal error mask - links 45. + // [55] Reserved. + // [56] DIB01_ERR_MASK: data inbound switch internal error mask - links 01. + // [57] DIB23_ERR_MASK: data inbound switch internal error mask - links 23. + // [58] DIB45_ERR_MASK: data inbound switch internal error mask - links 45. + // [59:61] Reserved. + // [62] FIR_SCOM_ERR_MASK_DUP: FIR SCOM err mask dup. + // [63] FIR_SCOM_ERR_MASK: FIR SCOM err mask. write_scom(PU_PB_IOE_FIR_MASK_REG, FBC_IOE_TL_FIR_MASK | FBC_IOE_TL_FIR_MASK_X0_NF); } void ioel_fir(void) { + // IOEL_FIR_ACTION0: processor bus FIR MSB of action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) = Checkstop. + // (0,1) = Recoverable error to service processor. + // (1,0) = Special attention to service processor. + // (1,1) = Invalid. write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0); + // IOEL_FIR_ACTION1: processor bus FIR LSB of action select for corresponding bit in FIR. + // (Action0,Action1) = Action Select. + // (0,0) = Checkstop. + // (0,1) = Recoverable error to service processor. + // (1,0) = Special attention to service processor. + // (1,1) = Invalid. write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1); + // XBUS_LL0_IOEL_FIR_MASK_REG: This register provides a bit mask for the ELL FIR Register. + // [0:1] FIR_LINK[0:1]_TRAINED_MASK: Link [0:1] trained mask. + // [2:3] RESERVED. + // [4:5] FIR_LINK[0:1]_REPLAY_THRESHOLD_MASK: Link [0:1] replay threshold mask. + // [6:7] FIR_LINK[0:1]_CRC_ERROR_MASK: Link [0:1] CRC error mask. + // [8:9] FIR_LINK[0:1]_NAK_RECEIVED_MASK: Link [0:1] NAK received mask. + // [10:11] FIR_LINK[0:1]_REPLAY_BUFFER_FULL_MASK: Link [0:1] replay buffer full mask. + // [12:13] FIR_LINK[0:1]_SL_ECC_THRESHOLD_MASK: Link [0:1] SL ECC threshold mask. + // [14:15] FIR_LINK[0:1]_SL_ECC_CORRECTABLE_MASK: Link [0:1] SL ECC correctable mask. + // [16:17] FIR_LINK[0:1]_SL_ECC_UE_MASK: Link [0:1] SL ECC UE mask. + // [18:39] RESERVED. + // [40:41] FIR_LINK[0:1]_TCOMPLETE_BAD_MASK: Link [0:1] complete bad mask. + // [42:43] RESERVED. + // [44:45] FIR_LINK[0:1]_SPARE_DONE_MASK: Link [0:1] spare done mask. + // [46:47] FIR_LINK[0:1]_TOO_MANY_CRC_ERRORS_MASK: Link [0:1] too many CRC errors mask. + // [48:50] RESERVED. + // [51] FIR_PSAVE_INVALID_STATE_MASK: Psave invalid state mask. + // [52:53] FIR_LINK[0:1]_CORRECTABLE_ARRAY_ERROR_MASK: Link [0:1] correctable array error mask. + // [54:55] FIR_LINK[0:1]_UNCORRECTABLE_ARRAY_ERROR_MASK: Link [0:1] uncorrectable array error mask. + // [56:57] FIR_LINK[0:1]_TRAINING_FAILED_MASK: Link [0:1] training failed mask. + // [58:59] FIR_LINK[0:1]_UNRECOVERABLE_ERROR_MASK: Link [0:1] unrecoverable error mask. + // [60:61] FIR_LINK[0:1]_INTERNAL_ERROR_MASK: Link [0:1] internal error mask. + // [62] FIR_SCOM_ERR_DUP_MASK: FIR SCOM error dup mask. + // [63] FIR_SCOM_ERR_MASK: FIR SCOM error mask. write_scom_for_chiplet(XB_CHIPLET_ID, XBUS_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK); } void p9_fbc_no_hp_scom(void) { - scom_and_or(PB_WEST_MODE_CFG_REG, 0xFFFF00000FFFFFFF, 0xFAFEA0000000); - scom_and_or(PB_CENT_MODE_CFG_REG, 0xFFFF00000FFFFFFF, 0x7EFEA0000000); + // PB_WEST_MODE_CFG_REG: Power Bus west mode configuration register + // [16:22] PB_CFG_SP_HW_MARK: configures the maximum system pumps an IO unit may issue. + // [23:29] PB_CFG_GP_HW_MARK: configures the maximum group pumps this chip may issue. + // [30:35] PB_CFG_LCL_HW_MARK: configures the maximum local pumps this chip may issue. + scom_and_or(PB_WEST_MODE_CFG_REG, ~PPC_BITMASK(16, 35), 0xFAFEA0000000); + // PB_CENT_MODE_CFG_REG: Power Bus PB CENT Mode Register + // [16:22] PB_CFG_SP_HW_MARK: Configures the maximum system pumps an IO unit may issue. + // [23:29] PB_CFG_GP_HW_MARK: Configures the maximum group pumps this chip may issue. + // [30:35] PB_CFG_LCL_HW_MARK: Configures the maximum local pumps this chip may issue. + scom_and_or(PB_CENT_MODE_CFG_REG, ~PPC_BITMASK(16, 35), 0x7EFEA0000000); + // PB_CENT_GP_COMMAND_RATE_DP0_REG: Power Bus PB CENT GP command RATE DP0 Register + // PB_CFG_GP_CMD_RATE_DP0_LVL[0:7]: Configures the command rate for group pump drop priority 0 at level [0:7]. write_scom(PB_CENT_GP_COMMAND_RATE_DP0_REG, 0); + // PB_CENT_GP_COMMAND_RATE_DP1_REG: Power Bus PB CENT GP command RATE DP1 Register + // PB_CFG_GP_CMD_RATE_DP1_LVL[0:7]: Configures the command rate for group pump drop priority 1 at level [0:7]. write_scom(PB_CENT_GP_COMMAND_RATE_DP1_REG, 0); + // PB_CENT_RGP_COMMAND_RATE_DP0_REG: Power Bus PB CENT RGP command RATE DP0 Register + // RWX PB_CFG_RNS_CMD_RATE_DP0_LVL[0:7]: Configures the command rate for remote group pump drop priority 0 at level [0:7]. write_scom(PB_CENT_RGP_COMMAND_RATE_DP0_REG, 0x30406080A0C1218); + // PB_CENT_RGP_COMMAND_RATE_DP1_REG: Power Bus PB CENT RGP command RATE DP1 Register + // PB_CFG_RNS_CMD_RATE_DP1_LVL[0:7]: Configures the command rate for remote group pump drop priority 1 at level [0:7]. write_scom(PB_CENT_RGP_COMMAND_RATE_DP1_REG, 0x40508080A0C1218); + // PB_CENT_SP_COMMAND_RATE_DP0_REG: Power Bus PB CENT SP command RATE DP0 Register + // PB_CFG_VG_CMD_RATE_DP0_LVL[0:7]: Configures the command rate for system pump drop priority 0 at level [0:7]. write_scom(PB_CENT_SP_COMMAND_RATE_DP0_REG, 0x30406080A0C1218); + // PB_CENT_SP_COMMAND_RATE_DP1_REG: Power Bus PB CENT SP command RATE DP1 Register + // PB_CFG_VG_CMD_RATE_DP1_LVL[0:7]: Configures the command rate for system pump drop priority 1 at level [0:7]. write_scom(PB_CENT_SP_COMMAND_RATE_DP1_REG, 0x30406080A0C1218); + // PB_EAST_MODE_CFG_REG: Power Bus PB East Mode Configuration Register + // [0] pb_east_pbixxx_init + // [1:3] spare + // [4] PB_CFG_CHIP_IS_SYSTEM: configures whether there are other POWER9s in the system. + // [5:7] spare + // [8] PB_CFG_HNG_CHK_DISABLE: Hang Check Disable. + // [9] PB_DBG_CLR_MAX_HANG_STAGE: Resets the maximum hang state level (pb_hang_level). + // [10:11] spare 12:15 pb_cfg_east_sw_ab_wait(0:3) + // [12:15] PB_CFG_SW_AB_WAIT: Adds delay to tc_pb_switch_ab input from TPC during hot plug sequence. scom_and_or(PB_EAST_MODE_CFG_REG, 0xF1FF00000FFFFFFF, 0x7EFE0000000); } void p9_fbc_ioe_tl_scom(void) { + // PB_ELE_PB_FRAMER_PARSER_01_CFG_REG Power Bus Electrical Framer/Parser 01 Configuration Register + // [0] FP0_CREDIT_PRIORITY_4_NOT_8: fp0 credit priority 4 not 8. + // [1] FP0_DISABLE_GATHERING: fp0 disable data gathering. + // [2] FP0_DISABLE_CMD_COMPRESSION: fp0 disable command compression. + // [3] FP0_DISABLE_PRSP_COMPRESSION: fp0 disable prsp compression. + // [4:11] FP0_LL_CREDIT_LO_LIMIT: fp0 ll credit low limit - normal frames in flight limit. Set to ROUNDUP(25.5 - (nest freq/elec freq)*10.75)). + // [12:19] FP0_LL_CREDIT_HI_LIMIT: fp0 ll credit high limit - frames in flight limit during stop_cmds/replay. + // [20] FP0_FMR_DISABLE: fp0 framer disable - turn the framer clocks OFF. + // [21] FP0_FMR_SPARE: fp0 framer spare. + // [22:23] FP01_CMD_EXP_TIME: obs/fmr/prs command expiration time = (value * 2) + 9. + // [24] FP0_RUN_AFTER_FRAME_ERROR: fp0 run after frame error. + // [25] FP0_PRS_DISABLE: fp0 parser disable - turn the parser clocks OFF. + // [26:31] FP0_PRS_SPARE: fp0 parser spare. + // [32] FP1_CREDIT_PRIORITY_4_NOT_8: fp1 credit priority 4 not 8. + // [33] FP1_DISABLE_GATHERING: fp1 disable data gathering. + // [34] FP1_DISABLE_CMD_COMPRESSION: fp1 disable command compression. + // [35] FP1_DISABLE_PRSP_COMPRESSION: fp1 disable prsp compression. + // [36:43] FP1_LL_CREDIT_LO_LIMIT: fp1 ll credit low limit - normal frames in flight limit. Set to ROUNDUP(25.5 - (nest freq/elec freq)*10.75)). + // [44:51] FP1_LL_CREDIT_HI_LIMIT: fp1 ll credit high limit - frames in flight limit during stop_cmds/replay. + // [52] FP1_FMR_DISABLE: fp1 framer disable - turn the framer clocks OFF. + // [53:55] FP1_FMR_SPARE: fp1 framer spare. + // [56] FP1_RUN_AFTER_FRAME_ERROR: fp1 run after frame error. + // [57] FP1_PRS_DISABLE: fp1 parser disable - turn the parser clocks OFF. + // [58:63] FP1_PRS_SPARE: fp1 parser spare. scom_and_or(PB_ELE_PB_FRAMER_PARSER_01_CFG_REG, 0xfff004fffff007bf, 0x2010000020000); + // PB_ELE_PB_DATA_BUFF_01_CFG_REG: Power Bus Electrical Link Data Buffer 01 Configuration Register + // [0] Reserved. + // [1:7] PB_CFG_LINK0_DOB_LIMIT: pb configuration link0 dob limit - total link credits avail. + // [8] Reserved. + // [9:15] PB_CFG_LINK0_DOB_VC0_LIMIT: pb configuration link0 dob vc0 limit - vc0 link credits max. + // [16] Reserved. + // [17:23] PB_CFG_LINK0_DOB_VC1_LIMIT: pb configuration link0 dob vc1 limit - vc1 link credits max. + // [24:28] PB_CFG_LINK01_DIB_VC_LIMIT: pb configuration link01 dib vc limit - limit per VC for data inbound to + // pbien/s (set to 31/16/8 for 1/2/4 channels in use) (both links use same credit pool). + // [29:32] Reserved. + // [33:39] PB_CFG_LINK1_DOB_LIMIT: pb configuration link1 dob limit - total link credits avail. + // [40] Reserved. + // [41:47] PB_CFG_LINK1_DOB_VC0_LIMIT: pb configuration link1 dob vc0 limit - vc0 link credits max. + // [48] Reserved. + // [49:55] PB_CFG_LINK1_DOB_VC1_LIMIT: pb configuration link1 dob vc1 limit - vc1 link credits max. scom_and_or(PB_ELE_PB_DATA_BUFF_01_CFG_REG, 0x808080FF808080FF, 0x403C3C1F403C3C00); - scom_and_or(PB_ELE_LINK_TRACE_CFG_REG, 0xFFFFFFFFFFFF, 0x4141000000000000); - scom_or(PB_ELE_PB_FRAMER_PARSER_23_CFG_REG, 0x84000000840); - scom_or(PB_ELE_PB_FRAMER_PARSER_45_CFG_REG, 0x84000000840); - scom_and_or(PB_ELE_MISC_CFG_REG, 0x9FFFFFFFFFFFFFFF, 0x8000000000000000); + // PB_ELE_LINK_TRACE_CFG_REG:Power Bus Electrical Link Trace Configuration Register + // [0:3] LINK00_HI_TRACE_CFG: link00 high trace configuration. + // [4:7] LINK00_LO_TRACE_CFG: link00 low trace configuration. + // [8:11] LINK01_HI_TRACE_CFG: link01 high trace configuration. + // [12:15] LINK01_LO_TRACE_CFG: link01 low trace configuration. + scom_and_or(PB_ELE_LINK_TRACE_CFG_REG, 0x00FFFFFFFFFFFF, 0x4141000000000000); + // PB_ELE_PB_FRAMER_PARSER_23_CFG_REG: Power Bus Electrical Framer/Parser 23 Configuration Register + // [20] FP2_FMR_DISABLE: fp2 framer disable - turn the framer clocks OFF. + // [25] FP2_PRS_DISABLE: fp2 parser disable - turn the parser clocks OFF. + // [52] FP3_FMR_DISABLE: fp3 framer disable - turn the framer clocks OFF. + // [57] FP3_PRS_DISABLE: fp3 parser disable - turn the parser clocks OFF. + scom_or(PB_ELE_PB_FRAMER_PARSER_23_CFG_REG, PPC_BIT(20) | PPC_BIT(25) | PPC_BIT(52) | PPC_BIT(57)); + // PB_ELE_PB_FRAMER_PARSER_45_CFG_REG Power Bus Electrical Framer/Parser 45 Configuration Register + // [20] FP4_FMR_DISABLE: fp4 framer disable - turn the framer clocks OFF. + // [25] FP4_PRS_DISABLE: fp4 parser disable - turn the parser clocks OFF. + // [52] FP5_FMR_DISABLE: fp5 framer disable - turn the framer clocks OFF. + // [57] FP5_PRS_DISABLE: fp5 parser disable - turn the parser clocks OFF. + scom_or(PB_ELE_PB_FRAMER_PARSER_45_CFG_REG, PPC_BIT(20) | PPC_BIT(25) | PPC_BIT(52) | PPC_BIT(57)); + // PB_ELE_MISC_CFG_REG: Power Bus Electrical Miscellaneous Configuration Register + // [0] PB_CFG_IOE01_IS_LOGICAL_PAIR: pb configuration ioe01 is logical pair. + // [1] PB_CFG_IOE23_IS_LOGICAL_PAIR: pb configuration ioe23 is logical pair. + // [2] PB_CFG_IOE45_IS_LOGICAL_PAIR: pb configuration ioe45 is logical pair. + scom_and_or(PB_ELE_MISC_CFG_REG, ~PPC_BITMASK(1, 2), PPC_BIT(0)); } From 726b06726214f1222068a588675ab870960d3dcc Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Thu, 4 Mar 2021 15:04:20 +0100 Subject: [PATCH 85/90] src/soc/ibm/power9/istep_8_10.c: Clean up istep 8.10 --- src/mainboard/raptor-cs/talos-2/Kconfig | 1 - src/soc/ibm/power9/istep_8_10.c | 1089 ++++++++++++----------- 2 files changed, 580 insertions(+), 510 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig index b399f8403ca..ba231306bfd 100644 --- a/src/mainboard/raptor-cs/talos-2/Kconfig +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -4,7 +4,6 @@ if BOARD_RAPTOR_CS_TALOS_2 config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_POWER9 select CPU_IBM_POWER9 select BOARD_ROMSIZE_KB_16384 select ARCH_BOOTBLOCK_PPC64 diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index d9d03c0b63e..8c601563264 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -44,705 +44,776 @@ void p9_io_xbus_scominit(const uint8_t group) void p9_xbus_g0_scom() { - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000006010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000106010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000206010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000306010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000406010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000506010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000606010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000706010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000806010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000906010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000A06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000B06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000C06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000D06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000E06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000000F06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001006010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000001106010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080006010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080106010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080206010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080306010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080406010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080506010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080606010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080706010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080806010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080906010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080A06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080B06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080C06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080D06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080E06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000080F06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000081006010C3F, ~PPC_BIT(54)); + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DATA_DAC_SPARE_MODE_PL + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000000006010C3F | id << 32, + ~PPC_BITMASK(53, 55)); + } + + for(unsigned int id = 0; id <= 0x10; ++id) + { + // P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000080006010C3F | id << 32, + ~PPC_BIT(54)); + } // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, PPC_BIT(54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280006010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280106010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280206010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280306010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280406010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280506010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280606010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280706010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280806010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280906010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280A06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280B06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280C06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280D06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280E06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000280F06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281006010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000281106010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300206010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300306010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300406010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300506010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300606010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300706010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300806010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300906010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300A06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300B06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300C06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300D06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300E06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000300F06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000301106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00006010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00106010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00206010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00306010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00406010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00506010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00606010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00706010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00806010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00906010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00A06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00B06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00C06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00D06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00E06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C00F06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01006010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C01106010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200106010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200206010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200306010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200406010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200506010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200606010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200706010C3F, ~PPC_BIT(48)); - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200806010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200906010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200A06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200B06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200C06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200D06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200E06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002200F06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002201006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002201106010C3F, PPC_BIT(48)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000080006010C3F | 0x11 << 32, + PPC_BIT(54)); + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL5_EO_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000280006010C3F | id << 32, + ~PPC_BITMASK(44, 56)); + } + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL6_EO_PL + scom_and_or_for_chiplet(XB_CHIPLET_ID, + 0x8000300006010C3F | id << 32, + ~PPC_BITMASK(52, 60), + PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + } + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL9_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000C00006010C3F | id << 32, + ~PPC_BITMASK(48, 60)); + } + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + scom_and_for_chiplet(XB_CHIPLET_ID, + 0x8002200006010C3F | id << 32, + ~PPC_BIT(48)); + } + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00006010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00106010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00106010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00206010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00306010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00406010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00506010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00606010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(51, 52)); // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00706010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00706010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(48) | PPC_BITMASK(51, 53)); // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00806010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00806010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_H_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00906010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00906010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(48) | PPC_BITMASK(51, 53)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_G_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00A06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(51, 52)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_F_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00B06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(55, 59) | PPC_BITMASK(60, 63)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_E_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00C06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(54, 58) | PPC_BITMASK(60, 63)); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_D_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00D06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61) | PPC_BITMASK(61, 63) ); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_C_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00E06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(53, 56) | PPC_BITMASK(58, 61)); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_B_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C00F06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C00F06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(48, 51) | PPC_BITMASK(58, 62)); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C01006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C01006010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51)); + + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49) | PPC_BIT(52)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80106010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(50, 54)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80206010C3F, ~PPC_BITMASK(48, 54)); - // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80206010C3F, + ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80306010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(49, 50)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80406010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); // register P9A_XBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80506010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); // register P9A_XBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80606010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); // register P9A_XBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80706010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80706010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); // register P9A_XBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80806010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49) | PPC_BIT(52)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80906010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80906010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_GH_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(54, 55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80A06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(54, 55)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80B06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); // register P9A_XBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_EF_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80C06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49)); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_D_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(49, 50)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80D06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(49, 50)); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_C_12_ACGH_16_22 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002C80E06010C3F, ~PPC_BITMASK(48, 54)); - // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80E06010C3F, + ~PPC_BITMASK(48, 54)); + // register P9A_XBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_B_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C80F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(50, 54)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C80F06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(50, 54)); // register P9A_XBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL // IOF1_RX_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C81006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040106010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040206010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040306010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040406010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040506010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040606010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040706010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040806010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040906010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040A06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040B06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040C06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040D06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040E06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004040F06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE1_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004041006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0006010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0106010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0206010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0306010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0406010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0506010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0606010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0706010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0806010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0906010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0A06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0B06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0C06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0D06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0E06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C0F06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_MODE2_PL - // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C1006010C3F, PPC_BIT(62)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8002C81006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(49) | PPC_BIT(52)); + + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_TX0_TXPACKS[0:3]_SLICE[0:4]_TX_MODE1_PL + // IOF1_TX_WRAP_TX0_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8004040006010C3F | id << 32, + ~PPC_BIT(48)); + } + + for(unsigned int id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_TX0_TXPACKS[0:3]_SLICE[0:4]_TX_MODE2_PL + // IOF1_TX_WRAP_TX0_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x80040C0006010C3F | id << 32, + PPC_BIT(62)); + } + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0006010C3F, ~PPC_BITMASK(48, 63)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0006010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0106010C3F, ~PPC_BITMASK(48, 63)); - // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0106010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0206010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0206010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 62)); // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0306010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0306010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 63)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0406010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0406010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(60, 63)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0506010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0506010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0606010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0606010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0706010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0706010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0806010C3F, ~PPC_BITMASK(48, 63)); - // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0806010C3F, + ~PPC_BITMASK(48, 63)); + // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_H_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0906010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0906010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 54) | PPC_BITMASK(57, 59) | PPC_BITMASK(62, 63)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_G_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0A06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0A06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(52, 53) | PPC_BITMASK(57, 58) | PPC_BITMASK(62, 63)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_F_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0B06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(57, 61)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0B06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(57, 61)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_E_HALF_B_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0C06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(60, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0C06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(60, 63)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_D_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0D06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0D06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 63)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_C_0_15 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x80043C0E06010C3F, ~PPC_BITMASK(48, 63), PPC_BITMASK(59, 62)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0E06010C3F, + ~PPC_BITMASK(48, 63), + PPC_BITMASK(59, 62)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C0F06010C3F, ~PPC_BITMASK(48, 63)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C0F06010C3F, + ~PPC_BITMASK(48, 63)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C1006010C3F, ~PPC_BITMASK(48, 63)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x80043C1006010C3F, + ~PPC_BITMASK(48, 63)); + + // register P9A_XBUS_0_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48)); // register P9A_XBUS_0_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440106010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440106010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(48, 52)); // register P9A_XBUS_0_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440206010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440206010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(48, 51) | PPC_BITMASK(53, 54)); // register P9A_XBUS_0_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440306010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440306010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440406010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440406010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440506010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(50)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440506010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(50)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440606010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440606010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); // register P9A_XBUS_0_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440706010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440706010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440806010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440806010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_H_HALF_B_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440906010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(51, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440906010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(51, 53)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440A06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440A06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); // register P9A_XBUS_0_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_F_HALF_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440B06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440B06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_E_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440C06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440C06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_DG_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440D06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(51, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440D06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(51, 52)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_C_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440E06010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48) | PPC_BITMASK(50, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440E06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48) | PPC_BITMASK(50, 53)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_B_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004440F06010C3F, ~PPC_BITMASK(48, 54), PPC_BITMASK(48, 52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004440F06010C3F, + ~PPC_BITMASK(48, 54), + PPC_BITMASK(48, 52)); // register P9A_XBUS_0_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX0_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004441006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(48)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8004441006010C3F, + ~PPC_BITMASK(48, 54), + PPC_BIT(48)); + + // register P9A_XBUS_0_RX0_RX_SPARE_MODE_PG // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008000006010C3F, PPC_BIT(49)); + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008000006010C3F, + PPC_BIT(49)); // register P9A_XBUS_0_RX0_RX_ID1_PG - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008080006010C3F, ~PPC_BITMASK(48, 53)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8008080006010C3F, + ~PPC_BITMASK(48, 53)); // register P9A_XBUS_0_RX0_RX_CTL_MODE1_EO_PG // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_CLKDIST_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8008100006010C3F, ~PPC_BIT(48)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8008100006010C3F, + ~PPC_BIT(48)); // register P9A_XBUS_0_RX0_RX_CTL_MODE5_EO_PG // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 // IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008300006010C3F, ~PPC_BITMASK(51, 55), PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008300006010C3F, + ~PPC_BITMASK(51, 55), + PPC_BIT(51) | PPC_BIT(53) | PPC_BIT(55)); // register P9A_XBUS_0_RX0_RX_CTL_MODE7_EO_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008400006010C3F, ~PPC_BITMASK(60, 63), PPC_BIT(62) | PPC_BIT(60)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008400006010C3F, + ~PPC_BITMASK(60, 63), + PPC_BIT(62) | PPC_BIT(60)); // register P9A_XBUS_0_RX0_RX_CTL_MODE23_EO_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008C00006010C3F, ~PPC_BITMASK(55, 60), PPC_BIT(51) | PPC_BITMASK(56, 60)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008C00006010C3F, + ~PPC_BITMASK(55, 60), + PPC_BIT(51) | PPC_BITMASK(56, 60)); // register P9A_XBUS_0_RX1_RX_CTL_MODE23_EO_PG // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_LTE_EN_OFF // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFEHISPD_EN_ON // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DFE12_EN_ON - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8008D00006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8008D00006010C3F, + ~PPC_BITMASK(48, 63), + PPC_BIT(51) | PPC_BIT(57) | PPC_BIT(61)); // register P9A_XBUS_0_RX1_RX_CTL_MODE29_EO_PG - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009700006010C3F, PPC_BIT(48)); + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009700006010C3F, + PPC_BIT(48)); // register P9A_XBUS_0_RX1_RX_CTL_MODE27_EO_PG // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009800006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009800006010C3F, + ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), + PPC_BIT(59)); // P9A_XBUS_0_RX1_RX_ID2_PG - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8009900006010C3F, PPC_BITMASK(57, 58)); + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009900006010C3F, + PPC_BITMASK(57, 58)); // P9A_XBUS_0_RX1_RX_CTL_MODE1_E_PG // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_MASTER_MODE_MASTER // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PDWN_LITE_DISABLE_ON // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_FENCE_FENCED - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009980006010C3F, ~PPC_BITMASK(48, 52), PPC_BIT(52)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009980006010C3F, + ~PPC_BITMASK(48, 52), + PPC_BIT(52)); // register P9A_XBUS_0_RX1_RX_CTL_MODE2_E_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009A00006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(48) | PPC_BITMASK(50, 51)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009A00006010C3F, + ~PPC_BITMASK(48, 51), + PPC_BIT(48) | PPC_BITMASK(50, 51)); // register P9A_XBUS_0_RX1_RX_CTL_MODE3_E_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B00006010C3F, ~PPC_BITMASK(48, 51), PPC_BIT(51)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009B00006010C3F, + ~PPC_BITMASK(48, 51), + PPC_BIT(51)); // register P9A_XBUS_0_RX1_RX_CTL_MODE5_E_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009B80006010C3F, ~PPC_BITMASK(44, 56), PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009B80006010C3F, + ~PPC_BITMASK(44, 56), + PPC_BIT(50) | PPC_BIT(54) | PPC_BIT(57) | PPC_BIT(61)); // register P9A_XBUS_0_RX1_RX_CTL_MODE6_E_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009C80006010C3F, ~(PPC_BITMASK(48, 58) | PPC_BITMASK(61, 63)), PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009C80006010C3F, + ~(PPC_BITMASK(48, 58) | PPC_BITMASK(61, 63)), + PPC_BITMASK(51, 54) | PPC_BIT(56) | PPC_BIT(58) | PPC_BIT(61) | PPC_BIT(63)); // register P9A_XBUS_0_RX1_RX_CTL_MODE8_E_PG // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR1_DURATION_TAP5 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009D00006010C3F, ~PPC_BITMASK(48, 58), PPC_BITMASK(50, 56) | PPC_BIT(58)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009D00006010C3F, + ~PPC_BITMASK(48, 58), + PPC_BITMASK(50, 56) | PPC_BIT(58)); // register P9A_XBUS_0_RX1_RX_CTL_MODE9_E_PG // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DYN_RPR_ERR_CNTR2_DURATION_TAP5 - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8009E00006010C3F, ~PPC_BITMASK(48, 55)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8009E00006010C3F, + ~PPC_BITMASK(48, 55)); // register P9A_XBUS_0_RX1_RX_CTL_MODE12_E_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8009E80006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8009E80006010C3F, + ~PPC_BITMASK(48, 55), + PPC_BITMASK(49, 55)); // register P9A_XBUS_0_RX1_RX_GLBSM_SPARE_MODE_PG // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_DESKEW_BUMP_AFTER_AFTER // IOF1_RX_RX1_RXCTL_GLBSM_REGS_RX_PG_GLBSM_SPARE_MODE_2_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800A800006010C3F, PPC_BIT(11) | PPC_BIT(35)); + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x800A800006010C3F, + PPC_BIT(11) | PPC_BIT(35)); // register P9A_XBUS_0_RX1_RX_GLBSM_CNTL3_EO_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AE80006010C3F, ~PPC_BITMASK(56, 57), PPC_BIT(58)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800AE80006010C3F, + ~PPC_BITMASK(56, 57), + PPC_BIT(58)); // register P9A_XBUS_0_RX1_RX_GLBSM_MODE1_EO_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800AF80006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800AF80006010C3F, + ~PPC_BITMASK(48, 55), + PPC_BITMASK(48, 49) | PPC_BITMASK(52, 53)); // register P9A_XBUS_0_RX1_RX_DATASM_SPARE_MODE_PG // IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800B800006010C3F, ~PPC_BIT(60)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800B800006010C3F, + ~PPC_BIT(60)); // register P9A_XBUS_0_TX1_TX_SPARE_MODE_PG - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C040006010C3F, ~PPC_BITMASK(56, 57)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800C040006010C3F, + ~PPC_BITMASK(56, 57)); // register P9A_XBUS_0_TX1_TX_ID1_PG - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C0C0006010C3F, ~PPC_BITMASK(48, 53)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800C0C0006010C3F, + ~PPC_BITMASK(48, 53)); // register P9A_XBUS_0_TX1_TX_CTL_MODE1_EO_PG // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_CLKDIST_PDWN_OFF // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_PDWN_LITE_DISABLE_ON - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C140006010C3F, ~(PPC_BITMASK(53, 57) | PPC_BIT(48)), PPC_BIT(57) | PPC_BIT(59)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C140006010C3F, + ~(PPC_BITMASK(53, 57) | PPC_BIT(48)), + PPC_BIT(57) | PPC_BIT(59)); // register P9A_XBUS_0_TX1_TX_CTL_MODE2_EO_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C1C0006010C3F, ~PPC_BITMASK(56, 62), PPC_BIT(58) | PPC_BIT(62)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C1C0006010C3F, + ~PPC_BITMASK(56, 62), + PPC_BIT(58) | PPC_BIT(62)); // register P9A_XBUS_0_TX1_TX_CTL_CNTLG1_EO_PG // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DRV_CLK_PATTERN_GCRMSG_DRV_0S - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800C240006010C3F, ~PPC_BITMASK(48, 49)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800C240006010C3F, + ~PPC_BITMASK(48, 49)); // register P9A_XBUS_0_TX1_TX_ID2_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C840006010C3F, ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), PPC_BIT(59)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C840006010C3F, + ~(PPC_BITMASK(49, 55) | PPC_BITMASK(57, 63)), + PPC_BIT(59)); // register P9A_XBUS_0_TX1_TX_CTL_MODE1_E_PG // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_INTERVAL_TIMEOUT_SEL_TAP5 // IOF1_TX_WRAP_TX1_TXCTL_CTL_REGS_TX_CTL_REGS_TX_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_TAP1 - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800C8C0006010C3F, ~PPC_BITMASK(55, 59), PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800C8C0006010C3F, + ~PPC_BITMASK(55, 59), + PPC_BIT(55) | PPC_BIT(57) | PPC_BIT(59)); // register P9A_XBUS_0_TX1_TX_CTL_MODE2_E_PG - scom_and_for_chiplet(XB_CHIPLET_ID, 0x800CEC0006010C3F, ~PPC_BITMASK(48, 55)); + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x800CEC0006010C3F, + ~PPC_BITMASK(48, 55)); // register P9A_XBUS_0_TX1_TX_CTL_MODE3_E_PG - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800CF40006010C3F, ~PPC_BITMASK(48, 55), PPC_BITMASK(49, 55)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800CF40006010C3F, + ~PPC_BITMASK(48, 55), + PPC_BITMASK(49, 55)); // register P9A_XBUS_0_TX1_TX_CTLSM_MODE1_EO_PG // IOF1_TX_WRAP_TX1_TXCTL_TX_CTL_SM_REGS_TX_FFE_BOOST_EN_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x800D2C0006010C3F, PPC_BIT(59)); + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x800D2C0006010C3F, + PPC_BIT(59)); // register P9A_XBUS_0_TX_IMPCAL_P_4X_PB - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x800F1C0006010C3F, ~PPC_BITMASK(48, 52), PPC_BITMASK(49, 51)); + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x800F1C0006010C3F, + ~PPC_BITMASK(48, 52), + PPC_BITMASK(49, 51)); } void p9_xbus_g1_scom() From aa24675119baa7e7977625309caafd0116f3e4d1 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 5 Mar 2021 12:55:12 +0100 Subject: [PATCH 86/90] src/soc/ibm/power9/istep_8_10.c Clean up sitep 8.10 p9_xbus_g1_scom() --- src/soc/ibm/power9/istep_8_10.c | 495 ++++++-------------------------- 1 file changed, 93 insertions(+), 402 deletions(-) diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 8c601563264..74e340a035c 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -818,312 +818,75 @@ void p9_xbus_g0_scom() void p9_xbus_g1_scom() { - // register P9A_XBUS_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - //l_IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002006010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002106010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002206010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002306010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002406010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002506010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002606010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002706010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002806010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002906010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002A06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002B06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002C06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002D06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002E06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000002F06010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF); - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF); - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003006010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000003106010C3F, ~PPC_BITMASK(53, 55)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082006010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082106010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082206010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082306010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082406010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082506010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082606010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082706010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082806010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082906010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082A06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082B06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082C06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082D06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082E06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000082F06010C3F, ~PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000083006010C3F, ~PPC_BIT(54)); + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DATA_DAC_SPARE_MODE_PL + // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF + // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF + // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000002006010C3F | id << 32, + ~PPC_BITMASK(53, 55)); + } + + for(unsigned int id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL1_EO_PL + // IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000082006010C3F | id << 32, + ~PPC_BIT(54)); + } // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000083106010C3F, PPC_BIT(54)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282006010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282106010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282206010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282306010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282406010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282506010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282606010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282706010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282806010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282906010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282A06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282B06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282C06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282D06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282E06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000282F06010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283006010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000283106010C3F, ~PPC_BITMASK(44, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302206010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302306010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302406010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302506010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302606010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302706010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302806010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302906010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302A06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302B06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302C06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302D06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302E06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000302F06010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_ - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303006010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL - scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8000303106010C3F, ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02006010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02106010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_ - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02206010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02306010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_P - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02406010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02506010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02606010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02706010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02806010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02906010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02A06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02B06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02C06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02D06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02E06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C02F06010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03006010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8000C03106010C3F, ~PPC_BITMASK(48, 60)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202106010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202206010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202306010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202406010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202506010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202606010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_1_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202706010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202806010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202906010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202A06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202B06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_1_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202C06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202D06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_0_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202E06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_4_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002202F06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL - // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8002203006010C3F, ~PPC_BIT(48)); + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x8000083106010C3F | 0x11 << 32, + PPC_BIT(54)); + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL5_EO_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000282006010C3F | id << 32, + ~PPC_BITMASK(44, 56)); + } + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL6_EO_PL + scom_and_or_for_chiplet( + XB_CHIPLET_ID, + 0x8000302006010C3F | id << 32, + ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); + } + + for(unsigned int id = 0; id <= 0x11; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL9_E_PL + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8000C02006010C3F | id << 32, + ~PPC_BITMASK(48, 60)); + } + + for(unsigned int id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_BIT_MODE1_EO_PL + // IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8002202006010C3F | id << 32, + ~PPC_BIT(48)); + } // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002203106010C3F, PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F | 0x11 << 32, PPC_BIT(48)); + + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C02006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); @@ -1174,6 +937,8 @@ void p9_xbus_g1_scom() // register P9A_XBUS_0_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_0_15_PATTERN_24_A_0_15 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C03006010C3F, ~PPC_BITMASK(48, 63), PPC_BIT(51)); + + // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL // IOF1_RX_RX1_RXPACKS_0_RXPACK_RD_SLICE_2_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C82006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); @@ -1225,106 +990,28 @@ void p9_xbus_g1_scom() // register P9A_XBUS_0_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL // IOF1_RX_RX1_RXPACKS_3_RXPACK_RD_SLICE_5_RD_RX_BIT_REGS_RX_PRBS_SEED_VALUE_16_22_PATTERN_24_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042106010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042206010C3F, ~PPC_BIT(48)); - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042306010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042406010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042506010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042606010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042706010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042806010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042906010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042A06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042B06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042C06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042D06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042E06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004042F06010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE1_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED - scom_and_for_chiplet(XB_CHIPLET_ID, 0x8004043006010C3F, ~PPC_BIT(48)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2006010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2106010C3F, PPC_BIT(62)); - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2206010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS0_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2306010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2406010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2506010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2606010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS1_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_1_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2706010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2806010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2906010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2A06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS2_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_2_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2B06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE0_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2C06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE1_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_1_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2D06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE2_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_2_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2E06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE3_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_3_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C2F06010C3F, PPC_BIT(62)); - // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_MODE2_PL - // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x80040C3006010C3F, PPC_BIT(62)); + + + for(unsigned int id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_TX1_TXPACKS[0:3]_SLICE[0:4]_TX_MODE1_PL + // IOF1_TX_WRAP_TX1_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED + scom_and_for_chiplet( + XB_CHIPLET_ID, + 0x8004042006010C3F | id << 32, + ~PPC_BIT(48)); + } + + for(unsigned int id = 0; id <= 0x10; ++id) + { + // register P9A_XBUS_0_TX1_TXPACKS[0:3]_SLICE[0:4]_TX_MODE2_PL + // IOF1_TX_WRAP_TX1_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON + scom_or_for_chiplet( + XB_CHIPLET_ID, + 0x80040C2006010C3F | id << 32, + PPC_BIT(62)); + } + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C2006010C3F, ~PPC_BITMASK(48, 63)); @@ -1376,6 +1063,8 @@ void p9_xbus_g1_scom() // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_0_15_PATTERN_TX_AB_HALF_A_0_15 scom_and_for_chiplet(XB_CHIPLET_ID, 0x80043C3006010C3F, ~PPC_BITMASK(48, 63)); + + // register P9A_XBUS_0_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX1_TXPACKS_0_TXPACK_DD_SLICE_0_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004442006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); @@ -1427,6 +1116,8 @@ void p9_xbus_g1_scom() // register P9A_XBUS_0_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL // IOF1_TX_WRAP_TX1_TXPACKS_3_TXPACK_DD_SLICE_4_DD_TX_BIT_REGS_TX_PRBS_SEED_VALUE_16_22_PATTERN_TX_A_16_22 scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8004443006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(54)); + + // register P9A_XBUS_0_RX1_RX_SPARE_MODE_PG // IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_1_ON scom_or_for_chiplet(XB_CHIPLET_ID, 0x8008002006010C3F, PPC_BIT(49)); From 9c04be1ba33e6e660c9956ef798c64c3dbb41d83 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 5 Mar 2021 13:09:56 +0100 Subject: [PATCH 87/90] src/soc/ibm/power9/Makefile.inc: Rename CPU_IBM_POWER9 to SOC_IBM_POWER9 --- src/mainboard/raptor-cs/talos-2/Kconfig | 3 ++- src/soc/ibm/power9/Kconfig | 4 ++-- src/soc/ibm/power9/Makefile.inc | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig index ba231306bfd..066849c80af 100644 --- a/src/mainboard/raptor-cs/talos-2/Kconfig +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -4,7 +4,8 @@ if BOARD_RAPTOR_CS_TALOS_2 config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_IBM_POWER9 + select CPU_POWER9 + select SOC_IBM_POWER9 select BOARD_ROMSIZE_KB_16384 select ARCH_BOOTBLOCK_PPC64 select ARCH_VERSTAGE_PPC64 diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig index a94c41d606c..756ac70537d 100644 --- a/src/soc/ibm/power9/Kconfig +++ b/src/soc/ibm/power9/Kconfig @@ -1,9 +1,9 @@ -config CPU_IBM_POWER9 +config SOC_IBM_POWER9 bool help This SoC is the minimal template working on POWER9 Talos II platform. -if CPU_IBM_POWER9 +if SOC_IBM_POWER9 # nothing here yet endif diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index eaabab43919..60809afd480 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CPU_IBM_POWER9),y) +ifeq ($(SOC_IBM_POWER9),y) bootblock-y += bootblock.c postcar-y += exit_car.S From 33d090b6e51f7680a72e9c3e2f155b0583244f91 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 3 Sep 2021 10:55:39 +0200 Subject: [PATCH 88/90] Implement istep 8.9, 8.10 on top of staging branch Signed-off-by: Igor Bagnucki --- src/include/cpu/power/istep_8.h | 91 +++++++ src/include/cpu/power/istep_8_10.h | 12 - src/include/cpu/power/istep_8_9.h | 22 -- src/include/cpu/power/scom.h | 33 ++- src/soc/ibm/power9/Makefile.inc | 26 +- src/soc/ibm/power9/istep_8_10.c | 45 ++-- src/soc/ibm/power9/istep_8_9.c | 13 +- src/soc/ibm/power9/romstage.c | 381 ++++++++++++++++++++++++++++- 8 files changed, 542 insertions(+), 81 deletions(-) create mode 100644 src/include/cpu/power/istep_8.h delete mode 100644 src/include/cpu/power/istep_8_10.h delete mode 100644 src/include/cpu/power/istep_8_9.h diff --git a/src/include/cpu/power/istep_8.h b/src/include/cpu/power/istep_8.h new file mode 100644 index 00000000000..714a34c0968 --- /dev/null +++ b/src/include/cpu/power/istep_8.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) +#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) +#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) + +#define ATTR_PROC_FABRIC_X_LINKS_CNFG (1) + +#define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) +#define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) + +#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) +#define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) + +#define FBC_IOE_DL_FIR_ACTION0 (0) +#define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) +#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) + +// Power Bus PB West Mode Configuration Register +#define PB_WEST_MODE_CFG_REG (0x501180A) +// Power Bus PB CENT FIR Register +#define PB_CENT_SM0_PB_CENT_FIR_REG (0x5011C00) +// Power Bus PB CENT Mode Register +#define PB_CENT_MODE_CFG_REG (0x5011C0A) +// Power Bus PB CENT GP command RATE DP0 Register +#define PB_CENT_GP_COMMAND_RATE_DP0_REG (0x5011C26) +// Power Bus PB CENT GP command RATE DP1 Register +#define PB_CENT_GP_COMMAND_RATE_DP1_REG (0x5011C27) +// Power Bus PB CENT RGP command RATE DP0 Register +#define PB_CENT_RGP_COMMAND_RATE_DP0_REG (0x5011C28) +// Power Bus PB CENT RGP command RATE DP1 Register +#define PB_CENT_RGP_COMMAND_RATE_DP1_REG (0x5011C29) +// Power Bus PB CENT SP command RATE DP0 Register +#define PB_CENT_SP_COMMAND_RATE_DP0_REG (0x5011C2A) +// Power Bus PB CENT SP command RATE DP1 Register +#define PB_CENT_SP_COMMAND_RATE_DP1_REG (0x5011C2B) +// Power Bus PB East Mode Configuration Register +#define PB_EAST_MODE_CFG_REG (0x501200A) +// Power Bus PBEN IOX Domain FIR0 Mask Register +#define PU_PB_IOE_FIR_MASK_REG (0x5013403) +// Power Bus PBEN IOX Domain FIR Action 0 Register +#define PU_PB_IOE_FIR_ACTION0_REG (0x5013406) +// Power Bus PBEN IOX Domain FIR Action 1 Register +#define PU_PB_IOE_FIR_ACTION1_REG (0x5013407) +// Power bus Electrical Framer/Parser 01 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_01_CFG_REG (0x501340A) +// Power Bus Electrical Framer/Parser 23 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_23_CFG_REG (0x501340B) +// Power Bus Electrical Framer/Parser 45 Configuration Register +#define PB_ELE_PB_FRAMER_PARSER_45_CFG_REG (0x501340C) +// Power Bus Electrical Link Data Buffer 01 Configuration Register +#define PB_ELE_PB_DATA_BUFF_01_CFG_REG (0x5013410) +// Power Bus Electrical Link Data Buffer 23 Configuration Register +#define PB_ELE_PB_DATA_BUFF_23_CFG_REG (0x5013411) +// Power Bus Electrical Link Data Buffer 45 Configuration Register +#define PB_ELE_PB_DATA_BUFF_45_CFG_REG (0x5013412) +// Power Bus Electrical Miscellaneous Configuration Register +#define PB_ELE_MISC_CFG_REG (0x5013423) +// Power Bus Electrical Link Trace Configuration Register +#define PB_ELE_LINK_TRACE_CFG_REG (0x5013424) +// ELL FIR Mask Register +#define XBUS_LL0_IOEL_FIR_MASK_REG (0x6011803) +// ELL FIR Action 0 Register +#define XBUS_LL0_IOEL_FIR_ACTION0_REG (0x6011806) +// ELL FIR Action 1 Register +#define XBUS_LL0_IOEL_FIR_ACTION1_REG (0x6011807) +// Power Bus ELL Configuration Register +#define PB_ELL_CFG_REG (0x601180A) +// Power Bus ELL Replay Threshold Register +#define PB_ELL_REPLAY_TRESHOLD_REG (0x6011818) +// Power Bus ELL SL ECC Threshold Register +#define PB_ELL_SL_ECC_TRESHOLD_REG (0x6011819) +#define XBUS_FIR_MASK_REG (0x6010C03) +#define XBUS_FIR_ACTION0_REG (0x6010C06) +#define XBUS_FIR_ACTION1_REG (0x6010C07) + +void istep_8_10(void); +void p9_io_xbus_scominit(const uint8_t); +void p9_xbus_g0_scom(void); +void p9_xbus_g1_scom(void); + +void istep_8_9(void); +void p9_fbc_ioe_dl_scom(void); +void p9_fbc_ioe_tl_scom(void); +void p9_fbc_no_hp_scom(void); +void ioe_tl_fir(void); +void ioel_fir(void); + + diff --git a/src/include/cpu/power/istep_8_10.h b/src/include/cpu/power/istep_8_10.h deleted file mode 100644 index 8319050ed15..00000000000 --- a/src/include/cpu/power/istep_8_10.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#define XBUS_PHY_FIR_ACTION0 (0x0000000000000000ULL) -#define XBUS_PHY_FIR_ACTION1 (0x2068680000000000ULL) -#define XBUS_PHY_FIR_MASK (0xDF9797FFFFFFC000ULL) - -void istep_8_10(void); -void p9_io_xbus_scominit(const uint8_t); -void p9_xbus_g0_scom(void); -void p9_xbus_g1_scom(void); diff --git a/src/include/cpu/power/istep_8_9.h b/src/include/cpu/power/istep_8_9.h deleted file mode 100644 index 6d57392e53e..00000000000 --- a/src/include/cpu/power/istep_8_9.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#define ATTR_PROC_FABRIC_X_LINKS_CNFG (1) - -#define FBC_IOE_TL_FIR_ACTION0 (0x0000000000000000ULL) -#define FBC_IOE_TL_FIR_ACTION1 (0x0049000000000000ULL) - -#define FBC_IOE_TL_FIR_MASK (0xFF24F0303FFFF11FULL) -#define FBC_IOE_TL_FIR_MASK_X0_NF (0x00C00C0C00000880ULL) - -#define FBC_IOE_DL_FIR_ACTION0 (0) -#define FBC_IOE_DL_FIR_ACTION1 (0x303c00000001ffc) -#define FBC_IOE_DL_FIR_MASK (0xfcfc3fffffffe003) - -void istep_8_9(void); -void p9_fbc_ioe_dl_scom(void); -void p9_fbc_ioe_tl_scom(void); -void p9_fbc_no_hp_scom(void); -void ioe_tl_fir(void); -void ioel_fir(void); diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h index 85d3c263389..8a30387e53d 100644 --- a/src/include/cpu/power/scom.h +++ b/src/include/cpu/power/scom.h @@ -86,14 +86,28 @@ typedef enum EC23_CHIPLET_ID = 0x37 ///< Core23 chiplet (Quad5, EX11, C1) } chiplet_id_t; +static const chiplet_id_t mcs_to_nest[] = +{ + [MC01_CHIPLET_ID] = N3_CHIPLET_ID, + [MC23_CHIPLET_ID] = N1_CHIPLET_ID, +}; + void reset_scom_engine(void); static uint64_t read_scom_direct(uint64_t reg_address) { uint64_t val; - uint64_t hmer; + uint64_t hmer = 0; do { - clear_hmer(); + /* + * Clearing HMER on every SCOM access seems to slow down CCS up + * to a point where it starts hitting timeout on "less ideal" + * DIMMs for write centering. Clear it only if this do...while + * executes more than once. + */ + if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) + clear_hmer(); + eieio(); asm volatile( "ldcix %0, %1, %2": @@ -118,9 +132,12 @@ static uint64_t read_scom_direct(uint64_t reg_address) static void write_scom_direct(uint64_t reg_address, uint64_t data) { - uint64_t hmer; + uint64_t hmer = 0; do { - clear_hmer(); + /* See comment in read_scom_direct() */ + if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) + clear_hmer(); + eieio(); asm volatile( "stdcix %0, %1, %2":: @@ -135,14 +152,6 @@ static void write_scom_direct(uint64_t reg_address, uint64_t data) reset_scom_engine(); } -/* - * WARNING: - * Indirect access uses the same approach as Hostboot, yet all our tests so far - * were unsuccessful. It is possible that the devices we were trying to access - * must be initialized or otherwise enabled first. Because of that we decided to - * leave it as it is for now, with heavy debugging, and return to this when we - * are sure that it doesn't work because of error in implementation. - */ uint64_t read_scom_indirect(uint64_t reg_address); void write_scom_indirect(uint64_t reg_address, uint64_t data); diff --git a/src/soc/ibm/power9/Makefile.inc b/src/soc/ibm/power9/Makefile.inc index 60809afd480..f0d092b103c 100644 --- a/src/soc/ibm/power9/Makefile.inc +++ b/src/soc/ibm/power9/Makefile.inc @@ -1,14 +1,34 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(SOC_IBM_POWER9),y) +ifeq ($(CONFIG_CPU_IBM_POWER9),y) bootblock-y += bootblock.c -postcar-y += exit_car.S +bootblock-y += rom_media.c +romstage-y += rom_media.c romstage-y += romstage.c +romstage-y += vpd.c romstage-y += istep_8_9.c romstage-y += istep_8_10.c - +romstage-y += istep_13_2.c +romstage-y += istep_13_3.c +romstage-y += istep_13_4.c +romstage-y += istep_13_6.c +romstage-y += istep_13_8.c +romstage-y += istep_13_9.c +romstage-y += istep_13_10.c +romstage-y += istep_13_11.c +romstage-y += istep_13_13.c +romstage-y += istep_14_1.c +romstage-y += istep_14_2.c +romstage-y += istep_14_3.c +romstage-y += istep_14_5.c +romstage-y += i2c.c +romstage-y += ccs.c +romstage-y += timer.c ramstage-y += chip.c +ramstage-y += rom_media.c ramstage-y += timer.c +ramstage-y += istep_18_11.c +ramstage-y += istep_18_12.c endif diff --git a/src/soc/ibm/power9/istep_8_10.c b/src/soc/ibm/power9/istep_8_10.c index 74e340a035c..1ae419500f9 100644 --- a/src/soc/ibm/power9/istep_8_10.c +++ b/src/soc/ibm/power9/istep_8_10.c @@ -2,9 +2,8 @@ #include #include -#include +#include #include -#include #include #include @@ -12,8 +11,8 @@ void istep_8_10(void) { printk(BIOS_EMERG, "starting istep 8.10\n"); report_istep(8, 10); - // p9_io_xbus_scominit(0); - // p9_io_xbus_scominit(1); + p9_io_xbus_scominit(0); + p9_io_xbus_scominit(1); printk(BIOS_EMERG, "ending istep 8.10\n"); return; } @@ -44,7 +43,7 @@ void p9_io_xbus_scominit(const uint8_t group) void p9_xbus_g0_scom() { - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DATA_DAC_SPARE_MODE_PL // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF @@ -56,7 +55,7 @@ void p9_xbus_g0_scom() ~PPC_BITMASK(53, 55)); } - for(unsigned int id = 0; id <= 0x10; ++id) + for(uint64_t id = 0; id <= 0x10; ++id) { // P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL1_EO_PL // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF @@ -70,10 +69,10 @@ void p9_xbus_g0_scom() scom_or_for_chiplet(XB_CHIPLET_ID, 0x8000081106010C3F, PPC_BIT(54)); scom_and_for_chiplet( XB_CHIPLET_ID, - 0x8000080006010C3F | 0x11 << 32, + 0x8000080006010C3F | 0x11ull << 32, PPC_BIT(54)); - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet( @@ -82,7 +81,7 @@ void p9_xbus_g0_scom() ~PPC_BITMASK(44, 56)); } - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet(XB_CHIPLET_ID, @@ -91,7 +90,7 @@ void p9_xbus_g0_scom() PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); } - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL9_E_PL scom_and_for_chiplet( @@ -100,7 +99,7 @@ void p9_xbus_g0_scom() ~PPC_BITMASK(48, 60)); } - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX0_RXPACKS[0:3]_SLICE[0:5]_RX_BIT_MODE1_EO_PL // IOF1_RX_RX0_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF @@ -349,7 +348,7 @@ void p9_xbus_g0_scom() PPC_BIT(49) | PPC_BIT(52)); - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_TX0_TXPACKS[0:3]_SLICE[0:4]_TX_MODE1_PL // IOF1_TX_WRAP_TX0_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED @@ -359,7 +358,7 @@ void p9_xbus_g0_scom() ~PPC_BIT(48)); } - for(unsigned int id = 0; id <= 0x10; ++id) + for(uint64_t id = 0; id <= 0x10; ++id) { // register P9A_XBUS_0_TX0_TXPACKS[0:3]_SLICE[0:4]_TX_MODE2_PL // IOF1_TX_WRAP_TX0_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON @@ -818,7 +817,7 @@ void p9_xbus_g0_scom() void p9_xbus_g1_scom() { - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DATA_DAC_SPARE_MODE_PL // l_IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF @@ -830,7 +829,7 @@ void p9_xbus_g1_scom() ~PPC_BITMASK(53, 55)); } - for(unsigned int id = 0; id <= 0x10; ++id) + for(uint64_t id = 0; id <= 0x10; ++id) { // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL1_EO_PL // IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_OFF @@ -843,10 +842,10 @@ void p9_xbus_g1_scom() // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_LANE_ANA_PDWN_ON scom_or_for_chiplet( XB_CHIPLET_ID, - 0x8000083106010C3F | 0x11 << 32, + 0x8000083106010C3F | 0x11ull << 32, PPC_BIT(54)); - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL5_EO_PL scom_and_for_chiplet( @@ -855,7 +854,7 @@ void p9_xbus_g1_scom() ~PPC_BITMASK(44, 56)); } - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL6_EO_PL scom_and_or_for_chiplet( @@ -864,7 +863,7 @@ void p9_xbus_g1_scom() ~PPC_BITMASK(52, 60), PPC_BITMASK(49, 50) | PPC_BITMASK(54, 56)); } - for(unsigned int id = 0; id <= 0x11; ++id) + for(uint64_t id = 0; id <= 0x11; ++id) { // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_DAC_CNTL9_E_PL scom_and_for_chiplet( @@ -873,7 +872,7 @@ void p9_xbus_g1_scom() ~PPC_BITMASK(48, 60)); } - for(unsigned int id = 0; id <= 0x10; ++id) + for(uint64_t id = 0; id <= 0x10; ++id) { // register P9A_XBUS_0_RX1_RXPACKS[0:3]_SLICE[0:5]_RX_BIT_MODE1_EO_PL // IOF1_RX_RX1_RXPACKS_[0:3]_RXPACK_RD_SLICE_[0:5]_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_OFF @@ -884,7 +883,7 @@ void p9_xbus_g1_scom() } // register P9A_XBUS_0_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL // IOF1_RX_RX1_RXPACKS_2_RXPACK_RD_SLICE_3_RD_RX_BIT_REGS_RX_LANE_DIG_PDWN_ON - scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F | 0x11 << 32, PPC_BIT(48)); + scom_or_for_chiplet(XB_CHIPLET_ID, 0x8002202006010C3F | 0x11ull << 32, PPC_BIT(48)); // register P9A_XBUS_0_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL @@ -992,7 +991,7 @@ void p9_xbus_g1_scom() scom_and_or_for_chiplet(XB_CHIPLET_ID, 0x8002C83006010C3F, ~PPC_BITMASK(48, 54), PPC_BIT(49) | PPC_BIT(52)); - for(unsigned int id = 0; id <= 0x10; ++id) + for(uint64_t id = 0; id <= 0x10; ++id) { // register P9A_XBUS_0_TX1_TXPACKS[0:3]_SLICE[0:4]_TX_MODE1_PL // IOF1_TX_WRAP_TX1_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_LANE_PDWN_ENABLED @@ -1002,7 +1001,7 @@ void p9_xbus_g1_scom() ~PPC_BIT(48)); } - for(unsigned int id = 0; id <= 0x10; ++id) + for(uint64_t id = 0; id <= 0x10; ++id) { // register P9A_XBUS_0_TX1_TXPACKS[0:3]_SLICE[0:4]_TX_MODE2_PL // IOF1_TX_WRAP_TX1_TXPACKS_[0:3]_TXPACK_DD_SLICE_[0:4]_DD_TX_BIT_REGS_TX_CAL_LANE_SEL_ON diff --git a/src/soc/ibm/power9/istep_8_9.c b/src/soc/ibm/power9/istep_8_9.c index 0a4e165959d..18836e6a126 100644 --- a/src/soc/ibm/power9/istep_8_9.c +++ b/src/soc/ibm/power9/istep_8_9.c @@ -2,9 +2,8 @@ #include #include -#include +#include #include -#include void istep_8_9(void) { @@ -30,20 +29,20 @@ void p9_fbc_ioe_dl_scom(void) // [12:15] CONFIG_PACKET_DELAY_LIMIT: This field indicates the number // of cycles of delay of frame data that are required for the // packet to be considered delayed or replayed. (0 is 16 cycles.) - // [27:27] CONFIG_AUTO_TDM_BW_DIFF: Bandwidth difference - // for auto-entry TMD mode. - scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_CFG_REG, ~(PPC_BIT(0) | PPC_BIT(11)), PPC_BIT(2) | PPC_BIT(4) | PPC_BITMASK(12, 15) | PPC_BITMASK(24, 27)); + // [28:31] CONFIG_AUTO_TDM_ERROR_RATE: This field contains the error rate + // for the auto-entry TDM mode. + scom_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_CFG_REG, PPC_BIT(0) | PPC_BIT(2) | PPC_BIT(4) | PPC_BITMASK(12, 15) | PPC_BITMASK(28, 31)); // PB_ELL_REPLAY_TRESHOLD_REG // [0:3] THRESH_REPLAY_TB_SEL: Replay threshold timebase select. // [4:7] THRESH_REPLAY_TAP_SEL: Replay threshold tap select. // [8:10] THRESH_REPLAY_ENABLE: Replay threshold error enable. - scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_REPLAY_TRESHOLD_REG, ~PPC_BITMASK(0, 3), PPC_BITMASK(1, 2) | PPC_BITMASK(4, 10)); + scom_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_REPLAY_TRESHOLD_REG, PPC_BITMASK(1, 2) | PPC_BITMASK(4, 10)); // PB_ELL_SL_ECC_TRESHOLD_REG // [0:3] THRESH_SL_ECC_TB_SEL: SL ECC threshold timebase select. // [4:7] THRESH_SL_ECC_TAP_SEL: SL ECC threshold tap select. // [8:9] THRESH_SL_ECC_ENABLE: SL ECC threshold error enable. // [10:25] THRESH_SL_ECC_UNUSED1: Spare bits. - scom_and_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_SL_ECC_TRESHOLD_REG, ~PPC_BIT(0), PPC_BITMASK(1, 7) | PPC_BITMASK(9, 11)); + scom_or_for_chiplet(XB_CHIPLET_ID, PB_ELL_SL_ECC_TRESHOLD_REG, PPC_BITMASK(1, 10)); } void ioe_tl_fir(void) diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c index 91074b20125..b0e398e9722 100644 --- a/src/soc/ibm/power9/romstage.c +++ b/src/soc/ibm/power9/romstage.c @@ -1,7 +1,384 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include +#include +#include +#include +#include +#include +#include // hexdump +#include +#include +#include +#include -asmlinkage void car_stage_entry(void) +mcbist_data_t mem_data; + +static void dump_mca_data(mca_data_t *mca) +{ + printk(BIOS_SPEW, "\tCL = %d\n", mca->cl); + printk(BIOS_SPEW, "\tCCD_L = %d\n", mca->nccd_l); + printk(BIOS_SPEW, "\tWTR_S = %d\n", mca->nwtr_s); + printk(BIOS_SPEW, "\tWTR_L = %d\n", mca->nwtr_l); + printk(BIOS_SPEW, "\tFAW = %d\n", mca->nfaw); + printk(BIOS_SPEW, "\tRCD = %d\n", mca->nrcd); + printk(BIOS_SPEW, "\tRP = %d\n", mca->nrp); + printk(BIOS_SPEW, "\tRAS = %d\n", mca->nras); + printk(BIOS_SPEW, "\tWR = %d\n", mca->nwr); + printk(BIOS_SPEW, "\tRRD_S = %d\n", mca->nrrd_s); + printk(BIOS_SPEW, "\tRRD_L = %d\n", mca->nrrd_l); + printk(BIOS_SPEW, "\tRFC = %d\n", mca->nrfc); + printk(BIOS_SPEW, "\tRFC_DLR = %d\n", mca->nrfc_dlr); + + int i; + for (i = 0; i < 2; i++) { + if (mca->dimm[i].present) { + printk(BIOS_SPEW, "\tDIMM%d: %dRx%d ", i, mca->dimm[i].mranks, + (mca->dimm[i].width + 1) * 4); + + if (mca->dimm[i].log_ranks != mca->dimm[i].mranks) + printk(BIOS_SPEW, "%dH 3DS ", mca->dimm[i].log_ranks / mca->dimm[i].mranks); + + printk(BIOS_SPEW, "%dGB\n", mca->dimm[i].size_gb); + } + else + printk(BIOS_SPEW, "\tDIMM%d: not installed\n", i); + } +} + +/* TODO: add checks for same ranks configuration for both DIMMs under one MCA */ +static inline bool is_proper_dimm(spd_raw_data spd, int slot) +{ + struct dimm_attr_ddr4_st attr; + if (spd == NULL) + return false; + + if (spd_decode_ddr4(&attr, spd) != SPD_STATUS_OK) { + printk(BIOS_ERR, "Malformed SPD for slot %d\n", slot); + return false; + } + + if (attr.dram_type != SPD_MEMORY_TYPE_DDR4_SDRAM || + attr.dimm_type != SPD_DDR4_DIMM_TYPE_RDIMM || + attr.ecc_extension == false) { + printk(BIOS_ERR, "Bad DIMM type in slot %d\n", slot); + return false; + } + + return true; +} + +static void mark_nonfunctional(int mcs, int mca) +{ + mem_data.mcs[mcs].mca[mca].functional = false; + + /* Propagate upwards */ + if (mem_data.mcs[mcs].mca[mca ^ 1].functional == false) { + mem_data.mcs[mcs].functional = false; + if (mem_data.mcs[mcs ^ 1].functional == false) + die("No functional MCS left"); + } +} + +static uint64_t find_min_mtb_ftb(rdimm_data_t *dimm, int mtb_idx, int ftb_idx) +{ + uint64_t val0 = 0, val1 = 0; + + if (dimm[0].present) + val0 = mtb_ftb_to_nck(dimm[0].spd[mtb_idx], (int8_t)dimm[0].spd[ftb_idx]); + if (dimm[1].present) + val1 = mtb_ftb_to_nck(dimm[1].spd[mtb_idx], (int8_t)dimm[1].spd[ftb_idx]); + + return (val0 < val1) ? val1 : val0; +} + +static uint64_t find_min_multi_mtb(rdimm_data_t *dimm, int mtb_l, int mtb_h, uint8_t mask, int shift) +{ + uint64_t val0 = 0, val1 = 0; + + if (dimm[0].present) + val0 = dimm[0].spd[mtb_l] | ((dimm[0].spd[mtb_h] & mask) << shift); + if (dimm[1].present) + val1 = dimm[1].spd[mtb_l] | ((dimm[1].spd[mtb_h] & mask) << shift); + + return (val0 < val1) ? mtb_ftb_to_nck(val1, 0) : mtb_ftb_to_nck(val0, 0); +} + +/* https://review.coreboot.org/c/coreboot/+/52061 */ +/* DIMM SPD addresses */ +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + +/* This is most of step 7 condensed into one function */ +static void prepare_dimm_data(void) { + int i, mcs, mca; + int tckmin = 0x06; // Platform limit + + /* + * DIMMs 4-7 are under a different port. This is not the same as bus, but we + * need to pass that information to I2C function. As there is no easier way, + * use MSB of address and mask it out at the receiving side. This will print + * wrong addresses in dump_spd_info(), but that is small price to pay. + */ + struct spd_block blk = { + .addr_map = { DIMM0, DIMM1, DIMM2, DIMM3, + DIMM4 | 0x80, DIMM5 | 0x80, DIMM6 | 0x80, DIMM7 | 0x80}, + }; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + /* + * We need to find the highest common (for all DIMMs and the platform) + * supported frequency, meaning we need to compare minimum clock cycle times + * and choose the highest value. For the range supported by the platform we + * can check MTB only. + * + * TODO: check if we can have different frequencies across MCSs. + */ + for (i = 0; i < CONFIG_DIMM_MAX; i++) { + if (is_proper_dimm(blk.spd_array[i], i)) { + mcs = i / DIMMS_PER_MCS; + mca = (i % DIMMS_PER_MCS) / MCA_PER_MCS; + int dimm_idx = i % 2; // (i % DIMMS_PER_MCS) % MCA_PER_MCS + + + /* Maximum for 2 DIMMs on one port (channel, MCA) is 2400 MT/s */ + if (tckmin < 0x07 && mem_data.mcs[mcs].mca[mca].functional) + tckmin = 0x07; + + mem_data.mcs[mcs].functional = true; + mem_data.mcs[mcs].mca[mca].functional = true; + + rdimm_data_t *dimm = &mem_data.mcs[mcs].mca[mca].dimm[dimm_idx]; + + dimm->present = true; + dimm->spd = blk.spd_array[i]; + /* RCD address is the same as SPD, with one additional bit set */ + dimm->rcd_i2c_addr = blk.addr_map[i] | 0x08; + /* + * SPD fields in spd.h are not compatible with DDR4 and those in + * spd_bin.h are just a few of all required. + * + * TODO: add fields that are lacking to either of those files or + * add a file specific to DDR4 SPD. + */ + dimm->width = blk.spd_array[i][12] & 7; + dimm->mranks = ((blk.spd_array[i][12] >> 3) & 0x7) + 1; + dimm->log_ranks = dimm->mranks * (((blk.spd_array[i][6] >> 4) & 0x7) + 1); + dimm->density = blk.spd_array[i][4] & 0xF; + dimm->size_gb = (1 << (dimm->density - 2)) * (2 - dimm->width) * + dimm->log_ranks; + + if ((blk.spd_array[i][5] & 0x38) == 0x30) + die("DIMMs with 18 row address bits are not supported\n"); + + if (blk.spd_array[i][18] > tckmin) + tckmin = blk.spd_array[i][18]; + } + } + + /* + * There is one (?) MCBIST per CPU. Fail if there are no supported DIMMs + * connected, otherwise assume it is functional. There is no reason to redo + * this test in the rest of isteps. + * + * TODO: 2 CPUs with one DIMM (in total) will not work with this code. + */ + if (mem_data.mcs[0].functional == false && mem_data.mcs[1].functional == false) + die("No DIMMs detected, aborting\n"); + + switch (tckmin) { + /* For CWL assume 1tCK write preamble */ + case 0x06: + mem_data.speed = 2666; + mem_data.cwl = 14; + break; + case 0x07: + mem_data.speed = 2400; + mem_data.cwl = 12; + break; + case 0x08: + mem_data.speed = 2133; + mem_data.cwl = 11; + break; + case 0x09: + mem_data.speed = 1866; + mem_data.cwl = 10; + break; + default: + die("Unsupported tCKmin: %d ps (+/- 125)\n", tckmin * 125); + } + + /* Now that we know our speed, we can calculate the rest of the data */ + mem_data.nrefi = ns_to_nck(7800); + mem_data.nrtp = ps_to_nck(7500); + printk(BIOS_SPEW, "Common memory parameters:\n" + "\tspeed =\t%d MT/s\n" + "\tREFI =\t%d clock cycles\n" + "\tCWL =\t%d clock cycles\n" + "\tRTP =\t%d clock cycles\n", + mem_data.speed, mem_data.nrefi, mem_data.cwl, mem_data.nrtp); + + for (mcs = 0; mcs < MCS_PER_PROC; mcs++) { + if (!mem_data.mcs[mcs].functional) continue; + for (mca = 0; mca < MCA_PER_MCS; mca++) { + if (!mem_data.mcs[mcs].mca[mca].functional) continue; + + rdimm_data_t *dimm = mem_data.mcs[mcs].mca[mca].dimm; + uint32_t val0, val1, common; + int min; /* Minimum compatible with both DIMMs is the bigger value */ + + /* CAS Latency */ + val0 = dimm[0].present ? le32_to_cpu(*(uint32_t *)&dimm[0].spd[20]) : -1; + val1 = dimm[1].present ? le32_to_cpu(*(uint32_t *)&dimm[1].spd[20]) : -1; + /* Assuming both DIMMs are in low CL range, true for all DDR4 speed bins */ + common = val0 & val1; + + /* tAAmin - minimum CAS latency time */ + min = find_min_mtb_ftb(dimm, 24, 123); + while (min <= 36 && ((common >> (min - 7)) & 1) == 0) + min++; + + if (min > 36) { + /* Maybe just die() instead? */ + printk(BIOS_WARNING, "Cannot find CL supported by all DIMMs under MCS%d, MCA%d." + " Marking as nonfunctional.\n", mcs, mca); + mark_nonfunctional(mcs, mca); + continue; + } + + mem_data.mcs[mcs].mca[mca].cl = min; + + /* + * There are also minimal values in Table 170 of JEDEC Standard No. 79-4C which + * probably should also be honored. Some of them (e.g. RRD) depend on the page + * size, which depends on DRAM width. On tested DIMM they are just right - it is + * either minimal legal value or rounded up to whole clock cycle. Can we rely on + * vendors to put sane values in SPD or do we have to check them for validity? + */ + + /* Minimum CAS to CAS Delay Time, Same Bank Group */ + mem_data.mcs[mcs].mca[mca].nccd_l = find_min_mtb_ftb(dimm, 40, 117); + + /* Minimum Write to Read Time, Different Bank Group */ + mem_data.mcs[mcs].mca[mca].nwtr_s = find_min_multi_mtb(dimm, 44, 43, 0x0F, 8); + + /* Minimum Write to Read Time, Same Bank Group */ + mem_data.mcs[mcs].mca[mca].nwtr_l = find_min_multi_mtb(dimm, 45, 43, 0xF0, 4); + + /* Minimum Four Activate Window Delay Time */ + mem_data.mcs[mcs].mca[mca].nfaw = find_min_multi_mtb(dimm, 37, 36, 0x0F, 8); + + /* Minimum RAS to CAS Delay Time */ + mem_data.mcs[mcs].mca[mca].nrcd = find_min_mtb_ftb(dimm, 25, 122); + + /* Minimum Row Precharge Delay Time */ + mem_data.mcs[mcs].mca[mca].nrp = find_min_mtb_ftb(dimm, 26, 121); + + /* Minimum Active to Precharge Delay Time */ + mem_data.mcs[mcs].mca[mca].nras = find_min_multi_mtb(dimm, 28, 27, 0x0F, 8); + + /* Minimum Write Recovery Time */ + mem_data.mcs[mcs].mca[mca].nwr = find_min_multi_mtb(dimm, 42, 41, 0x0F, 8); + + /* Minimum Activate to Activate Delay Time, Different Bank Group */ + mem_data.mcs[mcs].mca[mca].nrrd_s = find_min_mtb_ftb(dimm, 38, 119); + + /* Minimum Activate to Activate Delay Time, Same Bank Group */ + mem_data.mcs[mcs].mca[mca].nrrd_l = find_min_mtb_ftb(dimm, 39, 118); + + /* Minimum Refresh Recovery Delay Time */ + /* Assuming no fine refresh mode. */ + mem_data.mcs[mcs].mca[mca].nrfc = find_min_multi_mtb(dimm, 30, 31, 0xFF, 8); + + /* Minimum Refresh Recovery Delay Time for Different Logical Rank (3DS only) */ + /* + * This one is set per MCA, but it depends on DRAM density, which can be + * mixed between DIMMs under the same channel. We need to choose the bigger + * minimum time, which corresponds to higher density. + * + * Assuming no fine refresh mode. + */ + val0 = dimm[0].present ? dimm[0].spd[4] & 0xF : 0; + val1 = dimm[1].present ? dimm[1].spd[4] & 0xF : 0; + min = (val0 < val1) ? val1 : val0; + + switch (min) { + case 0x4: + mem_data.mcs[mcs].mca[mca].nrfc_dlr = ns_to_nck(90); + break; + case 0x5: + mem_data.mcs[mcs].mca[mca].nrfc_dlr = ns_to_nck(120); + break; + case 0x6: + mem_data.mcs[mcs].mca[mca].nrfc_dlr = ns_to_nck(185); + break; + default: + die("Unsupported DRAM density\n"); + } + + printk(BIOS_SPEW, "MCS%d, MCA%d times (in clock cycles):\n", mcs, mca); + dump_mca_data(&mem_data.mcs[mcs].mca[mca]); + } + } +} + +void main(void) +{ + timestamp_add_now(TS_START_ROMSTAGE); + + console_init(); + + init_timer(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + vpd_pnor_main(); + prepare_dimm_data(); + + report_istep(13,1); // no-op + istep_8_9(); + istep_8_10(); + istep_13_2(); + istep_13_3(); + istep_13_4(); + report_istep(13,5); // no-op + istep_13_6(); + report_istep(13,7); // no-op + istep_13_8(); + istep_13_9(); + istep_13_10(); + istep_13_11(); + report_istep(13,12); // optional, not yet implemented + istep_13_13(); + + istep_14_1(); + istep_14_2(); + /* istep_14_3 doesn't work, probably due to missing SCOM init, skip for now. */ + // istep_14_3(); + report_istep(14,4); // no-op + istep_14_5(); + + timestamp_add_now(TS_AFTER_INITRAM); + + /* Test if SCOM still works. Maybe should check also indirect access? */ + printk(BIOS_DEBUG, "0xF000F = %llx\n", read_scom(0xf000f)); + + /* + * Halt to give a chance to inspect FIRs, otherwise checkstops from + * ramstage may cover up the failure in romstage. + */ + if (read_scom(0xf000f) != 0x223d104900008040) + die("SCOM stopped working, check FIRs, halting now\n"); + + cbmem_initialize_empty(); + run_ramstage(); } From f1ba4c080dfc218f90235319132d9896ae355ef0 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 3 Sep 2021 11:04:32 +0200 Subject: [PATCH 89/90] Fix gitmodules Signed-off-by: Igor Bagnucki --- .gitmodules | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index acbf512597d..8367b6b5b62 100644 --- a/.gitmodules +++ b/.gitmodules @@ -9,6 +9,7 @@ [submodule "vboot"] path = 3rdparty/vboot url = https://review.coreboot.org/vboot.git + branch = main [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware url = https://review.coreboot.org/arm-trusted-firmware.git @@ -54,10 +55,10 @@ [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools url = https://github.com/coreboot/9esec-security-tooling.git -[submodule "3rdparty/sb-signing-utils"] - path = 3rdparty/sb-signing-utils - url = https://github.com/open-power/sb-signing-utils.git [submodule "3rdparty/stm"] path = 3rdparty/stm - url = https://github.com/coreboot/STM + url = https://review.coreboot.org/STM branch = stmpe +[submodule "3rdparty/sb-signing-utils"] + path = 3rdparty/sb-signing-utils + url = https://github.com/open-power/sb-signing-utils.git From fd91b65a1a21af60acbe864241a7b47f78b9ad86 Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Fri, 3 Sep 2021 11:05:26 +0200 Subject: [PATCH 90/90] Fix makefile Signed-off-by: Igor Bagnucki --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 0cda398a758..6d36a4bd2fb 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -500,7 +500,7 @@ ifeq ($(CONFIG_DEBUG_ADA_CODE),y) ADAFLAGS_common += -gnata endif -additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \ +additional-dirs += $(objutil)/cbfstool $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ $(objutil)/cbootimage $(objutil)/ffs